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spapr: Enable in-kernel H_SET_MODE handling
[qemu/cris-port.git] / hw / arm / nseries.c
blob6a6b3e66420c9bf17b1c2a42d2086863ff267f76
1 /*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "sysemu/sysemu.h"
23 #include "hw/arm/omap.h"
24 #include "hw/arm/arm.h"
25 #include "hw/irq.h"
26 #include "ui/console.h"
27 #include "hw/boards.h"
28 #include "hw/i2c/i2c.h"
29 #include "hw/devices.h"
30 #include "hw/block/flash.h"
31 #include "hw/hw.h"
32 #include "hw/bt.h"
33 #include "hw/loader.h"
34 #include "sysemu/block-backend.h"
35 #include "hw/sysbus.h"
36 #include "exec/address-spaces.h"
37
38 /* Nokia N8x0 support */
39 struct n800_s {
40 struct omap_mpu_state_s *mpu;
41
42 struct rfbi_chip_s blizzard;
43 struct {
44 void *opaque;
45 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
46 uWireSlave *chip;
47 } ts;
48
49 int keymap[0x80];
50 DeviceState *kbd;
51
52 DeviceState *usb;
53 void *retu;
54 void *tahvo;
55 DeviceState *nand;
56 };
57
58 /* GPIO pins */
59 #define N8X0_TUSB_ENABLE_GPIO 0
60 #define N800_MMC2_WP_GPIO 8
61 #define N800_UNKNOWN_GPIO0 9 /* out */
62 #define N810_MMC2_VIOSD_GPIO 9
63 #define N810_HEADSET_AMP_GPIO 10
64 #define N800_CAM_TURN_GPIO 12
65 #define N810_GPS_RESET_GPIO 12
66 #define N800_BLIZZARD_POWERDOWN_GPIO 15
67 #define N800_MMC1_WP_GPIO 23
68 #define N810_MMC2_VSD_GPIO 23
69 #define N8X0_ONENAND_GPIO 26
70 #define N810_BLIZZARD_RESET_GPIO 30
71 #define N800_UNKNOWN_GPIO2 53 /* out */
72 #define N8X0_TUSB_INT_GPIO 58
73 #define N8X0_BT_WKUP_GPIO 61
74 #define N8X0_STI_GPIO 62
75 #define N8X0_CBUS_SEL_GPIO 64
76 #define N8X0_CBUS_DAT_GPIO 65
77 #define N8X0_CBUS_CLK_GPIO 66
78 #define N8X0_WLAN_IRQ_GPIO 87
79 #define N8X0_BT_RESET_GPIO 92
80 #define N8X0_TEA5761_CS_GPIO 93
81 #define N800_UNKNOWN_GPIO 94
82 #define N810_TSC_RESET_GPIO 94
83 #define N800_CAM_ACT_GPIO 95
84 #define N810_GPS_WAKEUP_GPIO 95
85 #define N8X0_MMC_CS_GPIO 96
86 #define N8X0_WLAN_PWR_GPIO 97
87 #define N8X0_BT_HOST_WKUP_GPIO 98
88 #define N810_SPEAKER_AMP_GPIO 101
89 #define N810_KB_LOCK_GPIO 102
90 #define N800_TSC_TS_GPIO 103
91 #define N810_TSC_TS_GPIO 106
92 #define N8X0_HEADPHONE_GPIO 107
93 #define N8X0_RETU_GPIO 108
94 #define N800_TSC_KP_IRQ_GPIO 109
95 #define N810_KEYBOARD_GPIO 109
96 #define N800_BAT_COVER_GPIO 110
97 #define N810_SLIDE_GPIO 110
98 #define N8X0_TAHVO_GPIO 111
99 #define N800_UNKNOWN_GPIO4 112 /* out */
100 #define N810_SLEEPX_LED_GPIO 112
101 #define N800_TSC_RESET_GPIO 118 /* ? */
102 #define N810_AIC33_RESET_GPIO 118
103 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
104 #define N8X0_TMP105_GPIO 125
105
106 /* Config */
107 #define BT_UART 0
108 #define XLDR_LL_UART 1
109
110 /* Addresses on the I2C bus 0 */
111 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
112 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
113 #define N810_LP5521_ADDR 0x32 /* LEDs */
114 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
115 #define N810_LM8323_ADDR 0x45 /* Keyboard */
116 /* Addresses on the I2C bus 1 */
117 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
118 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
119
120 /* Chipselects on GPMC NOR interface */
121 #define N8X0_ONENAND_CS 0
122 #define N8X0_USB_ASYNC_CS 1
123 #define N8X0_USB_SYNC_CS 4
124
125 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
126
127 static void n800_mmc_cs_cb(void *opaque, int line, int level)
128 {
129 /* TODO: this seems to actually be connected to the menelaus, to
130 * which also both MMC slots connect. */
131 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
132 }
133
134 static void n8x0_gpio_setup(struct n800_s *s)
135 {
136 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO,
137 qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0));
138 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
139 }
140
141 #define MAEMO_CAL_HEADER(...) \
142 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
143 __VA_ARGS__, \
144 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
145
146 static const uint8_t n8x0_cal_wlan_mac[] = {
147 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
148 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
149 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
150 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
151 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
152 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
153 };
154
155 static const uint8_t n8x0_cal_bt_id[] = {
156 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
157 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
158 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
159 N8X0_BD_ADDR,
160 };
161
162 static void n8x0_nand_setup(struct n800_s *s)
163 {
164 char *otp_region;
165 DriveInfo *dinfo;
166
167 s->nand = qdev_create(NULL, "onenand");
168 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
169 /* Either 0x40 or 0x48 are OK for the device ID */
170 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
171 qdev_prop_set_uint16(s->nand, "version_id", 0);
172 qdev_prop_set_int32(s->nand, "shift", 1);
173 dinfo = drive_get(IF_MTD, 0, 0);
174 if (dinfo) {
175 qdev_prop_set_drive_nofail(s->nand, "drive",
176 blk_by_legacy_dinfo(dinfo));
177 }
178 qdev_init_nofail(s->nand);
179 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
180 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
181 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
182 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
183 otp_region = onenand_raw_otp(s->nand);
184
185 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
186 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
187 /* XXX: in theory should also update the OOB for both pages */
188 }
189
190 static qemu_irq n8x0_system_powerdown;
191
192 static void n8x0_powerdown_req(Notifier *n, void *opaque)
193 {
194 qemu_irq_raise(n8x0_system_powerdown);
195 }
196
197 static Notifier n8x0_system_powerdown_notifier = {
198 .notify = n8x0_powerdown_req
199 };
200
201 static void n8x0_i2c_setup(struct n800_s *s)
202 {
203 DeviceState *dev;
204 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
205 I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
206
207 /* Attach a menelaus PM chip */
208 dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
209 qdev_connect_gpio_out(dev, 3,
210 qdev_get_gpio_in(s->mpu->ih[0],
211 OMAP_INT_24XX_SYS_NIRQ));
212
213 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
214 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
215
216 /* Attach a TMP105 PM chip (A0 wired to ground) */
217 dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR);
218 qdev_connect_gpio_out(dev, 0, tmp_irq);
219 }
220
221 /* Touchscreen and keypad controller */
222 static MouseTransformInfo n800_pointercal = {
223 .x = 800,
224 .y = 480,
225 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
226 };
227
228 static MouseTransformInfo n810_pointercal = {
229 .x = 800,
230 .y = 480,
231 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
232 };
233
234 #define RETU_KEYCODE 61 /* F3 */
235
236 static void n800_key_event(void *opaque, int keycode)
237 {
238 struct n800_s *s = (struct n800_s *) opaque;
239 int code = s->keymap[keycode & 0x7f];
240
241 if (code == -1) {
242 if ((keycode & 0x7f) == RETU_KEYCODE) {
243 retu_key_event(s->retu, !(keycode & 0x80));
244 }
245 return;
246 }
247
248 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
249 }
250
251 static const int n800_keys[16] = {
252 -1,
253 72, /* Up */
254 63, /* Home (F5) */
255 -1,
256 75, /* Left */
257 28, /* Enter */
258 77, /* Right */
259 -1,
260 1, /* Cycle (ESC) */
261 80, /* Down */
262 62, /* Menu (F4) */
263 -1,
264 66, /* Zoom- (F8) */
265 64, /* FullScreen (F6) */
266 65, /* Zoom+ (F7) */
267 -1,
268 };
269
270 static void n800_tsc_kbd_setup(struct n800_s *s)
271 {
272 int i;
273
274 /* XXX: are the three pins inverted inside the chip between the
275 * tsc and the cpu (N4111)? */
276 qemu_irq penirq = NULL; /* NC */
277 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
278 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
279
280 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
281 s->ts.opaque = s->ts.chip->opaque;
282 s->ts.txrx = tsc210x_txrx;
283
284 for (i = 0; i < 0x80; i++) {
285 s->keymap[i] = -1;
286 }
287 for (i = 0; i < 0x10; i++) {
288 if (n800_keys[i] >= 0) {
289 s->keymap[n800_keys[i]] = i;
290 }
291 }
292
293 qemu_add_kbd_event_handler(n800_key_event, s);
294
295 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
296 }
297
298 static void n810_tsc_setup(struct n800_s *s)
299 {
300 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
301
302 s->ts.opaque = tsc2005_init(pintdav);
303 s->ts.txrx = tsc2005_txrx;
304
305 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
306 }
307
308 /* N810 Keyboard controller */
309 static void n810_key_event(void *opaque, int keycode)
310 {
311 struct n800_s *s = (struct n800_s *) opaque;
312 int code = s->keymap[keycode & 0x7f];
313
314 if (code == -1) {
315 if ((keycode & 0x7f) == RETU_KEYCODE) {
316 retu_key_event(s->retu, !(keycode & 0x80));
317 }
318 return;
319 }
320
321 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
322 }
323
324 #define M 0
325
326 static int n810_keys[0x80] = {
327 [0x01] = 16, /* Q */
328 [0x02] = 37, /* K */
329 [0x03] = 24, /* O */
330 [0x04] = 25, /* P */
331 [0x05] = 14, /* Backspace */
332 [0x06] = 30, /* A */
333 [0x07] = 31, /* S */
334 [0x08] = 32, /* D */
335 [0x09] = 33, /* F */
336 [0x0a] = 34, /* G */
337 [0x0b] = 35, /* H */
338 [0x0c] = 36, /* J */
339
340 [0x11] = 17, /* W */
341 [0x12] = 62, /* Menu (F4) */
342 [0x13] = 38, /* L */
343 [0x14] = 40, /* ' (Apostrophe) */
344 [0x16] = 44, /* Z */
345 [0x17] = 45, /* X */
346 [0x18] = 46, /* C */
347 [0x19] = 47, /* V */
348 [0x1a] = 48, /* B */
349 [0x1b] = 49, /* N */
350 [0x1c] = 42, /* Shift (Left shift) */
351 [0x1f] = 65, /* Zoom+ (F7) */
352
353 [0x21] = 18, /* E */
354 [0x22] = 39, /* ; (Semicolon) */
355 [0x23] = 12, /* - (Minus) */
356 [0x24] = 13, /* = (Equal) */
357 [0x2b] = 56, /* Fn (Left Alt) */
358 [0x2c] = 50, /* M */
359 [0x2f] = 66, /* Zoom- (F8) */
360
361 [0x31] = 19, /* R */
362 [0x32] = 29 | M, /* Right Ctrl */
363 [0x34] = 57, /* Space */
364 [0x35] = 51, /* , (Comma) */
365 [0x37] = 72 | M, /* Up */
366 [0x3c] = 82 | M, /* Compose (Insert) */
367 [0x3f] = 64, /* FullScreen (F6) */
368
369 [0x41] = 20, /* T */
370 [0x44] = 52, /* . (Dot) */
371 [0x46] = 77 | M, /* Right */
372 [0x4f] = 63, /* Home (F5) */
373 [0x51] = 21, /* Y */
374 [0x53] = 80 | M, /* Down */
375 [0x55] = 28, /* Enter */
376 [0x5f] = 1, /* Cycle (ESC) */
377
378 [0x61] = 22, /* U */
379 [0x64] = 75 | M, /* Left */
380
381 [0x71] = 23, /* I */
382 #if 0
383 [0x75] = 28 | M, /* KP Enter (KP Enter) */
384 #else
385 [0x75] = 15, /* KP Enter (Tab) */
386 #endif
387 };
388
389 #undef M
390
391 static void n810_kbd_setup(struct n800_s *s)
392 {
393 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
394 int i;
395
396 for (i = 0; i < 0x80; i++) {
397 s->keymap[i] = -1;
398 }
399 for (i = 0; i < 0x80; i++) {
400 if (n810_keys[i] > 0) {
401 s->keymap[n810_keys[i]] = i;
402 }
403 }
404
405 qemu_add_kbd_event_handler(n810_key_event, s);
406
407 /* Attach the LM8322 keyboard to the I2C bus,
408 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
409 s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
410 "lm8323", N810_LM8323_ADDR);
411 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
412 }
413
414 /* LCD MIPI DBI-C controller (URAL) */
415 struct mipid_s {
416 int resp[4];
417 int param[4];
418 int p;
419 int pm;
420 int cmd;
421
422 int sleep;
423 int booster;
424 int te;
425 int selfcheck;
426 int partial;
427 int normal;
428 int vscr;
429 int invert;
430 int onoff;
431 int gamma;
432 uint32_t id;
433 };
434
435 static void mipid_reset(struct mipid_s *s)
436 {
437 s->pm = 0;
438 s->cmd = 0;
439
440 s->sleep = 1;
441 s->booster = 0;
442 s->selfcheck =
443 (1 << 7) | /* Register loading OK. */
444 (1 << 5) | /* The chip is attached. */
445 (1 << 4); /* Display glass still in one piece. */
446 s->te = 0;
447 s->partial = 0;
448 s->normal = 1;
449 s->vscr = 0;
450 s->invert = 0;
451 s->onoff = 1;
452 s->gamma = 0;
453 }
454
455 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
456 {
457 struct mipid_s *s = (struct mipid_s *) opaque;
458 uint8_t ret;
459
460 if (len > 9) {
461 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
462 }
463
464 if (s->p >= ARRAY_SIZE(s->resp)) {
465 ret = 0;
466 } else {
467 ret = s->resp[s->p++];
468 }
469 if (s->pm-- > 0) {
470 s->param[s->pm] = cmd;
471 } else {
472 s->cmd = cmd;
473 }
474
475 switch (s->cmd) {
476 case 0x00: /* NOP */
477 break;
478
479 case 0x01: /* SWRESET */
480 mipid_reset(s);
481 break;
482
483 case 0x02: /* BSTROFF */
484 s->booster = 0;
485 break;
486 case 0x03: /* BSTRON */
487 s->booster = 1;
488 break;
489
490 case 0x04: /* RDDID */
491 s->p = 0;
492 s->resp[0] = (s->id >> 16) & 0xff;
493 s->resp[1] = (s->id >> 8) & 0xff;
494 s->resp[2] = (s->id >> 0) & 0xff;
495 break;
496
497 case 0x06: /* RD_RED */
498 case 0x07: /* RD_GREEN */
499 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
500 * for the bootloader one needs to change this. */
501 case 0x08: /* RD_BLUE */
502 s->p = 0;
503 /* TODO: return first pixel components */
504 s->resp[0] = 0x01;
505 break;
506
507 case 0x09: /* RDDST */
508 s->p = 0;
509 s->resp[0] = s->booster << 7;
510 s->resp[1] = (5 << 4) | (s->partial << 2) |
511 (s->sleep << 1) | s->normal;
512 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
513 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
514 s->resp[3] = s->gamma << 6;
515 break;
516
517 case 0x0a: /* RDDPM */
518 s->p = 0;
519 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
520 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
521 break;
522 case 0x0b: /* RDDMADCTR */
523 s->p = 0;
524 s->resp[0] = 0;
525 break;
526 case 0x0c: /* RDDCOLMOD */
527 s->p = 0;
528 s->resp[0] = 5; /* 65K colours */
529 break;
530 case 0x0d: /* RDDIM */
531 s->p = 0;
532 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
533 break;
534 case 0x0e: /* RDDSM */
535 s->p = 0;
536 s->resp[0] = s->te << 7;
537 break;
538 case 0x0f: /* RDDSDR */
539 s->p = 0;
540 s->resp[0] = s->selfcheck;
541 break;
542
543 case 0x10: /* SLPIN */
544 s->sleep = 1;
545 break;
546 case 0x11: /* SLPOUT */
547 s->sleep = 0;
548 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
549 break;
550
551 case 0x12: /* PTLON */
552 s->partial = 1;
553 s->normal = 0;
554 s->vscr = 0;
555 break;
556 case 0x13: /* NORON */
557 s->partial = 0;
558 s->normal = 1;
559 s->vscr = 0;
560 break;
561
562 case 0x20: /* INVOFF */
563 s->invert = 0;
564 break;
565 case 0x21: /* INVON */
566 s->invert = 1;
567 break;
568
569 case 0x22: /* APOFF */
570 case 0x23: /* APON */
571 goto bad_cmd;
572
573 case 0x25: /* WRCNTR */
574 if (s->pm < 0) {
575 s->pm = 1;
576 }
577 goto bad_cmd;
578
579 case 0x26: /* GAMSET */
580 if (!s->pm) {
581 s->gamma = ctz32(s->param[0] & 0xf);
582 if (s->gamma == 32) {
583 s->gamma = -1; /* XXX: should this be 0? */
584 }
585 } else if (s->pm < 0) {
586 s->pm = 1;
587 }
588 break;
589
590 case 0x28: /* DISPOFF */
591 s->onoff = 0;
592 break;
593 case 0x29: /* DISPON */
594 s->onoff = 1;
595 break;
596
597 case 0x2a: /* CASET */
598 case 0x2b: /* RASET */
599 case 0x2c: /* RAMWR */
600 case 0x2d: /* RGBSET */
601 case 0x2e: /* RAMRD */
602 case 0x30: /* PTLAR */
603 case 0x33: /* SCRLAR */
604 goto bad_cmd;
605
606 case 0x34: /* TEOFF */
607 s->te = 0;
608 break;
609 case 0x35: /* TEON */
610 if (!s->pm) {
611 s->te = 1;
612 } else if (s->pm < 0) {
613 s->pm = 1;
614 }
615 break;
616
617 case 0x36: /* MADCTR */
618 goto bad_cmd;
619
620 case 0x37: /* VSCSAD */
621 s->partial = 0;
622 s->normal = 0;
623 s->vscr = 1;
624 break;
625
626 case 0x38: /* IDMOFF */
627 case 0x39: /* IDMON */
628 case 0x3a: /* COLMOD */
629 goto bad_cmd;
630
631 case 0xb0: /* CLKINT / DISCTL */
632 case 0xb1: /* CLKEXT */
633 if (s->pm < 0) {
634 s->pm = 2;
635 }
636 break;
637
638 case 0xb4: /* FRMSEL */
639 break;
640
641 case 0xb5: /* FRM8SEL */
642 case 0xb6: /* TMPRNG / INIESC */
643 case 0xb7: /* TMPHIS / NOP2 */
644 case 0xb8: /* TMPREAD / MADCTL */
645 case 0xba: /* DISTCTR */
646 case 0xbb: /* EPVOL */
647 goto bad_cmd;
648
649 case 0xbd: /* Unknown */
650 s->p = 0;
651 s->resp[0] = 0;
652 s->resp[1] = 1;
653 break;
654
655 case 0xc2: /* IFMOD */
656 if (s->pm < 0) {
657 s->pm = 2;
658 }
659 break;
660
661 case 0xc6: /* PWRCTL */
662 case 0xc7: /* PPWRCTL */
663 case 0xd0: /* EPWROUT */
664 case 0xd1: /* EPWRIN */
665 case 0xd4: /* RDEV */
666 case 0xd5: /* RDRR */
667 goto bad_cmd;
668
669 case 0xda: /* RDID1 */
670 s->p = 0;
671 s->resp[0] = (s->id >> 16) & 0xff;
672 break;
673 case 0xdb: /* RDID2 */
674 s->p = 0;
675 s->resp[0] = (s->id >> 8) & 0xff;
676 break;
677 case 0xdc: /* RDID3 */
678 s->p = 0;
679 s->resp[0] = (s->id >> 0) & 0xff;
680 break;
681
682 default:
683 bad_cmd:
684 qemu_log_mask(LOG_GUEST_ERROR,
685 "%s: unknown command %02x\n", __func__, s->cmd);
686 break;
687 }
688
689 return ret;
690 }
691
692 static void *mipid_init(void)
693 {
694 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
695
696 s->id = 0x838f03;
697 mipid_reset(s);
698
699 return s;
700 }
701
702 static void n8x0_spi_setup(struct n800_s *s)
703 {
704 void *tsc = s->ts.opaque;
705 void *mipid = mipid_init();
706
707 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
708 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
709 }
710
711 /* This task is normally performed by the bootloader. If we're loading
712 * a kernel directly, we need to enable the Blizzard ourselves. */
713 static void n800_dss_init(struct rfbi_chip_s *chip)
714 {
715 uint8_t *fb_blank;
716
717 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
718 chip->write(chip->opaque, 1, 0x64);
719 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
720 chip->write(chip->opaque, 1, 0x1e);
721 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
722 chip->write(chip->opaque, 1, 0xe0);
723 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
724 chip->write(chip->opaque, 1, 0x01);
725 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
726 chip->write(chip->opaque, 1, 0x06);
727 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
728 chip->write(chip->opaque, 1, 1); /* Enable bit */
729
730 chip->write(chip->opaque, 0, 0x6c);
731 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
732 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
733 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
734 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
735 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
736 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
737 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
738 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
739 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
740 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
741 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
742 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
743 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
744 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
745 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
746 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
747 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
748 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
749
750 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
751 /* Display Memory Data Port */
752 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
753 g_free(fb_blank);
754 }
755
756 static void n8x0_dss_setup(struct n800_s *s)
757 {
758 s->blizzard.opaque = s1d13745_init(NULL);
759 s->blizzard.block = s1d13745_write_block;
760 s->blizzard.write = s1d13745_write;
761 s->blizzard.read = s1d13745_read;
762
763 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
764 }
765
766 static void n8x0_cbus_setup(struct n800_s *s)
767 {
768 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
769 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
770 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
771
772 CBus *cbus = cbus_init(dat_out);
773
774 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
775 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
776 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
777
778 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
779 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
780 }
781
782 static void n8x0_uart_setup(struct n800_s *s)
783 {
784 CharDriverState *radio = uart_hci_init(
785 qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
786
787 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
788 csrhci_pins_get(radio)[csrhci_pin_reset]);
789 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
790 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
791
792 omap_uart_attach(s->mpu->uart[BT_UART], radio);
793 }
794
795 static void n8x0_usb_setup(struct n800_s *s)
796 {
797 SysBusDevice *dev;
798 s->usb = qdev_create(NULL, "tusb6010");
799 dev = SYS_BUS_DEVICE(s->usb);
800 qdev_init_nofail(s->usb);
801 sysbus_connect_irq(dev, 0,
802 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
803 /* Using the NOR interface */
804 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
805 sysbus_mmio_get_region(dev, 0));
806 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
807 sysbus_mmio_get_region(dev, 1));
808 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
809 qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
810 }
811
812 /* Setup done before the main bootloader starts by some early setup code
813 * - used when we want to run the main bootloader in emulation. This
814 * isn't documented. */
815 static uint32_t n800_pinout[104] = {
816 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
817 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
818 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
819 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
820 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
821 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
822 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
823 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
824 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
825 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
826 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
827 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
828 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
829 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
830 0x00000000, 0x00000038, 0x00340000, 0x00000000,
831 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
832 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
833 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
834 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
835 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
836 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
837 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
838 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
839 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
840 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
841 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
842 };
843
844 static void n800_setup_nolo_tags(void *sram_base)
845 {
846 int i;
847 uint32_t *p = sram_base + 0x8000;
848 uint32_t *v = sram_base + 0xa000;
849
850 memset(p, 0, 0x3000);
851
852 strcpy((void *) (p + 0), "QEMU N800");
853
854 strcpy((void *) (p + 8), "F5");
855
856 stl_p(p + 10, 0x04f70000);
857 strcpy((void *) (p + 9), "RX-34");
858
859 /* RAM size in MB? */
860 stl_p(p + 12, 0x80);
861
862 /* Pointer to the list of tags */
863 stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000);
864
865 /* The NOLO tags start here */
866 p = sram_base + 0x9000;
867 #define ADD_TAG(tag, len) \
868 stw_p((uint16_t *) p + 0, tag); \
869 stw_p((uint16_t *) p + 1, len); p++; \
870 stl_p(p++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
871
872 /* OMAP STI console? Pin out settings? */
873 ADD_TAG(0x6e01, 414);
874 for (i = 0; i < ARRAY_SIZE(n800_pinout); i++) {
875 stl_p(v++, n800_pinout[i]);
876 }
877
878 /* Kernel memsize? */
879 ADD_TAG(0x6e05, 1);
880 stl_p(v++, 2);
881
882 /* NOLO serial console */
883 ADD_TAG(0x6e02, 4);
884 stl_p(v++, XLDR_LL_UART); /* UART number (1 - 3) */
885
886 #if 0
887 /* CBUS settings (Retu/AVilma) */
888 ADD_TAG(0x6e03, 6);
889 stw_p((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
890 stw_p((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
891 stw_p((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
892 v += 2;
893 #endif
894
895 /* Nokia ASIC BB5 (Retu/Tahvo) */
896 ADD_TAG(0x6e0a, 4);
897 stw_p((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
898 stw_p((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
899 v++;
900
901 /* LCD console? */
902 ADD_TAG(0x6e04, 4);
903 stw_p((uint16_t *) v + 0, 30); /* ??? */
904 stw_p((uint16_t *) v + 1, 24); /* ??? */
905 v++;
906
907 #if 0
908 /* LCD settings */
909 ADD_TAG(0x6e06, 2);
910 stw_p((uint16_t *) (v++), 15); /* ??? */
911 #endif
912
913 /* I^2C (Menelaus) */
914 ADD_TAG(0x6e07, 4);
915 stl_p(v++, 0x00720000); /* ??? */
916
917 /* Unknown */
918 ADD_TAG(0x6e0b, 6);
919 stw_p((uint16_t *) v + 0, 94); /* ??? */
920 stw_p((uint16_t *) v + 1, 23); /* ??? */
921 stw_p((uint16_t *) v + 2, 0); /* ??? */
922 v += 2;
923
924 /* OMAP gpio switch info */
925 ADD_TAG(0x6e0c, 80);
926 strcpy((void *) v, "bat_cover"); v += 3;
927 stw_p((uint16_t *) v + 0, 110); /* GPIO num ??? */
928 stw_p((uint16_t *) v + 1, 1); /* GPIO num ??? */
929 v += 2;
930 strcpy((void *) v, "cam_act"); v += 3;
931 stw_p((uint16_t *) v + 0, 95); /* GPIO num ??? */
932 stw_p((uint16_t *) v + 1, 32); /* GPIO num ??? */
933 v += 2;
934 strcpy((void *) v, "cam_turn"); v += 3;
935 stw_p((uint16_t *) v + 0, 12); /* GPIO num ??? */
936 stw_p((uint16_t *) v + 1, 33); /* GPIO num ??? */
937 v += 2;
938 strcpy((void *) v, "headphone"); v += 3;
939 stw_p((uint16_t *) v + 0, 107); /* GPIO num ??? */
940 stw_p((uint16_t *) v + 1, 17); /* GPIO num ??? */
941 v += 2;
942
943 /* Bluetooth */
944 ADD_TAG(0x6e0e, 12);
945 stl_p(v++, 0x5c623d01); /* ??? */
946 stl_p(v++, 0x00000201); /* ??? */
947 stl_p(v++, 0x00000000); /* ??? */
948
949 /* CX3110x WLAN settings */
950 ADD_TAG(0x6e0f, 8);
951 stl_p(v++, 0x00610025); /* ??? */
952 stl_p(v++, 0xffff0057); /* ??? */
953
954 /* MMC host settings */
955 ADD_TAG(0x6e10, 12);
956 stl_p(v++, 0xffff000f); /* ??? */
957 stl_p(v++, 0xffffffff); /* ??? */
958 stl_p(v++, 0x00000060); /* ??? */
959
960 /* OneNAND chip select */
961 ADD_TAG(0x6e11, 10);
962 stl_p(v++, 0x00000401); /* ??? */
963 stl_p(v++, 0x0002003a); /* ??? */
964 stl_p(v++, 0x00000002); /* ??? */
965
966 /* TEA5761 sensor settings */
967 ADD_TAG(0x6e12, 2);
968 stl_p(v++, 93); /* GPIO num ??? */
969
970 #if 0
971 /* Unknown tag */
972 ADD_TAG(6e09, 0);
973
974 /* Kernel UART / console */
975 ADD_TAG(6e12, 0);
976 #endif
977
978 /* End of the list */
979 stl_p(p++, 0x00000000);
980 stl_p(p++, 0x00000000);
981 }
982
983 /* This task is normally performed by the bootloader. If we're loading
984 * a kernel directly, we need to set up GPMC mappings ourselves. */
985 static void n800_gpmc_init(struct n800_s *s)
986 {
987 uint32_t config7 =
988 (0xf << 8) | /* MASKADDRESS */
989 (1 << 6) | /* CSVALID */
990 (4 << 0); /* BASEADDRESS */
991
992 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
993 &config7, sizeof(config7));
994 }
995
996 /* Setup sequence done by the bootloader */
997 static void n8x0_boot_init(void *opaque)
998 {
999 struct n800_s *s = (struct n800_s *) opaque;
1000 uint32_t buf;
1001
1002 /* PRCM setup */
1003 #define omap_writel(addr, val) \
1004 buf = (val); \
1005 cpu_physical_memory_write(addr, &buf, sizeof(buf))
1006
1007 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
1008 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
1009 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
1010 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
1011 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
1012 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
1013 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
1014 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
1015 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
1016 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
1017 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
1018 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
1019 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
1020 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
1021 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
1022 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
1023 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1024 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1025 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1026 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1027 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1028 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1029 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1030 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1031 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1032 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1033 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1034 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1035 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1036 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1037 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1038 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1039 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1040 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1041 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1042 (0x78 << 12) | (6 << 8));
1043 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1044
1045 /* GPMC setup */
1046 n800_gpmc_init(s);
1047
1048 /* Video setup */
1049 n800_dss_init(&s->blizzard);
1050
1051 /* CPU setup */
1052 s->mpu->cpu->env.GE = 0x5;
1053
1054 /* If the machine has a slided keyboard, open it */
1055 if (s->kbd) {
1056 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
1057 }
1058 }
1059
1060 #define OMAP_TAG_NOKIA_BT 0x4e01
1061 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1062 #define OMAP_TAG_CBUS 0x4e03
1063 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1064
1065 static struct omap_gpiosw_info_s {
1066 const char *name;
1067 int line;
1068 int type;
1069 } n800_gpiosw_info[] = {
1070 {
1071 "bat_cover", N800_BAT_COVER_GPIO,
1072 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1073 }, {
1074 "cam_act", N800_CAM_ACT_GPIO,
1075 OMAP_GPIOSW_TYPE_ACTIVITY,
1076 }, {
1077 "cam_turn", N800_CAM_TURN_GPIO,
1078 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1079 }, {
1080 "headphone", N8X0_HEADPHONE_GPIO,
1081 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1082 },
1083 { NULL }
1084 }, n810_gpiosw_info[] = {
1085 {
1086 "gps_reset", N810_GPS_RESET_GPIO,
1087 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1088 }, {
1089 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1090 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1091 }, {
1092 "headphone", N8X0_HEADPHONE_GPIO,
1093 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1094 }, {
1095 "kb_lock", N810_KB_LOCK_GPIO,
1096 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1097 }, {
1098 "sleepx_led", N810_SLEEPX_LED_GPIO,
1099 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1100 }, {
1101 "slide", N810_SLIDE_GPIO,
1102 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1103 },
1104 { NULL }
1105 };
1106
1107 static struct omap_partition_info_s {
1108 uint32_t offset;
1109 uint32_t size;
1110 int mask;
1111 const char *name;
1112 } n800_part_info[] = {
1113 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1114 { 0x00020000, 0x00060000, 0x0, "config" },
1115 { 0x00080000, 0x00200000, 0x0, "kernel" },
1116 { 0x00280000, 0x00200000, 0x3, "initfs" },
1117 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1118
1119 { 0, 0, 0, NULL }
1120 }, n810_part_info[] = {
1121 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1122 { 0x00020000, 0x00060000, 0x0, "config" },
1123 { 0x00080000, 0x00220000, 0x0, "kernel" },
1124 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1125 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1126
1127 { 0, 0, 0, NULL }
1128 };
1129
1130 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1131
1132 static int n8x0_atag_setup(void *p, int model)
1133 {
1134 uint8_t *b;
1135 uint16_t *w;
1136 uint32_t *l;
1137 struct omap_gpiosw_info_s *gpiosw;
1138 struct omap_partition_info_s *partition;
1139 const char *tag;
1140
1141 w = p;
1142
1143 stw_p(w++, OMAP_TAG_UART); /* u16 tag */
1144 stw_p(w++, 4); /* u16 len */
1145 stw_p(w++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1146 w++;
1147
1148 #if 0
1149 stw_p(w++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1150 stw_p(w++, 4); /* u16 len */
1151 stw_p(w++, XLDR_LL_UART + 1); /* u8 console_uart */
1152 stw_p(w++, 115200); /* u32 console_speed */
1153 #endif
1154
1155 stw_p(w++, OMAP_TAG_LCD); /* u16 tag */
1156 stw_p(w++, 36); /* u16 len */
1157 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1158 w += 8;
1159 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1160 w += 8;
1161 stw_p(w++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1162 stw_p(w++, 24); /* u8 data_lines */
1163
1164 stw_p(w++, OMAP_TAG_CBUS); /* u16 tag */
1165 stw_p(w++, 8); /* u16 len */
1166 stw_p(w++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1167 stw_p(w++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1168 stw_p(w++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1169 w++;
1170
1171 stw_p(w++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1172 stw_p(w++, 4); /* u16 len */
1173 stw_p(w++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1174 stw_p(w++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1175
1176 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1177 for (; gpiosw->name; gpiosw++) {
1178 stw_p(w++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1179 stw_p(w++, 20); /* u16 len */
1180 strcpy((void *) w, gpiosw->name); /* char name[12] */
1181 w += 6;
1182 stw_p(w++, gpiosw->line); /* u16 gpio */
1183 stw_p(w++, gpiosw->type);
1184 stw_p(w++, 0);
1185 stw_p(w++, 0);
1186 }
1187
1188 stw_p(w++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1189 stw_p(w++, 12); /* u16 len */
1190 b = (void *) w;
1191 stb_p(b++, 0x01); /* u8 chip_type (CSR) */
1192 stb_p(b++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1193 stb_p(b++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1194 stb_p(b++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1195 stb_p(b++, BT_UART + 1); /* u8 bt_uart */
1196 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1197 b += 6;
1198 stb_p(b++, 0x02); /* u8 bt_sysclk (38.4) */
1199 w = (void *) b;
1200
1201 stw_p(w++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1202 stw_p(w++, 8); /* u16 len */
1203 stw_p(w++, 0x25); /* u8 chip_type */
1204 stw_p(w++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1205 stw_p(w++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1206 stw_p(w++, -1); /* s16 spi_cs_gpio */
1207
1208 stw_p(w++, OMAP_TAG_MMC); /* u16 tag */
1209 stw_p(w++, 16); /* u16 len */
1210 if (model == 810) {
1211 stw_p(w++, 0x23f); /* unsigned flags */
1212 stw_p(w++, -1); /* s16 power_pin */
1213 stw_p(w++, -1); /* s16 switch_pin */
1214 stw_p(w++, -1); /* s16 wp_pin */
1215 stw_p(w++, 0x240); /* unsigned flags */
1216 stw_p(w++, 0xc000); /* s16 power_pin */
1217 stw_p(w++, 0x0248); /* s16 switch_pin */
1218 stw_p(w++, 0xc000); /* s16 wp_pin */
1219 } else {
1220 stw_p(w++, 0xf); /* unsigned flags */
1221 stw_p(w++, -1); /* s16 power_pin */
1222 stw_p(w++, -1); /* s16 switch_pin */
1223 stw_p(w++, -1); /* s16 wp_pin */
1224 stw_p(w++, 0); /* unsigned flags */
1225 stw_p(w++, 0); /* s16 power_pin */
1226 stw_p(w++, 0); /* s16 switch_pin */
1227 stw_p(w++, 0); /* s16 wp_pin */
1228 }
1229
1230 stw_p(w++, OMAP_TAG_TEA5761); /* u16 tag */
1231 stw_p(w++, 4); /* u16 len */
1232 stw_p(w++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1233 w++;
1234
1235 partition = (model == 810) ? n810_part_info : n800_part_info;
1236 for (; partition->name; partition++) {
1237 stw_p(w++, OMAP_TAG_PARTITION); /* u16 tag */
1238 stw_p(w++, 28); /* u16 len */
1239 strcpy((void *) w, partition->name); /* char name[16] */
1240 l = (void *) (w + 8);
1241 stl_p(l++, partition->size); /* unsigned int size */
1242 stl_p(l++, partition->offset); /* unsigned int offset */
1243 stl_p(l++, partition->mask); /* unsigned int mask_flags */
1244 w = (void *) l;
1245 }
1246
1247 stw_p(w++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1248 stw_p(w++, 12); /* u16 len */
1249 #if 0
1250 strcpy((void *) w, "por"); /* char reason_str[12] */
1251 strcpy((void *) w, "charger"); /* char reason_str[12] */
1252 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1253 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1254 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1255 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1256 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1257 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1258 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1259 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1260 #else
1261 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1262 #endif
1263 w += 6;
1264
1265 tag = (model == 810) ? "RX-44" : "RX-34";
1266 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1267 stw_p(w++, 24); /* u16 len */
1268 strcpy((void *) w, "product"); /* char component[12] */
1269 w += 6;
1270 strcpy((void *) w, tag); /* char version[12] */
1271 w += 6;
1272
1273 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1274 stw_p(w++, 24); /* u16 len */
1275 strcpy((void *) w, "hw-build"); /* char component[12] */
1276 w += 6;
1277 strcpy((void *) w, "QEMU ");
1278 pstrcat((void *) w, 12, qemu_get_version()); /* char version[12] */
1279 w += 6;
1280
1281 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1282 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1283 stw_p(w++, 24); /* u16 len */
1284 strcpy((void *) w, "nolo"); /* char component[12] */
1285 w += 6;
1286 strcpy((void *) w, tag); /* char version[12] */
1287 w += 6;
1288
1289 return (void *) w - p;
1290 }
1291
1292 static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1293 {
1294 return n8x0_atag_setup(p, 800);
1295 }
1296
1297 static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1298 {
1299 return n8x0_atag_setup(p, 810);
1300 }
1301
1302 static void n8x0_init(MachineState *machine,
1303 struct arm_boot_info *binfo, int model)
1304 {
1305 MemoryRegion *sysmem = get_system_memory();
1306 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1307 int sdram_size = binfo->ram_size;
1308
1309 s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);
1310
1311 /* Setup peripherals
1312 *
1313 * Believed external peripherals layout in the N810:
1314 * (spi bus 1)
1315 * tsc2005
1316 * lcd_mipid
1317 * (spi bus 2)
1318 * Conexant cx3110x (WLAN)
1319 * optional: pc2400m (WiMAX)
1320 * (i2c bus 0)
1321 * TLV320AIC33 (audio codec)
1322 * TCM825x (camera by Toshiba)
1323 * lp5521 (clever LEDs)
1324 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1325 * lm8323 (keypad, manf 00, rev 04)
1326 * (i2c bus 1)
1327 * tmp105 (temperature sensor, hwmon)
1328 * menelaus (pm)
1329 * (somewhere on i2c - maybe N800-only)
1330 * tea5761 (FM tuner)
1331 * (serial 0)
1332 * GPS
1333 * (some serial port)
1334 * csr41814 (Bluetooth)
1335 */
1336 n8x0_gpio_setup(s);
1337 n8x0_nand_setup(s);
1338 n8x0_i2c_setup(s);
1339 if (model == 800) {
1340 n800_tsc_kbd_setup(s);
1341 } else if (model == 810) {
1342 n810_tsc_setup(s);
1343 n810_kbd_setup(s);
1344 }
1345 n8x0_spi_setup(s);
1346 n8x0_dss_setup(s);
1347 n8x0_cbus_setup(s);
1348 n8x0_uart_setup(s);
1349 if (usb_enabled()) {
1350 n8x0_usb_setup(s);
1351 }
1352
1353 if (machine->kernel_filename) {
1354 /* Or at the linux loader. */
1355 binfo->kernel_filename = machine->kernel_filename;
1356 binfo->kernel_cmdline = machine->kernel_cmdline;
1357 binfo->initrd_filename = machine->initrd_filename;
1358 arm_load_kernel(s->mpu->cpu, binfo);
1359
1360 qemu_register_reset(n8x0_boot_init, s);
1361 }
1362
1363 if (option_rom[0].name &&
1364 (machine->boot_order[0] == 'n' || !machine->kernel_filename)) {
1365 uint8_t nolo_tags[0x10000];
1366 /* No, wait, better start at the ROM. */
1367 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
1368
1369 /* This is intended for loading the `secondary.bin' program from
1370 * Nokia images (the NOLO bootloader). The entry point seems
1371 * to be at OMAP2_Q2_BASE + 0x400000.
1372 *
1373 * The `2nd.bin' files contain some kind of earlier boot code and
1374 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1375 *
1376 * The code above is for loading the `zImage' file from Nokia
1377 * images. */
1378 load_image_targphys(option_rom[0].name,
1379 OMAP2_Q2_BASE + 0x400000,
1380 sdram_size - 0x400000);
1381
1382 n800_setup_nolo_tags(nolo_tags);
1383 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1384 }
1385 }
1386
1387 static struct arm_boot_info n800_binfo = {
1388 .loader_start = OMAP2_Q2_BASE,
1389 /* Actually two chips of 0x4000000 bytes each */
1390 .ram_size = 0x08000000,
1391 .board_id = 0x4f7,
1392 .atag_board = n800_atag_setup,
1393 };
1394
1395 static struct arm_boot_info n810_binfo = {
1396 .loader_start = OMAP2_Q2_BASE,
1397 /* Actually two chips of 0x4000000 bytes each */
1398 .ram_size = 0x08000000,
1399 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1400 * used by some older versions of the bootloader and 5555 is used
1401 * instead (including versions that shipped with many devices). */
1402 .board_id = 0x60c,
1403 .atag_board = n810_atag_setup,
1404 };
1405
1406 static void n800_init(MachineState *machine)
1407 {
1408 n8x0_init(machine, &n800_binfo, 800);
1409 }
1410
1411 static void n810_init(MachineState *machine)
1412 {
1413 n8x0_init(machine, &n810_binfo, 810);
1414 }
1415
1416 static void n800_class_init(ObjectClass *oc, void *data)
1417 {
1418 MachineClass *mc = MACHINE_CLASS(oc);
1419
1420 mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)";
1421 mc->init = n800_init;
1422 mc->default_boot_order = "";
1423 }
1424
1425 static const TypeInfo n800_type = {
1426 .name = MACHINE_TYPE_NAME("n800"),
1427 .parent = TYPE_MACHINE,
1428 .class_init = n800_class_init,
1429 };
1430
1431 static void n810_class_init(ObjectClass *oc, void *data)
1432 {
1433 MachineClass *mc = MACHINE_CLASS(oc);
1434
1435 mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)";
1436 mc->init = n810_init;
1437 mc->default_boot_order = "";
1438 }
1439
1440 static const TypeInfo n810_type = {
1441 .name = MACHINE_TYPE_NAME("n810"),
1442 .parent = TYPE_MACHINE,
1443 .class_init = n810_class_init,
1444 };
1445
1446 static void nseries_machine_init(void)
1447 {
1448 type_register_static(&n800_type);
1449 type_register_static(&n810_type);
1450 }
1451
1452 machine_init(nseries_machine_init)
CRIS target port of Qemu