2 * Device model for Cadence UART
4 * Copyright (c) 2010 Xilinx Inc.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
6 * Copyright (c) 2012 PetaLogix Pty Ltd.
7 * Written by Haibing Ma
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "hw/sysbus.h"
20 #include "sysemu/char.h"
21 #include "qemu/timer.h"
23 #ifdef CADENCE_UART_ERR_DEBUG
24 #define DB_PRINT(...) do { \
25 fprintf(stderr, ": %s: ", __func__); \
26 fprintf(stderr, ## __VA_ARGS__); \
32 #define UART_SR_INTR_RTRIG 0x00000001
33 #define UART_SR_INTR_REMPTY 0x00000002
34 #define UART_SR_INTR_RFUL 0x00000004
35 #define UART_SR_INTR_TEMPTY 0x00000008
36 #define UART_SR_INTR_TFUL 0x00000010
37 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
38 #define UART_SR_TTRIG 0x00002000
39 #define UART_INTR_TTRIG 0x00000400
40 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
41 * SR, then the same bit in CISR is set high too */
42 #define UART_SR_TO_CISR_MASK 0x0000001F
44 #define UART_INTR_ROVR 0x00000020
45 #define UART_INTR_FRAME 0x00000040
46 #define UART_INTR_PARE 0x00000080
47 #define UART_INTR_TIMEOUT 0x00000100
48 #define UART_INTR_DMSI 0x00000200
49 #define UART_INTR_TOVR 0x00001000
51 #define UART_SR_RACTIVE 0x00000400
52 #define UART_SR_TACTIVE 0x00000800
53 #define UART_SR_FDELT 0x00001000
55 #define UART_CR_RXRST 0x00000001
56 #define UART_CR_TXRST 0x00000002
57 #define UART_CR_RX_EN 0x00000004
58 #define UART_CR_RX_DIS 0x00000008
59 #define UART_CR_TX_EN 0x00000010
60 #define UART_CR_TX_DIS 0x00000020
61 #define UART_CR_RST_TO 0x00000040
62 #define UART_CR_STARTBRK 0x00000080
63 #define UART_CR_STOPBRK 0x00000100
65 #define UART_MR_CLKS 0x00000001
66 #define UART_MR_CHRL 0x00000006
67 #define UART_MR_CHRL_SH 1
68 #define UART_MR_PAR 0x00000038
69 #define UART_MR_PAR_SH 3
70 #define UART_MR_NBSTOP 0x000000C0
71 #define UART_MR_NBSTOP_SH 6
72 #define UART_MR_CHMODE 0x00000300
73 #define UART_MR_CHMODE_SH 8
74 #define UART_MR_UCLKEN 0x00000400
75 #define UART_MR_IRMODE 0x00000800
77 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
78 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
79 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
80 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
81 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
82 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
83 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
84 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
85 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
86 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
88 #define RX_FIFO_SIZE 16
89 #define TX_FIFO_SIZE 16
90 #define UART_INPUT_CLK 50000000
94 #define R_IER (0x08/4)
95 #define R_IDR (0x0C/4)
96 #define R_IMR (0x10/4)
97 #define R_CISR (0x14/4)
98 #define R_BRGR (0x18/4)
99 #define R_RTOR (0x1C/4)
100 #define R_RTRIG (0x20/4)
101 #define R_MCR (0x24/4)
102 #define R_MSR (0x28/4)
103 #define R_SR (0x2C/4)
104 #define R_TX_RX (0x30/4)
105 #define R_BDIV (0x34/4)
106 #define R_FDEL (0x38/4)
107 #define R_PMIN (0x3C/4)
108 #define R_PWID (0x40/4)
109 #define R_TTRIG (0x44/4)
111 #define R_MAX (R_TTRIG + 1)
113 #define TYPE_CADENCE_UART "cadence_uart"
114 #define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)
118 SysBusDevice parent_obj
;
123 uint8_t rx_fifo
[RX_FIFO_SIZE
];
124 uint8_t tx_fifo
[TX_FIFO_SIZE
];
128 uint64_t char_tx_time
;
129 CharDriverState
*chr
;
131 QEMUTimer
*fifo_trigger_handle
;
134 static void uart_update_status(UartState
*s
)
138 s
->r
[R_SR
] |= s
->rx_count
== RX_FIFO_SIZE
? UART_SR_INTR_RFUL
: 0;
139 s
->r
[R_SR
] |= !s
->rx_count
? UART_SR_INTR_REMPTY
: 0;
140 s
->r
[R_SR
] |= s
->rx_count
>= s
->r
[R_RTRIG
] ? UART_SR_INTR_RTRIG
: 0;
142 s
->r
[R_SR
] |= s
->tx_count
== TX_FIFO_SIZE
? UART_SR_INTR_TFUL
: 0;
143 s
->r
[R_SR
] |= !s
->tx_count
? UART_SR_INTR_TEMPTY
: 0;
144 s
->r
[R_SR
] |= s
->tx_count
>= s
->r
[R_TTRIG
] ? UART_SR_TTRIG
: 0;
146 s
->r
[R_CISR
] |= s
->r
[R_SR
] & UART_SR_TO_CISR_MASK
;
147 s
->r
[R_CISR
] |= s
->r
[R_SR
] & UART_SR_TTRIG
? UART_INTR_TTRIG
: 0;
148 qemu_set_irq(s
->irq
, !!(s
->r
[R_IMR
] & s
->r
[R_CISR
]));
151 static void fifo_trigger_update(void *opaque
)
153 UartState
*s
= (UartState
*)opaque
;
155 s
->r
[R_CISR
] |= UART_INTR_TIMEOUT
;
157 uart_update_status(s
);
160 static void uart_rx_reset(UartState
*s
)
165 qemu_chr_accept_input(s
->chr
);
169 static void uart_tx_reset(UartState
*s
)
174 static void uart_send_breaks(UartState
*s
)
176 int break_enabled
= 1;
179 qemu_chr_fe_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
184 static void uart_parameters_setup(UartState
*s
)
186 QEMUSerialSetParams ssp
;
187 unsigned int baud_rate
, packet_size
;
189 baud_rate
= (s
->r
[R_MR
] & UART_MR_CLKS
) ?
190 UART_INPUT_CLK
/ 8 : UART_INPUT_CLK
;
192 ssp
.speed
= baud_rate
/ (s
->r
[R_BRGR
] * (s
->r
[R_BDIV
] + 1));
195 switch (s
->r
[R_MR
] & UART_MR_PAR
) {
196 case UART_PARITY_EVEN
:
200 case UART_PARITY_ODD
:
209 switch (s
->r
[R_MR
] & UART_MR_CHRL
) {
210 case UART_DATA_BITS_6
:
213 case UART_DATA_BITS_7
:
221 switch (s
->r
[R_MR
] & UART_MR_NBSTOP
) {
222 case UART_STOP_BITS_1
:
230 packet_size
+= ssp
.data_bits
+ ssp
.stop_bits
;
231 s
->char_tx_time
= (get_ticks_per_sec() / ssp
.speed
) * packet_size
;
233 qemu_chr_fe_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
237 static int uart_can_receive(void *opaque
)
239 UartState
*s
= (UartState
*)opaque
;
240 int ret
= MAX(RX_FIFO_SIZE
, TX_FIFO_SIZE
);
241 uint32_t ch_mode
= s
->r
[R_MR
] & UART_MR_CHMODE
;
243 if (ch_mode
== NORMAL_MODE
|| ch_mode
== ECHO_MODE
) {
244 ret
= MIN(ret
, RX_FIFO_SIZE
- s
->rx_count
);
246 if (ch_mode
== REMOTE_LOOPBACK
|| ch_mode
== ECHO_MODE
) {
247 ret
= MIN(ret
, TX_FIFO_SIZE
- s
->tx_count
);
252 static void uart_ctrl_update(UartState
*s
)
254 if (s
->r
[R_CR
] & UART_CR_TXRST
) {
258 if (s
->r
[R_CR
] & UART_CR_RXRST
) {
262 s
->r
[R_CR
] &= ~(UART_CR_TXRST
| UART_CR_RXRST
);
264 if (s
->r
[R_CR
] & UART_CR_STARTBRK
&& !(s
->r
[R_CR
] & UART_CR_STOPBRK
)) {
269 static void uart_write_rx_fifo(void *opaque
, const uint8_t *buf
, int size
)
271 UartState
*s
= (UartState
*)opaque
;
272 uint64_t new_rx_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
275 if ((s
->r
[R_CR
] & UART_CR_RX_DIS
) || !(s
->r
[R_CR
] & UART_CR_RX_EN
)) {
279 if (s
->rx_count
== RX_FIFO_SIZE
) {
280 s
->r
[R_CISR
] |= UART_INTR_ROVR
;
282 for (i
= 0; i
< size
; i
++) {
283 s
->rx_fifo
[s
->rx_wpos
] = buf
[i
];
284 s
->rx_wpos
= (s
->rx_wpos
+ 1) % RX_FIFO_SIZE
;
287 timer_mod(s
->fifo_trigger_handle
, new_rx_time
+
288 (s
->char_tx_time
* 4));
290 uart_update_status(s
);
293 static gboolean
cadence_uart_xmit(GIOChannel
*chan
, GIOCondition cond
,
296 UartState
*s
= opaque
;
299 /* instant drain the fifo when there's no back-end */
309 ret
= qemu_chr_fe_write(s
->chr
, s
->tx_fifo
, s
->tx_count
);
311 memmove(s
->tx_fifo
, s
->tx_fifo
+ ret
, s
->tx_count
);
314 int r
= qemu_chr_fe_add_watch(s
->chr
, G_IO_OUT
|G_IO_HUP
,
315 cadence_uart_xmit
, s
);
319 uart_update_status(s
);
323 static void uart_write_tx_fifo(UartState
*s
, const uint8_t *buf
, int size
)
325 if ((s
->r
[R_CR
] & UART_CR_TX_DIS
) || !(s
->r
[R_CR
] & UART_CR_TX_EN
)) {
329 if (size
> TX_FIFO_SIZE
- s
->tx_count
) {
330 size
= TX_FIFO_SIZE
- s
->tx_count
;
332 * This can only be a guest error via a bad tx fifo register push,
333 * as can_receive() should stop remote loop and echo modes ever getting
336 qemu_log_mask(LOG_GUEST_ERROR
, "cadence_uart: TxFIFO overflow");
337 s
->r
[R_CISR
] |= UART_INTR_ROVR
;
340 memcpy(s
->tx_fifo
+ s
->tx_count
, buf
, size
);
343 cadence_uart_xmit(NULL
, G_IO_OUT
, s
);
346 static void uart_receive(void *opaque
, const uint8_t *buf
, int size
)
348 UartState
*s
= (UartState
*)opaque
;
349 uint32_t ch_mode
= s
->r
[R_MR
] & UART_MR_CHMODE
;
351 if (ch_mode
== NORMAL_MODE
|| ch_mode
== ECHO_MODE
) {
352 uart_write_rx_fifo(opaque
, buf
, size
);
354 if (ch_mode
== REMOTE_LOOPBACK
|| ch_mode
== ECHO_MODE
) {
355 uart_write_tx_fifo(s
, buf
, size
);
359 static void uart_event(void *opaque
, int event
)
361 UartState
*s
= (UartState
*)opaque
;
364 if (event
== CHR_EVENT_BREAK
) {
365 uart_write_rx_fifo(opaque
, &buf
, 1);
368 uart_update_status(s
);
371 static void uart_read_rx_fifo(UartState
*s
, uint32_t *c
)
373 if ((s
->r
[R_CR
] & UART_CR_RX_DIS
) || !(s
->r
[R_CR
] & UART_CR_RX_EN
)) {
379 (RX_FIFO_SIZE
+ s
->rx_wpos
- s
->rx_count
) % RX_FIFO_SIZE
;
380 *c
= s
->rx_fifo
[rx_rpos
];
384 qemu_chr_accept_input(s
->chr
);
390 uart_update_status(s
);
393 static void uart_write(void *opaque
, hwaddr offset
,
394 uint64_t value
, unsigned size
)
396 UartState
*s
= (UartState
*)opaque
;
398 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset
, (unsigned)value
);
401 case R_IER
: /* ier (wts imr) */
402 s
->r
[R_IMR
] |= value
;
404 case R_IDR
: /* idr (wtc imr) */
405 s
->r
[R_IMR
] &= ~value
;
407 case R_IMR
: /* imr (read only) */
409 case R_CISR
: /* cisr (wtc) */
410 s
->r
[R_CISR
] &= ~value
;
412 case R_TX_RX
: /* UARTDR */
413 switch (s
->r
[R_MR
] & UART_MR_CHMODE
) {
415 uart_write_tx_fifo(s
, (uint8_t *) &value
, 1);
418 uart_write_rx_fifo(opaque
, (uint8_t *) &value
, 1);
423 s
->r
[offset
] = value
;
431 uart_parameters_setup(s
);
434 uart_update_status(s
);
437 static uint64_t uart_read(void *opaque
, hwaddr offset
,
440 UartState
*s
= (UartState
*)opaque
;
444 if (offset
>= R_MAX
) {
446 } else if (offset
== R_TX_RX
) {
447 uart_read_rx_fifo(s
, &c
);
452 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset
<< 2), (unsigned)c
);
456 static const MemoryRegionOps uart_ops
= {
459 .endianness
= DEVICE_NATIVE_ENDIAN
,
462 static void cadence_uart_reset(DeviceState
*dev
)
464 UartState
*s
= CADENCE_UART(dev
);
466 s
->r
[R_CR
] = 0x00000128;
469 s
->r
[R_RTRIG
] = 0x00000020;
470 s
->r
[R_BRGR
] = 0x0000000F;
471 s
->r
[R_TTRIG
] = 0x00000020;
476 uart_update_status(s
);
479 static int cadence_uart_init(SysBusDevice
*dev
)
481 UartState
*s
= CADENCE_UART(dev
);
483 memory_region_init_io(&s
->iomem
, OBJECT(s
), &uart_ops
, s
, "uart", 0x1000);
484 sysbus_init_mmio(dev
, &s
->iomem
);
485 sysbus_init_irq(dev
, &s
->irq
);
487 s
->fifo_trigger_handle
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
488 (QEMUTimerCB
*)fifo_trigger_update
, s
);
490 s
->char_tx_time
= (get_ticks_per_sec() / 9600) * 10;
492 s
->chr
= qemu_char_get_next_serial();
495 qemu_chr_add_handlers(s
->chr
, uart_can_receive
, uart_receive
,
502 static int cadence_uart_post_load(void *opaque
, int version_id
)
504 UartState
*s
= opaque
;
506 uart_parameters_setup(s
);
507 uart_update_status(s
);
511 static const VMStateDescription vmstate_cadence_uart
= {
512 .name
= "cadence_uart",
514 .minimum_version_id
= 2,
515 .post_load
= cadence_uart_post_load
,
516 .fields
= (VMStateField
[]) {
517 VMSTATE_UINT32_ARRAY(r
, UartState
, R_MAX
),
518 VMSTATE_UINT8_ARRAY(rx_fifo
, UartState
, RX_FIFO_SIZE
),
519 VMSTATE_UINT8_ARRAY(tx_fifo
, UartState
, RX_FIFO_SIZE
),
520 VMSTATE_UINT32(rx_count
, UartState
),
521 VMSTATE_UINT32(tx_count
, UartState
),
522 VMSTATE_UINT32(rx_wpos
, UartState
),
523 VMSTATE_TIMER_PTR(fifo_trigger_handle
, UartState
),
524 VMSTATE_END_OF_LIST()
528 static void cadence_uart_class_init(ObjectClass
*klass
, void *data
)
530 DeviceClass
*dc
= DEVICE_CLASS(klass
);
531 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
533 sdc
->init
= cadence_uart_init
;
534 dc
->vmsd
= &vmstate_cadence_uart
;
535 dc
->reset
= cadence_uart_reset
;
538 static const TypeInfo cadence_uart_info
= {
539 .name
= TYPE_CADENCE_UART
,
540 .parent
= TYPE_SYS_BUS_DEVICE
,
541 .instance_size
= sizeof(UartState
),
542 .class_init
= cadence_uart_class_init
,
545 static void cadence_uart_register_types(void)
547 type_register_static(&cadence_uart_info
);
550 type_init(cadence_uart_register_types
)