target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13
  14 #ifndef CONFIG_USER_ONLY
  15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
  16                                 int access_type, int is_user,
  17                                 hwaddr *phys_ptr, int *prot,
  18                                 target_ulong *page_size);
  19
  20 /* Definitions for the PMCCNTR and PMCR registers */
  21 #define PMCRD   0x8
  22 #define PMCRC   0x4
  23 #define PMCRE   0x1
  24 #endif
  25
  26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  27 {
  28     int nregs;
  29
  30     /* VFP data registers are always little-endian.  */
  31     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  32     if (reg < nregs) {
  33         stfq_le_p(buf, env->vfp.regs[reg]);
  34         return 8;
  35     }
  36     if (arm_feature(env, ARM_FEATURE_NEON)) {
  37         /* Aliases for Q regs.  */
  38         nregs += 16;
  39         if (reg < nregs) {
  40             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  41             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  42             return 16;
  43         }
  44     }
  45     switch (reg - nregs) {
  46     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  47     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  48     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  49     }
  50     return 0;
  51 }
  52
  53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  54 {
  55     int nregs;
  56
  57     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  58     if (reg < nregs) {
  59         env->vfp.regs[reg] = ldfq_le_p(buf);
  60         return 8;
  61     }
  62     if (arm_feature(env, ARM_FEATURE_NEON)) {
  63         nregs += 16;
  64         if (reg < nregs) {
  65             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  66             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  67             return 16;
  68         }
  69     }
  70     switch (reg - nregs) {
  71     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  72     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  73     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  74     }
  75     return 0;
  76 }
  77
  78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  79 {
  80     switch (reg) {
  81     case 0 ... 31:
  82         /* 128 bit FP register */
  83         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  84         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  85         return 16;
  86     case 32:
  87         /* FPSR */
  88         stl_p(buf, vfp_get_fpsr(env));
  89         return 4;
  90     case 33:
  91         /* FPCR */
  92         stl_p(buf, vfp_get_fpcr(env));
  93         return 4;
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 100 {
 101     switch (reg) {
 102     case 0 ... 31:
 103         /* 128 bit FP register */
 104         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 105         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 106         return 16;
 107     case 32:
 108         /* FPSR */
 109         vfp_set_fpsr(env, ldl_p(buf));
 110         return 4;
 111     case 33:
 112         /* FPCR */
 113         vfp_set_fpcr(env, ldl_p(buf));
 114         return 4;
 115     default:
 116         return 0;
 117     }
 118 }
 119
 120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 121 {
 122     if (cpreg_field_is_64bit(ri)) {
 123         return CPREG_FIELD64(env, ri);
 124     } else {
 125         return CPREG_FIELD32(env, ri);
 126     }
 127 }
 128
 129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 130                       uint64_t value)
 131 {
 132     if (cpreg_field_is_64bit(ri)) {
 133         CPREG_FIELD64(env, ri) = value;
 134     } else {
 135         CPREG_FIELD32(env, ri) = value;
 136     }
 137 }
 138
 139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 140 {
 141     /* Raw read of a coprocessor register (as needed for migration, etc). */
 142     if (ri->type & ARM_CP_CONST) {
 143         return ri->resetvalue;
 144     } else if (ri->raw_readfn) {
 145         return ri->raw_readfn(env, ri);
 146     } else if (ri->readfn) {
 147         return ri->readfn(env, ri);
 148     } else {
 149         return raw_read(env, ri);
 150     }
 151 }
 152
 153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 154                              uint64_t v)
 155 {
 156     /* Raw write of a coprocessor register (as needed for migration, etc).
 157      * Note that constant registers are treated as write-ignored; the
 158      * caller should check for success by whether a readback gives the
 159      * value written.
 160      */
 161     if (ri->type & ARM_CP_CONST) {
 162         return;
 163     } else if (ri->raw_writefn) {
 164         ri->raw_writefn(env, ri, v);
 165     } else if (ri->writefn) {
 166         ri->writefn(env, ri, v);
 167     } else {
 168         raw_write(env, ri, v);
 169     }
 170 }
 171
 172 bool write_cpustate_to_list(ARMCPU *cpu)
 173 {
 174     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 175     int i;
 176     bool ok = true;
 177
 178     for (i = 0; i < cpu->cpreg_array_len; i++) {
 179         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 180         const ARMCPRegInfo *ri;
 181
 182         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 183         if (!ri) {
 184             ok = false;
 185             continue;
 186         }
 187         if (ri->type & ARM_CP_NO_MIGRATE) {
 188             continue;
 189         }
 190         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 191     }
 192     return ok;
 193 }
 194
 195 bool write_list_to_cpustate(ARMCPU *cpu)
 196 {
 197     int i;
 198     bool ok = true;
 199
 200     for (i = 0; i < cpu->cpreg_array_len; i++) {
 201         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 202         uint64_t v = cpu->cpreg_values[i];
 203         const ARMCPRegInfo *ri;
 204
 205         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 206         if (!ri) {
 207             ok = false;
 208             continue;
 209         }
 210         if (ri->type & ARM_CP_NO_MIGRATE) {
 211             continue;
 212         }
 213         /* Write value and confirm it reads back as written
 214          * (to catch read-only registers and partially read-only
 215          * registers where the incoming migration value doesn't match)
 216          */
 217         write_raw_cp_reg(&cpu->env, ri, v);
 218         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 219             ok = false;
 220         }
 221     }
 222     return ok;
 223 }
 224
 225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 226 {
 227     ARMCPU *cpu = opaque;
 228     uint64_t regidx;
 229     const ARMCPRegInfo *ri;
 230
 231     regidx = *(uint32_t *)key;
 232     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 233
 234     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 235         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 236         /* The value array need not be initialized at this point */
 237         cpu->cpreg_array_len++;
 238     }
 239 }
 240
 241 static void count_cpreg(gpointer key, gpointer opaque)
 242 {
 243     ARMCPU *cpu = opaque;
 244     uint64_t regidx;
 245     const ARMCPRegInfo *ri;
 246
 247     regidx = *(uint32_t *)key;
 248     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 249
 250     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 251         cpu->cpreg_array_len++;
 252     }
 253 }
 254
 255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 256 {
 257     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 258     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 259
 260     if (aidx > bidx) {
 261         return 1;
 262     }
 263     if (aidx < bidx) {
 264         return -1;
 265     }
 266     return 0;
 267 }
 268
 269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 270 {
 271     GList **plist = udata;
 272
 273     *plist = g_list_prepend(*plist, key);
 274 }
 275
 276 void init_cpreg_list(ARMCPU *cpu)
 277 {
 278     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 279      * Note that we require cpreg_tuples[] to be sorted by key ID.
 280      */
 281     GList *keys = NULL;
 282     int arraylen;
 283
 284     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 285
 286     keys = g_list_sort(keys, cpreg_key_compare);
 287
 288     cpu->cpreg_array_len = 0;
 289
 290     g_list_foreach(keys, count_cpreg, cpu);
 291
 292     arraylen = cpu->cpreg_array_len;
 293     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 294     cpu->cpreg_values = g_new(uint64_t, arraylen);
 295     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 296     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 297     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 298     cpu->cpreg_array_len = 0;
 299
 300     g_list_foreach(keys, add_cpreg_to_list, cpu);
 301
 302     assert(cpu->cpreg_array_len == arraylen);
 303
 304     g_list_free(keys);
 305 }
 306
 307 /* Return true if extended addresses are enabled.
 308  * This is always the case if our translation regime is 64 bit,
 309  * but depends on TTBCR.EAE for 32 bit.
 310  */
 311 static inline bool extended_addresses_enabled(CPUARMState *env)
 312 {
 313     return arm_el_is_aa64(env, 1)
 314         || ((arm_feature(env, ARM_FEATURE_LPAE)
 315              && (env->cp15.c2_control & TTBCR_EAE)));
 316 }
 317
 318 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 319 {
 320     ARMCPU *cpu = arm_env_get_cpu(env);
 321
 322     raw_write(env, ri, value);
 323     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 324 }
 325
 326 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 327 {
 328     ARMCPU *cpu = arm_env_get_cpu(env);
 329
 330     if (raw_read(env, ri) != value) {
 331         /* Unlike real hardware the qemu TLB uses virtual addresses,
 332          * not modified virtual addresses, so this causes a TLB flush.
 333          */
 334         tlb_flush(CPU(cpu), 1);
 335         raw_write(env, ri, value);
 336     }
 337 }
 338
 339 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 340                              uint64_t value)
 341 {
 342     ARMCPU *cpu = arm_env_get_cpu(env);
 343
 344     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 345         && !extended_addresses_enabled(env)) {
 346         /* For VMSA (when not using the LPAE long descriptor page table
 347          * format) this register includes the ASID, so do a TLB flush.
 348          * For PMSA it is purely a process ID and no action is needed.
 349          */
 350         tlb_flush(CPU(cpu), 1);
 351     }
 352     raw_write(env, ri, value);
 353 }
 354
 355 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 356                           uint64_t value)
 357 {
 358     /* Invalidate all (TLBIALL) */
 359     ARMCPU *cpu = arm_env_get_cpu(env);
 360
 361     tlb_flush(CPU(cpu), 1);
 362 }
 363
 364 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 365                           uint64_t value)
 366 {
 367     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 368     ARMCPU *cpu = arm_env_get_cpu(env);
 369
 370     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 371 }
 372
 373 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 374                            uint64_t value)
 375 {
 376     /* Invalidate by ASID (TLBIASID) */
 377     ARMCPU *cpu = arm_env_get_cpu(env);
 378
 379     tlb_flush(CPU(cpu), value == 0);
 380 }
 381
 382 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 383                            uint64_t value)
 384 {
 385     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 386     ARMCPU *cpu = arm_env_get_cpu(env);
 387
 388     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 389 }
 390
 391 static const ARMCPRegInfo cp_reginfo[] = {
 392     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
 393       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 394       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 395     { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
 396       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 397       .access = PL1_RW,
 398       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
 399       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 400     REGINFO_SENTINEL
 401 };
 402
 403 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 404     /* NB: Some of these registers exist in v8 but with more precise
 405      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 406      */
 407     /* MMU Domain access control / MPU write buffer control */
 408     { .name = "DACR", .cp = 15,
 409       .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 410       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
 411       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
 412     /* ??? This covers not just the impdef TLB lockdown registers but also
 413      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 414      */
 415     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 416       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 417     /* MMU TLB control. Note that the wildcarding means we cover not just
 418      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 419      */
 420     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 421       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 422       .type = ARM_CP_NO_MIGRATE },
 423     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 424       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 425       .type = ARM_CP_NO_MIGRATE },
 426     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 427       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 428       .type = ARM_CP_NO_MIGRATE },
 429     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 430       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 431       .type = ARM_CP_NO_MIGRATE },
 432     /* Cache maintenance ops; some of this space may be overridden later. */
 433     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 434       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 435       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 436     REGINFO_SENTINEL
 437 };
 438
 439 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 440     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 441      * over-broad.
 442      */
 443     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 444       .access = PL1_W, .type = ARM_CP_WFI },
 445     REGINFO_SENTINEL
 446 };
 447
 448 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 449     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 450      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 451      */
 452     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 453       .access = PL1_W, .type = ARM_CP_WFI },
 454     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 455      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 456      * OMAPCP will override this space.
 457      */
 458     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 459       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 460       .resetvalue = 0 },
 461     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 462       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 463       .resetvalue = 0 },
 464     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 465     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 466       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
 467       .resetvalue = 0 },
 468     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 469      * implementing it as RAZ means the "debug architecture version" bits
 470      * will read as a reserved value, which should cause Linux to not try
 471      * to use the debug hardware.
 472      */
 473     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 474       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 475     REGINFO_SENTINEL
 476 };
 477
 478 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 479                         uint64_t value)
 480 {
 481     uint32_t mask = 0;
 482
 483     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 484     if (!arm_feature(env, ARM_FEATURE_V8)) {
 485         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 486          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 487          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 488          */
 489         if (arm_feature(env, ARM_FEATURE_VFP)) {
 490             /* VFP coprocessor: cp10 & cp11 [23:20] */
 491             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 492
 493             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 494                 /* ASEDIS [31] bit is RAO/WI */
 495                 value |= (1 << 31);
 496             }
 497
 498             /* VFPv3 and upwards with NEON implement 32 double precision
 499              * registers (D0-D31).
 500              */
 501             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 502                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 503                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 504                 value |= (1 << 30);
 505             }
 506         }
 507         value &= mask;
 508     }
 509     env->cp15.c1_coproc = value;
 510 }
 511
 512 static const ARMCPRegInfo v6_cp_reginfo[] = {
 513     /* prefetch by MVA in v6, NOP in v7 */
 514     { .name = "MVA_prefetch",
 515       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 516       .access = PL1_W, .type = ARM_CP_NOP },
 517     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 518       .access = PL0_W, .type = ARM_CP_NOP },
 519     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 520       .access = PL0_W, .type = ARM_CP_NOP },
 521     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 522       .access = PL0_W, .type = ARM_CP_NOP },
 523     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 524       .access = PL1_RW,
 525       .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 526       .resetvalue = 0, },
 527     /* Watchpoint Fault Address Register : should actually only be present
 528      * for 1136, 1176, 11MPCore.
 529      */
 530     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 531       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 532     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 533       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 534       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 535       .resetvalue = 0, .writefn = cpacr_write },
 536     REGINFO_SENTINEL
 537 };
 538
 539 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 540 {
 541     /* Performance monitor registers user accessibility is controlled
 542      * by PMUSERENR.
 543      */
 544     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 545         return CP_ACCESS_TRAP;
 546     }
 547     return CP_ACCESS_OK;
 548 }
 549
 550 #ifndef CONFIG_USER_ONLY
 551
 552 static inline bool arm_ccnt_enabled(CPUARMState *env)
 553 {
 554     /* This does not support checking PMCCFILTR_EL0 register */
 555
 556     if (!(env->cp15.c9_pmcr & PMCRE)) {
 557         return false;
 558     }
 559
 560     return true;
 561 }
 562
 563 void pmccntr_sync(CPUARMState *env)
 564 {
 565     uint64_t temp_ticks;
 566
 567     temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 568                           get_ticks_per_sec(), 1000000);
 569
 570     if (env->cp15.c9_pmcr & PMCRD) {
 571         /* Increment once every 64 processor clock cycles */
 572         temp_ticks /= 64;
 573     }
 574
 575     if (arm_ccnt_enabled(env)) {
 576         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 577     }
 578 }
 579
 580 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 581                        uint64_t value)
 582 {
 583     uint64_t temp_ticks;
 584
 585     temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 586                           get_ticks_per_sec(), 1000000);
 587
 588     if (env->cp15.c9_pmcr & PMCRE) {
 589         /* If the counter is enabled */
 590         if (env->cp15.c9_pmcr & PMCRD) {
 591             /* Increment once every 64 processor clock cycles */
 592             env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
 593         } else {
 594             env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 595         }
 596     }
 597
 598     if (value & PMCRC) {
 599         /* The counter has been reset */
 600         env->cp15.c15_ccnt = 0;
 601     }
 602
 603     /* only the DP, X, D and E bits are writable */
 604     env->cp15.c9_pmcr &= ~0x39;
 605     env->cp15.c9_pmcr |= (value & 0x39);
 606
 607     if (env->cp15.c9_pmcr & PMCRE) {
 608         if (env->cp15.c9_pmcr & PMCRD) {
 609             /* Increment once every 64 processor clock cycles */
 610             temp_ticks /= 64;
 611         }
 612         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 613     }
 614 }
 615
 616 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 617 {
 618     uint64_t total_ticks;
 619
 620     if (!(env->cp15.c9_pmcr & PMCRE)) {
 621         /* Counter is disabled, do not change value */
 622         return env->cp15.c15_ccnt;
 623     }
 624
 625     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 626                            get_ticks_per_sec(), 1000000);
 627
 628     if (env->cp15.c9_pmcr & PMCRD) {
 629         /* Increment once every 64 processor clock cycles */
 630         total_ticks /= 64;
 631     }
 632     return total_ticks - env->cp15.c15_ccnt;
 633 }
 634
 635 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 636                         uint64_t value)
 637 {
 638     uint64_t total_ticks;
 639
 640     if (!(env->cp15.c9_pmcr & PMCRE)) {
 641         /* Counter is disabled, set the absolute value */
 642         env->cp15.c15_ccnt = value;
 643         return;
 644     }
 645
 646     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 647                            get_ticks_per_sec(), 1000000);
 648
 649     if (env->cp15.c9_pmcr & PMCRD) {
 650         /* Increment once every 64 processor clock cycles */
 651         total_ticks /= 64;
 652     }
 653     env->cp15.c15_ccnt = total_ticks - value;
 654 }
 655
 656 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 657                             uint64_t value)
 658 {
 659     uint64_t cur_val = pmccntr_read(env, NULL);
 660
 661     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 662 }
 663
 664 #else /* CONFIG_USER_ONLY */
 665
 666 void pmccntr_sync(CPUARMState *env)
 667 {
 668 }
 669
 670 #endif
 671
 672 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 673                             uint64_t value)
 674 {
 675     value &= (1 << 31);
 676     env->cp15.c9_pmcnten |= value;
 677 }
 678
 679 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 680                              uint64_t value)
 681 {
 682     value &= (1 << 31);
 683     env->cp15.c9_pmcnten &= ~value;
 684 }
 685
 686 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 687                          uint64_t value)
 688 {
 689     env->cp15.c9_pmovsr &= ~value;
 690 }
 691
 692 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 693                              uint64_t value)
 694 {
 695     env->cp15.c9_pmxevtyper = value & 0xff;
 696 }
 697
 698 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 699                             uint64_t value)
 700 {
 701     env->cp15.c9_pmuserenr = value & 1;
 702 }
 703
 704 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 705                              uint64_t value)
 706 {
 707     /* We have no event counters so only the C bit can be changed */
 708     value &= (1 << 31);
 709     env->cp15.c9_pminten |= value;
 710 }
 711
 712 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 713                              uint64_t value)
 714 {
 715     value &= (1 << 31);
 716     env->cp15.c9_pminten &= ~value;
 717 }
 718
 719 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 720                        uint64_t value)
 721 {
 722     /* Note that even though the AArch64 view of this register has bits
 723      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 724      * architectural requirements for bits which are RES0 only in some
 725      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 726      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 727      */
 728     raw_write(env, ri, value & ~0x1FULL);
 729 }
 730
 731 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 732 {
 733     ARMCPU *cpu = arm_env_get_cpu(env);
 734     return cpu->ccsidr[env->cp15.c0_cssel];
 735 }
 736
 737 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 738                          uint64_t value)
 739 {
 740     raw_write(env, ri, value & 0xf);
 741 }
 742
 743 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 744 {
 745     CPUState *cs = ENV_GET_CPU(env);
 746     uint64_t ret = 0;
 747
 748     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 749         ret |= CPSR_I;
 750     }
 751     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 752         ret |= CPSR_F;
 753     }
 754     /* External aborts are not possible in QEMU so A bit is always clear */
 755     return ret;
 756 }
 757
 758 static const ARMCPRegInfo v7_cp_reginfo[] = {
 759     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 760     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 761       .access = PL1_W, .type = ARM_CP_NOP },
 762     /* Performance monitors are implementation defined in v7,
 763      * but with an ARM recommended set of registers, which we
 764      * follow (although we don't actually implement any counters)
 765      *
 766      * Performance registers fall into three categories:
 767      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 768      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 769      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 770      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 771      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 772      */
 773     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 774       .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
 775       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 776       .writefn = pmcntenset_write,
 777       .accessfn = pmreg_access,
 778       .raw_writefn = raw_write },
 779     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 780       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 781       .access = PL0_RW, .accessfn = pmreg_access,
 782       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 783       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 784     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 785       .access = PL0_RW,
 786       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 787       .accessfn = pmreg_access,
 788       .writefn = pmcntenclr_write,
 789       .type = ARM_CP_NO_MIGRATE },
 790     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 791       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 792       .access = PL0_RW, .accessfn = pmreg_access,
 793       .type = ARM_CP_NO_MIGRATE,
 794       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 795       .writefn = pmcntenclr_write },
 796     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 797       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 798       .accessfn = pmreg_access,
 799       .writefn = pmovsr_write,
 800       .raw_writefn = raw_write },
 801     /* Unimplemented so WI. */
 802     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 803       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 804     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 805      * We choose to RAZ/WI.
 806      */
 807     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 808       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 809       .accessfn = pmreg_access },
 810 #ifndef CONFIG_USER_ONLY
 811     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 812       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 813       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 814       .accessfn = pmreg_access },
 815     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 816       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 817       .access = PL0_RW, .accessfn = pmreg_access,
 818       .type = ARM_CP_IO,
 819       .readfn = pmccntr_read, .writefn = pmccntr_write, },
 820 #endif
 821     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
 822       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
 823       .access = PL0_RW, .accessfn = pmreg_access,
 824       .type = ARM_CP_IO,
 825       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
 826       .resetvalue = 0, },
 827     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 828       .access = PL0_RW,
 829       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 830       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 831       .raw_writefn = raw_write },
 832     /* Unimplemented, RAZ/WI. */
 833     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 834       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 835       .accessfn = pmreg_access },
 836     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 837       .access = PL0_R | PL1_RW,
 838       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 839       .resetvalue = 0,
 840       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 841     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 842       .access = PL1_RW,
 843       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 844       .resetvalue = 0,
 845       .writefn = pmintenset_write, .raw_writefn = raw_write },
 846     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 847       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
 848       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 849       .resetvalue = 0, .writefn = pmintenclr_write, },
 850     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 851       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 852       .access = PL1_RW, .writefn = vbar_write,
 853       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
 854       .resetvalue = 0 },
 855     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 856       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
 857       .resetvalue = 0, },
 858     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 859       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 860       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
 861     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 862       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 863       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
 864       .writefn = csselr_write, .resetvalue = 0 },
 865     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 866      * just RAZ for all cores:
 867      */
 868     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
 869       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
 870       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 871     /* Auxiliary fault status registers: these also are IMPDEF, and we
 872      * choose to RAZ/WI for all cores.
 873      */
 874     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
 875       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
 876       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 877     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
 878       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
 879       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 880     /* MAIR can just read-as-written because we don't implement caches
 881      * and so don't need to care about memory attributes.
 882      */
 883     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
 884       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
 885       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
 886       .resetvalue = 0 },
 887     /* For non-long-descriptor page tables these are PRRR and NMRR;
 888      * regardless they still act as reads-as-written for QEMU.
 889      * The override is necessary because of the overly-broad TLB_LOCKDOWN
 890      * definition.
 891      */
 892     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 893       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
 894       .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
 895       .resetfn = arm_cp_reset_ignore },
 896     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 897       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
 898       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
 899       .resetfn = arm_cp_reset_ignore },
 900     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
 901       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
 902       .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
 903     REGINFO_SENTINEL
 904 };
 905
 906 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 907                         uint64_t value)
 908 {
 909     value &= 1;
 910     env->teecr = value;
 911 }
 912
 913 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 914 {
 915     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
 916         return CP_ACCESS_TRAP;
 917     }
 918     return CP_ACCESS_OK;
 919 }
 920
 921 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
 922     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
 923       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
 924       .resetvalue = 0,
 925       .writefn = teecr_write },
 926     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
 927       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
 928       .accessfn = teehbr_access, .resetvalue = 0 },
 929     REGINFO_SENTINEL
 930 };
 931
 932 static const ARMCPRegInfo v6k_cp_reginfo[] = {
 933     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
 934       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
 935       .access = PL0_RW,
 936       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
 937     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
 938       .access = PL0_RW,
 939       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
 940       .resetfn = arm_cp_reset_ignore },
 941     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
 942       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
 943       .access = PL0_R|PL1_W,
 944       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
 945     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
 946       .access = PL0_R|PL1_W,
 947       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
 948       .resetfn = arm_cp_reset_ignore },
 949     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
 950       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
 951       .access = PL1_RW,
 952       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
 953     REGINFO_SENTINEL
 954 };
 955
 956 #ifndef CONFIG_USER_ONLY
 957
 958 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
 959 {
 960     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
 961     if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
 962         return CP_ACCESS_TRAP;
 963     }
 964     return CP_ACCESS_OK;
 965 }
 966
 967 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
 968 {
 969     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
 970     if (arm_current_pl(env) == 0 &&
 971         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
 972         return CP_ACCESS_TRAP;
 973     }
 974     return CP_ACCESS_OK;
 975 }
 976
 977 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
 978 {
 979     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
 980      * EL0[PV]TEN is zero.
 981      */
 982     if (arm_current_pl(env) == 0 &&
 983         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
 984         return CP_ACCESS_TRAP;
 985     }
 986     return CP_ACCESS_OK;
 987 }
 988
 989 static CPAccessResult gt_pct_access(CPUARMState *env,
 990                                          const ARMCPRegInfo *ri)
 991 {
 992     return gt_counter_access(env, GTIMER_PHYS);
 993 }
 994
 995 static CPAccessResult gt_vct_access(CPUARMState *env,
 996                                          const ARMCPRegInfo *ri)
 997 {
 998     return gt_counter_access(env, GTIMER_VIRT);
 999 }
1000
1001 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1002 {
1003     return gt_timer_access(env, GTIMER_PHYS);
1004 }
1005
1006 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1007 {
1008     return gt_timer_access(env, GTIMER_VIRT);
1009 }
1010
1011 static uint64_t gt_get_countervalue(CPUARMState *env)
1012 {
1013     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1014 }
1015
1016 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1017 {
1018     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1019
1020     if (gt->ctl & 1) {
1021         /* Timer enabled: calculate and set current ISTATUS, irq, and
1022          * reset timer to when ISTATUS next has to change
1023          */
1024         uint64_t count = gt_get_countervalue(&cpu->env);
1025         /* Note that this must be unsigned 64 bit arithmetic: */
1026         int istatus = count >= gt->cval;
1027         uint64_t nexttick;
1028
1029         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1030         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1031                      (istatus && !(gt->ctl & 2)));
1032         if (istatus) {
1033             /* Next transition is when count rolls back over to zero */
1034             nexttick = UINT64_MAX;
1035         } else {
1036             /* Next transition is when we hit cval */
1037             nexttick = gt->cval;
1038         }
1039         /* Note that the desired next expiry time might be beyond the
1040          * signed-64-bit range of a QEMUTimer -- in this case we just
1041          * set the timer for as far in the future as possible. When the
1042          * timer expires we will reset the timer for any remaining period.
1043          */
1044         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1045             nexttick = INT64_MAX / GTIMER_SCALE;
1046         }
1047         timer_mod(cpu->gt_timer[timeridx], nexttick);
1048     } else {
1049         /* Timer disabled: ISTATUS and timer output always clear */
1050         gt->ctl &= ~4;
1051         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1052         timer_del(cpu->gt_timer[timeridx]);
1053     }
1054 }
1055
1056 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1057 {
1058     ARMCPU *cpu = arm_env_get_cpu(env);
1059     int timeridx = ri->opc1 & 1;
1060
1061     timer_del(cpu->gt_timer[timeridx]);
1062 }
1063
1064 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1065 {
1066     return gt_get_countervalue(env);
1067 }
1068
1069 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1070                           uint64_t value)
1071 {
1072     int timeridx = ri->opc1 & 1;
1073
1074     env->cp15.c14_timer[timeridx].cval = value;
1075     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1076 }
1077
1078 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1079 {
1080     int timeridx = ri->crm & 1;
1081
1082     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1083                       gt_get_countervalue(env));
1084 }
1085
1086 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1087                           uint64_t value)
1088 {
1089     int timeridx = ri->crm & 1;
1090
1091     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1092         + sextract64(value, 0, 32);
1093     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1094 }
1095
1096 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1097                          uint64_t value)
1098 {
1099     ARMCPU *cpu = arm_env_get_cpu(env);
1100     int timeridx = ri->crm & 1;
1101     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1102
1103     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1104     if ((oldval ^ value) & 1) {
1105         /* Enable toggled */
1106         gt_recalc_timer(cpu, timeridx);
1107     } else if ((oldval ^ value) & 2) {
1108         /* IMASK toggled: don't need to recalculate,
1109          * just set the interrupt line based on ISTATUS
1110          */
1111         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1112                      (oldval & 4) && !(value & 2));
1113     }
1114 }
1115
1116 void arm_gt_ptimer_cb(void *opaque)
1117 {
1118     ARMCPU *cpu = opaque;
1119
1120     gt_recalc_timer(cpu, GTIMER_PHYS);
1121 }
1122
1123 void arm_gt_vtimer_cb(void *opaque)
1124 {
1125     ARMCPU *cpu = opaque;
1126
1127     gt_recalc_timer(cpu, GTIMER_VIRT);
1128 }
1129
1130 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1131     /* Note that CNTFRQ is purely reads-as-written for the benefit
1132      * of software; writing it doesn't actually change the timer frequency.
1133      * Our reset value matches the fixed frequency we implement the timer at.
1134      */
1135     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1136       .type = ARM_CP_NO_MIGRATE,
1137       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1138       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1139       .resetfn = arm_cp_reset_ignore,
1140     },
1141     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1142       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1143       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1144       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1145       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1146     },
1147     /* overall control: mostly access permissions */
1148     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1149       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1150       .access = PL1_RW,
1151       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1152       .resetvalue = 0,
1153     },
1154     /* per-timer control */
1155     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1156       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1157       .accessfn = gt_ptimer_access,
1158       .fieldoffset = offsetoflow32(CPUARMState,
1159                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1160       .resetfn = arm_cp_reset_ignore,
1161       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1162     },
1163     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1164       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1165       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1166       .accessfn = gt_ptimer_access,
1167       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1168       .resetvalue = 0,
1169       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1170     },
1171     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1172       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1173       .accessfn = gt_vtimer_access,
1174       .fieldoffset = offsetoflow32(CPUARMState,
1175                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1176       .resetfn = arm_cp_reset_ignore,
1177       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1178     },
1179     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1180       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1181       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1182       .accessfn = gt_vtimer_access,
1183       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1184       .resetvalue = 0,
1185       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1186     },
1187     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1188     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1189       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1190       .accessfn = gt_ptimer_access,
1191       .readfn = gt_tval_read, .writefn = gt_tval_write,
1192     },
1193     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1194       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1195       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1196       .readfn = gt_tval_read, .writefn = gt_tval_write,
1197     },
1198     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1199       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1200       .accessfn = gt_vtimer_access,
1201       .readfn = gt_tval_read, .writefn = gt_tval_write,
1202     },
1203     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1204       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1205       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1206       .readfn = gt_tval_read, .writefn = gt_tval_write,
1207     },
1208     /* The counter itself */
1209     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1210       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1211       .accessfn = gt_pct_access,
1212       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1213     },
1214     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1215       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1216       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1217       .accessfn = gt_pct_access,
1218       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1219     },
1220     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1221       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1222       .accessfn = gt_vct_access,
1223       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1224     },
1225     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1226       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1227       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1228       .accessfn = gt_vct_access,
1229       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1230     },
1231     /* Comparison value, indicating when the timer goes off */
1232     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1233       .access = PL1_RW | PL0_R,
1234       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1235       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1236       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1237       .writefn = gt_cval_write, .raw_writefn = raw_write,
1238     },
1239     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1240       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1241       .access = PL1_RW | PL0_R,
1242       .type = ARM_CP_IO,
1243       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1244       .resetvalue = 0, .accessfn = gt_vtimer_access,
1245       .writefn = gt_cval_write, .raw_writefn = raw_write,
1246     },
1247     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1248       .access = PL1_RW | PL0_R,
1249       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1250       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1251       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1252       .writefn = gt_cval_write, .raw_writefn = raw_write,
1253     },
1254     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1255       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1256       .access = PL1_RW | PL0_R,
1257       .type = ARM_CP_IO,
1258       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1259       .resetvalue = 0, .accessfn = gt_vtimer_access,
1260       .writefn = gt_cval_write, .raw_writefn = raw_write,
1261     },
1262     REGINFO_SENTINEL
1263 };
1264
1265 #else
1266 /* In user-mode none of the generic timer registers are accessible,
1267  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1268  * so instead just don't register any of them.
1269  */
1270 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1271     REGINFO_SENTINEL
1272 };
1273
1274 #endif
1275
1276 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1277 {
1278     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1279         raw_write(env, ri, value);
1280     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1281         raw_write(env, ri, value & 0xfffff6ff);
1282     } else {
1283         raw_write(env, ri, value & 0xfffff1ff);
1284     }
1285 }
1286
1287 #ifndef CONFIG_USER_ONLY
1288 /* get_phys_addr() isn't present for user-mode-only targets */
1289
1290 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1291 {
1292     if (ri->opc2 & 4) {
1293         /* Other states are only available with TrustZone; in
1294          * a non-TZ implementation these registers don't exist
1295          * at all, which is an Uncategorized trap. This underdecoding
1296          * is safe because the reginfo is NO_MIGRATE.
1297          */
1298         return CP_ACCESS_TRAP_UNCATEGORIZED;
1299     }
1300     return CP_ACCESS_OK;
1301 }
1302
1303 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1304 {
1305     hwaddr phys_addr;
1306     target_ulong page_size;
1307     int prot;
1308     int ret, is_user = ri->opc2 & 2;
1309     int access_type = ri->opc2 & 1;
1310
1311     ret = get_phys_addr(env, value, access_type, is_user,
1312                         &phys_addr, &prot, &page_size);
1313     if (extended_addresses_enabled(env)) {
1314         /* ret is a DFSR/IFSR value for the long descriptor
1315          * translation table format, but with WnR always clear.
1316          * Convert it to a 64-bit PAR.
1317          */
1318         uint64_t par64 = (1 << 11); /* LPAE bit always set */
1319         if (ret == 0) {
1320             par64 |= phys_addr & ~0xfffULL;
1321             /* We don't set the ATTR or SH fields in the PAR. */
1322         } else {
1323             par64 |= 1; /* F */
1324             par64 |= (ret & 0x3f) << 1; /* FS */
1325             /* Note that S2WLK and FSTAGE are always zero, because we don't
1326              * implement virtualization and therefore there can't be a stage 2
1327              * fault.
1328              */
1329         }
1330         env->cp15.par_el1 = par64;
1331     } else {
1332         /* ret is a DFSR/IFSR value for the short descriptor
1333          * translation table format (with WnR always clear).
1334          * Convert it to a 32-bit PAR.
1335          */
1336         if (ret == 0) {
1337             /* We do not set any attribute bits in the PAR */
1338             if (page_size == (1 << 24)
1339                 && arm_feature(env, ARM_FEATURE_V7)) {
1340                 env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
1341             } else {
1342                 env->cp15.par_el1 = phys_addr & 0xfffff000;
1343             }
1344         } else {
1345             env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
1346                 ((ret & (1 << 12)) >> 6) |
1347                 ((ret & 0xf) << 1) | 1;
1348         }
1349     }
1350 }
1351 #endif
1352
1353 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1354     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1355       .access = PL1_RW, .resetvalue = 0,
1356       .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
1357       .writefn = par_write },
1358 #ifndef CONFIG_USER_ONLY
1359     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1360       .access = PL1_W, .accessfn = ats_access,
1361       .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1362 #endif
1363     REGINFO_SENTINEL
1364 };
1365
1366 /* Return basic MPU access permission bits.  */
1367 static uint32_t simple_mpu_ap_bits(uint32_t val)
1368 {
1369     uint32_t ret;
1370     uint32_t mask;
1371     int i;
1372     ret = 0;
1373     mask = 3;
1374     for (i = 0; i < 16; i += 2) {
1375         ret |= (val >> i) & mask;
1376         mask <<= 2;
1377     }
1378     return ret;
1379 }
1380
1381 /* Pad basic MPU access permission bits to extended format.  */
1382 static uint32_t extended_mpu_ap_bits(uint32_t val)
1383 {
1384     uint32_t ret;
1385     uint32_t mask;
1386     int i;
1387     ret = 0;
1388     mask = 3;
1389     for (i = 0; i < 16; i += 2) {
1390         ret |= (val & mask) << i;
1391         mask <<= 2;
1392     }
1393     return ret;
1394 }
1395
1396 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1397                                  uint64_t value)
1398 {
1399     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1400 }
1401
1402 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1403 {
1404     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1405 }
1406
1407 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1408                                  uint64_t value)
1409 {
1410     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1411 }
1412
1413 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1414 {
1415     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1416 }
1417
1418 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1419     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1420       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1421       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1422       .resetvalue = 0,
1423       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1424     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1425       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1426       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1427       .resetvalue = 0,
1428       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1429     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1430       .access = PL1_RW,
1431       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1432       .resetvalue = 0, },
1433     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1434       .access = PL1_RW,
1435       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1436       .resetvalue = 0, },
1437     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1438       .access = PL1_RW,
1439       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1440     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1441       .access = PL1_RW,
1442       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1443     /* Protection region base and size registers */
1444     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1445       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1446       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1447     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1448       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1449       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1450     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1451       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1452       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1453     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1454       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1455       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1456     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1457       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1458       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1459     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1460       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1461       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1462     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1463       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1464       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1465     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1466       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1467       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1468     REGINFO_SENTINEL
1469 };
1470
1471 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1472                                  uint64_t value)
1473 {
1474     int maskshift = extract32(value, 0, 3);
1475
1476     if (!arm_feature(env, ARM_FEATURE_V8)) {
1477         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1478             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1479              * using Long-desciptor translation table format */
1480             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1481         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1482             /* In an implementation that includes the Security Extensions
1483              * TTBCR has additional fields PD0 [4] and PD1 [5] for
1484              * Short-descriptor translation table format.
1485              */
1486             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1487         } else {
1488             value &= TTBCR_N;
1489         }
1490     }
1491
1492     /* Note that we always calculate c2_mask and c2_base_mask, but
1493      * they are only used for short-descriptor tables (ie if EAE is 0);
1494      * for long-descriptor tables the TTBCR fields are used differently
1495      * and the c2_mask and c2_base_mask values are meaningless.
1496      */
1497     raw_write(env, ri, value);
1498     env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1499     env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1500 }
1501
1502 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1503                              uint64_t value)
1504 {
1505     ARMCPU *cpu = arm_env_get_cpu(env);
1506
1507     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1508         /* With LPAE the TTBCR could result in a change of ASID
1509          * via the TTBCR.A1 bit, so do a TLB flush.
1510          */
1511         tlb_flush(CPU(cpu), 1);
1512     }
1513     vmsa_ttbcr_raw_write(env, ri, value);
1514 }
1515
1516 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1517 {
1518     env->cp15.c2_base_mask = 0xffffc000u;
1519     raw_write(env, ri, 0);
1520     env->cp15.c2_mask = 0;
1521 }
1522
1523 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1524                                uint64_t value)
1525 {
1526     ARMCPU *cpu = arm_env_get_cpu(env);
1527
1528     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1529     tlb_flush(CPU(cpu), 1);
1530     raw_write(env, ri, value);
1531 }
1532
1533 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1534                             uint64_t value)
1535 {
1536     /* 64 bit accesses to the TTBRs can change the ASID and so we
1537      * must flush the TLB.
1538      */
1539     if (cpreg_field_is_64bit(ri)) {
1540         ARMCPU *cpu = arm_env_get_cpu(env);
1541
1542         tlb_flush(CPU(cpu), 1);
1543     }
1544     raw_write(env, ri, value);
1545 }
1546
1547 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1548     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1549       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1550       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1551       .resetfn = arm_cp_reset_ignore, },
1552     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1553       .access = PL1_RW,
1554       .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1555     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1556       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1557       .access = PL1_RW,
1558       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1559     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1560       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1561       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1562       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1563     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1564       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1565       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1566       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1567     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1568       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1569       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1570       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1571       .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1572     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1573       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1574       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1575       .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1576     /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1577     { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1578       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1579       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1580       .resetvalue = 0, },
1581     REGINFO_SENTINEL
1582 };
1583
1584 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1585                                 uint64_t value)
1586 {
1587     env->cp15.c15_ticonfig = value & 0xe7;
1588     /* The OS_TYPE bit in this register changes the reported CPUID! */
1589     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1590         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1591 }
1592
1593 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1594                                 uint64_t value)
1595 {
1596     env->cp15.c15_threadid = value & 0xffff;
1597 }
1598
1599 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1600                            uint64_t value)
1601 {
1602     /* Wait-for-interrupt (deprecated) */
1603     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1604 }
1605
1606 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1607                                   uint64_t value)
1608 {
1609     /* On OMAP there are registers indicating the max/min index of dcache lines
1610      * containing a dirty line; cache flush operations have to reset these.
1611      */
1612     env->cp15.c15_i_max = 0x000;
1613     env->cp15.c15_i_min = 0xff0;
1614 }
1615
1616 static const ARMCPRegInfo omap_cp_reginfo[] = {
1617     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1618       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1619       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1620       .resetvalue = 0, },
1621     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1622       .access = PL1_RW, .type = ARM_CP_NOP },
1623     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1624       .access = PL1_RW,
1625       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1626       .writefn = omap_ticonfig_write },
1627     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1628       .access = PL1_RW,
1629       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1630     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1631       .access = PL1_RW, .resetvalue = 0xff0,
1632       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1633     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1634       .access = PL1_RW,
1635       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1636       .writefn = omap_threadid_write },
1637     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1638       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1639       .type = ARM_CP_NO_MIGRATE,
1640       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1641     /* TODO: Peripheral port remap register:
1642      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1643      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1644      * when MMU is off.
1645      */
1646     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1647       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1648       .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1649       .writefn = omap_cachemaint_write },
1650     { .name = "C9", .cp = 15, .crn = 9,
1651       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1652       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1653     REGINFO_SENTINEL
1654 };
1655
1656 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1657                               uint64_t value)
1658 {
1659     value &= 0x3fff;
1660     if (env->cp15.c15_cpar != value) {
1661         /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
1662         tb_flush(env);
1663         env->cp15.c15_cpar = value;
1664     }
1665 }
1666
1667 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1668     { .name = "XSCALE_CPAR",
1669       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1670       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1671       .writefn = xscale_cpar_write, },
1672     { .name = "XSCALE_AUXCR",
1673       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1674       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1675       .resetvalue = 0, },
1676     /* XScale specific cache-lockdown: since we have no cache we NOP these
1677      * and hope the guest does not really rely on cache behaviour.
1678      */
1679     { .name = "XSCALE_LOCK_ICACHE_LINE",
1680       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1681       .access = PL1_W, .type = ARM_CP_NOP },
1682     { .name = "XSCALE_UNLOCK_ICACHE",
1683       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1684       .access = PL1_W, .type = ARM_CP_NOP },
1685     { .name = "XSCALE_DCACHE_LOCK",
1686       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1687       .access = PL1_RW, .type = ARM_CP_NOP },
1688     { .name = "XSCALE_UNLOCK_DCACHE",
1689       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1690       .access = PL1_W, .type = ARM_CP_NOP },
1691     REGINFO_SENTINEL
1692 };
1693
1694 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1695     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1696      * implementation of this implementation-defined space.
1697      * Ideally this should eventually disappear in favour of actually
1698      * implementing the correct behaviour for all cores.
1699      */
1700     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1701       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1702       .access = PL1_RW,
1703       .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1704       .resetvalue = 0 },
1705     REGINFO_SENTINEL
1706 };
1707
1708 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1709     /* Cache status: RAZ because we have no cache so it's always clean */
1710     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1711       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1712       .resetvalue = 0 },
1713     REGINFO_SENTINEL
1714 };
1715
1716 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1717     /* We never have a a block transfer operation in progress */
1718     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1719       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1720       .resetvalue = 0 },
1721     /* The cache ops themselves: these all NOP for QEMU */
1722     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1723       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1724     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1725       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1726     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1727       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1728     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1729       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1730     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1731       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1732     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1733       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1734     REGINFO_SENTINEL
1735 };
1736
1737 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1738     /* The cache test-and-clean instructions always return (1 << 30)
1739      * to indicate that there are no dirty cache lines.
1740      */
1741     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1742       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1743       .resetvalue = (1 << 30) },
1744     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1745       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1746       .resetvalue = (1 << 30) },
1747     REGINFO_SENTINEL
1748 };
1749
1750 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1751     /* Ignore ReadBuffer accesses */
1752     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1753       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1754       .access = PL1_RW, .resetvalue = 0,
1755       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1756     REGINFO_SENTINEL
1757 };
1758
1759 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1760 {
1761     CPUState *cs = CPU(arm_env_get_cpu(env));
1762     uint32_t mpidr = cs->cpu_index;
1763     /* We don't support setting cluster ID ([8..11]) (known as Aff1
1764      * in later ARM ARM versions), or any of the higher affinity level fields,
1765      * so these bits always RAZ.
1766      */
1767     if (arm_feature(env, ARM_FEATURE_V7MP)) {
1768         mpidr |= (1U << 31);
1769         /* Cores which are uniprocessor (non-coherent)
1770          * but still implement the MP extensions set
1771          * bit 30. (For instance, A9UP.) However we do
1772          * not currently model any of those cores.
1773          */
1774     }
1775     return mpidr;
1776 }
1777
1778 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1779     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1780       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1781       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1782     REGINFO_SENTINEL
1783 };
1784
1785 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1786     /* NOP AMAIR0/1: the override is because these clash with the rather
1787      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1788      */
1789     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1790       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1791       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1792       .resetvalue = 0 },
1793     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1794     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1795       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1796       .resetvalue = 0 },
1797     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1798       .access = PL1_RW, .type = ARM_CP_64BIT,
1799       .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
1800     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1801       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1802       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1803       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1804     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1805       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1806       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1807       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1808     REGINFO_SENTINEL
1809 };
1810
1811 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1812 {
1813     return vfp_get_fpcr(env);
1814 }
1815
1816 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1817                             uint64_t value)
1818 {
1819     vfp_set_fpcr(env, value);
1820 }
1821
1822 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1823 {
1824     return vfp_get_fpsr(env);
1825 }
1826
1827 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1828                             uint64_t value)
1829 {
1830     vfp_set_fpsr(env, value);
1831 }
1832
1833 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1834 {
1835     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1836         return CP_ACCESS_TRAP;
1837     }
1838     return CP_ACCESS_OK;
1839 }
1840
1841 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1842                             uint64_t value)
1843 {
1844     env->daif = value & PSTATE_DAIF;
1845 }
1846
1847 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1848                                           const ARMCPRegInfo *ri)
1849 {
1850     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1851      * SCTLR_EL1.UCI is set.
1852      */
1853     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1854         return CP_ACCESS_TRAP;
1855     }
1856     return CP_ACCESS_OK;
1857 }
1858
1859 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
1860  * Page D4-1736 (DDI0487A.b)
1861  */
1862
1863 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1864                                uint64_t value)
1865 {
1866     /* Invalidate by VA (AArch64 version) */
1867     ARMCPU *cpu = arm_env_get_cpu(env);
1868     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1869
1870     tlb_flush_page(CPU(cpu), pageaddr);
1871 }
1872
1873 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1874                                 uint64_t value)
1875 {
1876     /* Invalidate by VA, all ASIDs (AArch64 version) */
1877     ARMCPU *cpu = arm_env_get_cpu(env);
1878     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1879
1880     tlb_flush_page(CPU(cpu), pageaddr);
1881 }
1882
1883 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1884                                  uint64_t value)
1885 {
1886     /* Invalidate by ASID (AArch64 version) */
1887     ARMCPU *cpu = arm_env_get_cpu(env);
1888     int asid = extract64(value, 48, 16);
1889     tlb_flush(CPU(cpu), asid == 0);
1890 }
1891
1892 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
1893 {
1894     /* We don't implement EL2, so the only control on DC ZVA is the
1895      * bit in the SCTLR which can prohibit access for EL0.
1896      */
1897     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
1898         return CP_ACCESS_TRAP;
1899     }
1900     return CP_ACCESS_OK;
1901 }
1902
1903 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
1904 {
1905     ARMCPU *cpu = arm_env_get_cpu(env);
1906     int dzp_bit = 1 << 4;
1907
1908     /* DZP indicates whether DC ZVA access is allowed */
1909     if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
1910         dzp_bit = 0;
1911     }
1912     return cpu->dcz_blocksize | dzp_bit;
1913 }
1914
1915 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1916 {
1917     if (!(env->pstate & PSTATE_SP)) {
1918         /* Access to SP_EL0 is undefined if it's being used as
1919          * the stack pointer.
1920          */
1921         return CP_ACCESS_TRAP_UNCATEGORIZED;
1922     }
1923     return CP_ACCESS_OK;
1924 }
1925
1926 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
1927 {
1928     return env->pstate & PSTATE_SP;
1929 }
1930
1931 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
1932 {
1933     update_spsel(env, val);
1934 }
1935
1936 static const ARMCPRegInfo v8_cp_reginfo[] = {
1937     /* Minimal set of EL0-visible registers. This will need to be expanded
1938      * significantly for system emulation of AArch64 CPUs.
1939      */
1940     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1941       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1942       .access = PL0_RW, .type = ARM_CP_NZCV },
1943     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
1944       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
1945       .type = ARM_CP_NO_MIGRATE,
1946       .access = PL0_RW, .accessfn = aa64_daif_access,
1947       .fieldoffset = offsetof(CPUARMState, daif),
1948       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1949     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1950       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1951       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1952     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1953       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1954       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1955     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1956       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1957       .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
1958       .readfn = aa64_dczid_read },
1959     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
1960       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
1961       .access = PL0_W, .type = ARM_CP_DC_ZVA,
1962 #ifndef CONFIG_USER_ONLY
1963       /* Avoid overhead of an access check that always passes in user-mode */
1964       .accessfn = aa64_zva_access,
1965 #endif
1966     },
1967     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1968       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1969       .access = PL1_R, .type = ARM_CP_CURRENTEL },
1970     /* Cache ops: all NOPs since we don't emulate caches */
1971     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1972       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1973       .access = PL1_W, .type = ARM_CP_NOP },
1974     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1975       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1976       .access = PL1_W, .type = ARM_CP_NOP },
1977     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1978       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1979       .access = PL0_W, .type = ARM_CP_NOP,
1980       .accessfn = aa64_cacheop_access },
1981     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1982       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1983       .access = PL1_W, .type = ARM_CP_NOP },
1984     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1985       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1986       .access = PL1_W, .type = ARM_CP_NOP },
1987     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1988       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1989       .access = PL0_W, .type = ARM_CP_NOP,
1990       .accessfn = aa64_cacheop_access },
1991     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1992       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1993       .access = PL1_W, .type = ARM_CP_NOP },
1994     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1995       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1996       .access = PL0_W, .type = ARM_CP_NOP,
1997       .accessfn = aa64_cacheop_access },
1998     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1999       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2000       .access = PL0_W, .type = ARM_CP_NOP,
2001       .accessfn = aa64_cacheop_access },
2002     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2003       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2004       .access = PL1_W, .type = ARM_CP_NOP },
2005     /* TLBI operations */
2006     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2007       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2008       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2009       .writefn = tlbiall_write },
2010     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2011       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2012       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2013       .writefn = tlbi_aa64_va_write },
2014     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2015       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2016       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2017       .writefn = tlbi_aa64_asid_write },
2018     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2019       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2020       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2021       .writefn = tlbi_aa64_vaa_write },
2022     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2023       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2024       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2025       .writefn = tlbi_aa64_va_write },
2026     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2027       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2028       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2029       .writefn = tlbi_aa64_vaa_write },
2030     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2031       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2032       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2033       .writefn = tlbiall_write },
2034     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2035       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2036       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2037       .writefn = tlbi_aa64_va_write },
2038     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2039       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2040       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2041       .writefn = tlbi_aa64_asid_write },
2042     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2043       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2044       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2045       .writefn = tlbi_aa64_vaa_write },
2046     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2047       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2048       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2049       .writefn = tlbi_aa64_va_write },
2050     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2051       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2052       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2053       .writefn = tlbi_aa64_vaa_write },
2054 #ifndef CONFIG_USER_ONLY
2055     /* 64 bit address translation operations */
2056     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2057       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2058       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2059     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2060       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2061       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2062     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2063       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2064       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2065     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2066       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2067       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2068 #endif
2069     /* 32 bit TLB invalidates, Inner Shareable */
2070     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2071       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2072     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2073       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2074     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2075       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2076     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2077       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2078     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2079       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2080     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2081       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2082     /* 32 bit ITLB invalidates */
2083     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
2084       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2085     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
2086       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2087     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
2088       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2089     /* 32 bit DTLB invalidates */
2090     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
2091       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2092     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
2093       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2094     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
2095       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2096     /* 32 bit TLB invalidates */
2097     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2098       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2099     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2100       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2101     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2102       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2103     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2104       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2105     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2106       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2107     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2108       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2109     /* 32 bit cache operations */
2110     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2111       .type = ARM_CP_NOP, .access = PL1_W },
2112     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2113       .type = ARM_CP_NOP, .access = PL1_W },
2114     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2115       .type = ARM_CP_NOP, .access = PL1_W },
2116     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2117       .type = ARM_CP_NOP, .access = PL1_W },
2118     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2119       .type = ARM_CP_NOP, .access = PL1_W },
2120     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2121       .type = ARM_CP_NOP, .access = PL1_W },
2122     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2123       .type = ARM_CP_NOP, .access = PL1_W },
2124     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2125       .type = ARM_CP_NOP, .access = PL1_W },
2126     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2127       .type = ARM_CP_NOP, .access = PL1_W },
2128     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2129       .type = ARM_CP_NOP, .access = PL1_W },
2130     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2131       .type = ARM_CP_NOP, .access = PL1_W },
2132     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2133       .type = ARM_CP_NOP, .access = PL1_W },
2134     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2135       .type = ARM_CP_NOP, .access = PL1_W },
2136     /* MMU Domain access control / MPU write buffer control */
2137     { .name = "DACR", .cp = 15,
2138       .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2139       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
2140       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
2141     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2142       .type = ARM_CP_NO_MIGRATE,
2143       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2144       .access = PL1_RW,
2145       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2146     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2147       .type = ARM_CP_NO_MIGRATE,
2148       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2149       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2150     /* We rely on the access checks not allowing the guest to write to the
2151      * state field when SPSel indicates that it's being used as the stack
2152      * pointer.
2153      */
2154     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2155       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2156       .access = PL1_RW, .accessfn = sp_el0_access,
2157       .type = ARM_CP_NO_MIGRATE,
2158       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2159     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2160       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2161       .type = ARM_CP_NO_MIGRATE,
2162       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2163     REGINFO_SENTINEL
2164 };
2165
2166 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
2167 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2168     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2169       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2170       .access = PL2_RW,
2171       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2172     REGINFO_SENTINEL
2173 };
2174
2175 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2176     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2177       .type = ARM_CP_NO_MIGRATE,
2178       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2179       .access = PL2_RW,
2180       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2181     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2182       .type = ARM_CP_NO_MIGRATE,
2183       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2184       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2185     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2186       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2187       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2188     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2189       .type = ARM_CP_NO_MIGRATE,
2190       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2191       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2192     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2193       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2194       .access = PL2_RW, .writefn = vbar_write,
2195       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2196       .resetvalue = 0 },
2197     REGINFO_SENTINEL
2198 };
2199
2200 static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
2201     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2202       .type = ARM_CP_NO_MIGRATE,
2203       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2204       .access = PL3_RW,
2205       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2206     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2207       .type = ARM_CP_NO_MIGRATE,
2208       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2209       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2210     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2211       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2212       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2213     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2214       .type = ARM_CP_NO_MIGRATE,
2215       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2216       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2217     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2218       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2219       .access = PL3_RW, .writefn = vbar_write,
2220       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2221       .resetvalue = 0 },
2222     REGINFO_SENTINEL
2223 };
2224
2225 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2226                         uint64_t value)
2227 {
2228     ARMCPU *cpu = arm_env_get_cpu(env);
2229
2230     if (raw_read(env, ri) == value) {
2231         /* Skip the TLB flush if nothing actually changed; Linux likes
2232          * to do a lot of pointless SCTLR writes.
2233          */
2234         return;
2235     }
2236
2237     raw_write(env, ri, value);
2238     /* ??? Lots of these bits are not implemented.  */
2239     /* This may enable/disable the MMU, so do a TLB flush.  */
2240     tlb_flush(CPU(cpu), 1);
2241 }
2242
2243 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2244 {
2245     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2246      * but the AArch32 CTR has its own reginfo struct)
2247      */
2248     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
2249         return CP_ACCESS_TRAP;
2250     }
2251     return CP_ACCESS_OK;
2252 }
2253
2254 static const ARMCPRegInfo debug_cp_reginfo[] = {
2255     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2256      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2257      * unlike DBGDRAR it is never accessible from EL0.
2258      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2259      * accessor.
2260      */
2261     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2262       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2263     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2264       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2265       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2266     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2267       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2268     /* Dummy implementation of monitor debug system control register:
2269      * we don't support debug. (The 32-bit alias is DBGDSCRext.)
2270      */
2271     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2272       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2273       .access = PL1_RW,
2274       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2275       .resetvalue = 0 },
2276     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2277     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2278       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2279       .access = PL1_W, .type = ARM_CP_NOP },
2280     REGINFO_SENTINEL
2281 };
2282
2283 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2284     /* 64 bit access versions of the (dummy) debug registers */
2285     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2286       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2287     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2288       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2289     REGINFO_SENTINEL
2290 };
2291
2292 static void define_debug_regs(ARMCPU *cpu)
2293 {
2294     /* Define v7 and v8 architectural debug registers.
2295      * These are just dummy implementations for now.
2296      */
2297     int i;
2298     int wrps, brps;
2299     ARMCPRegInfo dbgdidr = {
2300         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
2301         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
2302     };
2303
2304     brps = extract32(cpu->dbgdidr, 24, 4);
2305     wrps = extract32(cpu->dbgdidr, 28, 4);
2306
2307     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
2308      * of the debug registers such as number of breakpoints;
2309      * check that if they both exist then they agree.
2310      */
2311     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2312         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
2313         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
2314     }
2315
2316     define_one_arm_cp_reg(cpu, &dbgdidr);
2317     define_arm_cp_regs(cpu, debug_cp_reginfo);
2318
2319     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
2320         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
2321     }
2322
2323     for (i = 0; i < brps + 1; i++) {
2324         ARMCPRegInfo dbgregs[] = {
2325             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
2326               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2327               .access = PL1_RW,
2328               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
2329             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
2330               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2331               .access = PL1_RW,
2332               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
2333             REGINFO_SENTINEL
2334         };
2335         define_arm_cp_regs(cpu, dbgregs);
2336     }
2337
2338     for (i = 0; i < wrps + 1; i++) {
2339         ARMCPRegInfo dbgregs[] = {
2340             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
2341               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2342               .access = PL1_RW,
2343               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
2344             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
2345               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2346               .access = PL1_RW,
2347               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
2348                REGINFO_SENTINEL
2349         };
2350         define_arm_cp_regs(cpu, dbgregs);
2351     }
2352 }
2353
2354 void register_cp_regs_for_features(ARMCPU *cpu)
2355 {
2356     /* Register all the coprocessor registers based on feature bits */
2357     CPUARMState *env = &cpu->env;
2358     if (arm_feature(env, ARM_FEATURE_M)) {
2359         /* M profile has no coprocessor registers */
2360         return;
2361     }
2362
2363     define_arm_cp_regs(cpu, cp_reginfo);
2364     if (!arm_feature(env, ARM_FEATURE_V8)) {
2365         /* Must go early as it is full of wildcards that may be
2366          * overridden by later definitions.
2367          */
2368         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2369     }
2370
2371     if (arm_feature(env, ARM_FEATURE_V6)) {
2372         /* The ID registers all have impdef reset values */
2373         ARMCPRegInfo v6_idregs[] = {
2374             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2375               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2376               .access = PL1_R, .type = ARM_CP_CONST,
2377               .resetvalue = cpu->id_pfr0 },
2378             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2379               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2380               .access = PL1_R, .type = ARM_CP_CONST,
2381               .resetvalue = cpu->id_pfr1 },
2382             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2383               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2384               .access = PL1_R, .type = ARM_CP_CONST,
2385               .resetvalue = cpu->id_dfr0 },
2386             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2387               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2388               .access = PL1_R, .type = ARM_CP_CONST,
2389               .resetvalue = cpu->id_afr0 },
2390             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2391               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2392               .access = PL1_R, .type = ARM_CP_CONST,
2393               .resetvalue = cpu->id_mmfr0 },
2394             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2395               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2396               .access = PL1_R, .type = ARM_CP_CONST,
2397               .resetvalue = cpu->id_mmfr1 },
2398             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2399               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2400               .access = PL1_R, .type = ARM_CP_CONST,
2401               .resetvalue = cpu->id_mmfr2 },
2402             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2403               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2404               .access = PL1_R, .type = ARM_CP_CONST,
2405               .resetvalue = cpu->id_mmfr3 },
2406             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2407               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2408               .access = PL1_R, .type = ARM_CP_CONST,
2409               .resetvalue = cpu->id_isar0 },
2410             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2411               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2412               .access = PL1_R, .type = ARM_CP_CONST,
2413               .resetvalue = cpu->id_isar1 },
2414             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2415               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2416               .access = PL1_R, .type = ARM_CP_CONST,
2417               .resetvalue = cpu->id_isar2 },
2418             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2419               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2420               .access = PL1_R, .type = ARM_CP_CONST,
2421               .resetvalue = cpu->id_isar3 },
2422             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2423               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2424               .access = PL1_R, .type = ARM_CP_CONST,
2425               .resetvalue = cpu->id_isar4 },
2426             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2427               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2428               .access = PL1_R, .type = ARM_CP_CONST,
2429               .resetvalue = cpu->id_isar5 },
2430             /* 6..7 are as yet unallocated and must RAZ */
2431             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2432               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2433               .resetvalue = 0 },
2434             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2435               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2436               .resetvalue = 0 },
2437             REGINFO_SENTINEL
2438         };
2439         define_arm_cp_regs(cpu, v6_idregs);
2440         define_arm_cp_regs(cpu, v6_cp_reginfo);
2441     } else {
2442         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2443     }
2444     if (arm_feature(env, ARM_FEATURE_V6K)) {
2445         define_arm_cp_regs(cpu, v6k_cp_reginfo);
2446     }
2447     if (arm_feature(env, ARM_FEATURE_V7)) {
2448         /* v7 performance monitor control register: same implementor
2449          * field as main ID register, and we implement only the cycle
2450          * count register.
2451          */
2452 #ifndef CONFIG_USER_ONLY
2453         ARMCPRegInfo pmcr = {
2454             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2455             .access = PL0_RW,
2456             .type = ARM_CP_IO | ARM_CP_NO_MIGRATE,
2457             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
2458             .accessfn = pmreg_access, .writefn = pmcr_write,
2459             .raw_writefn = raw_write,
2460         };
2461         ARMCPRegInfo pmcr64 = {
2462             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
2463             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
2464             .access = PL0_RW, .accessfn = pmreg_access,
2465             .type = ARM_CP_IO,
2466             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2467             .resetvalue = cpu->midr & 0xff000000,
2468             .writefn = pmcr_write, .raw_writefn = raw_write,
2469         };
2470         define_one_arm_cp_reg(cpu, &pmcr);
2471         define_one_arm_cp_reg(cpu, &pmcr64);
2472 #endif
2473         ARMCPRegInfo clidr = {
2474             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2475             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2476             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2477         };
2478         define_one_arm_cp_reg(cpu, &clidr);
2479         define_arm_cp_regs(cpu, v7_cp_reginfo);
2480         define_debug_regs(cpu);
2481     } else {
2482         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2483     }
2484     if (arm_feature(env, ARM_FEATURE_V8)) {
2485         /* AArch64 ID registers, which all have impdef reset values */
2486         ARMCPRegInfo v8_idregs[] = {
2487             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2488               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2489               .access = PL1_R, .type = ARM_CP_CONST,
2490               .resetvalue = cpu->id_aa64pfr0 },
2491             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2492               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2493               .access = PL1_R, .type = ARM_CP_CONST,
2494               .resetvalue = cpu->id_aa64pfr1},
2495             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2496               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2497               .access = PL1_R, .type = ARM_CP_CONST,
2498               /* We mask out the PMUVer field, because we don't currently
2499                * implement the PMU. Not advertising it prevents the guest
2500                * from trying to use it and getting UNDEFs on registers we
2501                * don't implement.
2502                */
2503               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
2504             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2505               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2506               .access = PL1_R, .type = ARM_CP_CONST,
2507               .resetvalue = cpu->id_aa64dfr1 },
2508             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2509               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2510               .access = PL1_R, .type = ARM_CP_CONST,
2511               .resetvalue = cpu->id_aa64afr0 },
2512             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2513               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2514               .access = PL1_R, .type = ARM_CP_CONST,
2515               .resetvalue = cpu->id_aa64afr1 },
2516             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2517               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2518               .access = PL1_R, .type = ARM_CP_CONST,
2519               .resetvalue = cpu->id_aa64isar0 },
2520             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2521               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2522               .access = PL1_R, .type = ARM_CP_CONST,
2523               .resetvalue = cpu->id_aa64isar1 },
2524             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2525               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2526               .access = PL1_R, .type = ARM_CP_CONST,
2527               .resetvalue = cpu->id_aa64mmfr0 },
2528             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2529               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2530               .access = PL1_R, .type = ARM_CP_CONST,
2531               .resetvalue = cpu->id_aa64mmfr1 },
2532             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
2533               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
2534               .access = PL1_R, .type = ARM_CP_CONST,
2535               .resetvalue = cpu->mvfr0 },
2536             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
2537               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
2538               .access = PL1_R, .type = ARM_CP_CONST,
2539               .resetvalue = cpu->mvfr1 },
2540             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
2541               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
2542               .access = PL1_R, .type = ARM_CP_CONST,
2543               .resetvalue = cpu->mvfr2 },
2544             REGINFO_SENTINEL
2545         };
2546         ARMCPRegInfo rvbar = {
2547             .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
2548             .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
2549             .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
2550         };
2551         define_one_arm_cp_reg(cpu, &rvbar);
2552         define_arm_cp_regs(cpu, v8_idregs);
2553         define_arm_cp_regs(cpu, v8_cp_reginfo);
2554     }
2555     if (arm_feature(env, ARM_FEATURE_EL2)) {
2556         define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
2557     } else {
2558         /* If EL2 is missing but higher ELs are enabled, we need to
2559          * register the no_el2 reginfos.
2560          */
2561         if (arm_feature(env, ARM_FEATURE_EL3)) {
2562             define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
2563         }
2564     }
2565     if (arm_feature(env, ARM_FEATURE_EL3)) {
2566         define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
2567     }
2568     if (arm_feature(env, ARM_FEATURE_MPU)) {
2569         /* These are the MPU registers prior to PMSAv6. Any new
2570          * PMSA core later than the ARM946 will require that we
2571          * implement the PMSAv6 or PMSAv7 registers, which are
2572          * completely different.
2573          */
2574         assert(!arm_feature(env, ARM_FEATURE_V6));
2575         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2576     } else {
2577         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2578     }
2579     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2580         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2581     }
2582     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2583         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2584     }
2585     if (arm_feature(env, ARM_FEATURE_VAPA)) {
2586         define_arm_cp_regs(cpu, vapa_cp_reginfo);
2587     }
2588     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2589         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2590     }
2591     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2592         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2593     }
2594     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2595         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2596     }
2597     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2598         define_arm_cp_regs(cpu, omap_cp_reginfo);
2599     }
2600     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2601         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2602     }
2603     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2604         define_arm_cp_regs(cpu, xscale_cp_reginfo);
2605     }
2606     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2607         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2608     }
2609     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2610         define_arm_cp_regs(cpu, lpae_cp_reginfo);
2611     }
2612     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2613      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2614      * be read-only (ie write causes UNDEF exception).
2615      */
2616     {
2617         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
2618             /* Pre-v8 MIDR space.
2619              * Note that the MIDR isn't a simple constant register because
2620              * of the TI925 behaviour where writes to another register can
2621              * cause the MIDR value to change.
2622              *
2623              * Unimplemented registers in the c15 0 0 0 space default to
2624              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2625              * and friends override accordingly.
2626              */
2627             { .name = "MIDR",
2628               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2629               .access = PL1_R, .resetvalue = cpu->midr,
2630               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2631               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2632               .type = ARM_CP_OVERRIDE },
2633             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2634             { .name = "DUMMY",
2635               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2636               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2637             { .name = "DUMMY",
2638               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2639               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2640             { .name = "DUMMY",
2641               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2642               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2643             { .name = "DUMMY",
2644               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2645               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2646             { .name = "DUMMY",
2647               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2648               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2649             REGINFO_SENTINEL
2650         };
2651         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
2652             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
2653              * variable-MIDR TI925 behaviour. Instead we have a single
2654              * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
2655              */
2656             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
2657               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
2658               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2659             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
2660               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
2661               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2662             REGINFO_SENTINEL
2663         };
2664         ARMCPRegInfo id_cp_reginfo[] = {
2665             /* These are common to v8 and pre-v8 */
2666             { .name = "CTR",
2667               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2668               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2669             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2670               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2671               .access = PL0_R, .accessfn = ctr_el0_access,
2672               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2673             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
2674             { .name = "TCMTR",
2675               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2676               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2677             { .name = "TLBTR",
2678               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2679               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2680             REGINFO_SENTINEL
2681         };
2682         ARMCPRegInfo crn0_wi_reginfo = {
2683             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2684             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2685             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2686         };
2687         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2688             arm_feature(env, ARM_FEATURE_STRONGARM)) {
2689             ARMCPRegInfo *r;
2690             /* Register the blanket "writes ignored" value first to cover the
2691              * whole space. Then update the specific ID registers to allow write
2692              * access, so that they ignore writes rather than causing them to
2693              * UNDEF.
2694              */
2695             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2696             for (r = id_pre_v8_midr_cp_reginfo;
2697                  r->type != ARM_CP_SENTINEL; r++) {
2698                 r->access = PL1_RW;
2699             }
2700             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2701                 r->access = PL1_RW;
2702             }
2703         }
2704         if (arm_feature(env, ARM_FEATURE_V8)) {
2705             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
2706         } else {
2707             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
2708         }
2709         define_arm_cp_regs(cpu, id_cp_reginfo);
2710     }
2711
2712     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2713         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2714     }
2715
2716     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2717         ARMCPRegInfo auxcr = {
2718             .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
2719             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
2720             .access = PL1_RW, .type = ARM_CP_CONST,
2721             .resetvalue = cpu->reset_auxcr
2722         };
2723         define_one_arm_cp_reg(cpu, &auxcr);
2724     }
2725
2726     if (arm_feature(env, ARM_FEATURE_CBAR)) {
2727         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2728             /* 32 bit view is [31:18] 0...0 [43:32]. */
2729             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
2730                 | extract64(cpu->reset_cbar, 32, 12);
2731             ARMCPRegInfo cbar_reginfo[] = {
2732                 { .name = "CBAR",
2733                   .type = ARM_CP_CONST,
2734                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2735                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
2736                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
2737                   .type = ARM_CP_CONST,
2738                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
2739                   .access = PL1_R, .resetvalue = cbar32 },
2740                 REGINFO_SENTINEL
2741             };
2742             /* We don't implement a r/w 64 bit CBAR currently */
2743             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
2744             define_arm_cp_regs(cpu, cbar_reginfo);
2745         } else {
2746             ARMCPRegInfo cbar = {
2747                 .name = "CBAR",
2748                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2749                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2750                 .fieldoffset = offsetof(CPUARMState,
2751                                         cp15.c15_config_base_address)
2752             };
2753             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
2754                 cbar.access = PL1_R;
2755                 cbar.fieldoffset = 0;
2756                 cbar.type = ARM_CP_CONST;
2757             }
2758             define_one_arm_cp_reg(cpu, &cbar);
2759         }
2760     }
2761
2762     /* Generic registers whose values depend on the implementation */
2763     {
2764         ARMCPRegInfo sctlr = {
2765             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2766             .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2767             .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2768             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2769             .raw_writefn = raw_write,
2770         };
2771         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2772             /* Normally we would always end the TB on an SCTLR write, but Linux
2773              * arch/arm/mach-pxa/sleep.S expects two instructions following
2774              * an MMU enable to execute from cache.  Imitate this behaviour.
2775              */
2776             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2777         }
2778         define_one_arm_cp_reg(cpu, &sctlr);
2779     }
2780 }
2781
2782 ARMCPU *cpu_arm_init(const char *cpu_model)
2783 {
2784     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2785 }
2786
2787 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2788 {
2789     CPUState *cs = CPU(cpu);
2790     CPUARMState *env = &cpu->env;
2791
2792     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2793         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2794                                  aarch64_fpu_gdb_set_reg,
2795                                  34, "aarch64-fpu.xml", 0);
2796     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2797         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2798                                  51, "arm-neon.xml", 0);
2799     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2800         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2801                                  35, "arm-vfp3.xml", 0);
2802     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2803         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2804                                  19, "arm-vfp.xml", 0);
2805     }
2806 }
2807
2808 /* Sort alphabetically by type name, except for "any". */
2809 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2810 {
2811     ObjectClass *class_a = (ObjectClass *)a;
2812     ObjectClass *class_b = (ObjectClass *)b;
2813     const char *name_a, *name_b;
2814
2815     name_a = object_class_get_name(class_a);
2816     name_b = object_class_get_name(class_b);
2817     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2818         return 1;
2819     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2820         return -1;
2821     } else {
2822         return strcmp(name_a, name_b);
2823     }
2824 }
2825
2826 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2827 {
2828     ObjectClass *oc = data;
2829     CPUListState *s = user_data;
2830     const char *typename;
2831     char *name;
2832
2833     typename = object_class_get_name(oc);
2834     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2835     (*s->cpu_fprintf)(s->file, "  %s\n",
2836                       name);
2837     g_free(name);
2838 }
2839
2840 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2841 {
2842     CPUListState s = {
2843         .file = f,
2844         .cpu_fprintf = cpu_fprintf,
2845     };
2846     GSList *list;
2847
2848     list = object_class_get_list(TYPE_ARM_CPU, false);
2849     list = g_slist_sort(list, arm_cpu_list_compare);
2850     (*cpu_fprintf)(f, "Available CPUs:\n");
2851     g_slist_foreach(list, arm_cpu_list_entry, &s);
2852     g_slist_free(list);
2853 #ifdef CONFIG_KVM
2854     /* The 'host' CPU type is dynamically registered only if KVM is
2855      * enabled, so we have to special-case it here:
2856      */
2857     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
2858 #endif
2859 }
2860
2861 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2862 {
2863     ObjectClass *oc = data;
2864     CpuDefinitionInfoList **cpu_list = user_data;
2865     CpuDefinitionInfoList *entry;
2866     CpuDefinitionInfo *info;
2867     const char *typename;
2868
2869     typename = object_class_get_name(oc);
2870     info = g_malloc0(sizeof(*info));
2871     info->name = g_strndup(typename,
2872                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
2873
2874     entry = g_malloc0(sizeof(*entry));
2875     entry->value = info;
2876     entry->next = *cpu_list;
2877     *cpu_list = entry;
2878 }
2879
2880 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2881 {
2882     CpuDefinitionInfoList *cpu_list = NULL;
2883     GSList *list;
2884
2885     list = object_class_get_list(TYPE_ARM_CPU, false);
2886     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2887     g_slist_free(list);
2888
2889     return cpu_list;
2890 }
2891
2892 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2893                                    void *opaque, int state,
2894                                    int crm, int opc1, int opc2)
2895 {
2896     /* Private utility function for define_one_arm_cp_reg_with_opaque():
2897      * add a single reginfo struct to the hash table.
2898      */
2899     uint32_t *key = g_new(uint32_t, 1);
2900     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2901     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2902     if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2903         /* The AArch32 view of a shared register sees the lower 32 bits
2904          * of a 64 bit backing field. It is not migratable as the AArch64
2905          * view handles that. AArch64 also handles reset.
2906          * We assume it is a cp15 register if the .cp field is left unset.
2907          */
2908         if (r2->cp == 0) {
2909             r2->cp = 15;
2910         }
2911         r2->type |= ARM_CP_NO_MIGRATE;
2912         r2->resetfn = arm_cp_reset_ignore;
2913 #ifdef HOST_WORDS_BIGENDIAN
2914         if (r2->fieldoffset) {
2915             r2->fieldoffset += sizeof(uint32_t);
2916         }
2917 #endif
2918     }
2919     if (state == ARM_CP_STATE_AA64) {
2920         /* To allow abbreviation of ARMCPRegInfo
2921          * definitions, we treat cp == 0 as equivalent to
2922          * the value for "standard guest-visible sysreg".
2923          * STATE_BOTH definitions are also always "standard
2924          * sysreg" in their AArch64 view (the .cp value may
2925          * be non-zero for the benefit of the AArch32 view).
2926          */
2927         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
2928             r2->cp = CP_REG_ARM64_SYSREG_CP;
2929         }
2930         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2931                                   r2->opc0, opc1, opc2);
2932     } else {
2933         *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2934     }
2935     if (opaque) {
2936         r2->opaque = opaque;
2937     }
2938     /* reginfo passed to helpers is correct for the actual access,
2939      * and is never ARM_CP_STATE_BOTH:
2940      */
2941     r2->state = state;
2942     /* Make sure reginfo passed to helpers for wildcarded regs
2943      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2944      */
2945     r2->crm = crm;
2946     r2->opc1 = opc1;
2947     r2->opc2 = opc2;
2948     /* By convention, for wildcarded registers only the first
2949      * entry is used for migration; the others are marked as
2950      * NO_MIGRATE so we don't try to transfer the register
2951      * multiple times. Special registers (ie NOP/WFI) are
2952      * never migratable.
2953      */
2954     if ((r->type & ARM_CP_SPECIAL) ||
2955         ((r->crm == CP_ANY) && crm != 0) ||
2956         ((r->opc1 == CP_ANY) && opc1 != 0) ||
2957         ((r->opc2 == CP_ANY) && opc2 != 0)) {
2958         r2->type |= ARM_CP_NO_MIGRATE;
2959     }
2960
2961     /* Overriding of an existing definition must be explicitly
2962      * requested.
2963      */
2964     if (!(r->type & ARM_CP_OVERRIDE)) {
2965         ARMCPRegInfo *oldreg;
2966         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2967         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2968             fprintf(stderr, "Register redefined: cp=%d %d bit "
2969                     "crn=%d crm=%d opc1=%d opc2=%d, "
2970                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2971                     r2->crn, r2->crm, r2->opc1, r2->opc2,
2972                     oldreg->name, r2->name);
2973             g_assert_not_reached();
2974         }
2975     }
2976     g_hash_table_insert(cpu->cp_regs, key, r2);
2977 }
2978
2979
2980 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2981                                        const ARMCPRegInfo *r, void *opaque)
2982 {
2983     /* Define implementations of coprocessor registers.
2984      * We store these in a hashtable because typically
2985      * there are less than 150 registers in a space which
2986      * is 16*16*16*8*8 = 262144 in size.
2987      * Wildcarding is supported for the crm, opc1 and opc2 fields.
2988      * If a register is defined twice then the second definition is
2989      * used, so this can be used to define some generic registers and
2990      * then override them with implementation specific variations.
2991      * At least one of the original and the second definition should
2992      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2993      * against accidental use.
2994      *
2995      * The state field defines whether the register is to be
2996      * visible in the AArch32 or AArch64 execution state. If the
2997      * state is set to ARM_CP_STATE_BOTH then we synthesise a
2998      * reginfo structure for the AArch32 view, which sees the lower
2999      * 32 bits of the 64 bit register.
3000      *
3001      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
3002      * be wildcarded. AArch64 registers are always considered to be 64
3003      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
3004      * the register, if any.
3005      */
3006     int crm, opc1, opc2, state;
3007     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
3008     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
3009     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
3010     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
3011     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
3012     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
3013     /* 64 bit registers have only CRm and Opc1 fields */
3014     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
3015     /* op0 only exists in the AArch64 encodings */
3016     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
3017     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
3018     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
3019     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
3020      * encodes a minimum access level for the register. We roll this
3021      * runtime check into our general permission check code, so check
3022      * here that the reginfo's specified permissions are strict enough
3023      * to encompass the generic architectural permission check.
3024      */
3025     if (r->state != ARM_CP_STATE_AA32) {
3026         int mask = 0;
3027         switch (r->opc1) {
3028         case 0: case 1: case 2:
3029             /* min_EL EL1 */
3030             mask = PL1_RW;
3031             break;
3032         case 3:
3033             /* min_EL EL0 */
3034             mask = PL0_RW;
3035             break;
3036         case 4:
3037             /* min_EL EL2 */
3038             mask = PL2_RW;
3039             break;
3040         case 5:
3041             /* unallocated encoding, so not possible */
3042             assert(false);
3043             break;
3044         case 6:
3045             /* min_EL EL3 */
3046             mask = PL3_RW;
3047             break;
3048         case 7:
3049             /* min_EL EL1, secure mode only (we don't check the latter) */
3050             mask = PL1_RW;
3051             break;
3052         default:
3053             /* broken reginfo with out-of-range opc1 */
3054             assert(false);
3055             break;
3056         }
3057         /* assert our permissions are not too lax (stricter is fine) */
3058         assert((r->access & ~mask) == 0);
3059     }
3060
3061     /* Check that the register definition has enough info to handle
3062      * reads and writes if they are permitted.
3063      */
3064     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
3065         if (r->access & PL3_R) {
3066             assert(r->fieldoffset || r->readfn);
3067         }
3068         if (r->access & PL3_W) {
3069             assert(r->fieldoffset || r->writefn);
3070         }
3071     }
3072     /* Bad type field probably means missing sentinel at end of reg list */
3073     assert(cptype_valid(r->type));
3074     for (crm = crmmin; crm <= crmmax; crm++) {
3075         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
3076             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
3077                 for (state = ARM_CP_STATE_AA32;
3078                      state <= ARM_CP_STATE_AA64; state++) {
3079                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
3080                         continue;
3081                     }
3082                     add_cpreg_to_hashtable(cpu, r, opaque, state,
3083                                            crm, opc1, opc2);
3084                 }
3085             }
3086         }
3087     }
3088 }
3089
3090 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
3091                                     const ARMCPRegInfo *regs, void *opaque)
3092 {
3093     /* Define a whole list of registers */
3094     const ARMCPRegInfo *r;
3095     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
3096         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
3097     }
3098 }
3099
3100 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
3101 {
3102     return g_hash_table_lookup(cpregs, &encoded_cp);
3103 }
3104
3105 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
3106                          uint64_t value)
3107 {
3108     /* Helper coprocessor write function for write-ignore registers */
3109 }
3110
3111 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
3112 {
3113     /* Helper coprocessor write function for read-as-zero registers */
3114     return 0;
3115 }
3116
3117 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
3118 {
3119     /* Helper coprocessor reset function for do-nothing-on-reset registers */
3120 }
3121
3122 static int bad_mode_switch(CPUARMState *env, int mode)
3123 {
3124     /* Return true if it is not valid for us to switch to
3125      * this CPU mode (ie all the UNPREDICTABLE cases in
3126      * the ARM ARM CPSRWriteByInstr pseudocode).
3127      */
3128     switch (mode) {
3129     case ARM_CPU_MODE_USR:
3130     case ARM_CPU_MODE_SYS:
3131     case ARM_CPU_MODE_SVC:
3132     case ARM_CPU_MODE_ABT:
3133     case ARM_CPU_MODE_UND:
3134     case ARM_CPU_MODE_IRQ:
3135     case ARM_CPU_MODE_FIQ:
3136         return 0;
3137     default:
3138         return 1;
3139     }
3140 }
3141
3142 uint32_t cpsr_read(CPUARMState *env)
3143 {
3144     int ZF;
3145     ZF = (env->ZF == 0);
3146     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
3147         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
3148         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
3149         | ((env->condexec_bits & 0xfc) << 8)
3150         | (env->GE << 16) | (env->daif & CPSR_AIF);
3151 }
3152
3153 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
3154 {
3155     if (mask & CPSR_NZCV) {
3156         env->ZF = (~val) & CPSR_Z;
3157         env->NF = val;
3158         env->CF = (val >> 29) & 1;
3159         env->VF = (val << 3) & 0x80000000;
3160     }
3161     if (mask & CPSR_Q)
3162         env->QF = ((val & CPSR_Q) != 0);
3163     if (mask & CPSR_T)
3164         env->thumb = ((val & CPSR_T) != 0);
3165     if (mask & CPSR_IT_0_1) {
3166         env->condexec_bits &= ~3;
3167         env->condexec_bits |= (val >> 25) & 3;
3168     }
3169     if (mask & CPSR_IT_2_7) {
3170         env->condexec_bits &= 3;
3171         env->condexec_bits |= (val >> 8) & 0xfc;
3172     }
3173     if (mask & CPSR_GE) {
3174         env->GE = (val >> 16) & 0xf;
3175     }
3176
3177     env->daif &= ~(CPSR_AIF & mask);
3178     env->daif |= val & CPSR_AIF & mask;
3179
3180     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
3181         if (bad_mode_switch(env, val & CPSR_M)) {
3182             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3183              * We choose to ignore the attempt and leave the CPSR M field
3184              * untouched.
3185              */
3186             mask &= ~CPSR_M;
3187         } else {
3188             switch_mode(env, val & CPSR_M);
3189         }
3190     }
3191     mask &= ~CACHED_CPSR_BITS;
3192     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
3193 }
3194
3195 /* Sign/zero extend */
3196 uint32_t HELPER(sxtb16)(uint32_t x)
3197 {
3198     uint32_t res;
3199     res = (uint16_t)(int8_t)x;
3200     res |= (uint32_t)(int8_t)(x >> 16) << 16;
3201     return res;
3202 }
3203
3204 uint32_t HELPER(uxtb16)(uint32_t x)
3205 {
3206     uint32_t res;
3207     res = (uint16_t)(uint8_t)x;
3208     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
3209     return res;
3210 }
3211
3212 uint32_t HELPER(clz)(uint32_t x)
3213 {
3214     return clz32(x);
3215 }
3216
3217 int32_t HELPER(sdiv)(int32_t num, int32_t den)
3218 {
3219     if (den == 0)
3220       return 0;
3221     if (num == INT_MIN && den == -1)
3222       return INT_MIN;
3223     return num / den;
3224 }
3225
3226 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
3227 {
3228     if (den == 0)
3229       return 0;
3230     return num / den;
3231 }
3232
3233 uint32_t HELPER(rbit)(uint32_t x)
3234 {
3235     x =  ((x & 0xff000000) >> 24)
3236        | ((x & 0x00ff0000) >> 8)
3237        | ((x & 0x0000ff00) << 8)
3238        | ((x & 0x000000ff) << 24);
3239     x =  ((x & 0xf0f0f0f0) >> 4)
3240        | ((x & 0x0f0f0f0f) << 4);
3241     x =  ((x & 0x88888888) >> 3)
3242        | ((x & 0x44444444) >> 1)
3243        | ((x & 0x22222222) << 1)
3244        | ((x & 0x11111111) << 3);
3245     return x;
3246 }
3247
3248 #if defined(CONFIG_USER_ONLY)
3249
3250 void arm_cpu_do_interrupt(CPUState *cs)
3251 {
3252     cs->exception_index = -1;
3253 }
3254
3255 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
3256                              int mmu_idx)
3257 {
3258     ARMCPU *cpu = ARM_CPU(cs);
3259     CPUARMState *env = &cpu->env;
3260
3261     env->exception.vaddress = address;
3262     if (rw == 2) {
3263         cs->exception_index = EXCP_PREFETCH_ABORT;
3264     } else {
3265         cs->exception_index = EXCP_DATA_ABORT;
3266     }
3267     return 1;
3268 }
3269
3270 /* These should probably raise undefined insn exceptions.  */
3271 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3272 {
3273     ARMCPU *cpu = arm_env_get_cpu(env);
3274
3275     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
3276 }
3277
3278 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3279 {
3280     ARMCPU *cpu = arm_env_get_cpu(env);
3281
3282     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
3283     return 0;
3284 }
3285
3286 void switch_mode(CPUARMState *env, int mode)
3287 {
3288     ARMCPU *cpu = arm_env_get_cpu(env);
3289
3290     if (mode != ARM_CPU_MODE_USR) {
3291         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
3292     }
3293 }
3294
3295 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3296 {
3297     ARMCPU *cpu = arm_env_get_cpu(env);
3298
3299     cpu_abort(CPU(cpu), "banked r13 write\n");
3300 }
3301
3302 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3303 {
3304     ARMCPU *cpu = arm_env_get_cpu(env);
3305
3306     cpu_abort(CPU(cpu), "banked r13 read\n");
3307     return 0;
3308 }
3309
3310 #else
3311
3312 /* Map CPU modes onto saved register banks.  */
3313 int bank_number(int mode)
3314 {
3315     switch (mode) {
3316     case ARM_CPU_MODE_USR:
3317     case ARM_CPU_MODE_SYS:
3318         return 0;
3319     case ARM_CPU_MODE_SVC:
3320         return 1;
3321     case ARM_CPU_MODE_ABT:
3322         return 2;
3323     case ARM_CPU_MODE_UND:
3324         return 3;
3325     case ARM_CPU_MODE_IRQ:
3326         return 4;
3327     case ARM_CPU_MODE_FIQ:
3328         return 5;
3329     case ARM_CPU_MODE_HYP:
3330         return 6;
3331     case ARM_CPU_MODE_MON:
3332         return 7;
3333     }
3334     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
3335 }
3336
3337 void switch_mode(CPUARMState *env, int mode)
3338 {
3339     int old_mode;
3340     int i;
3341
3342     old_mode = env->uncached_cpsr & CPSR_M;
3343     if (mode == old_mode)
3344         return;
3345
3346     if (old_mode == ARM_CPU_MODE_FIQ) {
3347         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
3348         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
3349     } else if (mode == ARM_CPU_MODE_FIQ) {
3350         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
3351         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
3352     }
3353
3354     i = bank_number(old_mode);
3355     env->banked_r13[i] = env->regs[13];
3356     env->banked_r14[i] = env->regs[14];
3357     env->banked_spsr[i] = env->spsr;
3358
3359     i = bank_number(mode);
3360     env->regs[13] = env->banked_r13[i];
3361     env->regs[14] = env->banked_r14[i];
3362     env->spsr = env->banked_spsr[i];
3363 }
3364
3365 static void v7m_push(CPUARMState *env, uint32_t val)
3366 {
3367     CPUState *cs = CPU(arm_env_get_cpu(env));
3368
3369     env->regs[13] -= 4;
3370     stl_phys(cs->as, env->regs[13], val);
3371 }
3372
3373 static uint32_t v7m_pop(CPUARMState *env)
3374 {
3375     CPUState *cs = CPU(arm_env_get_cpu(env));
3376     uint32_t val;
3377
3378     val = ldl_phys(cs->as, env->regs[13]);
3379     env->regs[13] += 4;
3380     return val;
3381 }
3382
3383 /* Switch to V7M main or process stack pointer.  */
3384 static void switch_v7m_sp(CPUARMState *env, int process)
3385 {
3386     uint32_t tmp;
3387     if (env->v7m.current_sp != process) {
3388         tmp = env->v7m.other_sp;
3389         env->v7m.other_sp = env->regs[13];
3390         env->regs[13] = tmp;
3391         env->v7m.current_sp = process;
3392     }
3393 }
3394
3395 static void do_v7m_exception_exit(CPUARMState *env)
3396 {
3397     uint32_t type;
3398     uint32_t xpsr;
3399
3400     type = env->regs[15];
3401     if (env->v7m.exception != 0)
3402         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
3403
3404     /* Switch to the target stack.  */
3405     switch_v7m_sp(env, (type & 4) != 0);
3406     /* Pop registers.  */
3407     env->regs[0] = v7m_pop(env);
3408     env->regs[1] = v7m_pop(env);
3409     env->regs[2] = v7m_pop(env);
3410     env->regs[3] = v7m_pop(env);
3411     env->regs[12] = v7m_pop(env);
3412     env->regs[14] = v7m_pop(env);
3413     env->regs[15] = v7m_pop(env);
3414     xpsr = v7m_pop(env);
3415     xpsr_write(env, xpsr, 0xfffffdff);
3416     /* Undo stack alignment.  */
3417     if (xpsr & 0x200)
3418         env->regs[13] |= 4;
3419     /* ??? The exception return type specifies Thread/Handler mode.  However
3420        this is also implied by the xPSR value. Not sure what to do
3421        if there is a mismatch.  */
3422     /* ??? Likewise for mismatches between the CONTROL register and the stack
3423        pointer.  */
3424 }
3425
3426 void arm_v7m_cpu_do_interrupt(CPUState *cs)
3427 {
3428     ARMCPU *cpu = ARM_CPU(cs);
3429     CPUARMState *env = &cpu->env;
3430     uint32_t xpsr = xpsr_read(env);
3431     uint32_t lr;
3432     uint32_t addr;
3433
3434     arm_log_exception(cs->exception_index);
3435
3436     lr = 0xfffffff1;
3437     if (env->v7m.current_sp)
3438         lr |= 4;
3439     if (env->v7m.exception == 0)
3440         lr |= 8;
3441
3442     /* For exceptions we just mark as pending on the NVIC, and let that
3443        handle it.  */
3444     /* TODO: Need to escalate if the current priority is higher than the
3445        one we're raising.  */
3446     switch (cs->exception_index) {
3447     case EXCP_UDEF:
3448         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
3449         return;
3450     case EXCP_SWI:
3451         /* The PC already points to the next instruction.  */
3452         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
3453         return;
3454     case EXCP_PREFETCH_ABORT:
3455     case EXCP_DATA_ABORT:
3456         /* TODO: if we implemented the MPU registers, this is where we
3457          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3458          */
3459         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
3460         return;
3461     case EXCP_BKPT:
3462         if (semihosting_enabled) {
3463             int nr;
3464             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3465             if (nr == 0xab) {
3466                 env->regs[15] += 2;
3467                 env->regs[0] = do_arm_semihosting(env);
3468                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3469                 return;
3470             }
3471         }
3472         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
3473         return;
3474     case EXCP_IRQ:
3475         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
3476         break;
3477     case EXCP_EXCEPTION_EXIT:
3478         do_v7m_exception_exit(env);
3479         return;
3480     default:
3481         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3482         return; /* Never happens.  Keep compiler happy.  */
3483     }
3484
3485     /* Align stack pointer.  */
3486     /* ??? Should only do this if Configuration Control Register
3487        STACKALIGN bit is set.  */
3488     if (env->regs[13] & 4) {
3489         env->regs[13] -= 4;
3490         xpsr |= 0x200;
3491     }
3492     /* Switch to the handler mode.  */
3493     v7m_push(env, xpsr);
3494     v7m_push(env, env->regs[15]);
3495     v7m_push(env, env->regs[14]);
3496     v7m_push(env, env->regs[12]);
3497     v7m_push(env, env->regs[3]);
3498     v7m_push(env, env->regs[2]);
3499     v7m_push(env, env->regs[1]);
3500     v7m_push(env, env->regs[0]);
3501     switch_v7m_sp(env, 0);
3502     /* Clear IT bits */
3503     env->condexec_bits = 0;
3504     env->regs[14] = lr;
3505     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
3506     env->regs[15] = addr & 0xfffffffe;
3507     env->thumb = addr & 1;
3508 }
3509
3510 /* Handle a CPU exception.  */
3511 void arm_cpu_do_interrupt(CPUState *cs)
3512 {
3513     ARMCPU *cpu = ARM_CPU(cs);
3514     CPUARMState *env = &cpu->env;
3515     uint32_t addr;
3516     uint32_t mask;
3517     int new_mode;
3518     uint32_t offset;
3519
3520     assert(!IS_M(env));
3521
3522     arm_log_exception(cs->exception_index);
3523
3524     /* TODO: Vectored interrupt controller.  */
3525     switch (cs->exception_index) {
3526     case EXCP_UDEF:
3527         new_mode = ARM_CPU_MODE_UND;
3528         addr = 0x04;
3529         mask = CPSR_I;
3530         if (env->thumb)
3531             offset = 2;
3532         else
3533             offset = 4;
3534         break;
3535     case EXCP_SWI:
3536         if (semihosting_enabled) {
3537             /* Check for semihosting interrupt.  */
3538             if (env->thumb) {
3539                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
3540                     & 0xff;
3541             } else {
3542                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
3543                     & 0xffffff;
3544             }
3545             /* Only intercept calls from privileged modes, to provide some
3546                semblance of security.  */
3547             if (((mask == 0x123456 && !env->thumb)
3548                     || (mask == 0xab && env->thumb))
3549                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3550                 env->regs[0] = do_arm_semihosting(env);
3551                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3552                 return;
3553             }
3554         }
3555         new_mode = ARM_CPU_MODE_SVC;
3556         addr = 0x08;
3557         mask = CPSR_I;
3558         /* The PC already points to the next instruction.  */
3559         offset = 0;
3560         break;
3561     case EXCP_BKPT:
3562         /* See if this is a semihosting syscall.  */
3563         if (env->thumb && semihosting_enabled) {
3564             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3565             if (mask == 0xab
3566                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3567                 env->regs[15] += 2;
3568                 env->regs[0] = do_arm_semihosting(env);
3569                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3570                 return;
3571             }
3572         }
3573         env->exception.fsr = 2;
3574         /* Fall through to prefetch abort.  */
3575     case EXCP_PREFETCH_ABORT:
3576         env->cp15.ifsr_el2 = env->exception.fsr;
3577         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
3578                                         env->exception.vaddress);
3579         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
3580                       env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
3581         new_mode = ARM_CPU_MODE_ABT;
3582         addr = 0x0c;
3583         mask = CPSR_A | CPSR_I;
3584         offset = 4;
3585         break;
3586     case EXCP_DATA_ABORT:
3587         env->cp15.esr_el[1] = env->exception.fsr;
3588         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
3589                                         env->exception.vaddress);
3590         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
3591                       (uint32_t)env->cp15.esr_el[1],
3592                       (uint32_t)env->exception.vaddress);
3593         new_mode = ARM_CPU_MODE_ABT;
3594         addr = 0x10;
3595         mask = CPSR_A | CPSR_I;
3596         offset = 8;
3597         break;
3598     case EXCP_IRQ:
3599         new_mode = ARM_CPU_MODE_IRQ;
3600         addr = 0x18;
3601         /* Disable IRQ and imprecise data aborts.  */
3602         mask = CPSR_A | CPSR_I;
3603         offset = 4;
3604         break;
3605     case EXCP_FIQ:
3606         new_mode = ARM_CPU_MODE_FIQ;
3607         addr = 0x1c;
3608         /* Disable FIQ, IRQ and imprecise data aborts.  */
3609         mask = CPSR_A | CPSR_I | CPSR_F;
3610         offset = 4;
3611         break;
3612     default:
3613         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3614         return; /* Never happens.  Keep compiler happy.  */
3615     }
3616     /* High vectors.  */
3617     if (env->cp15.c1_sys & SCTLR_V) {
3618         /* when enabled, base address cannot be remapped.  */
3619         addr += 0xffff0000;
3620     } else {
3621         /* ARM v7 architectures provide a vector base address register to remap
3622          * the interrupt vector table.
3623          * This register is only followed in non-monitor mode, and has a secure
3624          * and un-secure copy. Since the cpu is always in a un-secure operation
3625          * and is never in monitor mode this feature is always active.
3626          * Note: only bits 31:5 are valid.
3627          */
3628         addr += env->cp15.vbar_el[1];
3629     }
3630     switch_mode (env, new_mode);
3631     /* For exceptions taken to AArch32 we must clear the SS bit in both
3632      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
3633      */
3634     env->uncached_cpsr &= ~PSTATE_SS;
3635     env->spsr = cpsr_read(env);
3636     /* Clear IT bits.  */
3637     env->condexec_bits = 0;
3638     /* Switch to the new mode, and to the correct instruction set.  */
3639     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3640     env->daif |= mask;
3641     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3642      * and we should just guard the thumb mode on V4 */
3643     if (arm_feature(env, ARM_FEATURE_V4T)) {
3644         env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3645     }
3646     env->regs[14] = env->regs[15] + offset;
3647     env->regs[15] = addr;
3648     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
3649 }
3650
3651 /* Check section/page access permissions.
3652    Returns the page protection flags, or zero if the access is not
3653    permitted.  */
3654 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3655                            int access_type, int is_user)
3656 {
3657   int prot_ro;
3658
3659   if (domain_prot == 3) {
3660     return PAGE_READ | PAGE_WRITE;
3661   }
3662
3663   if (access_type == 1)
3664       prot_ro = 0;
3665   else
3666       prot_ro = PAGE_READ;
3667
3668   switch (ap) {
3669   case 0:
3670       if (arm_feature(env, ARM_FEATURE_V7)) {
3671           return 0;
3672       }
3673       if (access_type == 1)
3674           return 0;
3675       switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3676       case SCTLR_S:
3677           return is_user ? 0 : PAGE_READ;
3678       case SCTLR_R:
3679           return PAGE_READ;
3680       default:
3681           return 0;
3682       }
3683   case 1:
3684       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3685   case 2:
3686       if (is_user)
3687           return prot_ro;
3688       else
3689           return PAGE_READ | PAGE_WRITE;
3690   case 3:
3691       return PAGE_READ | PAGE_WRITE;
3692   case 4: /* Reserved.  */
3693       return 0;
3694   case 5:
3695       return is_user ? 0 : prot_ro;
3696   case 6:
3697       return prot_ro;
3698   case 7:
3699       if (!arm_feature (env, ARM_FEATURE_V6K))
3700           return 0;
3701       return prot_ro;
3702   default:
3703       abort();
3704   }
3705 }
3706
3707 static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
3708                                          uint32_t address)
3709 {
3710     if (address & env->cp15.c2_mask) {
3711         if ((env->cp15.c2_control & TTBCR_PD1)) {
3712             /* Translation table walk disabled for TTBR1 */
3713             return false;
3714         }
3715         *table = env->cp15.ttbr1_el1 & 0xffffc000;
3716     } else {
3717         if ((env->cp15.c2_control & TTBCR_PD0)) {
3718             /* Translation table walk disabled for TTBR0 */
3719             return false;
3720         }
3721         *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3722     }
3723     *table |= (address >> 18) & 0x3ffc;
3724     return true;
3725 }
3726
3727 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3728                             int is_user, hwaddr *phys_ptr,
3729                             int *prot, target_ulong *page_size)
3730 {
3731     CPUState *cs = CPU(arm_env_get_cpu(env));
3732     int code;
3733     uint32_t table;
3734     uint32_t desc;
3735     int type;
3736     int ap;
3737     int domain = 0;
3738     int domain_prot;
3739     hwaddr phys_addr;
3740
3741     /* Pagetable walk.  */
3742     /* Lookup l1 descriptor.  */
3743     if (!get_level1_table_address(env, &table, address)) {
3744         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3745         code = 5;
3746         goto do_fault;
3747     }
3748     desc = ldl_phys(cs->as, table);
3749     type = (desc & 3);
3750     domain = (desc >> 5) & 0x0f;
3751     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3752     if (type == 0) {
3753         /* Section translation fault.  */
3754         code = 5;
3755         goto do_fault;
3756     }
3757     if (domain_prot == 0 || domain_prot == 2) {
3758         if (type == 2)
3759             code = 9; /* Section domain fault.  */
3760         else
3761             code = 11; /* Page domain fault.  */
3762         goto do_fault;
3763     }
3764     if (type == 2) {
3765         /* 1Mb section.  */
3766         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3767         ap = (desc >> 10) & 3;
3768         code = 13;
3769         *page_size = 1024 * 1024;
3770     } else {
3771         /* Lookup l2 entry.  */
3772         if (type == 1) {
3773             /* Coarse pagetable.  */
3774             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3775         } else {
3776             /* Fine pagetable.  */
3777             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3778         }
3779         desc = ldl_phys(cs->as, table);
3780         switch (desc & 3) {
3781         case 0: /* Page translation fault.  */
3782             code = 7;
3783             goto do_fault;
3784         case 1: /* 64k page.  */
3785             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3786             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3787             *page_size = 0x10000;
3788             break;
3789         case 2: /* 4k page.  */
3790             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3791             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3792             *page_size = 0x1000;
3793             break;
3794         case 3: /* 1k page.  */
3795             if (type == 1) {
3796                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3797                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3798                 } else {
3799                     /* Page translation fault.  */
3800                     code = 7;
3801                     goto do_fault;
3802                 }
3803             } else {
3804                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3805             }
3806             ap = (desc >> 4) & 3;
3807             *page_size = 0x400;
3808             break;
3809         default:
3810             /* Never happens, but compiler isn't smart enough to tell.  */
3811             abort();
3812         }
3813         code = 15;
3814     }
3815     *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3816     if (!*prot) {
3817         /* Access permission fault.  */
3818         goto do_fault;
3819     }
3820     *prot |= PAGE_EXEC;
3821     *phys_ptr = phys_addr;
3822     return 0;
3823 do_fault:
3824     return code | (domain << 4);
3825 }
3826
3827 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3828                             int is_user, hwaddr *phys_ptr,
3829                             int *prot, target_ulong *page_size)
3830 {
3831     CPUState *cs = CPU(arm_env_get_cpu(env));
3832     int code;
3833     uint32_t table;
3834     uint32_t desc;
3835     uint32_t xn;
3836     uint32_t pxn = 0;
3837     int type;
3838     int ap;
3839     int domain = 0;
3840     int domain_prot;
3841     hwaddr phys_addr;
3842
3843     /* Pagetable walk.  */
3844     /* Lookup l1 descriptor.  */
3845     if (!get_level1_table_address(env, &table, address)) {
3846         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3847         code = 5;
3848         goto do_fault;
3849     }
3850     desc = ldl_phys(cs->as, table);
3851     type = (desc & 3);
3852     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3853         /* Section translation fault, or attempt to use the encoding
3854          * which is Reserved on implementations without PXN.
3855          */
3856         code = 5;
3857         goto do_fault;
3858     }
3859     if ((type == 1) || !(desc & (1 << 18))) {
3860         /* Page or Section.  */
3861         domain = (desc >> 5) & 0x0f;
3862     }
3863     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3864     if (domain_prot == 0 || domain_prot == 2) {
3865         if (type != 1) {
3866             code = 9; /* Section domain fault.  */
3867         } else {
3868             code = 11; /* Page domain fault.  */
3869         }
3870         goto do_fault;
3871     }
3872     if (type != 1) {
3873         if (desc & (1 << 18)) {
3874             /* Supersection.  */
3875             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3876             *page_size = 0x1000000;
3877         } else {
3878             /* Section.  */
3879             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3880             *page_size = 0x100000;
3881         }
3882         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3883         xn = desc & (1 << 4);
3884         pxn = desc & 1;
3885         code = 13;
3886     } else {
3887         if (arm_feature(env, ARM_FEATURE_PXN)) {
3888             pxn = (desc >> 2) & 1;
3889         }
3890         /* Lookup l2 entry.  */
3891         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3892         desc = ldl_phys(cs->as, table);
3893         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3894         switch (desc & 3) {
3895         case 0: /* Page translation fault.  */
3896             code = 7;
3897             goto do_fault;
3898         case 1: /* 64k page.  */
3899             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3900             xn = desc & (1 << 15);
3901             *page_size = 0x10000;
3902             break;
3903         case 2: case 3: /* 4k page.  */
3904             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3905             xn = desc & 1;
3906             *page_size = 0x1000;
3907             break;
3908         default:
3909             /* Never happens, but compiler isn't smart enough to tell.  */
3910             abort();
3911         }
3912         code = 15;
3913     }
3914     if (domain_prot == 3) {
3915         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3916     } else {
3917         if (pxn && !is_user) {
3918             xn = 1;
3919         }
3920         if (xn && access_type == 2)
3921             goto do_fault;
3922
3923         /* The simplified model uses AP[0] as an access control bit.  */
3924         if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3925             /* Access flag fault.  */
3926             code = (code == 15) ? 6 : 3;
3927             goto do_fault;
3928         }
3929         *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3930         if (!*prot) {
3931             /* Access permission fault.  */
3932             goto do_fault;
3933         }
3934         if (!xn) {
3935             *prot |= PAGE_EXEC;
3936         }
3937     }
3938     *phys_ptr = phys_addr;
3939     return 0;
3940 do_fault:
3941     return code | (domain << 4);
3942 }
3943
3944 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3945  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3946  */
3947 typedef enum {
3948     translation_fault = 1,
3949     access_fault = 2,
3950     permission_fault = 3,
3951 } MMUFaultType;
3952
3953 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
3954                               int access_type, int is_user,
3955                               hwaddr *phys_ptr, int *prot,
3956                               target_ulong *page_size_ptr)
3957 {
3958     CPUState *cs = CPU(arm_env_get_cpu(env));
3959     /* Read an LPAE long-descriptor translation table. */
3960     MMUFaultType fault_type = translation_fault;
3961     uint32_t level = 1;
3962     uint32_t epd;
3963     int32_t tsz;
3964     uint32_t tg;
3965     uint64_t ttbr;
3966     int ttbr_select;
3967     hwaddr descaddr, descmask;
3968     uint32_t tableattrs;
3969     target_ulong page_size;
3970     uint32_t attrs;
3971     int32_t granule_sz = 9;
3972     int32_t va_size = 32;
3973     int32_t tbi = 0;
3974
3975     if (arm_el_is_aa64(env, 1)) {
3976         va_size = 64;
3977         if (extract64(address, 55, 1))
3978             tbi = extract64(env->cp15.c2_control, 38, 1);
3979         else
3980             tbi = extract64(env->cp15.c2_control, 37, 1);
3981         tbi *= 8;
3982     }
3983
3984     /* Determine whether this address is in the region controlled by
3985      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3986      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3987      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3988      */
3989     uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
3990     if (arm_el_is_aa64(env, 1)) {
3991         t0sz = MIN(t0sz, 39);
3992         t0sz = MAX(t0sz, 16);
3993     }
3994     uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
3995     if (arm_el_is_aa64(env, 1)) {
3996         t1sz = MIN(t1sz, 39);
3997         t1sz = MAX(t1sz, 16);
3998     }
3999     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
4000         /* there is a ttbr0 region and we are in it (high bits all zero) */
4001         ttbr_select = 0;
4002     } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
4003         /* there is a ttbr1 region and we are in it (high bits all one) */
4004         ttbr_select = 1;
4005     } else if (!t0sz) {
4006         /* ttbr0 region is "everything not in the ttbr1 region" */
4007         ttbr_select = 0;
4008     } else if (!t1sz) {
4009         /* ttbr1 region is "everything not in the ttbr0 region" */
4010         ttbr_select = 1;
4011     } else {
4012         /* in the gap between the two regions, this is a Translation fault */
4013         fault_type = translation_fault;
4014         goto do_fault;
4015     }
4016
4017     /* Note that QEMU ignores shareability and cacheability attributes,
4018      * so we don't need to do anything with the SH, ORGN, IRGN fields
4019      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
4020      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
4021      * implement any ASID-like capability so we can ignore it (instead
4022      * we will always flush the TLB any time the ASID is changed).
4023      */
4024     if (ttbr_select == 0) {
4025         ttbr = env->cp15.ttbr0_el1;
4026         epd = extract32(env->cp15.c2_control, 7, 1);
4027         tsz = t0sz;
4028
4029         tg = extract32(env->cp15.c2_control, 14, 2);
4030         if (tg == 1) { /* 64KB pages */
4031             granule_sz = 13;
4032         }
4033         if (tg == 2) { /* 16KB pages */
4034             granule_sz = 11;
4035         }
4036     } else {
4037         ttbr = env->cp15.ttbr1_el1;
4038         epd = extract32(env->cp15.c2_control, 23, 1);
4039         tsz = t1sz;
4040
4041         tg = extract32(env->cp15.c2_control, 30, 2);
4042         if (tg == 3)  { /* 64KB pages */
4043             granule_sz = 13;
4044         }
4045         if (tg == 1) { /* 16KB pages */
4046             granule_sz = 11;
4047         }
4048     }
4049
4050     if (epd) {
4051         /* Translation table walk disabled => Translation fault on TLB miss */
4052         goto do_fault;
4053     }
4054
4055     /* The starting level depends on the virtual address size which can be
4056      * up to 48-bits and the translation granule size.
4057      */
4058     if ((va_size - tsz) > (granule_sz * 4 + 3)) {
4059         level = 0;
4060     } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
4061         level = 1;
4062     } else {
4063         level = 2;
4064     }
4065
4066     /* Clear the vaddr bits which aren't part of the within-region address,
4067      * so that we don't have to special case things when calculating the
4068      * first descriptor address.
4069      */
4070     if (tsz) {
4071         address &= (1ULL << (va_size - tsz)) - 1;
4072     }
4073
4074     descmask = (1ULL << (granule_sz + 3)) - 1;
4075
4076     /* Now we can extract the actual base address from the TTBR */
4077     descaddr = extract64(ttbr, 0, 48);
4078     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
4079
4080     tableattrs = 0;
4081     for (;;) {
4082         uint64_t descriptor;
4083
4084         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
4085         descaddr &= ~7ULL;
4086         descriptor = ldq_phys(cs->as, descaddr);
4087         if (!(descriptor & 1) ||
4088             (!(descriptor & 2) && (level == 3))) {
4089             /* Invalid, or the Reserved level 3 encoding */
4090             goto do_fault;
4091         }
4092         descaddr = descriptor & 0xfffffff000ULL;
4093
4094         if ((descriptor & 2) && (level < 3)) {
4095             /* Table entry. The top five bits are attributes which  may
4096              * propagate down through lower levels of the table (and
4097              * which are all arranged so that 0 means "no effect", so
4098              * we can gather them up by ORing in the bits at each level).
4099              */
4100             tableattrs |= extract64(descriptor, 59, 5);
4101             level++;
4102             continue;
4103         }
4104         /* Block entry at level 1 or 2, or page entry at level 3.
4105          * These are basically the same thing, although the number
4106          * of bits we pull in from the vaddr varies.
4107          */
4108         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
4109         descaddr |= (address & (page_size - 1));
4110         /* Extract attributes from the descriptor and merge with table attrs */
4111         attrs = extract64(descriptor, 2, 10)
4112             | (extract64(descriptor, 52, 12) << 10);
4113         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
4114         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
4115         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
4116          * means "force PL1 access only", which means forcing AP[1] to 0.
4117          */
4118         if (extract32(tableattrs, 2, 1)) {
4119             attrs &= ~(1 << 4);
4120         }
4121         /* Since we're always in the Non-secure state, NSTable is ignored. */
4122         break;
4123     }
4124     /* Here descaddr is the final physical address, and attributes
4125      * are all in attrs.
4126      */
4127     fault_type = access_fault;
4128     if ((attrs & (1 << 8)) == 0) {
4129         /* Access flag */
4130         goto do_fault;
4131     }
4132     fault_type = permission_fault;
4133     if (is_user && !(attrs & (1 << 4))) {
4134         /* Unprivileged access not enabled */
4135         goto do_fault;
4136     }
4137     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4138     if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) ||
4139         (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) ||
4140         (!is_user && (attrs & (1 << 11)))) {
4141         /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
4142          * treat XN/UXN as UXN for v8.
4143          */
4144         if (access_type == 2) {
4145             goto do_fault;
4146         }
4147         *prot &= ~PAGE_EXEC;
4148     }
4149     if (attrs & (1 << 5)) {
4150         /* Write access forbidden */
4151         if (access_type == 1) {
4152             goto do_fault;
4153         }
4154         *prot &= ~PAGE_WRITE;
4155     }
4156
4157     *phys_ptr = descaddr;
4158     *page_size_ptr = page_size;
4159     return 0;
4160
4161 do_fault:
4162     /* Long-descriptor format IFSR/DFSR value */
4163     return (1 << 9) | (fault_type << 2) | level;
4164 }
4165
4166 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
4167                              int access_type, int is_user,
4168                              hwaddr *phys_ptr, int *prot)
4169 {
4170     int n;
4171     uint32_t mask;
4172     uint32_t base;
4173
4174     *phys_ptr = address;
4175     for (n = 7; n >= 0; n--) {
4176         base = env->cp15.c6_region[n];
4177         if ((base & 1) == 0)
4178             continue;
4179         mask = 1 << ((base >> 1) & 0x1f);
4180         /* Keep this shift separate from the above to avoid an
4181            (undefined) << 32.  */
4182         mask = (mask << 1) - 1;
4183         if (((base ^ address) & ~mask) == 0)
4184             break;
4185     }
4186     if (n < 0)
4187         return 2;
4188
4189     if (access_type == 2) {
4190         mask = env->cp15.pmsav5_insn_ap;
4191     } else {
4192         mask = env->cp15.pmsav5_data_ap;
4193     }
4194     mask = (mask >> (n * 4)) & 0xf;
4195     switch (mask) {
4196     case 0:
4197         return 1;
4198     case 1:
4199         if (is_user)
4200           return 1;
4201         *prot = PAGE_READ | PAGE_WRITE;
4202         break;
4203     case 2:
4204         *prot = PAGE_READ;
4205         if (!is_user)
4206             *prot |= PAGE_WRITE;
4207         break;
4208     case 3:
4209         *prot = PAGE_READ | PAGE_WRITE;
4210         break;
4211     case 5:
4212         if (is_user)
4213             return 1;
4214         *prot = PAGE_READ;
4215         break;
4216     case 6:
4217         *prot = PAGE_READ;
4218         break;
4219     default:
4220         /* Bad permission.  */
4221         return 1;
4222     }
4223     *prot |= PAGE_EXEC;
4224     return 0;
4225 }
4226
4227 /* get_phys_addr - get the physical address for this virtual address
4228  *
4229  * Find the physical address corresponding to the given virtual address,
4230  * by doing a translation table walk on MMU based systems or using the
4231  * MPU state on MPU based systems.
4232  *
4233  * Returns 0 if the translation was successful. Otherwise, phys_ptr,
4234  * prot and page_size are not filled in, and the return value provides
4235  * information on why the translation aborted, in the format of a
4236  * DFSR/IFSR fault register, with the following caveats:
4237  *  * we honour the short vs long DFSR format differences.
4238  *  * the WnR bit is never set (the caller must do this).
4239  *  * for MPU based systems we don't bother to return a full FSR format
4240  *    value.
4241  *
4242  * @env: CPUARMState
4243  * @address: virtual address to get physical address for
4244  * @access_type: 0 for read, 1 for write, 2 for execute
4245  * @is_user: 0 for privileged access, 1 for user
4246  * @phys_ptr: set to the physical address corresponding to the virtual address
4247  * @prot: set to the permissions for the page containing phys_ptr
4248  * @page_size: set to the size of the page containing phys_ptr
4249  */
4250 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
4251                                 int access_type, int is_user,
4252                                 hwaddr *phys_ptr, int *prot,
4253                                 target_ulong *page_size)
4254 {
4255     /* Fast Context Switch Extension.  */
4256     if (address < 0x02000000)
4257         address += env->cp15.c13_fcse;
4258
4259     if ((env->cp15.c1_sys & SCTLR_M) == 0) {
4260         /* MMU/MPU disabled.  */
4261         *phys_ptr = address;
4262         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4263         *page_size = TARGET_PAGE_SIZE;
4264         return 0;
4265     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
4266         *page_size = TARGET_PAGE_SIZE;
4267         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
4268                                  prot);
4269     } else if (extended_addresses_enabled(env)) {
4270         return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
4271                                   prot, page_size);
4272     } else if (env->cp15.c1_sys & SCTLR_XP) {
4273         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
4274                                 prot, page_size);
4275     } else {
4276         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
4277                                 prot, page_size);
4278     }
4279 }
4280
4281 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
4282                              int access_type, int mmu_idx)
4283 {
4284     ARMCPU *cpu = ARM_CPU(cs);
4285     CPUARMState *env = &cpu->env;
4286     hwaddr phys_addr;
4287     target_ulong page_size;
4288     int prot;
4289     int ret, is_user;
4290     uint32_t syn;
4291     bool same_el = (arm_current_pl(env) != 0);
4292
4293     is_user = mmu_idx == MMU_USER_IDX;
4294     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
4295                         &page_size);
4296     if (ret == 0) {
4297         /* Map a single [sub]page.  */
4298         phys_addr &= TARGET_PAGE_MASK;
4299         address &= TARGET_PAGE_MASK;
4300         tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
4301         return 0;
4302     }
4303
4304     /* AArch64 syndrome does not have an LPAE bit */
4305     syn = ret & ~(1 << 9);
4306
4307     /* For insn and data aborts we assume there is no instruction syndrome
4308      * information; this is always true for exceptions reported to EL1.
4309      */
4310     if (access_type == 2) {
4311         syn = syn_insn_abort(same_el, 0, 0, syn);
4312         cs->exception_index = EXCP_PREFETCH_ABORT;
4313     } else {
4314         syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
4315         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
4316             ret |= (1 << 11);
4317         }
4318         cs->exception_index = EXCP_DATA_ABORT;
4319     }
4320
4321     env->exception.syndrome = syn;
4322     env->exception.vaddress = address;
4323     env->exception.fsr = ret;
4324     return 1;
4325 }
4326
4327 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4328 {
4329     ARMCPU *cpu = ARM_CPU(cs);
4330     hwaddr phys_addr;
4331     target_ulong page_size;
4332     int prot;
4333     int ret;
4334
4335     ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
4336
4337     if (ret != 0) {
4338         return -1;
4339     }
4340
4341     return phys_addr;
4342 }
4343
4344 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4345 {
4346     if ((env->uncached_cpsr & CPSR_M) == mode) {
4347         env->regs[13] = val;
4348     } else {
4349         env->banked_r13[bank_number(mode)] = val;
4350     }
4351 }
4352
4353 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4354 {
4355     if ((env->uncached_cpsr & CPSR_M) == mode) {
4356         return env->regs[13];
4357     } else {
4358         return env->banked_r13[bank_number(mode)];
4359     }
4360 }
4361
4362 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4363 {
4364     ARMCPU *cpu = arm_env_get_cpu(env);
4365
4366     switch (reg) {
4367     case 0: /* APSR */
4368         return xpsr_read(env) & 0xf8000000;
4369     case 1: /* IAPSR */
4370         return xpsr_read(env) & 0xf80001ff;
4371     case 2: /* EAPSR */
4372         return xpsr_read(env) & 0xff00fc00;
4373     case 3: /* xPSR */
4374         return xpsr_read(env) & 0xff00fdff;
4375     case 5: /* IPSR */
4376         return xpsr_read(env) & 0x000001ff;
4377     case 6: /* EPSR */
4378         return xpsr_read(env) & 0x0700fc00;
4379     case 7: /* IEPSR */
4380         return xpsr_read(env) & 0x0700edff;
4381     case 8: /* MSP */
4382         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
4383     case 9: /* PSP */
4384         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
4385     case 16: /* PRIMASK */
4386         return (env->daif & PSTATE_I) != 0;
4387     case 17: /* BASEPRI */
4388     case 18: /* BASEPRI_MAX */
4389         return env->v7m.basepri;
4390     case 19: /* FAULTMASK */
4391         return (env->daif & PSTATE_F) != 0;
4392     case 20: /* CONTROL */
4393         return env->v7m.control;
4394     default:
4395         /* ??? For debugging only.  */
4396         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
4397         return 0;
4398     }
4399 }
4400
4401 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4402 {
4403     ARMCPU *cpu = arm_env_get_cpu(env);
4404
4405     switch (reg) {
4406     case 0: /* APSR */
4407         xpsr_write(env, val, 0xf8000000);
4408         break;
4409     case 1: /* IAPSR */
4410         xpsr_write(env, val, 0xf8000000);
4411         break;
4412     case 2: /* EAPSR */
4413         xpsr_write(env, val, 0xfe00fc00);
4414         break;
4415     case 3: /* xPSR */
4416         xpsr_write(env, val, 0xfe00fc00);
4417         break;
4418     case 5: /* IPSR */
4419         /* IPSR bits are readonly.  */
4420         break;
4421     case 6: /* EPSR */
4422         xpsr_write(env, val, 0x0600fc00);
4423         break;
4424     case 7: /* IEPSR */
4425         xpsr_write(env, val, 0x0600fc00);
4426         break;
4427     case 8: /* MSP */
4428         if (env->v7m.current_sp)
4429             env->v7m.other_sp = val;
4430         else
4431             env->regs[13] = val;
4432         break;
4433     case 9: /* PSP */
4434         if (env->v7m.current_sp)
4435             env->regs[13] = val;
4436         else
4437             env->v7m.other_sp = val;
4438         break;
4439     case 16: /* PRIMASK */
4440         if (val & 1) {
4441             env->daif |= PSTATE_I;
4442         } else {
4443             env->daif &= ~PSTATE_I;
4444         }
4445         break;
4446     case 17: /* BASEPRI */
4447         env->v7m.basepri = val & 0xff;
4448         break;
4449     case 18: /* BASEPRI_MAX */
4450         val &= 0xff;
4451         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
4452             env->v7m.basepri = val;
4453         break;
4454     case 19: /* FAULTMASK */
4455         if (val & 1) {
4456             env->daif |= PSTATE_F;
4457         } else {
4458             env->daif &= ~PSTATE_F;
4459         }
4460         break;
4461     case 20: /* CONTROL */
4462         env->v7m.control = val & 3;
4463         switch_v7m_sp(env, (val & 2) != 0);
4464         break;
4465     default:
4466         /* ??? For debugging only.  */
4467         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
4468         return;
4469     }
4470 }
4471
4472 #endif
4473
4474 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
4475 {
4476     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4477      * Note that we do not implement the (architecturally mandated)
4478      * alignment fault for attempts to use this on Device memory
4479      * (which matches the usual QEMU behaviour of not implementing either
4480      * alignment faults or any memory attribute handling).
4481      */
4482
4483     ARMCPU *cpu = arm_env_get_cpu(env);
4484     uint64_t blocklen = 4 << cpu->dcz_blocksize;
4485     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
4486
4487 #ifndef CONFIG_USER_ONLY
4488     {
4489         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4490          * the block size so we might have to do more than one TLB lookup.
4491          * We know that in fact for any v8 CPU the page size is at least 4K
4492          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4493          * 1K as an artefact of legacy v5 subpage support being present in the
4494          * same QEMU executable.
4495          */
4496         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
4497         void *hostaddr[maxidx];
4498         int try, i;
4499
4500         for (try = 0; try < 2; try++) {
4501
4502             for (i = 0; i < maxidx; i++) {
4503                 hostaddr[i] = tlb_vaddr_to_host(env,
4504                                                 vaddr + TARGET_PAGE_SIZE * i,
4505                                                 1, cpu_mmu_index(env));
4506                 if (!hostaddr[i]) {
4507                     break;
4508                 }
4509             }
4510             if (i == maxidx) {
4511                 /* If it's all in the TLB it's fair game for just writing to;
4512                  * we know we don't need to update dirty status, etc.
4513                  */
4514                 for (i = 0; i < maxidx - 1; i++) {
4515                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
4516                 }
4517                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
4518                 return;
4519             }
4520             /* OK, try a store and see if we can populate the tlb. This
4521              * might cause an exception if the memory isn't writable,
4522              * in which case we will longjmp out of here. We must for
4523              * this purpose use the actual register value passed to us
4524              * so that we get the fault address right.
4525              */
4526             helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
4527             /* Now we can populate the other TLB entries, if any */
4528             for (i = 0; i < maxidx; i++) {
4529                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
4530                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
4531                     helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
4532                 }
4533             }
4534         }
4535
4536         /* Slow path (probably attempt to do this to an I/O device or
4537          * similar, or clearing of a block of code we have translations
4538          * cached for). Just do a series of byte writes as the architecture
4539          * demands. It's not worth trying to use a cpu_physical_memory_map(),
4540          * memset(), unmap() sequence here because:
4541          *  + we'd need to account for the blocksize being larger than a page
4542          *  + the direct-RAM access case is almost always going to be dealt
4543          *    with in the fastpath code above, so there's no speed benefit
4544          *  + we would have to deal with the map returning NULL because the
4545          *    bounce buffer was in use
4546          */
4547         for (i = 0; i < blocklen; i++) {
4548             helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
4549         }
4550     }
4551 #else
4552     memset(g2h(vaddr), 0, blocklen);
4553 #endif
4554 }
4555
4556 /* Note that signed overflow is undefined in C.  The following routines are
4557    careful to use unsigned types where modulo arithmetic is required.
4558    Failure to do so _will_ break on newer gcc.  */
4559
4560 /* Signed saturating arithmetic.  */
4561
4562 /* Perform 16-bit signed saturating addition.  */
4563 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
4564 {
4565     uint16_t res;
4566
4567     res = a + b;
4568     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
4569         if (a & 0x8000)
4570             res = 0x8000;
4571         else
4572             res = 0x7fff;
4573     }
4574     return res;
4575 }
4576
4577 /* Perform 8-bit signed saturating addition.  */
4578 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
4579 {
4580     uint8_t res;
4581
4582     res = a + b;
4583     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
4584         if (a & 0x80)
4585             res = 0x80;
4586         else
4587             res = 0x7f;
4588     }
4589     return res;
4590 }
4591
4592 /* Perform 16-bit signed saturating subtraction.  */
4593 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
4594 {
4595     uint16_t res;
4596
4597     res = a - b;
4598     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
4599         if (a & 0x8000)
4600             res = 0x8000;
4601         else
4602             res = 0x7fff;
4603     }
4604     return res;
4605 }
4606
4607 /* Perform 8-bit signed saturating subtraction.  */
4608 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
4609 {
4610     uint8_t res;
4611
4612     res = a - b;
4613     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
4614         if (a & 0x80)
4615             res = 0x80;
4616         else
4617             res = 0x7f;
4618     }
4619     return res;
4620 }
4621
4622 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4623 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4624 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
4625 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
4626 #define PFX q
4627
4628 #include "op_addsub.h"
4629
4630 /* Unsigned saturating arithmetic.  */
4631 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
4632 {
4633     uint16_t res;
4634     res = a + b;
4635     if (res < a)
4636         res = 0xffff;
4637     return res;
4638 }
4639
4640 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
4641 {
4642     if (a > b)
4643         return a - b;
4644     else
4645         return 0;
4646 }
4647
4648 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
4649 {
4650     uint8_t res;
4651     res = a + b;
4652     if (res < a)
4653         res = 0xff;
4654     return res;
4655 }
4656
4657 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
4658 {
4659     if (a > b)
4660         return a - b;
4661     else
4662         return 0;
4663 }
4664
4665 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4666 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4667 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
4668 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
4669 #define PFX uq
4670
4671 #include "op_addsub.h"
4672
4673 /* Signed modulo arithmetic.  */
4674 #define SARITH16(a, b, n, op) do { \
4675     int32_t sum; \
4676     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4677     RESULT(sum, n, 16); \
4678     if (sum >= 0) \
4679         ge |= 3 << (n * 2); \
4680     } while(0)
4681
4682 #define SARITH8(a, b, n, op) do { \
4683     int32_t sum; \
4684     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4685     RESULT(sum, n, 8); \
4686     if (sum >= 0) \
4687         ge |= 1 << n; \
4688     } while(0)
4689
4690
4691 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4692 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4693 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
4694 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
4695 #define PFX s
4696 #define ARITH_GE
4697
4698 #include "op_addsub.h"
4699
4700 /* Unsigned modulo arithmetic.  */
4701 #define ADD16(a, b, n) do { \
4702     uint32_t sum; \
4703     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4704     RESULT(sum, n, 16); \
4705     if ((sum >> 16) == 1) \
4706         ge |= 3 << (n * 2); \
4707     } while(0)
4708
4709 #define ADD8(a, b, n) do { \
4710     uint32_t sum; \
4711     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4712     RESULT(sum, n, 8); \
4713     if ((sum >> 8) == 1) \
4714         ge |= 1 << n; \
4715     } while(0)
4716
4717 #define SUB16(a, b, n) do { \
4718     uint32_t sum; \
4719     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4720     RESULT(sum, n, 16); \
4721     if ((sum >> 16) == 0) \
4722         ge |= 3 << (n * 2); \
4723     } while(0)
4724
4725 #define SUB8(a, b, n) do { \
4726     uint32_t sum; \
4727     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4728     RESULT(sum, n, 8); \
4729     if ((sum >> 8) == 0) \
4730         ge |= 1 << n; \
4731     } while(0)
4732
4733 #define PFX u
4734 #define ARITH_GE
4735
4736 #include "op_addsub.h"
4737
4738 /* Halved signed arithmetic.  */
4739 #define ADD16(a, b, n) \
4740   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4741 #define SUB16(a, b, n) \
4742   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4743 #define ADD8(a, b, n) \
4744   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4745 #define SUB8(a, b, n) \
4746   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4747 #define PFX sh
4748
4749 #include "op_addsub.h"
4750
4751 /* Halved unsigned arithmetic.  */
4752 #define ADD16(a, b, n) \
4753   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4754 #define SUB16(a, b, n) \
4755   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4756 #define ADD8(a, b, n) \
4757   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4758 #define SUB8(a, b, n) \
4759   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4760 #define PFX uh
4761
4762 #include "op_addsub.h"
4763
4764 static inline uint8_t do_usad(uint8_t a, uint8_t b)
4765 {
4766     if (a > b)
4767         return a - b;
4768     else
4769         return b - a;
4770 }
4771
4772 /* Unsigned sum of absolute byte differences.  */
4773 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
4774 {
4775     uint32_t sum;
4776     sum = do_usad(a, b);
4777     sum += do_usad(a >> 8, b >> 8);
4778     sum += do_usad(a >> 16, b >>16);
4779     sum += do_usad(a >> 24, b >> 24);
4780     return sum;
4781 }
4782
4783 /* For ARMv6 SEL instruction.  */
4784 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
4785 {
4786     uint32_t mask;
4787
4788     mask = 0;
4789     if (flags & 1)
4790         mask |= 0xff;
4791     if (flags & 2)
4792         mask |= 0xff00;
4793     if (flags & 4)
4794         mask |= 0xff0000;
4795     if (flags & 8)
4796         mask |= 0xff000000;
4797     return (a & mask) | (b & ~mask);
4798 }
4799
4800 /* VFP support.  We follow the convention used for VFP instructions:
4801    Single precision routines have a "s" suffix, double precision a
4802    "d" suffix.  */
4803
4804 /* Convert host exception flags to vfp form.  */
4805 static inline int vfp_exceptbits_from_host(int host_bits)
4806 {
4807     int target_bits = 0;
4808
4809     if (host_bits & float_flag_invalid)
4810         target_bits |= 1;
4811     if (host_bits & float_flag_divbyzero)
4812         target_bits |= 2;
4813     if (host_bits & float_flag_overflow)
4814         target_bits |= 4;
4815     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4816         target_bits |= 8;
4817     if (host_bits & float_flag_inexact)
4818         target_bits |= 0x10;
4819     if (host_bits & float_flag_input_denormal)
4820         target_bits |= 0x80;
4821     return target_bits;
4822 }
4823
4824 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4825 {
4826     int i;
4827     uint32_t fpscr;
4828
4829     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4830             | (env->vfp.vec_len << 16)
4831             | (env->vfp.vec_stride << 20);
4832     i = get_float_exception_flags(&env->vfp.fp_status);
4833     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4834     fpscr |= vfp_exceptbits_from_host(i);
4835     return fpscr;
4836 }
4837
4838 uint32_t vfp_get_fpscr(CPUARMState *env)
4839 {
4840     return HELPER(vfp_get_fpscr)(env);
4841 }
4842
4843 /* Convert vfp exception flags to target form.  */
4844 static inline int vfp_exceptbits_to_host(int target_bits)
4845 {
4846     int host_bits = 0;
4847
4848     if (target_bits & 1)
4849         host_bits |= float_flag_invalid;
4850     if (target_bits & 2)
4851         host_bits |= float_flag_divbyzero;
4852     if (target_bits & 4)
4853         host_bits |= float_flag_overflow;
4854     if (target_bits & 8)
4855         host_bits |= float_flag_underflow;
4856     if (target_bits & 0x10)
4857         host_bits |= float_flag_inexact;
4858     if (target_bits & 0x80)
4859         host_bits |= float_flag_input_denormal;
4860     return host_bits;
4861 }
4862
4863 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4864 {
4865     int i;
4866     uint32_t changed;
4867
4868     changed = env->vfp.xregs[ARM_VFP_FPSCR];
4869     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4870     env->vfp.vec_len = (val >> 16) & 7;
4871     env->vfp.vec_stride = (val >> 20) & 3;
4872
4873     changed ^= val;
4874     if (changed & (3 << 22)) {
4875         i = (val >> 22) & 3;
4876         switch (i) {
4877         case FPROUNDING_TIEEVEN:
4878             i = float_round_nearest_even;
4879             break;
4880         case FPROUNDING_POSINF:
4881             i = float_round_up;
4882             break;
4883         case FPROUNDING_NEGINF:
4884             i = float_round_down;
4885             break;
4886         case FPROUNDING_ZERO:
4887             i = float_round_to_zero;
4888             break;
4889         }
4890         set_float_rounding_mode(i, &env->vfp.fp_status);
4891     }
4892     if (changed & (1 << 24)) {
4893         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4894         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4895     }
4896     if (changed & (1 << 25))
4897         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4898
4899     i = vfp_exceptbits_to_host(val);
4900     set_float_exception_flags(i, &env->vfp.fp_status);
4901     set_float_exception_flags(0, &env->vfp.standard_fp_status);
4902 }
4903
4904 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4905 {
4906     HELPER(vfp_set_fpscr)(env, val);
4907 }
4908
4909 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4910
4911 #define VFP_BINOP(name) \
4912 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4913 { \
4914     float_status *fpst = fpstp; \
4915     return float32_ ## name(a, b, fpst); \
4916 } \
4917 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4918 { \
4919     float_status *fpst = fpstp; \
4920     return float64_ ## name(a, b, fpst); \
4921 }
4922 VFP_BINOP(add)
4923 VFP_BINOP(sub)
4924 VFP_BINOP(mul)
4925 VFP_BINOP(div)
4926 VFP_BINOP(min)
4927 VFP_BINOP(max)
4928 VFP_BINOP(minnum)
4929 VFP_BINOP(maxnum)
4930 #undef VFP_BINOP
4931
4932 float32 VFP_HELPER(neg, s)(float32 a)
4933 {
4934     return float32_chs(a);
4935 }
4936
4937 float64 VFP_HELPER(neg, d)(float64 a)
4938 {
4939     return float64_chs(a);
4940 }
4941
4942 float32 VFP_HELPER(abs, s)(float32 a)
4943 {
4944     return float32_abs(a);
4945 }
4946
4947 float64 VFP_HELPER(abs, d)(float64 a)
4948 {
4949     return float64_abs(a);
4950 }
4951
4952 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4953 {
4954     return float32_sqrt(a, &env->vfp.fp_status);
4955 }
4956
4957 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4958 {
4959     return float64_sqrt(a, &env->vfp.fp_status);
4960 }
4961
4962 /* XXX: check quiet/signaling case */
4963 #define DO_VFP_cmp(p, type) \
4964 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
4965 { \
4966     uint32_t flags; \
4967     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4968     case 0: flags = 0x6; break; \
4969     case -1: flags = 0x8; break; \
4970     case 1: flags = 0x2; break; \
4971     default: case 2: flags = 0x3; break; \
4972     } \
4973     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4974         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4975 } \
4976 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4977 { \
4978     uint32_t flags; \
4979     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4980     case 0: flags = 0x6; break; \
4981     case -1: flags = 0x8; break; \
4982     case 1: flags = 0x2; break; \
4983     default: case 2: flags = 0x3; break; \
4984     } \
4985     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4986         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4987 }
4988 DO_VFP_cmp(s, float32)
4989 DO_VFP_cmp(d, float64)
4990 #undef DO_VFP_cmp
4991
4992 /* Integer to float and float to integer conversions */
4993
4994 #define CONV_ITOF(name, fsz, sign) \
4995     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4996 { \
4997     float_status *fpst = fpstp; \
4998     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4999 }
5000
5001 #define CONV_FTOI(name, fsz, sign, round) \
5002 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
5003 { \
5004     float_status *fpst = fpstp; \
5005     if (float##fsz##_is_any_nan(x)) { \
5006         float_raise(float_flag_invalid, fpst); \
5007         return 0; \
5008     } \
5009     return float##fsz##_to_##sign##int32##round(x, fpst); \
5010 }
5011
5012 #define FLOAT_CONVS(name, p, fsz, sign) \
5013 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
5014 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
5015 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
5016
5017 FLOAT_CONVS(si, s, 32, )
5018 FLOAT_CONVS(si, d, 64, )
5019 FLOAT_CONVS(ui, s, 32, u)
5020 FLOAT_CONVS(ui, d, 64, u)
5021
5022 #undef CONV_ITOF
5023 #undef CONV_FTOI
5024 #undef FLOAT_CONVS
5025
5026 /* floating point conversion */
5027 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
5028 {
5029     float64 r = float32_to_float64(x, &env->vfp.fp_status);
5030     /* ARM requires that S<->D conversion of any kind of NaN generates
5031      * a quiet NaN by forcing the most significant frac bit to 1.
5032      */
5033     return float64_maybe_silence_nan(r);
5034 }
5035
5036 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
5037 {
5038     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
5039     /* ARM requires that S<->D conversion of any kind of NaN generates
5040      * a quiet NaN by forcing the most significant frac bit to 1.
5041      */
5042     return float32_maybe_silence_nan(r);
5043 }
5044
5045 /* VFP3 fixed point conversion.  */
5046 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
5047 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
5048                                      void *fpstp) \
5049 { \
5050     float_status *fpst = fpstp; \
5051     float##fsz tmp; \
5052     tmp = itype##_to_##float##fsz(x, fpst); \
5053     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
5054 }
5055
5056 /* Notice that we want only input-denormal exception flags from the
5057  * scalbn operation: the other possible flags (overflow+inexact if
5058  * we overflow to infinity, output-denormal) aren't correct for the
5059  * complete scale-and-convert operation.
5060  */
5061 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
5062 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
5063                                              uint32_t shift, \
5064                                              void *fpstp) \
5065 { \
5066     float_status *fpst = fpstp; \
5067     int old_exc_flags = get_float_exception_flags(fpst); \
5068     float##fsz tmp; \
5069     if (float##fsz##_is_any_nan(x)) { \
5070         float_raise(float_flag_invalid, fpst); \
5071         return 0; \
5072     } \
5073     tmp = float##fsz##_scalbn(x, shift, fpst); \
5074     old_exc_flags |= get_float_exception_flags(fpst) \
5075         & float_flag_input_denormal; \
5076     set_float_exception_flags(old_exc_flags, fpst); \
5077     return float##fsz##_to_##itype##round(tmp, fpst); \
5078 }
5079
5080 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
5081 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5082 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
5083 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5084
5085 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
5086 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5087 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5088
5089 VFP_CONV_FIX(sh, d, 64, 64, int16)
5090 VFP_CONV_FIX(sl, d, 64, 64, int32)
5091 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
5092 VFP_CONV_FIX(uh, d, 64, 64, uint16)
5093 VFP_CONV_FIX(ul, d, 64, 64, uint32)
5094 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
5095 VFP_CONV_FIX(sh, s, 32, 32, int16)
5096 VFP_CONV_FIX(sl, s, 32, 32, int32)
5097 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
5098 VFP_CONV_FIX(uh, s, 32, 32, uint16)
5099 VFP_CONV_FIX(ul, s, 32, 32, uint32)
5100 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
5101 #undef VFP_CONV_FIX
5102 #undef VFP_CONV_FIX_FLOAT
5103 #undef VFP_CONV_FLOAT_FIX_ROUND
5104
5105 /* Set the current fp rounding mode and return the old one.
5106  * The argument is a softfloat float_round_ value.
5107  */
5108 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
5109 {
5110     float_status *fp_status = &env->vfp.fp_status;
5111
5112     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5113     set_float_rounding_mode(rmode, fp_status);
5114
5115     return prev_rmode;
5116 }
5117
5118 /* Set the current fp rounding mode in the standard fp status and return
5119  * the old one. This is for NEON instructions that need to change the
5120  * rounding mode but wish to use the standard FPSCR values for everything
5121  * else. Always set the rounding mode back to the correct value after
5122  * modifying it.
5123  * The argument is a softfloat float_round_ value.
5124  */
5125 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
5126 {
5127     float_status *fp_status = &env->vfp.standard_fp_status;
5128
5129     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5130     set_float_rounding_mode(rmode, fp_status);
5131
5132     return prev_rmode;
5133 }
5134
5135 /* Half precision conversions.  */
5136 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
5137 {
5138     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5139     float32 r = float16_to_float32(make_float16(a), ieee, s);
5140     if (ieee) {
5141         return float32_maybe_silence_nan(r);
5142     }
5143     return r;
5144 }
5145
5146 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
5147 {
5148     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5149     float16 r = float32_to_float16(a, ieee, s);
5150     if (ieee) {
5151         r = float16_maybe_silence_nan(r);
5152     }
5153     return float16_val(r);
5154 }
5155
5156 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5157 {
5158     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
5159 }
5160
5161 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5162 {
5163     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
5164 }
5165
5166 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5167 {
5168     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
5169 }
5170
5171 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5172 {
5173     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
5174 }
5175
5176 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
5177 {
5178     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5179     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
5180     if (ieee) {
5181         return float64_maybe_silence_nan(r);
5182     }
5183     return r;
5184 }
5185
5186 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
5187 {
5188     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5189     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
5190     if (ieee) {
5191         r = float16_maybe_silence_nan(r);
5192     }
5193     return float16_val(r);
5194 }
5195
5196 #define float32_two make_float32(0x40000000)
5197 #define float32_three make_float32(0x40400000)
5198 #define float32_one_point_five make_float32(0x3fc00000)
5199
5200 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
5201 {
5202     float_status *s = &env->vfp.standard_fp_status;
5203     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5204         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5205         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5206             float_raise(float_flag_input_denormal, s);
5207         }
5208         return float32_two;
5209     }
5210     return float32_sub(float32_two, float32_mul(a, b, s), s);
5211 }
5212
5213 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
5214 {
5215     float_status *s = &env->vfp.standard_fp_status;
5216     float32 product;
5217     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5218         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5219         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5220             float_raise(float_flag_input_denormal, s);
5221         }
5222         return float32_one_point_five;
5223     }
5224     product = float32_mul(a, b, s);
5225     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
5226 }
5227
5228 /* NEON helpers.  */
5229
5230 /* Constants 256 and 512 are used in some helpers; we avoid relying on
5231  * int->float conversions at run-time.  */
5232 #define float64_256 make_float64(0x4070000000000000LL)
5233 #define float64_512 make_float64(0x4080000000000000LL)
5234 #define float32_maxnorm make_float32(0x7f7fffff)
5235 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
5236
5237 /* Reciprocal functions
5238  *
5239  * The algorithm that must be used to calculate the estimate
5240  * is specified by the ARM ARM, see FPRecipEstimate()
5241  */
5242
5243 static float64 recip_estimate(float64 a, float_status *real_fp_status)
5244 {
5245     /* These calculations mustn't set any fp exception flags,
5246      * so we use a local copy of the fp_status.
5247      */
5248     float_status dummy_status = *real_fp_status;
5249     float_status *s = &dummy_status;
5250     /* q = (int)(a * 512.0) */
5251     float64 q = float64_mul(float64_512, a, s);
5252     int64_t q_int = float64_to_int64_round_to_zero(q, s);
5253
5254     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
5255     q = int64_to_float64(q_int, s);
5256     q = float64_add(q, float64_half, s);
5257     q = float64_div(q, float64_512, s);
5258     q = float64_div(float64_one, q, s);
5259
5260     /* s = (int)(256.0 * r + 0.5) */
5261     q = float64_mul(q, float64_256, s);
5262     q = float64_add(q, float64_half, s);
5263     q_int = float64_to_int64_round_to_zero(q, s);
5264
5265     /* return (double)s / 256.0 */
5266     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5267 }
5268
5269 /* Common wrapper to call recip_estimate */
5270 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
5271 {
5272     uint64_t val64 = float64_val(num);
5273     uint64_t frac = extract64(val64, 0, 52);
5274     int64_t exp = extract64(val64, 52, 11);
5275     uint64_t sbit;
5276     float64 scaled, estimate;
5277
5278     /* Generate the scaled number for the estimate function */
5279     if (exp == 0) {
5280         if (extract64(frac, 51, 1) == 0) {
5281             exp = -1;
5282             frac = extract64(frac, 0, 50) << 2;
5283         } else {
5284             frac = extract64(frac, 0, 51) << 1;
5285         }
5286     }
5287
5288     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
5289     scaled = make_float64((0x3feULL << 52)
5290                           | extract64(frac, 44, 8) << 44);
5291
5292     estimate = recip_estimate(scaled, fpst);
5293
5294     /* Build new result */
5295     val64 = float64_val(estimate);
5296     sbit = 0x8000000000000000ULL & val64;
5297     exp = off - exp;
5298     frac = extract64(val64, 0, 52);
5299
5300     if (exp == 0) {
5301         frac = 1ULL << 51 | extract64(frac, 1, 51);
5302     } else if (exp == -1) {
5303         frac = 1ULL << 50 | extract64(frac, 2, 50);
5304         exp = 0;
5305     }
5306
5307     return make_float64(sbit | (exp << 52) | frac);
5308 }
5309
5310 static bool round_to_inf(float_status *fpst, bool sign_bit)
5311 {
5312     switch (fpst->float_rounding_mode) {
5313     case float_round_nearest_even: /* Round to Nearest */
5314         return true;
5315     case float_round_up: /* Round to +Inf */
5316         return !sign_bit;
5317     case float_round_down: /* Round to -Inf */
5318         return sign_bit;
5319     case float_round_to_zero: /* Round to Zero */
5320         return false;
5321     }
5322
5323     g_assert_not_reached();
5324 }
5325
5326 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
5327 {
5328     float_status *fpst = fpstp;
5329     float32 f32 = float32_squash_input_denormal(input, fpst);
5330     uint32_t f32_val = float32_val(f32);
5331     uint32_t f32_sbit = 0x80000000ULL & f32_val;
5332     int32_t f32_exp = extract32(f32_val, 23, 8);
5333     uint32_t f32_frac = extract32(f32_val, 0, 23);
5334     float64 f64, r64;
5335     uint64_t r64_val;
5336     int64_t r64_exp;
5337     uint64_t r64_frac;
5338
5339     if (float32_is_any_nan(f32)) {
5340         float32 nan = f32;
5341         if (float32_is_signaling_nan(f32)) {
5342             float_raise(float_flag_invalid, fpst);
5343             nan = float32_maybe_silence_nan(f32);
5344         }
5345         if (fpst->default_nan_mode) {
5346             nan =  float32_default_nan;
5347         }
5348         return nan;
5349     } else if (float32_is_infinity(f32)) {
5350         return float32_set_sign(float32_zero, float32_is_neg(f32));
5351     } else if (float32_is_zero(f32)) {
5352         float_raise(float_flag_divbyzero, fpst);
5353         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5354     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
5355         /* Abs(value) < 2.0^-128 */
5356         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5357         if (round_to_inf(fpst, f32_sbit)) {
5358             return float32_set_sign(float32_infinity, float32_is_neg(f32));
5359         } else {
5360             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
5361         }
5362     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
5363         float_raise(float_flag_underflow, fpst);
5364         return float32_set_sign(float32_zero, float32_is_neg(f32));
5365     }
5366
5367
5368     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
5369     r64 = call_recip_estimate(f64, 253, fpst);
5370     r64_val = float64_val(r64);
5371     r64_exp = extract64(r64_val, 52, 11);
5372     r64_frac = extract64(r64_val, 0, 52);
5373
5374     /* result = sign : result_exp<7:0> : fraction<51:29>; */
5375     return make_float32(f32_sbit |
5376                         (r64_exp & 0xff) << 23 |
5377                         extract64(r64_frac, 29, 24));
5378 }
5379
5380 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
5381 {
5382     float_status *fpst = fpstp;
5383     float64 f64 = float64_squash_input_denormal(input, fpst);
5384     uint64_t f64_val = float64_val(f64);
5385     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
5386     int64_t f64_exp = extract64(f64_val, 52, 11);
5387     float64 r64;
5388     uint64_t r64_val;
5389     int64_t r64_exp;
5390     uint64_t r64_frac;
5391
5392     /* Deal with any special cases */
5393     if (float64_is_any_nan(f64)) {
5394         float64 nan = f64;
5395         if (float64_is_signaling_nan(f64)) {
5396             float_raise(float_flag_invalid, fpst);
5397             nan = float64_maybe_silence_nan(f64);
5398         }
5399         if (fpst->default_nan_mode) {
5400             nan =  float64_default_nan;
5401         }
5402         return nan;
5403     } else if (float64_is_infinity(f64)) {
5404         return float64_set_sign(float64_zero, float64_is_neg(f64));
5405     } else if (float64_is_zero(f64)) {
5406         float_raise(float_flag_divbyzero, fpst);
5407         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5408     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
5409         /* Abs(value) < 2.0^-1024 */
5410         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5411         if (round_to_inf(fpst, f64_sbit)) {
5412             return float64_set_sign(float64_infinity, float64_is_neg(f64));
5413         } else {
5414             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
5415         }
5416     } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
5417         float_raise(float_flag_underflow, fpst);
5418         return float64_set_sign(float64_zero, float64_is_neg(f64));
5419     }
5420
5421     r64 = call_recip_estimate(f64, 2045, fpst);
5422     r64_val = float64_val(r64);
5423     r64_exp = extract64(r64_val, 52, 11);
5424     r64_frac = extract64(r64_val, 0, 52);
5425
5426     /* result = sign : result_exp<10:0> : fraction<51:0> */
5427     return make_float64(f64_sbit |
5428                         ((r64_exp & 0x7ff) << 52) |
5429                         r64_frac);
5430 }
5431
5432 /* The algorithm that must be used to calculate the estimate
5433  * is specified by the ARM ARM.
5434  */
5435 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
5436 {
5437     /* These calculations mustn't set any fp exception flags,
5438      * so we use a local copy of the fp_status.
5439      */
5440     float_status dummy_status = *real_fp_status;
5441     float_status *s = &dummy_status;
5442     float64 q;
5443     int64_t q_int;
5444
5445     if (float64_lt(a, float64_half, s)) {
5446         /* range 0.25 <= a < 0.5 */
5447
5448         /* a in units of 1/512 rounded down */
5449         /* q0 = (int)(a * 512.0);  */
5450         q = float64_mul(float64_512, a, s);
5451         q_int = float64_to_int64_round_to_zero(q, s);
5452
5453         /* reciprocal root r */
5454         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
5455         q = int64_to_float64(q_int, s);
5456         q = float64_add(q, float64_half, s);
5457         q = float64_div(q, float64_512, s);
5458         q = float64_sqrt(q, s);
5459         q = float64_div(float64_one, q, s);
5460     } else {
5461         /* range 0.5 <= a < 1.0 */
5462
5463         /* a in units of 1/256 rounded down */
5464         /* q1 = (int)(a * 256.0); */
5465         q = float64_mul(float64_256, a, s);
5466         int64_t q_int = float64_to_int64_round_to_zero(q, s);
5467
5468         /* reciprocal root r */
5469         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5470         q = int64_to_float64(q_int, s);
5471         q = float64_add(q, float64_half, s);
5472         q = float64_div(q, float64_256, s);
5473         q = float64_sqrt(q, s);
5474         q = float64_div(float64_one, q, s);
5475     }
5476     /* r in units of 1/256 rounded to nearest */
5477     /* s = (int)(256.0 * r + 0.5); */
5478
5479     q = float64_mul(q, float64_256,s );
5480     q = float64_add(q, float64_half, s);
5481     q_int = float64_to_int64_round_to_zero(q, s);
5482
5483     /* return (double)s / 256.0;*/
5484     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5485 }
5486
5487 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
5488 {
5489     float_status *s = fpstp;
5490     float32 f32 = float32_squash_input_denormal(input, s);
5491     uint32_t val = float32_val(f32);
5492     uint32_t f32_sbit = 0x80000000 & val;
5493     int32_t f32_exp = extract32(val, 23, 8);
5494     uint32_t f32_frac = extract32(val, 0, 23);
5495     uint64_t f64_frac;
5496     uint64_t val64;
5497     int result_exp;
5498     float64 f64;
5499
5500     if (float32_is_any_nan(f32)) {
5501         float32 nan = f32;
5502         if (float32_is_signaling_nan(f32)) {
5503             float_raise(float_flag_invalid, s);
5504             nan = float32_maybe_silence_nan(f32);
5505         }
5506         if (s->default_nan_mode) {
5507             nan =  float32_default_nan;
5508         }
5509         return nan;
5510     } else if (float32_is_zero(f32)) {
5511         float_raise(float_flag_divbyzero, s);
5512         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5513     } else if (float32_is_neg(f32)) {
5514         float_raise(float_flag_invalid, s);
5515         return float32_default_nan;
5516     } else if (float32_is_infinity(f32)) {
5517         return float32_zero;
5518     }
5519
5520     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5521      * preserving the parity of the exponent.  */
5522
5523     f64_frac = ((uint64_t) f32_frac) << 29;
5524     if (f32_exp == 0) {
5525         while (extract64(f64_frac, 51, 1) == 0) {
5526             f64_frac = f64_frac << 1;
5527             f32_exp = f32_exp-1;
5528         }
5529         f64_frac = extract64(f64_frac, 0, 51) << 1;
5530     }
5531
5532     if (extract64(f32_exp, 0, 1) == 0) {
5533         f64 = make_float64(((uint64_t) f32_sbit) << 32
5534                            | (0x3feULL << 52)
5535                            | f64_frac);
5536     } else {
5537         f64 = make_float64(((uint64_t) f32_sbit) << 32
5538                            | (0x3fdULL << 52)
5539                            | f64_frac);
5540     }
5541
5542     result_exp = (380 - f32_exp) / 2;
5543
5544     f64 = recip_sqrt_estimate(f64, s);
5545
5546     val64 = float64_val(f64);
5547
5548     val = ((result_exp & 0xff) << 23)
5549         | ((val64 >> 29)  & 0x7fffff);
5550     return make_float32(val);
5551 }
5552
5553 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
5554 {
5555     float_status *s = fpstp;
5556     float64 f64 = float64_squash_input_denormal(input, s);
5557     uint64_t val = float64_val(f64);
5558     uint64_t f64_sbit = 0x8000000000000000ULL & val;
5559     int64_t f64_exp = extract64(val, 52, 11);
5560     uint64_t f64_frac = extract64(val, 0, 52);
5561     int64_t result_exp;
5562     uint64_t result_frac;
5563
5564     if (float64_is_any_nan(f64)) {
5565         float64 nan = f64;
5566         if (float64_is_signaling_nan(f64)) {
5567             float_raise(float_flag_invalid, s);
5568             nan = float64_maybe_silence_nan(f64);
5569         }
5570         if (s->default_nan_mode) {
5571             nan =  float64_default_nan;
5572         }
5573         return nan;
5574     } else if (float64_is_zero(f64)) {
5575         float_raise(float_flag_divbyzero, s);
5576         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5577     } else if (float64_is_neg(f64)) {
5578         float_raise(float_flag_invalid, s);
5579         return float64_default_nan;
5580     } else if (float64_is_infinity(f64)) {
5581         return float64_zero;
5582     }
5583
5584     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5585      * preserving the parity of the exponent.  */
5586
5587     if (f64_exp == 0) {
5588         while (extract64(f64_frac, 51, 1) == 0) {
5589             f64_frac = f64_frac << 1;
5590             f64_exp = f64_exp - 1;
5591         }
5592         f64_frac = extract64(f64_frac, 0, 51) << 1;
5593     }
5594
5595     if (extract64(f64_exp, 0, 1) == 0) {
5596         f64 = make_float64(f64_sbit
5597                            | (0x3feULL << 52)
5598                            | f64_frac);
5599     } else {
5600         f64 = make_float64(f64_sbit
5601                            | (0x3fdULL << 52)
5602                            | f64_frac);
5603     }
5604
5605     result_exp = (3068 - f64_exp) / 2;
5606
5607     f64 = recip_sqrt_estimate(f64, s);
5608
5609     result_frac = extract64(float64_val(f64), 0, 52);
5610
5611     return make_float64(f64_sbit |
5612                         ((result_exp & 0x7ff) << 52) |
5613                         result_frac);
5614 }
5615
5616 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
5617 {
5618     float_status *s = fpstp;
5619     float64 f64;
5620
5621     if ((a & 0x80000000) == 0) {
5622         return 0xffffffff;
5623     }
5624
5625     f64 = make_float64((0x3feULL << 52)
5626                        | ((int64_t)(a & 0x7fffffff) << 21));
5627
5628     f64 = recip_estimate(f64, s);
5629
5630     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5631 }
5632
5633 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
5634 {
5635     float_status *fpst = fpstp;
5636     float64 f64;
5637
5638     if ((a & 0xc0000000) == 0) {
5639         return 0xffffffff;
5640     }
5641
5642     if (a & 0x80000000) {
5643         f64 = make_float64((0x3feULL << 52)
5644                            | ((uint64_t)(a & 0x7fffffff) << 21));
5645     } else { /* bits 31-30 == '01' */
5646         f64 = make_float64((0x3fdULL << 52)
5647                            | ((uint64_t)(a & 0x3fffffff) << 22));
5648     }
5649
5650     f64 = recip_sqrt_estimate(f64, fpst);
5651
5652     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5653 }
5654
5655 /* VFPv4 fused multiply-accumulate */
5656 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
5657 {
5658     float_status *fpst = fpstp;
5659     return float32_muladd(a, b, c, 0, fpst);
5660 }
5661
5662 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
5663 {
5664     float_status *fpst = fpstp;
5665     return float64_muladd(a, b, c, 0, fpst);
5666 }
5667
5668 /* ARMv8 round to integral */
5669 float32 HELPER(rints_exact)(float32 x, void *fp_status)
5670 {
5671     return float32_round_to_int(x, fp_status);
5672 }
5673
5674 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
5675 {
5676     return float64_round_to_int(x, fp_status);
5677 }
5678
5679 float32 HELPER(rints)(float32 x, void *fp_status)
5680 {
5681     int old_flags = get_float_exception_flags(fp_status), new_flags;
5682     float32 ret;
5683
5684     ret = float32_round_to_int(x, fp_status);
5685
5686     /* Suppress any inexact exceptions the conversion produced */
5687     if (!(old_flags & float_flag_inexact)) {
5688         new_flags = get_float_exception_flags(fp_status);
5689         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5690     }
5691
5692     return ret;
5693 }
5694
5695 float64 HELPER(rintd)(float64 x, void *fp_status)
5696 {
5697     int old_flags = get_float_exception_flags(fp_status), new_flags;
5698     float64 ret;
5699
5700     ret = float64_round_to_int(x, fp_status);
5701
5702     new_flags = get_float_exception_flags(fp_status);
5703
5704     /* Suppress any inexact exceptions the conversion produced */
5705     if (!(old_flags & float_flag_inexact)) {
5706         new_flags = get_float_exception_flags(fp_status);
5707         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5708     }
5709
5710     return ret;
5711 }
5712
5713 /* Convert ARM rounding mode to softfloat */
5714 int arm_rmode_to_sf(int rmode)
5715 {
5716     switch (rmode) {
5717     case FPROUNDING_TIEAWAY:
5718         rmode = float_round_ties_away;
5719         break;
5720     case FPROUNDING_ODD:
5721         /* FIXME: add support for TIEAWAY and ODD */
5722         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
5723                       rmode);
5724     case FPROUNDING_TIEEVEN:
5725     default:
5726         rmode = float_round_nearest_even;
5727         break;
5728     case FPROUNDING_POSINF:
5729         rmode = float_round_up;
5730         break;
5731     case FPROUNDING_NEGINF:
5732         rmode = float_round_down;
5733         break;
5734     case FPROUNDING_ZERO:
5735         rmode = float_round_to_zero;
5736         break;
5737     }
5738     return rmode;
5739 }
5740
5741 /* CRC helpers.
5742  * The upper bytes of val (above the number specified by 'bytes') must have
5743  * been zeroed out by the caller.
5744  */
5745 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
5746 {
5747     uint8_t buf[4];
5748
5749     stl_le_p(buf, val);
5750
5751     /* zlib crc32 converts the accumulator and output to one's complement.  */
5752     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
5753 }
5754
5755 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
5756 {
5757     uint8_t buf[4];
5758
5759     stl_le_p(buf, val);
5760
5761     /* Linux crc32c converts the output to one's complement.  */
5762     return crc32c(acc, buf, bytes) ^ 0xffffffff;
5763 }