hw/arm/fsl-imx6.c

   1 /*
   2  * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX6 SOC emulation.
   5  *
   6  * Based on hw/arm/fsl-imx31.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License as published by the
  10  *  Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "qemu-common.h"
  25 #include "hw/arm/fsl-imx6.h"
  26 #include "sysemu/sysemu.h"
  27 #include "sysemu/char.h"
  28 #include "qemu/error-report.h"
  29
  30 #define NAME_SIZE 20
  31
  32 static void fsl_imx6_init(Object *obj)
  33 {
  34     FslIMX6State *s = FSL_IMX6(obj);
  35     char name[NAME_SIZE];
  36     int i;
  37
  38     if (smp_cpus > FSL_IMX6_NUM_CPUS) {
  39         error_report("%s: Only %d CPUs are supported (%d requested)",
  40                      TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
  41         exit(1);
  42     }
  43
  44     for (i = 0; i < smp_cpus; i++) {
  45         object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
  46                           "cortex-a9-" TYPE_ARM_CPU);
  47         snprintf(name, NAME_SIZE, "cpu%d", i);
  48         object_property_add_child(obj, name, OBJECT(&s->cpu[i]), NULL);
  49     }
  50
  51     object_initialize(&s->a9mpcore, sizeof(s->a9mpcore), TYPE_A9MPCORE_PRIV);
  52     qdev_set_parent_bus(DEVICE(&s->a9mpcore), sysbus_get_default());
  53     object_property_add_child(obj, "a9mpcore", OBJECT(&s->a9mpcore), NULL);
  54
  55     object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM);
  56     qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
  57     object_property_add_child(obj, "ccm", OBJECT(&s->ccm), NULL);
  58
  59     object_initialize(&s->src, sizeof(s->src), TYPE_IMX6_SRC);
  60     qdev_set_parent_bus(DEVICE(&s->src), sysbus_get_default());
  61     object_property_add_child(obj, "src", OBJECT(&s->src), NULL);
  62
  63     for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
  64         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
  65         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
  66         snprintf(name, NAME_SIZE, "uart%d", i + 1);
  67         object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL);
  68     }
  69
  70     object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
  71     qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
  72     object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL);
  73
  74     for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
  75         object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
  76         qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
  77         snprintf(name, NAME_SIZE, "epit%d", i + 1);
  78         object_property_add_child(obj, name, OBJECT(&s->epit[i]), NULL);
  79     }
  80
  81     for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
  82         object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
  83         qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
  84         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
  85         object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL);
  86     }
  87
  88     for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
  89         object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
  90         qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
  91         snprintf(name, NAME_SIZE, "gpio%d", i + 1);
  92         object_property_add_child(obj, name, OBJECT(&s->gpio[i]), NULL);
  93     }
  94
  95     for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
  96         object_initialize(&s->esdhc[i], sizeof(s->esdhc[i]), TYPE_SYSBUS_SDHCI);
  97         qdev_set_parent_bus(DEVICE(&s->esdhc[i]), sysbus_get_default());
  98         snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
  99         object_property_add_child(obj, name, OBJECT(&s->esdhc[i]), NULL);
 100     }
 101
 102     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
 103         object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI);
 104         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 105         snprintf(name, NAME_SIZE, "spi%d", i + 1);
 106         object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL);
 107     }
 108 }
 109
 110 static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 111 {
 112     FslIMX6State *s = FSL_IMX6(dev);
 113     uint16_t i;
 114     Error *err = NULL;
 115
 116     for (i = 0; i < smp_cpus; i++) {
 117
 118         /* On uniprocessor, the CBAR is set to 0 */
 119         if (smp_cpus > 1) {
 120             object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
 121                                     "reset-cbar", &error_abort);
 122         }
 123
 124         /* All CPU but CPU 0 start in power off mode */
 125         if (i) {
 126             object_property_set_bool(OBJECT(&s->cpu[i]), true,
 127                                      "start-powered-off", &error_abort);
 128         }
 129
 130         object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
 131         if (err) {
 132             error_propagate(errp, err);
 133             return;
 134         }
 135     }
 136
 137     object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
 138                             &error_abort);
 139
 140     object_property_set_int(OBJECT(&s->a9mpcore),
 141                             FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
 142                             &error_abort);
 143
 144     object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
 145     if (err) {
 146         error_propagate(errp, err);
 147         return;
 148     }
 149     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
 150
 151     for (i = 0; i < smp_cpus; i++) {
 152         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
 153                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
 154         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
 155                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
 156     }
 157
 158     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
 159     if (err) {
 160         error_propagate(errp, err);
 161         return;
 162     }
 163     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
 164
 165     object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
 166     if (err) {
 167         error_propagate(errp, err);
 168         return;
 169     }
 170     sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
 171
 172     /* Initialize all UARTs */
 173     for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
 174         static const struct {
 175             hwaddr addr;
 176             unsigned int irq;
 177         } serial_table[FSL_IMX6_NUM_UARTS] = {
 178             { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
 179             { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
 180             { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
 181             { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
 182             { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
 183         };
 184
 185         if (i < MAX_SERIAL_PORTS) {
 186             CharDriverState *chr;
 187
 188             chr = serial_hds[i];
 189
 190             if (!chr) {
 191                 char *label = g_strdup_printf("imx6.uart%d", i + 1);
 192                 chr = qemu_chr_new(label, "null", NULL);
 193                 g_free(label);
 194                 serial_hds[i] = chr;
 195             }
 196
 197             qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
 198         }
 199
 200         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 201         if (err) {
 202             error_propagate(errp, err);
 203             return;
 204         }
 205
 206         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 207         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 208                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 209                                             serial_table[i].irq));
 210     }
 211
 212     s->gpt.ccm = IMX_CCM(&s->ccm);
 213
 214     object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
 215     if (err) {
 216         error_propagate(errp, err);
 217         return;
 218     }
 219
 220     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
 221     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
 222                        qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 223                                         FSL_IMX6_GPT_IRQ));
 224
 225     /* Initialize all EPIT timers */
 226     for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
 227         static const struct {
 228             hwaddr addr;
 229             unsigned int irq;
 230         } epit_table[FSL_IMX6_NUM_EPITS] = {
 231             { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
 232             { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
 233         };
 234
 235         s->epit[i].ccm = IMX_CCM(&s->ccm);
 236
 237         object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
 238         if (err) {
 239             error_propagate(errp, err);
 240             return;
 241         }
 242
 243         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 244         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 245                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 246                                             epit_table[i].irq));
 247     }
 248
 249     /* Initialize all I2C */
 250     for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
 251         static const struct {
 252             hwaddr addr;
 253             unsigned int irq;
 254         } i2c_table[FSL_IMX6_NUM_I2CS] = {
 255             { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
 256             { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
 257             { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
 258         };
 259
 260         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
 261         if (err) {
 262             error_propagate(errp, err);
 263             return;
 264         }
 265
 266         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 267         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 268                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 269                                             i2c_table[i].irq));
 270     }
 271
 272     /* Initialize all GPIOs */
 273     for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
 274         static const struct {
 275             hwaddr addr;
 276             unsigned int irq_low;
 277             unsigned int irq_high;
 278         } gpio_table[FSL_IMX6_NUM_GPIOS] = {
 279             {
 280                 FSL_IMX6_GPIO1_ADDR,
 281                 FSL_IMX6_GPIO1_LOW_IRQ,
 282                 FSL_IMX6_GPIO1_HIGH_IRQ
 283             },
 284             {
 285                 FSL_IMX6_GPIO2_ADDR,
 286                 FSL_IMX6_GPIO2_LOW_IRQ,
 287                 FSL_IMX6_GPIO2_HIGH_IRQ
 288             },
 289             {
 290                 FSL_IMX6_GPIO3_ADDR,
 291                 FSL_IMX6_GPIO3_LOW_IRQ,
 292                 FSL_IMX6_GPIO3_HIGH_IRQ
 293             },
 294             {
 295                 FSL_IMX6_GPIO4_ADDR,
 296                 FSL_IMX6_GPIO4_LOW_IRQ,
 297                 FSL_IMX6_GPIO4_HIGH_IRQ
 298             },
 299             {
 300                 FSL_IMX6_GPIO5_ADDR,
 301                 FSL_IMX6_GPIO5_LOW_IRQ,
 302                 FSL_IMX6_GPIO5_HIGH_IRQ
 303             },
 304             {
 305                 FSL_IMX6_GPIO6_ADDR,
 306                 FSL_IMX6_GPIO6_LOW_IRQ,
 307                 FSL_IMX6_GPIO6_HIGH_IRQ
 308             },
 309             {
 310                 FSL_IMX6_GPIO7_ADDR,
 311                 FSL_IMX6_GPIO7_LOW_IRQ,
 312                 FSL_IMX6_GPIO7_HIGH_IRQ
 313             },
 314         };
 315
 316         object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
 317                                  &error_abort);
 318         object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
 319                                  &error_abort);
 320         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
 321         if (err) {
 322             error_propagate(errp, err);
 323             return;
 324         }
 325
 326         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 327         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 328                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 329                                             gpio_table[i].irq_low));
 330         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
 331                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 332                                             gpio_table[i].irq_high));
 333     }
 334
 335     /* Initialize all SDHC */
 336     for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
 337         static const struct {
 338             hwaddr addr;
 339             unsigned int irq;
 340         } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
 341             { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
 342             { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
 343             { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
 344             { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
 345         };
 346
 347         object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
 348         if (err) {
 349             error_propagate(errp, err);
 350             return;
 351         }
 352         sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
 353         sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
 354                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 355                                             esdhc_table[i].irq));
 356     }
 357
 358     /* Initialize all ECSPI */
 359     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
 360         static const struct {
 361             hwaddr addr;
 362             unsigned int irq;
 363         } spi_table[FSL_IMX6_NUM_ECSPIS] = {
 364             { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
 365             { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
 366             { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
 367             { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
 368             { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
 369         };
 370
 371         /* Initialize the SPI */
 372         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 373         if (err) {
 374             error_propagate(errp, err);
 375             return;
 376         }
 377
 378         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
 379         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 380                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 381                                             spi_table[i].irq));
 382     }
 383
 384     /* ROM memory */
 385     memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx6.rom",
 386                                   FSL_IMX6_ROM_SIZE, &err);
 387     if (err) {
 388         error_propagate(errp, err);
 389         return;
 390     }
 391     memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
 392                                 &s->rom);
 393
 394     /* CAAM memory */
 395     memory_region_init_rom_device(&s->caam, NULL, NULL, NULL, "imx6.caam",
 396                                   FSL_IMX6_CAAM_MEM_SIZE, &err);
 397     if (err) {
 398         error_propagate(errp, err);
 399         return;
 400     }
 401     memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
 402                                 &s->caam);
 403
 404     /* OCRAM memory */
 405     memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
 406                            &err);
 407     if (err) {
 408         error_propagate(errp, err);
 409         return;
 410     }
 411     memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
 412                                 &s->ocram);
 413     vmstate_register_ram_global(&s->ocram);
 414
 415     /* internal OCRAM (256 KB) is aliased over 1 MB */
 416     memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias",
 417                              &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
 418     memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
 419                                 &s->ocram_alias);
 420 }
 421
 422 static void fsl_imx6_class_init(ObjectClass *oc, void *data)
 423 {
 424     DeviceClass *dc = DEVICE_CLASS(oc);
 425
 426     dc->realize = fsl_imx6_realize;
 427
 428     /*
 429      * Reason: creates an ARM CPU, thus use after free(), see
 430      * arm_cpu_class_init()
 431      */
 432     dc->cannot_destroy_with_object_finalize_yet = true;
 433     dc->desc = "i.MX6 SOC";
 434 }
 435
 436 static const TypeInfo fsl_imx6_type_info = {
 437     .name = TYPE_FSL_IMX6,
 438     .parent = TYPE_DEVICE,
 439     .instance_size = sizeof(FslIMX6State),
 440     .instance_init = fsl_imx6_init,
 441     .class_init = fsl_imx6_class_init,
 442 };
 443
 444 static void fsl_imx6_register_types(void)
 445 {
 446     type_register_static(&fsl_imx6_type_info);
 447 }
 448
 449 type_init(fsl_imx6_register_types)