3 #include "exec/gdbstub.h"
4 #include "exec/helper-proto.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include "exec/cpu_ldst.h"
12 #include <zlib.h> /* For crc32 */
14 #ifndef CONFIG_USER_ONLY
15 static inline int get_phys_addr(CPUARMState
*env
, target_ulong address
,
16 int access_type
, ARMMMUIdx mmu_idx
,
17 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
18 target_ulong
*page_size
);
20 /* Definitions for the PMCCNTR and PMCR registers */
26 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
30 /* VFP data registers are always little-endian. */
31 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
33 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
36 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
37 /* Aliases for Q regs. */
40 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
41 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
45 switch (reg
- nregs
) {
46 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
47 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
48 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
53 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
57 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
59 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
62 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
65 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
66 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
70 switch (reg
- nregs
) {
71 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
72 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
73 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
78 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
82 /* 128 bit FP register */
83 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
84 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
88 stl_p(buf
, vfp_get_fpsr(env
));
92 stl_p(buf
, vfp_get_fpcr(env
));
99 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
103 /* 128 bit FP register */
104 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
105 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
109 vfp_set_fpsr(env
, ldl_p(buf
));
113 vfp_set_fpcr(env
, ldl_p(buf
));
120 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
122 assert(ri
->fieldoffset
);
123 if (cpreg_field_is_64bit(ri
)) {
124 return CPREG_FIELD64(env
, ri
);
126 return CPREG_FIELD32(env
, ri
);
130 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
133 assert(ri
->fieldoffset
);
134 if (cpreg_field_is_64bit(ri
)) {
135 CPREG_FIELD64(env
, ri
) = value
;
137 CPREG_FIELD32(env
, ri
) = value
;
141 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
143 return (char *)env
+ ri
->fieldoffset
;
146 static uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
148 /* Raw read of a coprocessor register (as needed for migration, etc). */
149 if (ri
->type
& ARM_CP_CONST
) {
150 return ri
->resetvalue
;
151 } else if (ri
->raw_readfn
) {
152 return ri
->raw_readfn(env
, ri
);
153 } else if (ri
->readfn
) {
154 return ri
->readfn(env
, ri
);
156 return raw_read(env
, ri
);
160 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
163 /* Raw write of a coprocessor register (as needed for migration, etc).
164 * Note that constant registers are treated as write-ignored; the
165 * caller should check for success by whether a readback gives the
168 if (ri
->type
& ARM_CP_CONST
) {
170 } else if (ri
->raw_writefn
) {
171 ri
->raw_writefn(env
, ri
, v
);
172 } else if (ri
->writefn
) {
173 ri
->writefn(env
, ri
, v
);
175 raw_write(env
, ri
, v
);
179 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
181 /* Return true if the regdef would cause an assertion if you called
182 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
183 * program bug for it not to have the NO_RAW flag).
184 * NB that returning false here doesn't necessarily mean that calling
185 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
186 * read/write access functions which are safe for raw use" from "has
187 * read/write access functions which have side effects but has forgotten
188 * to provide raw access functions".
189 * The tests here line up with the conditions in read/write_raw_cp_reg()
190 * and assertions in raw_read()/raw_write().
192 if ((ri
->type
& ARM_CP_CONST
) ||
194 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
200 bool write_cpustate_to_list(ARMCPU
*cpu
)
202 /* Write the coprocessor state from cpu->env to the (index,value) list. */
206 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
207 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
208 const ARMCPRegInfo
*ri
;
210 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
215 if (ri
->type
& ARM_CP_NO_RAW
) {
218 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
223 bool write_list_to_cpustate(ARMCPU
*cpu
)
228 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
229 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
230 uint64_t v
= cpu
->cpreg_values
[i
];
231 const ARMCPRegInfo
*ri
;
233 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
238 if (ri
->type
& ARM_CP_NO_RAW
) {
241 /* Write value and confirm it reads back as written
242 * (to catch read-only registers and partially read-only
243 * registers where the incoming migration value doesn't match)
245 write_raw_cp_reg(&cpu
->env
, ri
, v
);
246 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
253 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
255 ARMCPU
*cpu
= opaque
;
257 const ARMCPRegInfo
*ri
;
259 regidx
= *(uint32_t *)key
;
260 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
262 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
263 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
264 /* The value array need not be initialized at this point */
265 cpu
->cpreg_array_len
++;
269 static void count_cpreg(gpointer key
, gpointer opaque
)
271 ARMCPU
*cpu
= opaque
;
273 const ARMCPRegInfo
*ri
;
275 regidx
= *(uint32_t *)key
;
276 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
278 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
279 cpu
->cpreg_array_len
++;
283 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
285 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
286 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
297 void init_cpreg_list(ARMCPU
*cpu
)
299 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
300 * Note that we require cpreg_tuples[] to be sorted by key ID.
305 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
306 keys
= g_list_sort(keys
, cpreg_key_compare
);
308 cpu
->cpreg_array_len
= 0;
310 g_list_foreach(keys
, count_cpreg
, cpu
);
312 arraylen
= cpu
->cpreg_array_len
;
313 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
314 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
315 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
316 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
317 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
318 cpu
->cpreg_array_len
= 0;
320 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
322 assert(cpu
->cpreg_array_len
== arraylen
);
327 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
329 ARMCPU
*cpu
= arm_env_get_cpu(env
);
331 raw_write(env
, ri
, value
);
332 tlb_flush(CPU(cpu
), 1); /* Flush TLB as domain not tracked in TLB */
335 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
337 ARMCPU
*cpu
= arm_env_get_cpu(env
);
339 if (raw_read(env
, ri
) != value
) {
340 /* Unlike real hardware the qemu TLB uses virtual addresses,
341 * not modified virtual addresses, so this causes a TLB flush.
343 tlb_flush(CPU(cpu
), 1);
344 raw_write(env
, ri
, value
);
348 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
351 ARMCPU
*cpu
= arm_env_get_cpu(env
);
353 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_MPU
)
354 && !extended_addresses_enabled(env
)) {
355 /* For VMSA (when not using the LPAE long descriptor page table
356 * format) this register includes the ASID, so do a TLB flush.
357 * For PMSA it is purely a process ID and no action is needed.
359 tlb_flush(CPU(cpu
), 1);
361 raw_write(env
, ri
, value
);
364 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
367 /* Invalidate all (TLBIALL) */
368 ARMCPU
*cpu
= arm_env_get_cpu(env
);
370 tlb_flush(CPU(cpu
), 1);
373 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
376 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
377 ARMCPU
*cpu
= arm_env_get_cpu(env
);
379 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
382 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
385 /* Invalidate by ASID (TLBIASID) */
386 ARMCPU
*cpu
= arm_env_get_cpu(env
);
388 tlb_flush(CPU(cpu
), value
== 0);
391 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
394 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
395 ARMCPU
*cpu
= arm_env_get_cpu(env
);
397 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
400 /* IS variants of TLB operations must affect all cores */
401 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
406 CPU_FOREACH(other_cs
) {
407 tlb_flush(other_cs
, 1);
411 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
416 CPU_FOREACH(other_cs
) {
417 tlb_flush(other_cs
, value
== 0);
421 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
426 CPU_FOREACH(other_cs
) {
427 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
431 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
436 CPU_FOREACH(other_cs
) {
437 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
441 static const ARMCPRegInfo cp_reginfo
[] = {
442 /* Define the secure and non-secure FCSE identifier CP registers
443 * separately because there is no secure bank in V8 (no _EL3). This allows
444 * the secure register to be properly reset and migrated. There is also no
445 * v8 EL1 version of the register so the non-secure instance stands alone.
447 { .name
= "FCSEIDR(NS)",
448 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
449 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
450 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
451 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
452 { .name
= "FCSEIDR(S)",
453 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
454 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
455 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
456 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
457 /* Define the secure and non-secure context identifier CP registers
458 * separately because there is no secure bank in V8 (no _EL3). This allows
459 * the secure register to be properly reset and migrated. In the
460 * non-secure case, the 32-bit register will have reset and migration
461 * disabled during registration as it is handled by the 64-bit instance.
463 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
464 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
465 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
466 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
467 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
468 { .name
= "CONTEXTIDR(S)", .state
= ARM_CP_STATE_AA32
,
469 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
470 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
471 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
472 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
476 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
477 /* NB: Some of these registers exist in v8 but with more precise
478 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
480 /* MMU Domain access control / MPU write buffer control */
482 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
483 .access
= PL1_RW
, .resetvalue
= 0,
484 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
485 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
486 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
487 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
488 * For v6 and v5, these mappings are overly broad.
490 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
491 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
492 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
493 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
494 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
495 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
496 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
497 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
498 /* Cache maintenance ops; some of this space may be overridden later. */
499 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
500 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
501 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
505 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
506 /* Not all pre-v6 cores implemented this WFI, so this is slightly
509 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
510 .access
= PL1_W
, .type
= ARM_CP_WFI
},
514 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
515 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
516 * is UNPREDICTABLE; we choose to NOP as most implementations do).
518 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
519 .access
= PL1_W
, .type
= ARM_CP_WFI
},
520 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
521 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
522 * OMAPCP will override this space.
524 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
525 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
527 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
528 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
530 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
531 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
532 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
534 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
535 * implementing it as RAZ means the "debug architecture version" bits
536 * will read as a reserved value, which should cause Linux to not try
537 * to use the debug hardware.
539 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
540 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
541 /* MMU TLB control. Note that the wildcarding means we cover not just
542 * the unified TLB ops but also the dside/iside/inner-shareable variants.
544 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
545 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
546 .type
= ARM_CP_NO_RAW
},
547 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
548 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
549 .type
= ARM_CP_NO_RAW
},
550 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
551 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
552 .type
= ARM_CP_NO_RAW
},
553 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
554 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
555 .type
= ARM_CP_NO_RAW
},
556 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
557 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
558 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
559 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
563 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
569 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
570 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
571 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
572 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
574 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
575 /* VFP coprocessor: cp10 & cp11 [23:20] */
576 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
578 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
579 /* ASEDIS [31] bit is RAO/WI */
583 /* VFPv3 and upwards with NEON implement 32 double precision
584 * registers (D0-D31).
586 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
587 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
588 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
594 env
->cp15
.cpacr_el1
= value
;
597 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
599 if (arm_feature(env
, ARM_FEATURE_V8
)) {
600 /* Check if CPACR accesses are to be trapped to EL2 */
601 if (arm_current_el(env
) == 1 &&
602 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
603 return CP_ACCESS_TRAP_EL2
;
604 /* Check if CPACR accesses are to be trapped to EL3 */
605 } else if (arm_current_el(env
) < 3 &&
606 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
607 return CP_ACCESS_TRAP_EL3
;
614 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
616 /* Check if CPTR accesses are set to trap to EL3 */
617 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
618 return CP_ACCESS_TRAP_EL3
;
624 static const ARMCPRegInfo v6_cp_reginfo
[] = {
625 /* prefetch by MVA in v6, NOP in v7 */
626 { .name
= "MVA_prefetch",
627 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
628 .access
= PL1_W
, .type
= ARM_CP_NOP
},
629 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
630 .access
= PL0_W
, .type
= ARM_CP_NOP
},
631 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
632 .access
= PL0_W
, .type
= ARM_CP_NOP
},
633 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
634 .access
= PL0_W
, .type
= ARM_CP_NOP
},
635 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
637 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
638 offsetof(CPUARMState
, cp15
.ifar_ns
) },
640 /* Watchpoint Fault Address Register : should actually only be present
641 * for 1136, 1176, 11MPCore.
643 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
644 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
645 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
646 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
647 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
648 .resetvalue
= 0, .writefn
= cpacr_write
},
652 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
654 /* Performance monitor registers user accessibility is controlled
657 if (arm_current_el(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
658 return CP_ACCESS_TRAP
;
663 #ifndef CONFIG_USER_ONLY
665 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
667 /* This does not support checking PMCCFILTR_EL0 register */
669 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
676 void pmccntr_sync(CPUARMState
*env
)
680 temp_ticks
= muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
),
681 get_ticks_per_sec(), 1000000);
683 if (env
->cp15
.c9_pmcr
& PMCRD
) {
684 /* Increment once every 64 processor clock cycles */
688 if (arm_ccnt_enabled(env
)) {
689 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
693 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
699 /* The counter has been reset */
700 env
->cp15
.c15_ccnt
= 0;
703 /* only the DP, X, D and E bits are writable */
704 env
->cp15
.c9_pmcr
&= ~0x39;
705 env
->cp15
.c9_pmcr
|= (value
& 0x39);
710 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
712 uint64_t total_ticks
;
714 if (!arm_ccnt_enabled(env
)) {
715 /* Counter is disabled, do not change value */
716 return env
->cp15
.c15_ccnt
;
719 total_ticks
= muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
),
720 get_ticks_per_sec(), 1000000);
722 if (env
->cp15
.c9_pmcr
& PMCRD
) {
723 /* Increment once every 64 processor clock cycles */
726 return total_ticks
- env
->cp15
.c15_ccnt
;
729 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
732 uint64_t total_ticks
;
734 if (!arm_ccnt_enabled(env
)) {
735 /* Counter is disabled, set the absolute value */
736 env
->cp15
.c15_ccnt
= value
;
740 total_ticks
= muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
),
741 get_ticks_per_sec(), 1000000);
743 if (env
->cp15
.c9_pmcr
& PMCRD
) {
744 /* Increment once every 64 processor clock cycles */
747 env
->cp15
.c15_ccnt
= total_ticks
- value
;
750 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
753 uint64_t cur_val
= pmccntr_read(env
, NULL
);
755 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
758 #else /* CONFIG_USER_ONLY */
760 void pmccntr_sync(CPUARMState
*env
)
766 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
770 env
->cp15
.pmccfiltr_el0
= value
& 0x7E000000;
774 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
778 env
->cp15
.c9_pmcnten
|= value
;
781 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
785 env
->cp15
.c9_pmcnten
&= ~value
;
788 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
791 env
->cp15
.c9_pmovsr
&= ~value
;
794 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
797 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
800 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
803 env
->cp15
.c9_pmuserenr
= value
& 1;
806 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
809 /* We have no event counters so only the C bit can be changed */
811 env
->cp15
.c9_pminten
|= value
;
814 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
818 env
->cp15
.c9_pminten
&= ~value
;
821 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
824 /* Note that even though the AArch64 view of this register has bits
825 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
826 * architectural requirements for bits which are RES0 only in some
827 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
828 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
830 raw_write(env
, ri
, value
& ~0x1FULL
);
833 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
835 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
836 * For bits that vary between AArch32/64, code needs to check the
837 * current execution mode before directly using the feature bit.
839 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
841 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
842 valid_mask
&= ~SCR_HCE
;
844 /* On ARMv7, SMD (or SCD as it is called in v7) is only
845 * supported if EL2 exists. The bit is UNK/SBZP when
846 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
847 * when EL2 is unavailable.
848 * On ARMv8, this bit is always available.
850 if (arm_feature(env
, ARM_FEATURE_V7
) &&
851 !arm_feature(env
, ARM_FEATURE_V8
)) {
852 valid_mask
&= ~SCR_SMD
;
856 /* Clear all-context RES0 bits. */
858 raw_write(env
, ri
, value
);
861 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
863 ARMCPU
*cpu
= arm_env_get_cpu(env
);
865 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
868 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
869 ri
->secure
& ARM_CP_SECSTATE_S
);
871 return cpu
->ccsidr
[index
];
874 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
877 raw_write(env
, ri
, value
& 0xf);
880 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
882 CPUState
*cs
= ENV_GET_CPU(env
);
885 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
888 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
891 /* External aborts are not possible in QEMU so A bit is always clear */
895 static const ARMCPRegInfo v7_cp_reginfo
[] = {
896 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
897 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
898 .access
= PL1_W
, .type
= ARM_CP_NOP
},
899 /* Performance monitors are implementation defined in v7,
900 * but with an ARM recommended set of registers, which we
901 * follow (although we don't actually implement any counters)
903 * Performance registers fall into three categories:
904 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
905 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
906 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
907 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
908 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
910 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
911 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
912 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
913 .writefn
= pmcntenset_write
,
914 .accessfn
= pmreg_access
,
915 .raw_writefn
= raw_write
},
916 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
917 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
918 .access
= PL0_RW
, .accessfn
= pmreg_access
,
919 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
920 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
921 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
923 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
924 .accessfn
= pmreg_access
,
925 .writefn
= pmcntenclr_write
,
926 .type
= ARM_CP_ALIAS
},
927 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
928 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
929 .access
= PL0_RW
, .accessfn
= pmreg_access
,
930 .type
= ARM_CP_ALIAS
,
931 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
932 .writefn
= pmcntenclr_write
},
933 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
934 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
935 .accessfn
= pmreg_access
,
936 .writefn
= pmovsr_write
,
937 .raw_writefn
= raw_write
},
938 /* Unimplemented so WI. */
939 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
940 .access
= PL0_W
, .accessfn
= pmreg_access
, .type
= ARM_CP_NOP
},
941 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
942 * We choose to RAZ/WI.
944 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
945 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
946 .accessfn
= pmreg_access
},
947 #ifndef CONFIG_USER_ONLY
948 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
949 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
950 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
951 .accessfn
= pmreg_access
},
952 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
953 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
954 .access
= PL0_RW
, .accessfn
= pmreg_access
,
956 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
958 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
959 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
960 .writefn
= pmccfiltr_write
,
961 .access
= PL0_RW
, .accessfn
= pmreg_access
,
963 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
965 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
967 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
968 .accessfn
= pmreg_access
, .writefn
= pmxevtyper_write
,
969 .raw_writefn
= raw_write
},
970 /* Unimplemented, RAZ/WI. */
971 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
972 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
973 .accessfn
= pmreg_access
},
974 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
975 .access
= PL0_R
| PL1_RW
,
976 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
978 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
979 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
981 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
983 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
984 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
985 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
986 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
987 .resetvalue
= 0, .writefn
= pmintenclr_write
, },
988 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
989 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
990 .access
= PL1_RW
, .writefn
= vbar_write
,
991 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
992 offsetof(CPUARMState
, cp15
.vbar_ns
) },
994 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
995 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
996 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
997 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
998 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
999 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1000 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1001 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1002 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1003 * just RAZ for all cores:
1005 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1006 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1007 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1008 /* Auxiliary fault status registers: these also are IMPDEF, and we
1009 * choose to RAZ/WI for all cores.
1011 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1012 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1013 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1014 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1015 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1016 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1017 /* MAIR can just read-as-written because we don't implement caches
1018 * and so don't need to care about memory attributes.
1020 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1021 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1022 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1024 /* For non-long-descriptor page tables these are PRRR and NMRR;
1025 * regardless they still act as reads-as-written for QEMU.
1027 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1028 * allows them to assign the correct fieldoffset based on the endianness
1029 * handled in the field definitions.
1031 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1032 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1033 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1034 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1035 .resetfn
= arm_cp_reset_ignore
},
1036 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1037 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1038 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1039 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1040 .resetfn
= arm_cp_reset_ignore
},
1041 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1042 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1043 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1044 /* 32 bit ITLB invalidates */
1045 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1046 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1047 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1048 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1049 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1050 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1051 /* 32 bit DTLB invalidates */
1052 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1053 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1054 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1055 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1056 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1057 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1058 /* 32 bit TLB invalidates */
1059 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1060 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1061 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1062 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1063 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1064 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1065 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1066 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1070 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1071 /* 32 bit TLB invalidates, Inner Shareable */
1072 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1073 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1074 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1075 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1076 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1077 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1078 .writefn
= tlbiasid_is_write
},
1079 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1080 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1081 .writefn
= tlbimvaa_is_write
},
1085 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1092 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1094 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1095 return CP_ACCESS_TRAP
;
1097 return CP_ACCESS_OK
;
1100 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1101 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1102 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1104 .writefn
= teecr_write
},
1105 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1106 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1107 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1111 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1112 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1113 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1115 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1116 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1118 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1119 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1120 .resetfn
= arm_cp_reset_ignore
},
1121 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1122 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1123 .access
= PL0_R
|PL1_W
,
1124 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1126 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1127 .access
= PL0_R
|PL1_W
,
1128 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1129 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1130 .resetfn
= arm_cp_reset_ignore
},
1131 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1132 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1134 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1135 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1137 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1138 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1143 #ifndef CONFIG_USER_ONLY
1145 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1147 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1148 if (arm_current_el(env
) == 0 && !extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1149 return CP_ACCESS_TRAP
;
1151 return CP_ACCESS_OK
;
1154 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
)
1156 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1157 if (arm_current_el(env
) == 0 &&
1158 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1159 return CP_ACCESS_TRAP
;
1161 return CP_ACCESS_OK
;
1164 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
)
1166 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1167 * EL0[PV]TEN is zero.
1169 if (arm_current_el(env
) == 0 &&
1170 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1171 return CP_ACCESS_TRAP
;
1173 return CP_ACCESS_OK
;
1176 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1177 const ARMCPRegInfo
*ri
)
1179 return gt_counter_access(env
, GTIMER_PHYS
);
1182 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1183 const ARMCPRegInfo
*ri
)
1185 return gt_counter_access(env
, GTIMER_VIRT
);
1188 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1190 return gt_timer_access(env
, GTIMER_PHYS
);
1193 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1195 return gt_timer_access(env
, GTIMER_VIRT
);
1198 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1200 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1203 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1205 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1208 /* Timer enabled: calculate and set current ISTATUS, irq, and
1209 * reset timer to when ISTATUS next has to change
1211 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1212 /* Note that this must be unsigned 64 bit arithmetic: */
1213 int istatus
= count
>= gt
->cval
;
1216 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1217 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
1218 (istatus
&& !(gt
->ctl
& 2)));
1220 /* Next transition is when count rolls back over to zero */
1221 nexttick
= UINT64_MAX
;
1223 /* Next transition is when we hit cval */
1224 nexttick
= gt
->cval
;
1226 /* Note that the desired next expiry time might be beyond the
1227 * signed-64-bit range of a QEMUTimer -- in this case we just
1228 * set the timer for as far in the future as possible. When the
1229 * timer expires we will reset the timer for any remaining period.
1231 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1232 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1234 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1236 /* Timer disabled: ISTATUS and timer output always clear */
1238 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1239 timer_del(cpu
->gt_timer
[timeridx
]);
1243 static void gt_cnt_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1245 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1246 int timeridx
= ri
->opc1
& 1;
1248 timer_del(cpu
->gt_timer
[timeridx
]);
1251 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1253 return gt_get_countervalue(env
);
1256 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1259 int timeridx
= ri
->opc1
& 1;
1261 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1262 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1265 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1267 int timeridx
= ri
->crm
& 1;
1269 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1270 gt_get_countervalue(env
));
1273 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1276 int timeridx
= ri
->crm
& 1;
1278 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) +
1279 sextract64(value
, 0, 32);
1280 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1283 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1286 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1287 int timeridx
= ri
->crm
& 1;
1288 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1290 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1291 if ((oldval
^ value
) & 1) {
1292 /* Enable toggled */
1293 gt_recalc_timer(cpu
, timeridx
);
1294 } else if ((oldval
^ value
) & 2) {
1295 /* IMASK toggled: don't need to recalculate,
1296 * just set the interrupt line based on ISTATUS
1298 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
1299 (oldval
& 4) && !(value
& 2));
1303 void arm_gt_ptimer_cb(void *opaque
)
1305 ARMCPU
*cpu
= opaque
;
1307 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1310 void arm_gt_vtimer_cb(void *opaque
)
1312 ARMCPU
*cpu
= opaque
;
1314 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1317 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1318 /* Note that CNTFRQ is purely reads-as-written for the benefit
1319 * of software; writing it doesn't actually change the timer frequency.
1320 * Our reset value matches the fixed frequency we implement the timer at.
1322 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1323 .type
= ARM_CP_ALIAS
,
1324 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1325 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1326 .resetfn
= arm_cp_reset_ignore
,
1328 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1329 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1330 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1331 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1332 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1334 /* overall control: mostly access permissions */
1335 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1336 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1338 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1341 /* per-timer control */
1342 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1343 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1344 .accessfn
= gt_ptimer_access
,
1345 .fieldoffset
= offsetoflow32(CPUARMState
,
1346 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1347 .resetfn
= arm_cp_reset_ignore
,
1348 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1350 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1351 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1352 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1353 .accessfn
= gt_ptimer_access
,
1354 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1356 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1358 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1359 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1360 .accessfn
= gt_vtimer_access
,
1361 .fieldoffset
= offsetoflow32(CPUARMState
,
1362 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1363 .resetfn
= arm_cp_reset_ignore
,
1364 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1366 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1367 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1368 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1369 .accessfn
= gt_vtimer_access
,
1370 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1372 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1374 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1375 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1376 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1377 .accessfn
= gt_ptimer_access
,
1378 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1380 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1381 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
1382 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1383 .accessfn
= gt_ptimer_access
,
1384 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1386 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
1387 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1388 .accessfn
= gt_vtimer_access
,
1389 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1391 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1392 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
1393 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1394 .accessfn
= gt_vtimer_access
,
1395 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1397 /* The counter itself */
1398 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
1399 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1400 .accessfn
= gt_pct_access
,
1401 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1403 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
1404 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
1405 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1406 .accessfn
= gt_pct_access
,
1407 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1409 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
1410 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1411 .accessfn
= gt_vct_access
,
1412 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1414 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
1415 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
1416 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1417 .accessfn
= gt_vct_access
,
1418 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1420 /* Comparison value, indicating when the timer goes off */
1421 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
1422 .access
= PL1_RW
| PL0_R
,
1423 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1424 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1425 .accessfn
= gt_ptimer_access
, .resetfn
= arm_cp_reset_ignore
,
1426 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1428 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1429 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
1430 .access
= PL1_RW
| PL0_R
,
1432 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1433 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
1434 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1436 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
1437 .access
= PL1_RW
| PL0_R
,
1438 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1439 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1440 .accessfn
= gt_vtimer_access
, .resetfn
= arm_cp_reset_ignore
,
1441 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1443 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1444 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
1445 .access
= PL1_RW
| PL0_R
,
1447 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1448 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1449 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1455 /* In user-mode none of the generic timer registers are accessible,
1456 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1457 * so instead just don't register any of them.
1459 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1465 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1467 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1468 raw_write(env
, ri
, value
);
1469 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1470 raw_write(env
, ri
, value
& 0xfffff6ff);
1472 raw_write(env
, ri
, value
& 0xfffff1ff);
1476 #ifndef CONFIG_USER_ONLY
1477 /* get_phys_addr() isn't present for user-mode-only targets */
1479 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1482 /* Other states are only available with TrustZone; in
1483 * a non-TZ implementation these registers don't exist
1484 * at all, which is an Uncategorized trap. This underdecoding
1485 * is safe because the reginfo is NO_RAW.
1487 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1489 return CP_ACCESS_OK
;
1492 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
1493 int access_type
, ARMMMUIdx mmu_idx
)
1496 target_ulong page_size
;
1500 MemTxAttrs attrs
= {};
1502 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
,
1503 &phys_addr
, &attrs
, &prot
, &page_size
);
1504 if (extended_addresses_enabled(env
)) {
1505 /* ret is a DFSR/IFSR value for the long descriptor
1506 * translation table format, but with WnR always clear.
1507 * Convert it to a 64-bit PAR.
1509 par64
= (1 << 11); /* LPAE bit always set */
1511 par64
|= phys_addr
& ~0xfffULL
;
1512 if (!attrs
.secure
) {
1513 par64
|= (1 << 9); /* NS */
1515 /* We don't set the ATTR or SH fields in the PAR. */
1518 par64
|= (ret
& 0x3f) << 1; /* FS */
1519 /* Note that S2WLK and FSTAGE are always zero, because we don't
1520 * implement virtualization and therefore there can't be a stage 2
1525 /* ret is a DFSR/IFSR value for the short descriptor
1526 * translation table format (with WnR always clear).
1527 * Convert it to a 32-bit PAR.
1530 /* We do not set any attribute bits in the PAR */
1531 if (page_size
== (1 << 24)
1532 && arm_feature(env
, ARM_FEATURE_V7
)) {
1533 par64
= (phys_addr
& 0xff000000) | (1 << 1);
1535 par64
= phys_addr
& 0xfffff000;
1537 if (!attrs
.secure
) {
1538 par64
|= (1 << 9); /* NS */
1541 par64
= ((ret
& (1 << 10)) >> 5) | ((ret
& (1 << 12)) >> 6) |
1542 ((ret
& 0xf) << 1) | 1;
1548 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1550 int access_type
= ri
->opc2
& 1;
1553 int el
= arm_current_el(env
);
1554 bool secure
= arm_is_secure_below_el3(env
);
1556 switch (ri
->opc2
& 6) {
1558 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1561 mmu_idx
= ARMMMUIdx_S1E3
;
1564 mmu_idx
= ARMMMUIdx_S1NSE1
;
1567 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
1570 g_assert_not_reached();
1574 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1577 mmu_idx
= ARMMMUIdx_S1SE0
;
1580 mmu_idx
= ARMMMUIdx_S1NSE0
;
1583 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
1586 g_assert_not_reached();
1590 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1591 mmu_idx
= ARMMMUIdx_S12NSE1
;
1594 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1595 mmu_idx
= ARMMMUIdx_S12NSE0
;
1598 g_assert_not_reached();
1601 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
1603 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
1606 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1609 int access_type
= ri
->opc2
& 1;
1611 int secure
= arm_is_secure_below_el3(env
);
1613 switch (ri
->opc2
& 6) {
1616 case 0: /* AT S1E1R, AT S1E1W */
1617 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
1619 case 4: /* AT S1E2R, AT S1E2W */
1620 mmu_idx
= ARMMMUIdx_S1E2
;
1622 case 6: /* AT S1E3R, AT S1E3W */
1623 mmu_idx
= ARMMMUIdx_S1E3
;
1626 g_assert_not_reached();
1629 case 2: /* AT S1E0R, AT S1E0W */
1630 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
1632 case 4: /* AT S12E1R, AT S12E1W */
1633 mmu_idx
= ARMMMUIdx_S12NSE1
;
1635 case 6: /* AT S12E0R, AT S12E0W */
1636 mmu_idx
= ARMMMUIdx_S12NSE0
;
1639 g_assert_not_reached();
1642 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
1646 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
1647 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
1648 .access
= PL1_RW
, .resetvalue
= 0,
1649 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
1650 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
1651 .writefn
= par_write
},
1652 #ifndef CONFIG_USER_ONLY
1653 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
1654 .access
= PL1_W
, .accessfn
= ats_access
,
1655 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
1660 /* Return basic MPU access permission bits. */
1661 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1668 for (i
= 0; i
< 16; i
+= 2) {
1669 ret
|= (val
>> i
) & mask
;
1675 /* Pad basic MPU access permission bits to extended format. */
1676 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1683 for (i
= 0; i
< 16; i
+= 2) {
1684 ret
|= (val
& mask
) << i
;
1690 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1693 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
1696 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1698 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
1701 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1704 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
1707 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1709 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
1712 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
1713 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1714 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
1715 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
1717 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
1718 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1719 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
1720 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
1722 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
1723 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
1725 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
1727 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
1729 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
1731 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1733 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
1734 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1736 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
1737 /* Protection region base and size registers */
1738 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
1739 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1740 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
1741 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
1742 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1743 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
1744 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
1745 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1746 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
1747 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
1748 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1749 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
1750 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
1751 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1752 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
1753 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
1754 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1755 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
1756 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
1757 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1758 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
1759 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
1760 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1761 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
1765 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1768 TCR
*tcr
= raw_ptr(env
, ri
);
1769 int maskshift
= extract32(value
, 0, 3);
1771 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
1772 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
1773 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1774 * using Long-desciptor translation table format */
1775 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
1776 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1777 /* In an implementation that includes the Security Extensions
1778 * TTBCR has additional fields PD0 [4] and PD1 [5] for
1779 * Short-descriptor translation table format.
1781 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
1787 /* Update the masks corresponding to the the TCR bank being written
1788 * Note that we always calculate mask and base_mask, but
1789 * they are only used for short-descriptor tables (ie if EAE is 0);
1790 * for long-descriptor tables the TCR fields are used differently
1791 * and the mask and base_mask values are meaningless.
1793 tcr
->raw_tcr
= value
;
1794 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
1795 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
1798 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1801 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1803 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1804 /* With LPAE the TTBCR could result in a change of ASID
1805 * via the TTBCR.A1 bit, so do a TLB flush.
1807 tlb_flush(CPU(cpu
), 1);
1809 vmsa_ttbcr_raw_write(env
, ri
, value
);
1812 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1814 TCR
*tcr
= raw_ptr(env
, ri
);
1816 /* Reset both the TCR as well as the masks corresponding to the bank of
1817 * the TCR being reset.
1821 tcr
->base_mask
= 0xffffc000u
;
1824 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1827 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1828 TCR
*tcr
= raw_ptr(env
, ri
);
1830 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1831 tlb_flush(CPU(cpu
), 1);
1832 tcr
->raw_tcr
= value
;
1835 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1838 /* 64 bit accesses to the TTBRs can change the ASID and so we
1839 * must flush the TLB.
1841 if (cpreg_field_is_64bit(ri
)) {
1842 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1844 tlb_flush(CPU(cpu
), 1);
1846 raw_write(env
, ri
, value
);
1849 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
1850 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1851 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
1852 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
1853 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) },
1854 .resetfn
= arm_cp_reset_ignore
, },
1855 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1856 .access
= PL1_RW
, .resetvalue
= 0,
1857 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
1858 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
1859 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
1860 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
1862 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
1863 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1864 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
1865 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
1866 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
1867 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
1868 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1869 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
1870 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
1871 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
1872 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
1873 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
1874 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1875 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
1876 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
1877 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
1878 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1879 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
1880 .resetfn
= arm_cp_reset_ignore
, .raw_writefn
= vmsa_ttbcr_raw_write
,
1881 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
1882 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
1883 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
1884 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
1885 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
1887 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
1888 .access
= PL1_RW
, .resetvalue
= 0,
1889 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
1890 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
1894 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1897 env
->cp15
.c15_ticonfig
= value
& 0xe7;
1898 /* The OS_TYPE bit in this register changes the reported CPUID! */
1899 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
1900 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1903 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1906 env
->cp15
.c15_threadid
= value
& 0xffff;
1909 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1912 /* Wait-for-interrupt (deprecated) */
1913 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
1916 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1919 /* On OMAP there are registers indicating the max/min index of dcache lines
1920 * containing a dirty line; cache flush operations have to reset these.
1922 env
->cp15
.c15_i_max
= 0x000;
1923 env
->cp15
.c15_i_min
= 0xff0;
1926 static const ARMCPRegInfo omap_cp_reginfo
[] = {
1927 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
1928 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
1929 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
1931 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1932 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
1933 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1935 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
1936 .writefn
= omap_ticonfig_write
},
1937 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
1939 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
1940 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
1941 .access
= PL1_RW
, .resetvalue
= 0xff0,
1942 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
1943 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
1945 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
1946 .writefn
= omap_threadid_write
},
1947 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
1948 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1949 .type
= ARM_CP_NO_RAW
,
1950 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
1951 /* TODO: Peripheral port remap register:
1952 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1953 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1956 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
1957 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
1958 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
1959 .writefn
= omap_cachemaint_write
},
1960 { .name
= "C9", .cp
= 15, .crn
= 9,
1961 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
1962 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
1966 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1969 env
->cp15
.c15_cpar
= value
& 0x3fff;
1972 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
1973 { .name
= "XSCALE_CPAR",
1974 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1975 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
1976 .writefn
= xscale_cpar_write
, },
1977 { .name
= "XSCALE_AUXCR",
1978 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
1979 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
1981 /* XScale specific cache-lockdown: since we have no cache we NOP these
1982 * and hope the guest does not really rely on cache behaviour.
1984 { .name
= "XSCALE_LOCK_ICACHE_LINE",
1985 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1986 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1987 { .name
= "XSCALE_UNLOCK_ICACHE",
1988 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1989 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1990 { .name
= "XSCALE_DCACHE_LOCK",
1991 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
1992 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
1993 { .name
= "XSCALE_UNLOCK_DCACHE",
1994 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
1995 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1999 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2000 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2001 * implementation of this implementation-defined space.
2002 * Ideally this should eventually disappear in favour of actually
2003 * implementing the correct behaviour for all cores.
2005 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2006 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2008 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2013 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2014 /* Cache status: RAZ because we have no cache so it's always clean */
2015 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2016 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2021 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2022 /* We never have a a block transfer operation in progress */
2023 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2024 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2026 /* The cache ops themselves: these all NOP for QEMU */
2027 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2028 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2029 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2030 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2031 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2032 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2033 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2034 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2035 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2036 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2037 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2038 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2042 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2043 /* The cache test-and-clean instructions always return (1 << 30)
2044 * to indicate that there are no dirty cache lines.
2046 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2047 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2048 .resetvalue
= (1 << 30) },
2049 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2050 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2051 .resetvalue
= (1 << 30) },
2055 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2056 /* Ignore ReadBuffer accesses */
2057 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2058 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2059 .access
= PL1_RW
, .resetvalue
= 0,
2060 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2064 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2066 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2067 uint64_t mpidr
= cpu
->mp_affinity
;
2069 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2070 mpidr
|= (1U << 31);
2071 /* Cores which are uniprocessor (non-coherent)
2072 * but still implement the MP extensions set
2073 * bit 30. (For instance, A9UP.) However we do
2074 * not currently model any of those cores.
2080 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2081 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2082 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2083 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2087 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2089 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2090 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
2091 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2093 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2094 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
2095 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2097 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
2098 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
2099 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
2100 offsetof(CPUARMState
, cp15
.par_ns
)} },
2101 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
2102 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2103 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2104 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
2105 .writefn
= vmsa_ttbr_write
, .resetfn
= arm_cp_reset_ignore
},
2106 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
2107 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2108 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2109 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
2110 .writefn
= vmsa_ttbr_write
, .resetfn
= arm_cp_reset_ignore
},
2114 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2116 return vfp_get_fpcr(env
);
2119 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2122 vfp_set_fpcr(env
, value
);
2125 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2127 return vfp_get_fpsr(env
);
2130 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2133 vfp_set_fpsr(env
, value
);
2136 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2138 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
2139 return CP_ACCESS_TRAP
;
2141 return CP_ACCESS_OK
;
2144 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2147 env
->daif
= value
& PSTATE_DAIF
;
2150 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
2151 const ARMCPRegInfo
*ri
)
2153 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2154 * SCTLR_EL1.UCI is set.
2156 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
2157 return CP_ACCESS_TRAP
;
2159 return CP_ACCESS_OK
;
2162 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2163 * Page D4-1736 (DDI0487A.b)
2166 static void tlbi_aa64_va_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2169 /* Invalidate by VA (AArch64 version) */
2170 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2171 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2173 tlb_flush_page(CPU(cpu
), pageaddr
);
2176 static void tlbi_aa64_vaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2179 /* Invalidate by VA, all ASIDs (AArch64 version) */
2180 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2181 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2183 tlb_flush_page(CPU(cpu
), pageaddr
);
2186 static void tlbi_aa64_asid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2189 /* Invalidate by ASID (AArch64 version) */
2190 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2191 int asid
= extract64(value
, 48, 16);
2192 tlb_flush(CPU(cpu
), asid
== 0);
2195 static void tlbi_aa64_va_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2199 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2201 CPU_FOREACH(other_cs
) {
2202 tlb_flush_page(other_cs
, pageaddr
);
2206 static void tlbi_aa64_vaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2210 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2212 CPU_FOREACH(other_cs
) {
2213 tlb_flush_page(other_cs
, pageaddr
);
2217 static void tlbi_aa64_asid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2221 int asid
= extract64(value
, 48, 16);
2223 CPU_FOREACH(other_cs
) {
2224 tlb_flush(other_cs
, asid
== 0);
2228 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2230 /* We don't implement EL2, so the only control on DC ZVA is the
2231 * bit in the SCTLR which can prohibit access for EL0.
2233 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
2234 return CP_ACCESS_TRAP
;
2236 return CP_ACCESS_OK
;
2239 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2241 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2242 int dzp_bit
= 1 << 4;
2244 /* DZP indicates whether DC ZVA access is allowed */
2245 if (aa64_zva_access(env
, NULL
) == CP_ACCESS_OK
) {
2248 return cpu
->dcz_blocksize
| dzp_bit
;
2251 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2253 if (!(env
->pstate
& PSTATE_SP
)) {
2254 /* Access to SP_EL0 is undefined if it's being used as
2255 * the stack pointer.
2257 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2259 return CP_ACCESS_OK
;
2262 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2264 return env
->pstate
& PSTATE_SP
;
2267 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
2269 update_spsel(env
, val
);
2272 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2275 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2277 if (raw_read(env
, ri
) == value
) {
2278 /* Skip the TLB flush if nothing actually changed; Linux likes
2279 * to do a lot of pointless SCTLR writes.
2284 raw_write(env
, ri
, value
);
2285 /* ??? Lots of these bits are not implemented. */
2286 /* This may enable/disable the MMU, so do a TLB flush. */
2287 tlb_flush(CPU(cpu
), 1);
2290 static const ARMCPRegInfo v8_cp_reginfo
[] = {
2291 /* Minimal set of EL0-visible registers. This will need to be expanded
2292 * significantly for system emulation of AArch64 CPUs.
2294 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
2295 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
2296 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
2297 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
2298 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
2299 .type
= ARM_CP_NO_RAW
,
2300 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
2301 .fieldoffset
= offsetof(CPUARMState
, daif
),
2302 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
2303 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
2304 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
2305 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
2306 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
2307 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
2308 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
2309 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
2310 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
2311 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
2312 .readfn
= aa64_dczid_read
},
2313 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
2314 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
2315 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
2316 #ifndef CONFIG_USER_ONLY
2317 /* Avoid overhead of an access check that always passes in user-mode */
2318 .accessfn
= aa64_zva_access
,
2321 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
2322 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
2323 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
2324 /* Cache ops: all NOPs since we don't emulate caches */
2325 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
2326 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
2327 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2328 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
2329 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
2330 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2331 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
2332 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
2333 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2334 .accessfn
= aa64_cacheop_access
},
2335 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
2336 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
2337 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2338 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
2339 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
2340 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2341 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
2342 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
2343 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2344 .accessfn
= aa64_cacheop_access
},
2345 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
2346 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
2347 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2348 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
2349 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
2350 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2351 .accessfn
= aa64_cacheop_access
},
2352 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
2353 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
2354 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2355 .accessfn
= aa64_cacheop_access
},
2356 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
2357 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
2358 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2359 /* TLBI operations */
2360 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
2361 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
2362 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
2363 .writefn
= tlbiall_write
},
2364 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
2365 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
2366 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
2367 .writefn
= tlbiall_write
},
2368 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
2369 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2370 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2371 .writefn
= tlbiall_is_write
},
2372 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
2373 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2374 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2375 .writefn
= tlbi_aa64_va_is_write
},
2376 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
2377 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2378 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2379 .writefn
= tlbi_aa64_asid_is_write
},
2380 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
2381 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2382 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2383 .writefn
= tlbi_aa64_vaa_is_write
},
2384 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
2385 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
2386 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2387 .writefn
= tlbi_aa64_va_is_write
},
2388 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
2389 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
2390 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2391 .writefn
= tlbi_aa64_vaa_is_write
},
2392 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
2393 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2394 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2395 .writefn
= tlbiall_write
},
2396 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
2397 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2398 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2399 .writefn
= tlbi_aa64_va_write
},
2400 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
2401 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2402 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2403 .writefn
= tlbi_aa64_asid_write
},
2404 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
2405 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2406 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2407 .writefn
= tlbi_aa64_vaa_write
},
2408 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
2409 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
2410 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2411 .writefn
= tlbi_aa64_va_write
},
2412 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
2413 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
2414 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2415 .writefn
= tlbi_aa64_vaa_write
},
2416 #ifndef CONFIG_USER_ONLY
2417 /* 64 bit address translation operations */
2418 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
2419 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
2420 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
2421 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
2422 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
2423 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
2424 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
2425 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
2426 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
2427 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
2428 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
2429 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
2431 /* TLB invalidate last level of translation table walk */
2432 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
2433 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
2434 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
2435 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2436 .writefn
= tlbimvaa_is_write
},
2437 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
2438 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2439 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
2440 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2441 /* 32 bit cache operations */
2442 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
2443 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2444 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
2445 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2446 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
2447 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2448 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
2449 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2450 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
2451 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2452 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
2453 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2454 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
2455 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2456 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
2457 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2458 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
2459 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2460 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
2461 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2462 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
2463 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2464 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
2465 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2466 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
2467 .type
= ARM_CP_NOP
, .access
= PL1_W
},
2468 /* MMU Domain access control / MPU write buffer control */
2469 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
2470 .access
= PL1_RW
, .resetvalue
= 0,
2471 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
2472 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
2473 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
2474 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
2475 .type
= ARM_CP_ALIAS
,
2476 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
2478 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
2479 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
2480 .type
= ARM_CP_ALIAS
,
2481 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
2482 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[1]) },
2483 /* We rely on the access checks not allowing the guest to write to the
2484 * state field when SPSel indicates that it's being used as the stack
2487 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
2488 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
2489 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
2490 .type
= ARM_CP_ALIAS
,
2491 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
2492 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
2493 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
2494 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
2495 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
2496 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
2497 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
2498 .type
= ARM_CP_NO_RAW
,
2499 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
2503 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
2504 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
2505 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
2506 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
2508 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
2509 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
2510 .type
= ARM_CP_NO_RAW
,
2511 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
2513 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
2514 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
2515 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
2516 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2517 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
2518 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
2519 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
2521 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
2522 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
2523 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2524 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
2525 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
2526 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2527 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
2528 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
2529 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2530 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
2531 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
2532 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2533 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
2534 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
2535 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2536 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
2537 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
2542 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2544 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2545 uint64_t valid_mask
= HCR_MASK
;
2547 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2548 valid_mask
&= ~HCR_HCD
;
2550 valid_mask
&= ~HCR_TSC
;
2553 /* Clear RES0 bits. */
2554 value
&= valid_mask
;
2556 /* These bits change the MMU setup:
2557 * HCR_VM enables stage 2 translation
2558 * HCR_PTW forbids certain page-table setups
2559 * HCR_DC Disables stage1 and enables stage2 translation
2561 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
2562 tlb_flush(CPU(cpu
), 1);
2564 raw_write(env
, ri
, value
);
2567 static const ARMCPRegInfo el2_cp_reginfo
[] = {
2568 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
2569 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
2570 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
2571 .writefn
= hcr_write
},
2572 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
2573 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
2574 .access
= PL2_RW
, .resetvalue
= 0,
2575 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
2576 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
2577 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
2578 .type
= ARM_CP_ALIAS
,
2579 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
2581 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
2582 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
2583 .type
= ARM_CP_ALIAS
,
2584 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
2585 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
2586 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
2587 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
2588 .access
= PL2_RW
, .resetvalue
= 0,
2589 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
2590 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
2591 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
2592 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
2593 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
2594 .type
= ARM_CP_ALIAS
,
2595 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
2596 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[6]) },
2597 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
2598 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
2599 .access
= PL2_RW
, .writefn
= vbar_write
,
2600 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
2602 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
2603 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
2604 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
2605 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
2606 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
2607 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
2608 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
2609 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
2610 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
2611 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
2612 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
2614 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
2615 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
2616 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
2617 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
2618 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
2619 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
2620 .access
= PL2_RW
, .writefn
= vmsa_tcr_el1_write
,
2621 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2622 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
2623 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
2624 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
2625 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
2626 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
2627 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
2628 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
2629 .access
= PL2_RW
, .resetvalue
= 0,
2630 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
2631 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
2632 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
2633 .access
= PL2_RW
, .resetvalue
= 0,
2634 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
2635 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
2636 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2638 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
2639 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
2640 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
2641 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
2642 .writefn
= tlbiall_write
},
2643 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
2644 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
2645 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
2646 .writefn
= tlbi_aa64_vaa_write
},
2647 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
2648 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
2649 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
2650 .writefn
= tlbi_aa64_vaa_write
},
2654 static const ARMCPRegInfo el3_cp_reginfo
[] = {
2655 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
2656 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
2657 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
2658 .resetvalue
= 0, .writefn
= scr_write
},
2659 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
2660 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
2661 .access
= PL3_RW
, .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
2662 .resetfn
= arm_cp_reset_ignore
, .writefn
= scr_write
},
2663 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
2664 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
2665 .access
= PL3_RW
, .resetvalue
= 0,
2666 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
2668 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
2669 .access
= PL3_RW
, .resetvalue
= 0,
2670 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
2671 /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
2672 { .name
= "NSACR", .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
2673 .access
= PL3_W
| PL1_R
, .resetvalue
= 0,
2674 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
) },
2675 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
2676 .access
= PL3_RW
, .writefn
= vbar_write
, .resetvalue
= 0,
2677 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
2678 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
2679 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
2680 .access
= PL3_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
2681 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]) },
2682 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
2683 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
2684 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2685 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
2686 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
2687 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
2688 .access
= PL3_RW
, .writefn
= vmsa_tcr_el1_write
,
2689 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2690 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
2691 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
2692 .type
= ARM_CP_ALIAS
,
2693 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
2695 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
2696 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
2697 .type
= ARM_CP_ALIAS
,
2698 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
2699 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
2700 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
2701 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
2702 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
2703 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
2704 .type
= ARM_CP_ALIAS
,
2705 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
2706 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[7]) },
2707 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
2708 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
2709 .access
= PL3_RW
, .writefn
= vbar_write
,
2710 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
2712 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
2713 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
2714 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
2715 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
2719 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2721 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2722 * but the AArch32 CTR has its own reginfo struct)
2724 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
2725 return CP_ACCESS_TRAP
;
2727 return CP_ACCESS_OK
;
2730 static const ARMCPRegInfo debug_cp_reginfo
[] = {
2731 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2732 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2733 * unlike DBGDRAR it is never accessible from EL0.
2734 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2737 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
2738 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2739 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
2740 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
2741 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2742 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2743 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2744 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
2745 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
2746 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
2748 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
2750 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
2751 * We don't implement the configurable EL0 access.
2753 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
2754 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
2755 .type
= ARM_CP_ALIAS
,
2757 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
2758 .resetfn
= arm_cp_reset_ignore
},
2759 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2760 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
2761 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
2762 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2763 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
2764 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
2765 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
2766 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2767 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
2768 * implement vector catch debug events yet.
2771 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
2772 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2776 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
2777 /* 64 bit access versions of the (dummy) debug registers */
2778 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
2779 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
2780 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
2781 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
2785 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
2787 CPUARMState
*env
= &cpu
->env
;
2789 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
2790 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
2792 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
2794 if (env
->cpu_watchpoint
[n
]) {
2795 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
2796 env
->cpu_watchpoint
[n
] = NULL
;
2799 if (!extract64(wcr
, 0, 1)) {
2800 /* E bit clear : watchpoint disabled */
2804 switch (extract64(wcr
, 3, 2)) {
2806 /* LSC 00 is reserved and must behave as if the wp is disabled */
2809 flags
|= BP_MEM_READ
;
2812 flags
|= BP_MEM_WRITE
;
2815 flags
|= BP_MEM_ACCESS
;
2819 /* Attempts to use both MASK and BAS fields simultaneously are
2820 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
2821 * thus generating a watchpoint for every byte in the masked region.
2823 mask
= extract64(wcr
, 24, 4);
2824 if (mask
== 1 || mask
== 2) {
2825 /* Reserved values of MASK; we must act as if the mask value was
2826 * some non-reserved value, or as if the watchpoint were disabled.
2827 * We choose the latter.
2831 /* Watchpoint covers an aligned area up to 2GB in size */
2833 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
2834 * whether the watchpoint fires when the unmasked bits match; we opt
2835 * to generate the exceptions.
2839 /* Watchpoint covers bytes defined by the byte address select bits */
2840 int bas
= extract64(wcr
, 5, 8);
2844 /* This must act as if the watchpoint is disabled */
2848 if (extract64(wvr
, 2, 1)) {
2849 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
2850 * ignored, and BAS[3:0] define which bytes to watch.
2854 /* The BAS bits are supposed to be programmed to indicate a contiguous
2855 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
2856 * we fire for each byte in the word/doubleword addressed by the WVR.
2857 * We choose to ignore any non-zero bits after the first range of 1s.
2859 basstart
= ctz32(bas
);
2860 len
= cto32(bas
>> basstart
);
2864 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
2865 &env
->cpu_watchpoint
[n
]);
2868 void hw_watchpoint_update_all(ARMCPU
*cpu
)
2871 CPUARMState
*env
= &cpu
->env
;
2873 /* Completely clear out existing QEMU watchpoints and our array, to
2874 * avoid possible stale entries following migration load.
2876 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
2877 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
2879 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
2880 hw_watchpoint_update(cpu
, i
);
2884 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2887 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2890 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
2891 * register reads and behaves as if values written are sign extended.
2892 * Bits [1:0] are RES0.
2894 value
= sextract64(value
, 0, 49) & ~3ULL;
2896 raw_write(env
, ri
, value
);
2897 hw_watchpoint_update(cpu
, i
);
2900 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2903 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2906 raw_write(env
, ri
, value
);
2907 hw_watchpoint_update(cpu
, i
);
2910 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
2912 CPUARMState
*env
= &cpu
->env
;
2913 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
2914 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
2919 if (env
->cpu_breakpoint
[n
]) {
2920 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
2921 env
->cpu_breakpoint
[n
] = NULL
;
2924 if (!extract64(bcr
, 0, 1)) {
2925 /* E bit clear : watchpoint disabled */
2929 bt
= extract64(bcr
, 20, 4);
2932 case 4: /* unlinked address mismatch (reserved if AArch64) */
2933 case 5: /* linked address mismatch (reserved if AArch64) */
2934 qemu_log_mask(LOG_UNIMP
,
2935 "arm: address mismatch breakpoint types not implemented");
2937 case 0: /* unlinked address match */
2938 case 1: /* linked address match */
2940 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
2941 * we behave as if the register was sign extended. Bits [1:0] are
2942 * RES0. The BAS field is used to allow setting breakpoints on 16
2943 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
2944 * a bp will fire if the addresses covered by the bp and the addresses
2945 * covered by the insn overlap but the insn doesn't start at the
2946 * start of the bp address range. We choose to require the insn and
2947 * the bp to have the same address. The constraints on writing to
2948 * BAS enforced in dbgbcr_write mean we have only four cases:
2949 * 0b0000 => no breakpoint
2950 * 0b0011 => breakpoint on addr
2951 * 0b1100 => breakpoint on addr + 2
2952 * 0b1111 => breakpoint on addr
2953 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
2955 int bas
= extract64(bcr
, 5, 4);
2956 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
2965 case 2: /* unlinked context ID match */
2966 case 8: /* unlinked VMID match (reserved if no EL2) */
2967 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
2968 qemu_log_mask(LOG_UNIMP
,
2969 "arm: unlinked context breakpoint types not implemented");
2971 case 9: /* linked VMID match (reserved if no EL2) */
2972 case 11: /* linked context ID and VMID match (reserved if no EL2) */
2973 case 3: /* linked context ID match */
2975 /* We must generate no events for Linked context matches (unless
2976 * they are linked to by some other bp/wp, which is handled in
2977 * updates for the linking bp/wp). We choose to also generate no events
2978 * for reserved values.
2983 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
2986 void hw_breakpoint_update_all(ARMCPU
*cpu
)
2989 CPUARMState
*env
= &cpu
->env
;
2991 /* Completely clear out existing QEMU breakpoints and our array, to
2992 * avoid possible stale entries following migration load.
2994 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
2995 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
2997 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
2998 hw_breakpoint_update(cpu
, i
);
3002 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3005 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3008 raw_write(env
, ri
, value
);
3009 hw_breakpoint_update(cpu
, i
);
3012 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3015 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3018 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3021 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
3022 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
3024 raw_write(env
, ri
, value
);
3025 hw_breakpoint_update(cpu
, i
);
3028 static void define_debug_regs(ARMCPU
*cpu
)
3030 /* Define v7 and v8 architectural debug registers.
3031 * These are just dummy implementations for now.
3034 int wrps
, brps
, ctx_cmps
;
3035 ARMCPRegInfo dbgdidr
= {
3036 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
3037 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
3040 /* Note that all these register fields hold "number of Xs minus 1". */
3041 brps
= extract32(cpu
->dbgdidr
, 24, 4);
3042 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
3043 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
3045 assert(ctx_cmps
<= brps
);
3047 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3048 * of the debug registers such as number of breakpoints;
3049 * check that if they both exist then they agree.
3051 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
3052 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
3053 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
3054 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
3057 define_one_arm_cp_reg(cpu
, &dbgdidr
);
3058 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
3060 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
3061 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
3064 for (i
= 0; i
< brps
+ 1; i
++) {
3065 ARMCPRegInfo dbgregs
[] = {
3066 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
3067 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
3069 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
3070 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
3072 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
3073 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
3075 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
3076 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
3080 define_arm_cp_regs(cpu
, dbgregs
);
3083 for (i
= 0; i
< wrps
+ 1; i
++) {
3084 ARMCPRegInfo dbgregs
[] = {
3085 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
3086 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
3088 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
3089 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
3091 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
3092 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
3094 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
3095 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
3099 define_arm_cp_regs(cpu
, dbgregs
);
3103 void register_cp_regs_for_features(ARMCPU
*cpu
)
3105 /* Register all the coprocessor registers based on feature bits */
3106 CPUARMState
*env
= &cpu
->env
;
3107 if (arm_feature(env
, ARM_FEATURE_M
)) {
3108 /* M profile has no coprocessor registers */
3112 define_arm_cp_regs(cpu
, cp_reginfo
);
3113 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3114 /* Must go early as it is full of wildcards that may be
3115 * overridden by later definitions.
3117 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
3120 if (arm_feature(env
, ARM_FEATURE_V6
)) {
3121 /* The ID registers all have impdef reset values */
3122 ARMCPRegInfo v6_idregs
[] = {
3123 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
3124 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
3125 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3126 .resetvalue
= cpu
->id_pfr0
},
3127 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
3128 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
3129 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3130 .resetvalue
= cpu
->id_pfr1
},
3131 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
3132 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
3133 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3134 .resetvalue
= cpu
->id_dfr0
},
3135 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
3136 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
3137 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3138 .resetvalue
= cpu
->id_afr0
},
3139 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
3140 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
3141 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3142 .resetvalue
= cpu
->id_mmfr0
},
3143 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
3144 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
3145 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3146 .resetvalue
= cpu
->id_mmfr1
},
3147 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
3148 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
3149 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3150 .resetvalue
= cpu
->id_mmfr2
},
3151 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
3152 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
3153 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3154 .resetvalue
= cpu
->id_mmfr3
},
3155 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
3156 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
3157 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3158 .resetvalue
= cpu
->id_isar0
},
3159 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
3160 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
3161 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3162 .resetvalue
= cpu
->id_isar1
},
3163 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
3164 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
3165 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3166 .resetvalue
= cpu
->id_isar2
},
3167 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
3168 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
3169 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3170 .resetvalue
= cpu
->id_isar3
},
3171 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
3172 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
3173 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3174 .resetvalue
= cpu
->id_isar4
},
3175 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
3176 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
3177 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3178 .resetvalue
= cpu
->id_isar5
},
3179 /* 6..7 are as yet unallocated and must RAZ */
3180 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
3181 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
3183 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
3184 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
3188 define_arm_cp_regs(cpu
, v6_idregs
);
3189 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
3191 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
3193 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
3194 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
3196 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
3197 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
3199 if (arm_feature(env
, ARM_FEATURE_V7
)) {
3200 /* v7 performance monitor control register: same implementor
3201 * field as main ID register, and we implement only the cycle
3204 #ifndef CONFIG_USER_ONLY
3205 ARMCPRegInfo pmcr
= {
3206 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
3208 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
3209 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
3210 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
3211 .raw_writefn
= raw_write
,
3213 ARMCPRegInfo pmcr64
= {
3214 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
3215 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
3216 .access
= PL0_RW
, .accessfn
= pmreg_access
,
3218 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
3219 .resetvalue
= cpu
->midr
& 0xff000000,
3220 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
3222 define_one_arm_cp_reg(cpu
, &pmcr
);
3223 define_one_arm_cp_reg(cpu
, &pmcr64
);
3225 ARMCPRegInfo clidr
= {
3226 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
3227 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
3228 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
3230 define_one_arm_cp_reg(cpu
, &clidr
);
3231 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
3232 define_debug_regs(cpu
);
3234 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
3236 if (arm_feature(env
, ARM_FEATURE_V8
)) {
3237 /* AArch64 ID registers, which all have impdef reset values */
3238 ARMCPRegInfo v8_idregs
[] = {
3239 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3240 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
3241 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3242 .resetvalue
= cpu
->id_aa64pfr0
},
3243 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3244 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
3245 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3246 .resetvalue
= cpu
->id_aa64pfr1
},
3247 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3248 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
3249 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3250 /* We mask out the PMUVer field, because we don't currently
3251 * implement the PMU. Not advertising it prevents the guest
3252 * from trying to use it and getting UNDEFs on registers we
3255 .resetvalue
= cpu
->id_aa64dfr0
& ~0xf00 },
3256 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3257 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
3258 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3259 .resetvalue
= cpu
->id_aa64dfr1
},
3260 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3261 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
3262 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3263 .resetvalue
= cpu
->id_aa64afr0
},
3264 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3265 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
3266 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3267 .resetvalue
= cpu
->id_aa64afr1
},
3268 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
3269 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
3270 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3271 .resetvalue
= cpu
->id_aa64isar0
},
3272 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
3273 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
3274 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3275 .resetvalue
= cpu
->id_aa64isar1
},
3276 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3277 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
3278 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3279 .resetvalue
= cpu
->id_aa64mmfr0
},
3280 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3281 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
3282 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3283 .resetvalue
= cpu
->id_aa64mmfr1
},
3284 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
3285 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
3286 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3287 .resetvalue
= cpu
->mvfr0
},
3288 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
3289 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
3290 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3291 .resetvalue
= cpu
->mvfr1
},
3292 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
3293 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
3294 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3295 .resetvalue
= cpu
->mvfr2
},
3298 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
3299 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
3300 !arm_feature(env
, ARM_FEATURE_EL2
)) {
3301 ARMCPRegInfo rvbar
= {
3302 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
3303 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
3304 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
3306 define_one_arm_cp_reg(cpu
, &rvbar
);
3308 define_arm_cp_regs(cpu
, v8_idregs
);
3309 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
3311 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3312 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
3313 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
3314 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
3315 ARMCPRegInfo rvbar
= {
3316 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3317 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
3318 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
3320 define_one_arm_cp_reg(cpu
, &rvbar
);
3323 /* If EL2 is missing but higher ELs are enabled, we need to
3324 * register the no_el2 reginfos.
3326 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3327 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
3330 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3331 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
3332 ARMCPRegInfo rvbar
= {
3333 .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
3334 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
3335 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
3337 define_one_arm_cp_reg(cpu
, &rvbar
);
3339 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
3340 /* These are the MPU registers prior to PMSAv6. Any new
3341 * PMSA core later than the ARM946 will require that we
3342 * implement the PMSAv6 or PMSAv7 registers, which are
3343 * completely different.
3345 assert(!arm_feature(env
, ARM_FEATURE_V6
));
3346 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
3348 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
3350 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
3351 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
3353 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
3354 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
3356 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
3357 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
3359 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
3360 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
3362 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
3363 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
3365 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
3366 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
3368 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
3369 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
3371 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
3372 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
3374 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
3375 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
3377 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
3378 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
3380 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3381 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
3383 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
3384 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
3385 * be read-only (ie write causes UNDEF exception).
3388 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
3389 /* Pre-v8 MIDR space.
3390 * Note that the MIDR isn't a simple constant register because
3391 * of the TI925 behaviour where writes to another register can
3392 * cause the MIDR value to change.
3394 * Unimplemented registers in the c15 0 0 0 space default to
3395 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
3396 * and friends override accordingly.
3399 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
3400 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
3401 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
3402 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
3403 .type
= ARM_CP_OVERRIDE
},
3404 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
3406 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
3407 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3409 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
3410 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3412 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
3413 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3415 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
3416 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3418 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
3419 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3422 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
3423 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
3424 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
3425 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
},
3426 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
3427 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
3428 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
3429 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
3430 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
3431 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
3432 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
3433 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
3434 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
3435 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
3438 ARMCPRegInfo id_cp_reginfo
[] = {
3439 /* These are common to v8 and pre-v8 */
3441 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
3442 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
3443 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
3444 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
3445 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
3446 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
3447 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
3449 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
3450 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3452 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
3453 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3456 ARMCPRegInfo crn0_wi_reginfo
= {
3457 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
3458 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
3459 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
3461 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
3462 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
3464 /* Register the blanket "writes ignored" value first to cover the
3465 * whole space. Then update the specific ID registers to allow write
3466 * access, so that they ignore writes rather than causing them to
3469 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
3470 for (r
= id_pre_v8_midr_cp_reginfo
;
3471 r
->type
!= ARM_CP_SENTINEL
; r
++) {
3474 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
3478 if (arm_feature(env
, ARM_FEATURE_V8
)) {
3479 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
3481 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
3483 define_arm_cp_regs(cpu
, id_cp_reginfo
);
3486 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
3487 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
3490 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
3491 ARMCPRegInfo auxcr
= {
3492 .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
3493 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
3494 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3495 .resetvalue
= cpu
->reset_auxcr
3497 define_one_arm_cp_reg(cpu
, &auxcr
);
3500 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
3501 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
3502 /* 32 bit view is [31:18] 0...0 [43:32]. */
3503 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
3504 | extract64(cpu
->reset_cbar
, 32, 12);
3505 ARMCPRegInfo cbar_reginfo
[] = {
3507 .type
= ARM_CP_CONST
,
3508 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
3509 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
3510 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
3511 .type
= ARM_CP_CONST
,
3512 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
3513 .access
= PL1_R
, .resetvalue
= cbar32
},
3516 /* We don't implement a r/w 64 bit CBAR currently */
3517 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
3518 define_arm_cp_regs(cpu
, cbar_reginfo
);
3520 ARMCPRegInfo cbar
= {
3522 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
3523 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
3524 .fieldoffset
= offsetof(CPUARMState
,
3525 cp15
.c15_config_base_address
)
3527 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
3528 cbar
.access
= PL1_R
;
3529 cbar
.fieldoffset
= 0;
3530 cbar
.type
= ARM_CP_CONST
;
3532 define_one_arm_cp_reg(cpu
, &cbar
);
3536 /* Generic registers whose values depend on the implementation */
3538 ARMCPRegInfo sctlr
= {
3539 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
3540 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
3542 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
3543 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
3544 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
3545 .raw_writefn
= raw_write
,
3547 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
3548 /* Normally we would always end the TB on an SCTLR write, but Linux
3549 * arch/arm/mach-pxa/sleep.S expects two instructions following
3550 * an MMU enable to execute from cache. Imitate this behaviour.
3552 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
3554 define_one_arm_cp_reg(cpu
, &sctlr
);
3558 ARMCPU
*cpu_arm_init(const char *cpu_model
)
3560 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU
, cpu_model
));
3563 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
3565 CPUState
*cs
= CPU(cpu
);
3566 CPUARMState
*env
= &cpu
->env
;
3568 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
3569 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
3570 aarch64_fpu_gdb_set_reg
,
3571 34, "aarch64-fpu.xml", 0);
3572 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
3573 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
3574 51, "arm-neon.xml", 0);
3575 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
3576 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
3577 35, "arm-vfp3.xml", 0);
3578 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
3579 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
3580 19, "arm-vfp.xml", 0);
3584 /* Sort alphabetically by type name, except for "any". */
3585 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
3587 ObjectClass
*class_a
= (ObjectClass
*)a
;
3588 ObjectClass
*class_b
= (ObjectClass
*)b
;
3589 const char *name_a
, *name_b
;
3591 name_a
= object_class_get_name(class_a
);
3592 name_b
= object_class_get_name(class_b
);
3593 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
3595 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
3598 return strcmp(name_a
, name_b
);
3602 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
3604 ObjectClass
*oc
= data
;
3605 CPUListState
*s
= user_data
;
3606 const char *typename
;
3609 typename
= object_class_get_name(oc
);
3610 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
3611 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
3616 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
3620 .cpu_fprintf
= cpu_fprintf
,
3624 list
= object_class_get_list(TYPE_ARM_CPU
, false);
3625 list
= g_slist_sort(list
, arm_cpu_list_compare
);
3626 (*cpu_fprintf
)(f
, "Available CPUs:\n");
3627 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
3630 /* The 'host' CPU type is dynamically registered only if KVM is
3631 * enabled, so we have to special-case it here:
3633 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
3637 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
3639 ObjectClass
*oc
= data
;
3640 CpuDefinitionInfoList
**cpu_list
= user_data
;
3641 CpuDefinitionInfoList
*entry
;
3642 CpuDefinitionInfo
*info
;
3643 const char *typename
;
3645 typename
= object_class_get_name(oc
);
3646 info
= g_malloc0(sizeof(*info
));
3647 info
->name
= g_strndup(typename
,
3648 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
3650 entry
= g_malloc0(sizeof(*entry
));
3651 entry
->value
= info
;
3652 entry
->next
= *cpu_list
;
3656 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
3658 CpuDefinitionInfoList
*cpu_list
= NULL
;
3661 list
= object_class_get_list(TYPE_ARM_CPU
, false);
3662 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
3668 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
3669 void *opaque
, int state
, int secstate
,
3670 int crm
, int opc1
, int opc2
)
3672 /* Private utility function for define_one_arm_cp_reg_with_opaque():
3673 * add a single reginfo struct to the hash table.
3675 uint32_t *key
= g_new(uint32_t, 1);
3676 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
3677 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
3678 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
3680 /* Reset the secure state to the specific incoming state. This is
3681 * necessary as the register may have been defined with both states.
3683 r2
->secure
= secstate
;
3685 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
3686 /* Register is banked (using both entries in array).
3687 * Overwriting fieldoffset as the array is only used to define
3688 * banked registers but later only fieldoffset is used.
3690 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
3693 if (state
== ARM_CP_STATE_AA32
) {
3694 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
3695 /* If the register is banked then we don't need to migrate or
3696 * reset the 32-bit instance in certain cases:
3698 * 1) If the register has both 32-bit and 64-bit instances then we
3699 * can count on the 64-bit instance taking care of the
3701 * 2) If ARMv8 is enabled then we can count on a 64-bit version
3702 * taking care of the secure bank. This requires that separate
3703 * 32 and 64-bit definitions are provided.
3705 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
3706 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
3707 r2
->type
|= ARM_CP_ALIAS
;
3708 r2
->resetfn
= arm_cp_reset_ignore
;
3710 } else if ((secstate
!= r
->secure
) && !ns
) {
3711 /* The register is not banked so we only want to allow migration of
3712 * the non-secure instance.
3714 r2
->type
|= ARM_CP_ALIAS
;
3715 r2
->resetfn
= arm_cp_reset_ignore
;
3718 if (r
->state
== ARM_CP_STATE_BOTH
) {
3719 /* We assume it is a cp15 register if the .cp field is left unset.
3725 #ifdef HOST_WORDS_BIGENDIAN
3726 if (r2
->fieldoffset
) {
3727 r2
->fieldoffset
+= sizeof(uint32_t);
3732 if (state
== ARM_CP_STATE_AA64
) {
3733 /* To allow abbreviation of ARMCPRegInfo
3734 * definitions, we treat cp == 0 as equivalent to
3735 * the value for "standard guest-visible sysreg".
3736 * STATE_BOTH definitions are also always "standard
3737 * sysreg" in their AArch64 view (the .cp value may
3738 * be non-zero for the benefit of the AArch32 view).
3740 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
3741 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
3743 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
3744 r2
->opc0
, opc1
, opc2
);
3746 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
3749 r2
->opaque
= opaque
;
3751 /* reginfo passed to helpers is correct for the actual access,
3752 * and is never ARM_CP_STATE_BOTH:
3755 /* Make sure reginfo passed to helpers for wildcarded regs
3756 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
3761 /* By convention, for wildcarded registers only the first
3762 * entry is used for migration; the others are marked as
3763 * ALIAS so we don't try to transfer the register
3764 * multiple times. Special registers (ie NOP/WFI) are
3765 * never migratable and not even raw-accessible.
3767 if ((r
->type
& ARM_CP_SPECIAL
)) {
3768 r2
->type
|= ARM_CP_NO_RAW
;
3770 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
3771 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
3772 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
3773 r2
->type
|= ARM_CP_ALIAS
;
3776 /* Check that raw accesses are either forbidden or handled. Note that
3777 * we can't assert this earlier because the setup of fieldoffset for
3778 * banked registers has to be done first.
3780 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
3781 assert(!raw_accessors_invalid(r2
));
3784 /* Overriding of an existing definition must be explicitly
3787 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
3788 ARMCPRegInfo
*oldreg
;
3789 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
3790 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
3791 fprintf(stderr
, "Register redefined: cp=%d %d bit "
3792 "crn=%d crm=%d opc1=%d opc2=%d, "
3793 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
3794 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
3795 oldreg
->name
, r2
->name
);
3796 g_assert_not_reached();
3799 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
3803 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
3804 const ARMCPRegInfo
*r
, void *opaque
)
3806 /* Define implementations of coprocessor registers.
3807 * We store these in a hashtable because typically
3808 * there are less than 150 registers in a space which
3809 * is 16*16*16*8*8 = 262144 in size.
3810 * Wildcarding is supported for the crm, opc1 and opc2 fields.
3811 * If a register is defined twice then the second definition is
3812 * used, so this can be used to define some generic registers and
3813 * then override them with implementation specific variations.
3814 * At least one of the original and the second definition should
3815 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
3816 * against accidental use.
3818 * The state field defines whether the register is to be
3819 * visible in the AArch32 or AArch64 execution state. If the
3820 * state is set to ARM_CP_STATE_BOTH then we synthesise a
3821 * reginfo structure for the AArch32 view, which sees the lower
3822 * 32 bits of the 64 bit register.
3824 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
3825 * be wildcarded. AArch64 registers are always considered to be 64
3826 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
3827 * the register, if any.
3829 int crm
, opc1
, opc2
, state
;
3830 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
3831 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
3832 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
3833 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
3834 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
3835 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
3836 /* 64 bit registers have only CRm and Opc1 fields */
3837 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
3838 /* op0 only exists in the AArch64 encodings */
3839 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
3840 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
3841 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
3842 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
3843 * encodes a minimum access level for the register. We roll this
3844 * runtime check into our general permission check code, so check
3845 * here that the reginfo's specified permissions are strict enough
3846 * to encompass the generic architectural permission check.
3848 if (r
->state
!= ARM_CP_STATE_AA32
) {
3851 case 0: case 1: case 2:
3864 /* unallocated encoding, so not possible */
3872 /* min_EL EL1, secure mode only (we don't check the latter) */
3876 /* broken reginfo with out-of-range opc1 */
3880 /* assert our permissions are not too lax (stricter is fine) */
3881 assert((r
->access
& ~mask
) == 0);
3884 /* Check that the register definition has enough info to handle
3885 * reads and writes if they are permitted.
3887 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
3888 if (r
->access
& PL3_R
) {
3889 assert((r
->fieldoffset
||
3890 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
3893 if (r
->access
& PL3_W
) {
3894 assert((r
->fieldoffset
||
3895 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
3899 /* Bad type field probably means missing sentinel at end of reg list */
3900 assert(cptype_valid(r
->type
));
3901 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
3902 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
3903 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
3904 for (state
= ARM_CP_STATE_AA32
;
3905 state
<= ARM_CP_STATE_AA64
; state
++) {
3906 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
3909 if (state
== ARM_CP_STATE_AA32
) {
3910 /* Under AArch32 CP registers can be common
3911 * (same for secure and non-secure world) or banked.
3913 switch (r
->secure
) {
3914 case ARM_CP_SECSTATE_S
:
3915 case ARM_CP_SECSTATE_NS
:
3916 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
3917 r
->secure
, crm
, opc1
, opc2
);
3920 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
3923 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
3929 /* AArch64 registers get mapped to non-secure instance
3931 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
3941 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
3942 const ARMCPRegInfo
*regs
, void *opaque
)
3944 /* Define a whole list of registers */
3945 const ARMCPRegInfo
*r
;
3946 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
3947 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
3951 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
3953 return g_hash_table_lookup(cpregs
, &encoded_cp
);
3956 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3959 /* Helper coprocessor write function for write-ignore registers */
3962 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3964 /* Helper coprocessor write function for read-as-zero registers */
3968 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3970 /* Helper coprocessor reset function for do-nothing-on-reset registers */
3973 static int bad_mode_switch(CPUARMState
*env
, int mode
)
3975 /* Return true if it is not valid for us to switch to
3976 * this CPU mode (ie all the UNPREDICTABLE cases in
3977 * the ARM ARM CPSRWriteByInstr pseudocode).
3980 case ARM_CPU_MODE_USR
:
3981 case ARM_CPU_MODE_SYS
:
3982 case ARM_CPU_MODE_SVC
:
3983 case ARM_CPU_MODE_ABT
:
3984 case ARM_CPU_MODE_UND
:
3985 case ARM_CPU_MODE_IRQ
:
3986 case ARM_CPU_MODE_FIQ
:
3988 case ARM_CPU_MODE_MON
:
3989 return !arm_is_secure(env
);
3995 uint32_t cpsr_read(CPUARMState
*env
)
3998 ZF
= (env
->ZF
== 0);
3999 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
4000 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
4001 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
4002 | ((env
->condexec_bits
& 0xfc) << 8)
4003 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
4006 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
4008 uint32_t changed_daif
;
4010 if (mask
& CPSR_NZCV
) {
4011 env
->ZF
= (~val
) & CPSR_Z
;
4013 env
->CF
= (val
>> 29) & 1;
4014 env
->VF
= (val
<< 3) & 0x80000000;
4017 env
->QF
= ((val
& CPSR_Q
) != 0);
4019 env
->thumb
= ((val
& CPSR_T
) != 0);
4020 if (mask
& CPSR_IT_0_1
) {
4021 env
->condexec_bits
&= ~3;
4022 env
->condexec_bits
|= (val
>> 25) & 3;
4024 if (mask
& CPSR_IT_2_7
) {
4025 env
->condexec_bits
&= 3;
4026 env
->condexec_bits
|= (val
>> 8) & 0xfc;
4028 if (mask
& CPSR_GE
) {
4029 env
->GE
= (val
>> 16) & 0xf;
4032 /* In a V7 implementation that includes the security extensions but does
4033 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
4034 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
4035 * bits respectively.
4037 * In a V8 implementation, it is permitted for privileged software to
4038 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
4040 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
4041 arm_feature(env
, ARM_FEATURE_EL3
) &&
4042 !arm_feature(env
, ARM_FEATURE_EL2
) &&
4043 !arm_is_secure(env
)) {
4045 changed_daif
= (env
->daif
^ val
) & mask
;
4047 if (changed_daif
& CPSR_A
) {
4048 /* Check to see if we are allowed to change the masking of async
4049 * abort exceptions from a non-secure state.
4051 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
4052 qemu_log_mask(LOG_GUEST_ERROR
,
4053 "Ignoring attempt to switch CPSR_A flag from "
4054 "non-secure world with SCR.AW bit clear\n");
4059 if (changed_daif
& CPSR_F
) {
4060 /* Check to see if we are allowed to change the masking of FIQ
4061 * exceptions from a non-secure state.
4063 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
4064 qemu_log_mask(LOG_GUEST_ERROR
,
4065 "Ignoring attempt to switch CPSR_F flag from "
4066 "non-secure world with SCR.FW bit clear\n");
4070 /* Check whether non-maskable FIQ (NMFI) support is enabled.
4071 * If this bit is set software is not allowed to mask
4072 * FIQs, but is allowed to set CPSR_F to 0.
4074 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
4076 qemu_log_mask(LOG_GUEST_ERROR
,
4077 "Ignoring attempt to enable CPSR_F flag "
4078 "(non-maskable FIQ [NMFI] support enabled)\n");
4084 env
->daif
&= ~(CPSR_AIF
& mask
);
4085 env
->daif
|= val
& CPSR_AIF
& mask
;
4087 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
4088 if (bad_mode_switch(env
, val
& CPSR_M
)) {
4089 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
4090 * We choose to ignore the attempt and leave the CPSR M field
4095 switch_mode(env
, val
& CPSR_M
);
4098 mask
&= ~CACHED_CPSR_BITS
;
4099 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
4102 /* Sign/zero extend */
4103 uint32_t HELPER(sxtb16
)(uint32_t x
)
4106 res
= (uint16_t)(int8_t)x
;
4107 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
4111 uint32_t HELPER(uxtb16
)(uint32_t x
)
4114 res
= (uint16_t)(uint8_t)x
;
4115 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
4119 uint32_t HELPER(clz
)(uint32_t x
)
4124 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
4128 if (num
== INT_MIN
&& den
== -1)
4133 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
4140 uint32_t HELPER(rbit
)(uint32_t x
)
4142 x
= ((x
& 0xff000000) >> 24)
4143 | ((x
& 0x00ff0000) >> 8)
4144 | ((x
& 0x0000ff00) << 8)
4145 | ((x
& 0x000000ff) << 24);
4146 x
= ((x
& 0xf0f0f0f0) >> 4)
4147 | ((x
& 0x0f0f0f0f) << 4);
4148 x
= ((x
& 0x88888888) >> 3)
4149 | ((x
& 0x44444444) >> 1)
4150 | ((x
& 0x22222222) << 1)
4151 | ((x
& 0x11111111) << 3);
4155 #if defined(CONFIG_USER_ONLY)
4157 /* These should probably raise undefined insn exceptions. */
4158 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
4160 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4162 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
4165 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
4167 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4169 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
4173 void switch_mode(CPUARMState
*env
, int mode
)
4175 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4177 if (mode
!= ARM_CPU_MODE_USR
) {
4178 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
4182 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
4184 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4186 cpu_abort(CPU(cpu
), "banked r13 write\n");
4189 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
4191 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4193 cpu_abort(CPU(cpu
), "banked r13 read\n");
4197 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
4198 uint32_t cur_el
, bool secure
)
4203 void aarch64_sync_64_to_32(CPUARMState
*env
)
4205 g_assert_not_reached();
4210 /* Map CPU modes onto saved register banks. */
4211 int bank_number(int mode
)
4214 case ARM_CPU_MODE_USR
:
4215 case ARM_CPU_MODE_SYS
:
4217 case ARM_CPU_MODE_SVC
:
4219 case ARM_CPU_MODE_ABT
:
4221 case ARM_CPU_MODE_UND
:
4223 case ARM_CPU_MODE_IRQ
:
4225 case ARM_CPU_MODE_FIQ
:
4227 case ARM_CPU_MODE_HYP
:
4229 case ARM_CPU_MODE_MON
:
4232 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode
);
4235 void switch_mode(CPUARMState
*env
, int mode
)
4240 old_mode
= env
->uncached_cpsr
& CPSR_M
;
4241 if (mode
== old_mode
)
4244 if (old_mode
== ARM_CPU_MODE_FIQ
) {
4245 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
4246 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
4247 } else if (mode
== ARM_CPU_MODE_FIQ
) {
4248 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
4249 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
4252 i
= bank_number(old_mode
);
4253 env
->banked_r13
[i
] = env
->regs
[13];
4254 env
->banked_r14
[i
] = env
->regs
[14];
4255 env
->banked_spsr
[i
] = env
->spsr
;
4257 i
= bank_number(mode
);
4258 env
->regs
[13] = env
->banked_r13
[i
];
4259 env
->regs
[14] = env
->banked_r14
[i
];
4260 env
->spsr
= env
->banked_spsr
[i
];
4263 /* Physical Interrupt Target EL Lookup Table
4265 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
4267 * The below multi-dimensional table is used for looking up the target
4268 * exception level given numerous condition criteria. Specifically, the
4269 * target EL is based on SCR and HCR routing controls as well as the
4270 * currently executing EL and secure state.
4273 * target_el_table[2][2][2][2][2][4]
4274 * | | | | | +--- Current EL
4275 * | | | | +------ Non-secure(0)/Secure(1)
4276 * | | | +--------- HCR mask override
4277 * | | +------------ SCR exec state control
4278 * | +--------------- SCR mask override
4279 * +------------------ 32-bit(0)/64-bit(1) EL3
4281 * The table values are as such:
4285 * The ARM ARM target EL table includes entries indicating that an "exception
4286 * is not taken". The two cases where this is applicable are:
4287 * 1) An exception is taken from EL3 but the SCR does not have the exception
4289 * 2) An exception is taken from EL2 but the HCR does not have the exception
4291 * In these two cases, the below table contain a target of EL1. This value is
4292 * returned as it is expected that the consumer of the table data will check
4293 * for "target EL >= current EL" to ensure the exception is not taken.
4297 * BIT IRQ IMO Non-secure Secure
4298 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
4300 const int8_t target_el_table
[2][2][2][2][2][4] = {
4301 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
4302 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
4303 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
4304 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
4305 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
4306 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
4307 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
4308 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
4309 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
4310 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
4311 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
4312 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
4313 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
4314 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
4315 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
4316 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
4320 * Determine the target EL for physical exceptions
4322 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
4323 uint32_t cur_el
, bool secure
)
4325 CPUARMState
*env
= cs
->env_ptr
;
4326 int rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
4330 int is64
= arm_el_is_aa64(env
, 3);
4334 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
4335 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
4338 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
4339 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
4342 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
4343 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
4347 /* If HCR.TGE is set then HCR is treated as being 1 */
4348 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
4350 /* Perform a table-lookup for the target EL given the current state */
4351 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
4353 assert(target_el
> 0);
4358 static void v7m_push(CPUARMState
*env
, uint32_t val
)
4360 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
4363 stl_phys(cs
->as
, env
->regs
[13], val
);
4366 static uint32_t v7m_pop(CPUARMState
*env
)
4368 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
4371 val
= ldl_phys(cs
->as
, env
->regs
[13]);
4376 /* Switch to V7M main or process stack pointer. */
4377 static void switch_v7m_sp(CPUARMState
*env
, int process
)
4380 if (env
->v7m
.current_sp
!= process
) {
4381 tmp
= env
->v7m
.other_sp
;
4382 env
->v7m
.other_sp
= env
->regs
[13];
4383 env
->regs
[13] = tmp
;
4384 env
->v7m
.current_sp
= process
;
4388 static void do_v7m_exception_exit(CPUARMState
*env
)
4393 type
= env
->regs
[15];
4394 if (env
->v7m
.exception
!= 0)
4395 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
4397 /* Switch to the target stack. */
4398 switch_v7m_sp(env
, (type
& 4) != 0);
4399 /* Pop registers. */
4400 env
->regs
[0] = v7m_pop(env
);
4401 env
->regs
[1] = v7m_pop(env
);
4402 env
->regs
[2] = v7m_pop(env
);
4403 env
->regs
[3] = v7m_pop(env
);
4404 env
->regs
[12] = v7m_pop(env
);
4405 env
->regs
[14] = v7m_pop(env
);
4406 env
->regs
[15] = v7m_pop(env
);
4407 if (env
->regs
[15] & 1) {
4408 qemu_log_mask(LOG_GUEST_ERROR
,
4409 "M profile return from interrupt with misaligned "
4410 "PC is UNPREDICTABLE\n");
4411 /* Actual hardware seems to ignore the lsbit, and there are several
4412 * RTOSes out there which incorrectly assume the r15 in the stack
4413 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
4415 env
->regs
[15] &= ~1U;
4417 xpsr
= v7m_pop(env
);
4418 xpsr_write(env
, xpsr
, 0xfffffdff);
4419 /* Undo stack alignment. */
4422 /* ??? The exception return type specifies Thread/Handler mode. However
4423 this is also implied by the xPSR value. Not sure what to do
4424 if there is a mismatch. */
4425 /* ??? Likewise for mismatches between the CONTROL register and the stack
4429 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
4431 ARMCPU
*cpu
= ARM_CPU(cs
);
4432 CPUARMState
*env
= &cpu
->env
;
4433 uint32_t xpsr
= xpsr_read(env
);
4437 arm_log_exception(cs
->exception_index
);
4440 if (env
->v7m
.current_sp
)
4442 if (env
->v7m
.exception
== 0)
4445 /* For exceptions we just mark as pending on the NVIC, and let that
4447 /* TODO: Need to escalate if the current priority is higher than the
4448 one we're raising. */
4449 switch (cs
->exception_index
) {
4451 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
4454 /* The PC already points to the next instruction. */
4455 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
4457 case EXCP_PREFETCH_ABORT
:
4458 case EXCP_DATA_ABORT
:
4459 /* TODO: if we implemented the MPU registers, this is where we
4460 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
4462 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
4465 if (semihosting_enabled
) {
4467 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
4470 env
->regs
[0] = do_arm_semihosting(env
);
4471 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
4475 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
4478 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
4480 case EXCP_EXCEPTION_EXIT
:
4481 do_v7m_exception_exit(env
);
4484 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
4485 return; /* Never happens. Keep compiler happy. */
4488 /* Align stack pointer. */
4489 /* ??? Should only do this if Configuration Control Register
4490 STACKALIGN bit is set. */
4491 if (env
->regs
[13] & 4) {
4495 /* Switch to the handler mode. */
4496 v7m_push(env
, xpsr
);
4497 v7m_push(env
, env
->regs
[15]);
4498 v7m_push(env
, env
->regs
[14]);
4499 v7m_push(env
, env
->regs
[12]);
4500 v7m_push(env
, env
->regs
[3]);
4501 v7m_push(env
, env
->regs
[2]);
4502 v7m_push(env
, env
->regs
[1]);
4503 v7m_push(env
, env
->regs
[0]);
4504 switch_v7m_sp(env
, 0);
4506 env
->condexec_bits
= 0;
4508 addr
= ldl_phys(cs
->as
, env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
4509 env
->regs
[15] = addr
& 0xfffffffe;
4510 env
->thumb
= addr
& 1;
4513 /* Function used to synchronize QEMU's AArch64 register set with AArch32
4514 * register set. This is necessary when switching between AArch32 and AArch64
4517 void aarch64_sync_32_to_64(CPUARMState
*env
)
4520 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
4522 /* We can blanket copy R[0:7] to X[0:7] */
4523 for (i
= 0; i
< 8; i
++) {
4524 env
->xregs
[i
] = env
->regs
[i
];
4527 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
4528 * Otherwise, they come from the banked user regs.
4530 if (mode
== ARM_CPU_MODE_FIQ
) {
4531 for (i
= 8; i
< 13; i
++) {
4532 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
4535 for (i
= 8; i
< 13; i
++) {
4536 env
->xregs
[i
] = env
->regs
[i
];
4540 /* Registers x13-x23 are the various mode SP and FP registers. Registers
4541 * r13 and r14 are only copied if we are in that mode, otherwise we copy
4542 * from the mode banked register.
4544 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
4545 env
->xregs
[13] = env
->regs
[13];
4546 env
->xregs
[14] = env
->regs
[14];
4548 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
4549 /* HYP is an exception in that it is copied from r14 */
4550 if (mode
== ARM_CPU_MODE_HYP
) {
4551 env
->xregs
[14] = env
->regs
[14];
4553 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
4557 if (mode
== ARM_CPU_MODE_HYP
) {
4558 env
->xregs
[15] = env
->regs
[13];
4560 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
4563 if (mode
== ARM_CPU_MODE_IRQ
) {
4564 env
->xregs
[16] = env
->regs
[13];
4565 env
->xregs
[17] = env
->regs
[14];
4567 env
->xregs
[16] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
4568 env
->xregs
[17] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
4571 if (mode
== ARM_CPU_MODE_SVC
) {
4572 env
->xregs
[18] = env
->regs
[13];
4573 env
->xregs
[19] = env
->regs
[14];
4575 env
->xregs
[18] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
4576 env
->xregs
[19] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
4579 if (mode
== ARM_CPU_MODE_ABT
) {
4580 env
->xregs
[20] = env
->regs
[13];
4581 env
->xregs
[21] = env
->regs
[14];
4583 env
->xregs
[20] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
4584 env
->xregs
[21] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
4587 if (mode
== ARM_CPU_MODE_UND
) {
4588 env
->xregs
[22] = env
->regs
[13];
4589 env
->xregs
[23] = env
->regs
[14];
4591 env
->xregs
[22] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
4592 env
->xregs
[23] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
4595 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
4596 * mode, then we can copy from r8-r14. Otherwise, we copy from the
4597 * FIQ bank for r8-r14.
4599 if (mode
== ARM_CPU_MODE_FIQ
) {
4600 for (i
= 24; i
< 31; i
++) {
4601 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
4604 for (i
= 24; i
< 29; i
++) {
4605 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
4607 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
4608 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
4611 env
->pc
= env
->regs
[15];
4614 /* Function used to synchronize QEMU's AArch32 register set with AArch64
4615 * register set. This is necessary when switching between AArch32 and AArch64
4618 void aarch64_sync_64_to_32(CPUARMState
*env
)
4621 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
4623 /* We can blanket copy X[0:7] to R[0:7] */
4624 for (i
= 0; i
< 8; i
++) {
4625 env
->regs
[i
] = env
->xregs
[i
];
4628 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
4629 * Otherwise, we copy x8-x12 into the banked user regs.
4631 if (mode
== ARM_CPU_MODE_FIQ
) {
4632 for (i
= 8; i
< 13; i
++) {
4633 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
4636 for (i
= 8; i
< 13; i
++) {
4637 env
->regs
[i
] = env
->xregs
[i
];
4641 /* Registers r13 & r14 depend on the current mode.
4642 * If we are in a given mode, we copy the corresponding x registers to r13
4643 * and r14. Otherwise, we copy the x register to the banked r13 and r14
4646 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
4647 env
->regs
[13] = env
->xregs
[13];
4648 env
->regs
[14] = env
->xregs
[14];
4650 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
4652 /* HYP is an exception in that it does not have its own banked r14 but
4653 * shares the USR r14
4655 if (mode
== ARM_CPU_MODE_HYP
) {
4656 env
->regs
[14] = env
->xregs
[14];
4658 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
4662 if (mode
== ARM_CPU_MODE_HYP
) {
4663 env
->regs
[13] = env
->xregs
[15];
4665 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
4668 if (mode
== ARM_CPU_MODE_IRQ
) {
4669 env
->regs
[13] = env
->xregs
[16];
4670 env
->regs
[14] = env
->xregs
[17];
4672 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
4673 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
4676 if (mode
== ARM_CPU_MODE_SVC
) {
4677 env
->regs
[13] = env
->xregs
[18];
4678 env
->regs
[14] = env
->xregs
[19];
4680 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
4681 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
4684 if (mode
== ARM_CPU_MODE_ABT
) {
4685 env
->regs
[13] = env
->xregs
[20];
4686 env
->regs
[14] = env
->xregs
[21];
4688 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
4689 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
4692 if (mode
== ARM_CPU_MODE_UND
) {
4693 env
->regs
[13] = env
->xregs
[22];
4694 env
->regs
[14] = env
->xregs
[23];
4696 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
4697 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
4700 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
4701 * mode, then we can copy to r8-r14. Otherwise, we copy to the
4702 * FIQ bank for r8-r14.
4704 if (mode
== ARM_CPU_MODE_FIQ
) {
4705 for (i
= 24; i
< 31; i
++) {
4706 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
4709 for (i
= 24; i
< 29; i
++) {
4710 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
4712 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
4713 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
4716 env
->regs
[15] = env
->pc
;
4719 /* Handle a CPU exception. */
4720 void arm_cpu_do_interrupt(CPUState
*cs
)
4722 ARMCPU
*cpu
= ARM_CPU(cs
);
4723 CPUARMState
*env
= &cpu
->env
;
4732 arm_log_exception(cs
->exception_index
);
4734 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
4735 arm_handle_psci_call(cpu
);
4736 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
4740 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
4741 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
4743 case EC_BREAKPOINT_SAME_EL
:
4747 case EC_WATCHPOINT_SAME_EL
:
4753 case EC_VECTORCATCH
:
4762 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
4765 /* TODO: Vectored interrupt controller. */
4766 switch (cs
->exception_index
) {
4768 new_mode
= ARM_CPU_MODE_UND
;
4777 if (semihosting_enabled
) {
4778 /* Check for semihosting interrupt. */
4780 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
4783 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
4786 /* Only intercept calls from privileged modes, to provide some
4787 semblance of security. */
4788 if (((mask
== 0x123456 && !env
->thumb
)
4789 || (mask
== 0xab && env
->thumb
))
4790 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
4791 env
->regs
[0] = do_arm_semihosting(env
);
4792 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
4796 new_mode
= ARM_CPU_MODE_SVC
;
4799 /* The PC already points to the next instruction. */
4803 /* See if this is a semihosting syscall. */
4804 if (env
->thumb
&& semihosting_enabled
) {
4805 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
4807 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
4809 env
->regs
[0] = do_arm_semihosting(env
);
4810 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
4814 env
->exception
.fsr
= 2;
4815 /* Fall through to prefetch abort. */
4816 case EXCP_PREFETCH_ABORT
:
4817 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
4818 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
4819 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
4820 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
4821 new_mode
= ARM_CPU_MODE_ABT
;
4823 mask
= CPSR_A
| CPSR_I
;
4826 case EXCP_DATA_ABORT
:
4827 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
4828 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
4829 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
4831 (uint32_t)env
->exception
.vaddress
);
4832 new_mode
= ARM_CPU_MODE_ABT
;
4834 mask
= CPSR_A
| CPSR_I
;
4838 new_mode
= ARM_CPU_MODE_IRQ
;
4840 /* Disable IRQ and imprecise data aborts. */
4841 mask
= CPSR_A
| CPSR_I
;
4843 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
4844 /* IRQ routed to monitor mode */
4845 new_mode
= ARM_CPU_MODE_MON
;
4850 new_mode
= ARM_CPU_MODE_FIQ
;
4852 /* Disable FIQ, IRQ and imprecise data aborts. */
4853 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
4854 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
4855 /* FIQ routed to monitor mode */
4856 new_mode
= ARM_CPU_MODE_MON
;
4861 new_mode
= ARM_CPU_MODE_MON
;
4863 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
4867 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
4868 return; /* Never happens. Keep compiler happy. */
4871 if (new_mode
== ARM_CPU_MODE_MON
) {
4872 addr
+= env
->cp15
.mvbar
;
4873 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
4874 /* High vectors. When enabled, base address cannot be remapped. */
4877 /* ARM v7 architectures provide a vector base address register to remap
4878 * the interrupt vector table.
4879 * This register is only followed in non-monitor mode, and is banked.
4880 * Note: only bits 31:5 are valid.
4882 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
4885 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
4886 env
->cp15
.scr_el3
&= ~SCR_NS
;
4889 switch_mode (env
, new_mode
);
4890 /* For exceptions taken to AArch32 we must clear the SS bit in both
4891 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
4893 env
->uncached_cpsr
&= ~PSTATE_SS
;
4894 env
->spsr
= cpsr_read(env
);
4895 /* Clear IT bits. */
4896 env
->condexec_bits
= 0;
4897 /* Switch to the new mode, and to the correct instruction set. */
4898 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
4900 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
4901 * and we should just guard the thumb mode on V4 */
4902 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
4903 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
4905 env
->regs
[14] = env
->regs
[15] + offset
;
4906 env
->regs
[15] = addr
;
4907 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
4911 /* Return the exception level which controls this address translation regime */
4912 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
4915 case ARMMMUIdx_S2NS
:
4916 case ARMMMUIdx_S1E2
:
4918 case ARMMMUIdx_S1E3
:
4920 case ARMMMUIdx_S1SE0
:
4921 return arm_el_is_aa64(env
, 3) ? 1 : 3;
4922 case ARMMMUIdx_S1SE1
:
4923 case ARMMMUIdx_S1NSE0
:
4924 case ARMMMUIdx_S1NSE1
:
4927 g_assert_not_reached();
4931 /* Return true if this address translation regime is secure */
4932 static inline bool regime_is_secure(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
4935 case ARMMMUIdx_S12NSE0
:
4936 case ARMMMUIdx_S12NSE1
:
4937 case ARMMMUIdx_S1NSE0
:
4938 case ARMMMUIdx_S1NSE1
:
4939 case ARMMMUIdx_S1E2
:
4940 case ARMMMUIdx_S2NS
:
4942 case ARMMMUIdx_S1E3
:
4943 case ARMMMUIdx_S1SE0
:
4944 case ARMMMUIdx_S1SE1
:
4947 g_assert_not_reached();
4951 /* Return the SCTLR value which controls this address translation regime */
4952 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
4954 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
4957 /* Return true if the specified stage of address translation is disabled */
4958 static inline bool regime_translation_disabled(CPUARMState
*env
,
4961 if (mmu_idx
== ARMMMUIdx_S2NS
) {
4962 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
4964 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
4967 /* Return the TCR controlling this translation regime */
4968 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
4970 if (mmu_idx
== ARMMMUIdx_S2NS
) {
4971 /* TODO: return VTCR_EL2 */
4972 g_assert_not_reached();
4974 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
4977 /* Return the TTBR associated with this translation regime */
4978 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4981 if (mmu_idx
== ARMMMUIdx_S2NS
) {
4982 /* TODO: return VTTBR_EL2 */
4983 g_assert_not_reached();
4986 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
4988 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
4992 /* Return true if the translation regime is using LPAE format page tables */
4993 static inline bool regime_using_lpae_format(CPUARMState
*env
,
4996 int el
= regime_el(env
, mmu_idx
);
4997 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
5000 if (arm_feature(env
, ARM_FEATURE_LPAE
)
5001 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
5007 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5010 case ARMMMUIdx_S1SE0
:
5011 case ARMMMUIdx_S1NSE0
:
5015 case ARMMMUIdx_S12NSE0
:
5016 case ARMMMUIdx_S12NSE1
:
5017 g_assert_not_reached();
5021 /* Translate section/page access permissions to page
5022 * R/W protection flags
5025 * @mmu_idx: MMU index indicating required translation regime
5026 * @ap: The 3-bit access permissions (AP[2:0])
5027 * @domain_prot: The 2-bit domain access permissions
5029 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
5030 int ap
, int domain_prot
)
5032 bool is_user
= regime_is_user(env
, mmu_idx
);
5034 if (domain_prot
== 3) {
5035 return PAGE_READ
| PAGE_WRITE
;
5040 if (arm_feature(env
, ARM_FEATURE_V7
)) {
5043 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
5045 return is_user
? 0 : PAGE_READ
;
5052 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
5057 return PAGE_READ
| PAGE_WRITE
;
5060 return PAGE_READ
| PAGE_WRITE
;
5061 case 4: /* Reserved. */
5064 return is_user
? 0 : PAGE_READ
;
5068 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
5073 g_assert_not_reached();
5077 /* Translate section/page access permissions to page
5078 * R/W protection flags.
5080 * @ap: The 2-bit simple AP (AP[2:1])
5081 * @is_user: TRUE if accessing from PL0
5083 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
5087 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
5089 return PAGE_READ
| PAGE_WRITE
;
5091 return is_user
? 0 : PAGE_READ
;
5095 g_assert_not_reached();
5100 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
5102 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
5105 /* Translate section/page access permissions to protection flags
5108 * @mmu_idx: MMU index indicating required translation regime
5109 * @is_aa64: TRUE if AArch64
5110 * @ap: The 2-bit simple AP (AP[2:1])
5111 * @ns: NS (non-secure) bit
5112 * @xn: XN (execute-never) bit
5113 * @pxn: PXN (privileged execute-never) bit
5115 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
5116 int ap
, int ns
, int xn
, int pxn
)
5118 bool is_user
= regime_is_user(env
, mmu_idx
);
5119 int prot_rw
, user_rw
;
5123 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
5125 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
5129 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
5132 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
5136 /* TODO have_wxn should be replaced with
5137 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
5138 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
5139 * compatible processors have EL2, which is required for [U]WXN.
5141 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
5144 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
5148 switch (regime_el(env
, mmu_idx
)) {
5151 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
5158 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
5159 switch (regime_el(env
, mmu_idx
)) {
5163 xn
= xn
|| !(user_rw
& PAGE_READ
);
5167 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
5169 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
5170 (uwxn
&& (user_rw
& PAGE_WRITE
));
5180 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
5183 return prot_rw
| PAGE_EXEC
;
5186 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
5187 uint32_t *table
, uint32_t address
)
5189 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
5190 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
5192 if (address
& tcr
->mask
) {
5193 if (tcr
->raw_tcr
& TTBCR_PD1
) {
5194 /* Translation table walk disabled for TTBR1 */
5197 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
5199 if (tcr
->raw_tcr
& TTBCR_PD0
) {
5200 /* Translation table walk disabled for TTBR0 */
5203 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
5205 *table
|= (address
>> 18) & 0x3ffc;
5209 /* All loads done in the course of a page table walk go through here.
5210 * TODO: rather than ignoring errors from physical memory reads (which
5211 * are external aborts in ARM terminology) we should propagate this
5212 * error out so that we can turn it into a Data Abort if this walk
5213 * was being done for a CPU load/store or an address translation instruction
5214 * (but not if it was for a debug access).
5216 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
)
5218 MemTxAttrs attrs
= {};
5220 attrs
.secure
= is_secure
;
5221 return address_space_ldl(cs
->as
, addr
, attrs
, NULL
);
5224 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
)
5226 MemTxAttrs attrs
= {};
5228 attrs
.secure
= is_secure
;
5229 return address_space_ldq(cs
->as
, addr
, attrs
, NULL
);
5232 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
5233 ARMMMUIdx mmu_idx
, hwaddr
*phys_ptr
,
5234 int *prot
, target_ulong
*page_size
)
5236 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5247 /* Pagetable walk. */
5248 /* Lookup l1 descriptor. */
5249 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
5250 /* Section translation fault if page walk is disabled by PD0 or PD1 */
5254 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
5256 domain
= (desc
>> 5) & 0x0f;
5257 if (regime_el(env
, mmu_idx
) == 1) {
5258 dacr
= env
->cp15
.dacr_ns
;
5260 dacr
= env
->cp15
.dacr_s
;
5262 domain_prot
= (dacr
>> (domain
* 2)) & 3;
5264 /* Section translation fault. */
5268 if (domain_prot
== 0 || domain_prot
== 2) {
5270 code
= 9; /* Section domain fault. */
5272 code
= 11; /* Page domain fault. */
5277 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
5278 ap
= (desc
>> 10) & 3;
5280 *page_size
= 1024 * 1024;
5282 /* Lookup l2 entry. */
5284 /* Coarse pagetable. */
5285 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
5287 /* Fine pagetable. */
5288 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
5290 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
5292 case 0: /* Page translation fault. */
5295 case 1: /* 64k page. */
5296 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
5297 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
5298 *page_size
= 0x10000;
5300 case 2: /* 4k page. */
5301 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
5302 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
5303 *page_size
= 0x1000;
5305 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
5307 /* ARMv6/XScale extended small page format */
5308 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
5309 || arm_feature(env
, ARM_FEATURE_V6
)) {
5310 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
5311 *page_size
= 0x1000;
5313 /* UNPREDICTABLE in ARMv5; we choose to take a
5314 * page translation fault.
5320 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
5323 ap
= (desc
>> 4) & 3;
5326 /* Never happens, but compiler isn't smart enough to tell. */
5331 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
5332 *prot
|= *prot
? PAGE_EXEC
: 0;
5333 if (!(*prot
& (1 << access_type
))) {
5334 /* Access permission fault. */
5337 *phys_ptr
= phys_addr
;
5340 return code
| (domain
<< 4);
5343 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
5344 ARMMMUIdx mmu_idx
, hwaddr
*phys_ptr
,
5346 int *prot
, target_ulong
*page_size
)
5348 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5362 /* Pagetable walk. */
5363 /* Lookup l1 descriptor. */
5364 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
5365 /* Section translation fault if page walk is disabled by PD0 or PD1 */
5369 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
5371 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
5372 /* Section translation fault, or attempt to use the encoding
5373 * which is Reserved on implementations without PXN.
5378 if ((type
== 1) || !(desc
& (1 << 18))) {
5379 /* Page or Section. */
5380 domain
= (desc
>> 5) & 0x0f;
5382 if (regime_el(env
, mmu_idx
) == 1) {
5383 dacr
= env
->cp15
.dacr_ns
;
5385 dacr
= env
->cp15
.dacr_s
;
5387 domain_prot
= (dacr
>> (domain
* 2)) & 3;
5388 if (domain_prot
== 0 || domain_prot
== 2) {
5390 code
= 9; /* Section domain fault. */
5392 code
= 11; /* Page domain fault. */
5397 if (desc
& (1 << 18)) {
5399 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
5400 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
5401 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
5402 *page_size
= 0x1000000;
5405 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
5406 *page_size
= 0x100000;
5408 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
5409 xn
= desc
& (1 << 4);
5412 ns
= extract32(desc
, 19, 1);
5414 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
5415 pxn
= (desc
>> 2) & 1;
5417 ns
= extract32(desc
, 3, 1);
5418 /* Lookup l2 entry. */
5419 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
5420 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
5421 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
5423 case 0: /* Page translation fault. */
5426 case 1: /* 64k page. */
5427 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
5428 xn
= desc
& (1 << 15);
5429 *page_size
= 0x10000;
5431 case 2: case 3: /* 4k page. */
5432 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
5434 *page_size
= 0x1000;
5437 /* Never happens, but compiler isn't smart enough to tell. */
5442 if (domain_prot
== 3) {
5443 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
5445 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
5448 if (xn
&& access_type
== 2)
5451 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
5452 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
5453 /* The simplified model uses AP[0] as an access control bit. */
5454 if ((ap
& 1) == 0) {
5455 /* Access flag fault. */
5456 code
= (code
== 15) ? 6 : 3;
5459 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
5461 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
5466 if (!(*prot
& (1 << access_type
))) {
5467 /* Access permission fault. */
5472 /* The NS bit will (as required by the architecture) have no effect if
5473 * the CPU doesn't support TZ or this is a non-secure translation
5474 * regime, because the attribute will already be non-secure.
5476 attrs
->secure
= false;
5478 *phys_ptr
= phys_addr
;
5481 return code
| (domain
<< 4);
5484 /* Fault type for long-descriptor MMU fault reporting; this corresponds
5485 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
5488 translation_fault
= 1,
5490 permission_fault
= 3,
5493 static int get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
5494 int access_type
, ARMMMUIdx mmu_idx
,
5495 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
5496 target_ulong
*page_size_ptr
)
5498 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5499 /* Read an LPAE long-descriptor translation table. */
5500 MMUFaultType fault_type
= translation_fault
;
5507 hwaddr descaddr
, descmask
;
5508 uint32_t tableattrs
;
5509 target_ulong page_size
;
5511 int32_t granule_sz
= 9;
5512 int32_t va_size
= 32;
5514 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
5515 int ap
, ns
, xn
, pxn
;
5516 uint32_t el
= regime_el(env
, mmu_idx
);
5517 bool ttbr1_valid
= true;
5520 * This code does not handle the different format TCR for VTCR_EL2.
5521 * This code also does not support shareability levels.
5522 * Attribute and permission bit handling should also be checked when adding
5523 * support for those page table walks.
5525 if (arm_el_is_aa64(env
, el
)) {
5528 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
5530 if (extract64(address
, 55, 1)) {
5531 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
5533 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
5538 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
5542 ttbr1_valid
= false;
5546 /* Determine whether this address is in the region controlled by
5547 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
5548 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
5549 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
5551 uint32_t t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
5552 if (va_size
== 64) {
5553 t0sz
= MIN(t0sz
, 39);
5554 t0sz
= MAX(t0sz
, 16);
5556 uint32_t t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
5557 if (va_size
== 64) {
5558 t1sz
= MIN(t1sz
, 39);
5559 t1sz
= MAX(t1sz
, 16);
5561 if (t0sz
&& !extract64(address
, va_size
- t0sz
, t0sz
- tbi
)) {
5562 /* there is a ttbr0 region and we are in it (high bits all zero) */
5564 } else if (ttbr1_valid
&& t1sz
&&
5565 !extract64(~address
, va_size
- t1sz
, t1sz
- tbi
)) {
5566 /* there is a ttbr1 region and we are in it (high bits all one) */
5569 /* ttbr0 region is "everything not in the ttbr1 region" */
5571 } else if (!t1sz
&& ttbr1_valid
) {
5572 /* ttbr1 region is "everything not in the ttbr0 region" */
5575 /* in the gap between the two regions, this is a Translation fault */
5576 fault_type
= translation_fault
;
5580 /* Note that QEMU ignores shareability and cacheability attributes,
5581 * so we don't need to do anything with the SH, ORGN, IRGN fields
5582 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
5583 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
5584 * implement any ASID-like capability so we can ignore it (instead
5585 * we will always flush the TLB any time the ASID is changed).
5587 if (ttbr_select
== 0) {
5588 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
5589 epd
= extract32(tcr
->raw_tcr
, 7, 1);
5592 tg
= extract32(tcr
->raw_tcr
, 14, 2);
5593 if (tg
== 1) { /* 64KB pages */
5596 if (tg
== 2) { /* 16KB pages */
5600 /* We should only be here if TTBR1 is valid */
5601 assert(ttbr1_valid
);
5603 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
5604 epd
= extract32(tcr
->raw_tcr
, 23, 1);
5607 tg
= extract32(tcr
->raw_tcr
, 30, 2);
5608 if (tg
== 3) { /* 64KB pages */
5611 if (tg
== 1) { /* 16KB pages */
5616 /* Here we should have set up all the parameters for the translation:
5617 * va_size, ttbr, epd, tsz, granule_sz, tbi
5621 /* Translation table walk disabled => Translation fault on TLB miss
5622 * Note: This is always 0 on 64-bit EL2 and EL3.
5627 /* The starting level depends on the virtual address size (which can be
5628 * up to 48 bits) and the translation granule size. It indicates the number
5629 * of strides (granule_sz bits at a time) needed to consume the bits
5630 * of the input address. In the pseudocode this is:
5631 * level = 4 - RoundUp((inputsize - grainsize) / stride)
5632 * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
5633 * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
5634 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
5635 * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
5636 * = 4 - (va_size - tsz - 4) / granule_sz;
5638 level
= 4 - (va_size
- tsz
- 4) / granule_sz
;
5640 /* Clear the vaddr bits which aren't part of the within-region address,
5641 * so that we don't have to special case things when calculating the
5642 * first descriptor address.
5645 address
&= (1ULL << (va_size
- tsz
)) - 1;
5648 descmask
= (1ULL << (granule_sz
+ 3)) - 1;
5650 /* Now we can extract the actual base address from the TTBR */
5651 descaddr
= extract64(ttbr
, 0, 48);
5652 descaddr
&= ~((1ULL << (va_size
- tsz
- (granule_sz
* (4 - level
)))) - 1);
5654 /* Secure accesses start with the page table in secure memory and
5655 * can be downgraded to non-secure at any step. Non-secure accesses
5656 * remain non-secure. We implement this by just ORing in the NSTable/NS
5657 * bits at each step.
5659 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
5661 uint64_t descriptor
;
5664 descaddr
|= (address
>> (granule_sz
* (4 - level
))) & descmask
;
5666 nstable
= extract32(tableattrs
, 4, 1);
5667 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
);
5668 if (!(descriptor
& 1) ||
5669 (!(descriptor
& 2) && (level
== 3))) {
5670 /* Invalid, or the Reserved level 3 encoding */
5673 descaddr
= descriptor
& 0xfffffff000ULL
;
5675 if ((descriptor
& 2) && (level
< 3)) {
5676 /* Table entry. The top five bits are attributes which may
5677 * propagate down through lower levels of the table (and
5678 * which are all arranged so that 0 means "no effect", so
5679 * we can gather them up by ORing in the bits at each level).
5681 tableattrs
|= extract64(descriptor
, 59, 5);
5685 /* Block entry at level 1 or 2, or page entry at level 3.
5686 * These are basically the same thing, although the number
5687 * of bits we pull in from the vaddr varies.
5689 page_size
= (1ULL << ((granule_sz
* (4 - level
)) + 3));
5690 descaddr
|= (address
& (page_size
- 1));
5691 /* Extract attributes from the descriptor and merge with table attrs */
5692 attrs
= extract64(descriptor
, 2, 10)
5693 | (extract64(descriptor
, 52, 12) << 10);
5694 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
5695 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
5696 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
5697 * means "force PL1 access only", which means forcing AP[1] to 0.
5699 if (extract32(tableattrs
, 2, 1)) {
5702 attrs
|= nstable
<< 3; /* NS */
5705 /* Here descaddr is the final physical address, and attributes
5708 fault_type
= access_fault
;
5709 if ((attrs
& (1 << 8)) == 0) {
5714 ap
= extract32(attrs
, 4, 2);
5715 ns
= extract32(attrs
, 3, 1);
5716 xn
= extract32(attrs
, 12, 1);
5717 pxn
= extract32(attrs
, 11, 1);
5719 *prot
= get_S1prot(env
, mmu_idx
, va_size
== 64, ap
, ns
, xn
, pxn
);
5721 fault_type
= permission_fault
;
5722 if (!(*prot
& (1 << access_type
))) {
5727 /* The NS bit will (as required by the architecture) have no effect if
5728 * the CPU doesn't support TZ or this is a non-secure translation
5729 * regime, because the attribute will already be non-secure.
5731 txattrs
->secure
= false;
5733 *phys_ptr
= descaddr
;
5734 *page_size_ptr
= page_size
;
5738 /* Long-descriptor format IFSR/DFSR value */
5739 return (1 << 9) | (fault_type
<< 2) | level
;
5742 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
,
5743 int access_type
, ARMMMUIdx mmu_idx
,
5744 hwaddr
*phys_ptr
, int *prot
)
5749 bool is_user
= regime_is_user(env
, mmu_idx
);
5751 *phys_ptr
= address
;
5752 for (n
= 7; n
>= 0; n
--) {
5753 base
= env
->cp15
.c6_region
[n
];
5754 if ((base
& 1) == 0) {
5757 mask
= 1 << ((base
>> 1) & 0x1f);
5758 /* Keep this shift separate from the above to avoid an
5759 (undefined) << 32. */
5760 mask
= (mask
<< 1) - 1;
5761 if (((base
^ address
) & ~mask
) == 0) {
5769 if (access_type
== 2) {
5770 mask
= env
->cp15
.pmsav5_insn_ap
;
5772 mask
= env
->cp15
.pmsav5_data_ap
;
5774 mask
= (mask
>> (n
* 4)) & 0xf;
5782 *prot
= PAGE_READ
| PAGE_WRITE
;
5787 *prot
|= PAGE_WRITE
;
5791 *prot
= PAGE_READ
| PAGE_WRITE
;
5803 /* Bad permission. */
5810 /* get_phys_addr - get the physical address for this virtual address
5812 * Find the physical address corresponding to the given virtual address,
5813 * by doing a translation table walk on MMU based systems or using the
5814 * MPU state on MPU based systems.
5816 * Returns 0 if the translation was successful. Otherwise, phys_ptr, attrs,
5817 * prot and page_size may not be filled in, and the return value provides
5818 * information on why the translation aborted, in the format of a
5819 * DFSR/IFSR fault register, with the following caveats:
5820 * * we honour the short vs long DFSR format differences.
5821 * * the WnR bit is never set (the caller must do this).
5822 * * for MPU based systems we don't bother to return a full FSR format
5826 * @address: virtual address to get physical address for
5827 * @access_type: 0 for read, 1 for write, 2 for execute
5828 * @mmu_idx: MMU index indicating required translation regime
5829 * @phys_ptr: set to the physical address corresponding to the virtual address
5830 * @attrs: set to the memory transaction attributes to use
5831 * @prot: set to the permissions for the page containing phys_ptr
5832 * @page_size: set to the size of the page containing phys_ptr
5834 static inline int get_phys_addr(CPUARMState
*env
, target_ulong address
,
5835 int access_type
, ARMMMUIdx mmu_idx
,
5836 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
5837 target_ulong
*page_size
)
5839 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
5840 /* TODO: when we support EL2 we should here call ourselves recursively
5841 * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw
5842 * functions will also need changing to perform ARMMMUIdx_S2NS loads
5843 * rather than direct physical memory loads when appropriate.
5844 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
5846 assert(!arm_feature(env
, ARM_FEATURE_EL2
));
5847 mmu_idx
+= ARMMMUIdx_S1NSE0
;
5850 /* The page table entries may downgrade secure to non-secure, but
5851 * cannot upgrade an non-secure translation regime's attributes
5854 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
5855 attrs
->user
= regime_is_user(env
, mmu_idx
);
5857 /* Fast Context Switch Extension. This doesn't exist at all in v8.
5858 * In v7 and earlier it affects all stage 1 translations.
5860 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
5861 && !arm_feature(env
, ARM_FEATURE_V8
)) {
5862 if (regime_el(env
, mmu_idx
) == 3) {
5863 address
+= env
->cp15
.fcseidr_s
;
5865 address
+= env
->cp15
.fcseidr_ns
;
5869 if (regime_translation_disabled(env
, mmu_idx
)) {
5870 /* MMU/MPU disabled. */
5871 *phys_ptr
= address
;
5872 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
5873 *page_size
= TARGET_PAGE_SIZE
;
5877 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
5878 *page_size
= TARGET_PAGE_SIZE
;
5879 return get_phys_addr_mpu(env
, address
, access_type
, mmu_idx
, phys_ptr
,
5883 if (regime_using_lpae_format(env
, mmu_idx
)) {
5884 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, phys_ptr
,
5885 attrs
, prot
, page_size
);
5886 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
5887 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
, phys_ptr
,
5888 attrs
, prot
, page_size
);
5890 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
, phys_ptr
,
5895 /* Walk the page table and (if the mapping exists) add the page
5896 * to the TLB. Return 0 on success, or an ARM DFSR/IFSR fault
5897 * register format value on failure.
5899 int arm_tlb_fill(CPUState
*cs
, vaddr address
,
5900 int access_type
, int mmu_idx
)
5902 ARMCPU
*cpu
= ARM_CPU(cs
);
5903 CPUARMState
*env
= &cpu
->env
;
5905 target_ulong page_size
;
5908 MemTxAttrs attrs
= {};
5910 ret
= get_phys_addr(env
, address
, access_type
, mmu_idx
, &phys_addr
,
5911 &attrs
, &prot
, &page_size
);
5913 /* Map a single [sub]page. */
5914 phys_addr
&= TARGET_PAGE_MASK
;
5915 address
&= TARGET_PAGE_MASK
;
5916 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
5917 prot
, mmu_idx
, page_size
);
5924 hwaddr
arm_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
5926 ARMCPU
*cpu
= ARM_CPU(cs
);
5927 CPUARMState
*env
= &cpu
->env
;
5929 target_ulong page_size
;
5932 MemTxAttrs attrs
= {};
5934 ret
= get_phys_addr(env
, addr
, 0, cpu_mmu_index(env
), &phys_addr
,
5935 &attrs
, &prot
, &page_size
);
5944 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
5946 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
5947 env
->regs
[13] = val
;
5949 env
->banked_r13
[bank_number(mode
)] = val
;
5953 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
5955 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
5956 return env
->regs
[13];
5958 return env
->banked_r13
[bank_number(mode
)];
5962 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
5964 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5968 return xpsr_read(env
) & 0xf8000000;
5970 return xpsr_read(env
) & 0xf80001ff;
5972 return xpsr_read(env
) & 0xff00fc00;
5974 return xpsr_read(env
) & 0xff00fdff;
5976 return xpsr_read(env
) & 0x000001ff;
5978 return xpsr_read(env
) & 0x0700fc00;
5980 return xpsr_read(env
) & 0x0700edff;
5982 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
5984 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
5985 case 16: /* PRIMASK */
5986 return (env
->daif
& PSTATE_I
) != 0;
5987 case 17: /* BASEPRI */
5988 case 18: /* BASEPRI_MAX */
5989 return env
->v7m
.basepri
;
5990 case 19: /* FAULTMASK */
5991 return (env
->daif
& PSTATE_F
) != 0;
5992 case 20: /* CONTROL */
5993 return env
->v7m
.control
;
5995 /* ??? For debugging only. */
5996 cpu_abort(CPU(cpu
), "Unimplemented system register read (%d)\n", reg
);
6001 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
6003 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6007 xpsr_write(env
, val
, 0xf8000000);
6010 xpsr_write(env
, val
, 0xf8000000);
6013 xpsr_write(env
, val
, 0xfe00fc00);
6016 xpsr_write(env
, val
, 0xfe00fc00);
6019 /* IPSR bits are readonly. */
6022 xpsr_write(env
, val
, 0x0600fc00);
6025 xpsr_write(env
, val
, 0x0600fc00);
6028 if (env
->v7m
.current_sp
)
6029 env
->v7m
.other_sp
= val
;
6031 env
->regs
[13] = val
;
6034 if (env
->v7m
.current_sp
)
6035 env
->regs
[13] = val
;
6037 env
->v7m
.other_sp
= val
;
6039 case 16: /* PRIMASK */
6041 env
->daif
|= PSTATE_I
;
6043 env
->daif
&= ~PSTATE_I
;
6046 case 17: /* BASEPRI */
6047 env
->v7m
.basepri
= val
& 0xff;
6049 case 18: /* BASEPRI_MAX */
6051 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
6052 env
->v7m
.basepri
= val
;
6054 case 19: /* FAULTMASK */
6056 env
->daif
|= PSTATE_F
;
6058 env
->daif
&= ~PSTATE_F
;
6061 case 20: /* CONTROL */
6062 env
->v7m
.control
= val
& 3;
6063 switch_v7m_sp(env
, (val
& 2) != 0);
6066 /* ??? For debugging only. */
6067 cpu_abort(CPU(cpu
), "Unimplemented system register write (%d)\n", reg
);
6074 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
6076 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
6077 * Note that we do not implement the (architecturally mandated)
6078 * alignment fault for attempts to use this on Device memory
6079 * (which matches the usual QEMU behaviour of not implementing either
6080 * alignment faults or any memory attribute handling).
6083 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6084 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
6085 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
6087 #ifndef CONFIG_USER_ONLY
6089 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
6090 * the block size so we might have to do more than one TLB lookup.
6091 * We know that in fact for any v8 CPU the page size is at least 4K
6092 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
6093 * 1K as an artefact of legacy v5 subpage support being present in the
6094 * same QEMU executable.
6096 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
6097 void *hostaddr
[maxidx
];
6099 unsigned mmu_idx
= cpu_mmu_index(env
);
6100 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
6102 for (try = 0; try < 2; try++) {
6104 for (i
= 0; i
< maxidx
; i
++) {
6105 hostaddr
[i
] = tlb_vaddr_to_host(env
,
6106 vaddr
+ TARGET_PAGE_SIZE
* i
,
6113 /* If it's all in the TLB it's fair game for just writing to;
6114 * we know we don't need to update dirty status, etc.
6116 for (i
= 0; i
< maxidx
- 1; i
++) {
6117 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
6119 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
6122 /* OK, try a store and see if we can populate the tlb. This
6123 * might cause an exception if the memory isn't writable,
6124 * in which case we will longjmp out of here. We must for
6125 * this purpose use the actual register value passed to us
6126 * so that we get the fault address right.
6128 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETRA());
6129 /* Now we can populate the other TLB entries, if any */
6130 for (i
= 0; i
< maxidx
; i
++) {
6131 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
6132 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
6133 helper_ret_stb_mmu(env
, va
, 0, oi
, GETRA());
6138 /* Slow path (probably attempt to do this to an I/O device or
6139 * similar, or clearing of a block of code we have translations
6140 * cached for). Just do a series of byte writes as the architecture
6141 * demands. It's not worth trying to use a cpu_physical_memory_map(),
6142 * memset(), unmap() sequence here because:
6143 * + we'd need to account for the blocksize being larger than a page
6144 * + the direct-RAM access case is almost always going to be dealt
6145 * with in the fastpath code above, so there's no speed benefit
6146 * + we would have to deal with the map returning NULL because the
6147 * bounce buffer was in use
6149 for (i
= 0; i
< blocklen
; i
++) {
6150 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETRA());
6154 memset(g2h(vaddr
), 0, blocklen
);
6158 /* Note that signed overflow is undefined in C. The following routines are
6159 careful to use unsigned types where modulo arithmetic is required.
6160 Failure to do so _will_ break on newer gcc. */
6162 /* Signed saturating arithmetic. */
6164 /* Perform 16-bit signed saturating addition. */
6165 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
6170 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
6179 /* Perform 8-bit signed saturating addition. */
6180 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
6185 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
6194 /* Perform 16-bit signed saturating subtraction. */
6195 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
6200 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
6209 /* Perform 8-bit signed saturating subtraction. */
6210 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
6215 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
6224 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
6225 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
6226 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
6227 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
6230 #include "op_addsub.h"
6232 /* Unsigned saturating arithmetic. */
6233 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
6242 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
6250 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
6259 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
6267 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
6268 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
6269 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
6270 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
6273 #include "op_addsub.h"
6275 /* Signed modulo arithmetic. */
6276 #define SARITH16(a, b, n, op) do { \
6278 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6279 RESULT(sum, n, 16); \
6281 ge |= 3 << (n * 2); \
6284 #define SARITH8(a, b, n, op) do { \
6286 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6287 RESULT(sum, n, 8); \
6293 #define ADD16(a, b, n) SARITH16(a, b, n, +)
6294 #define SUB16(a, b, n) SARITH16(a, b, n, -)
6295 #define ADD8(a, b, n) SARITH8(a, b, n, +)
6296 #define SUB8(a, b, n) SARITH8(a, b, n, -)
6300 #include "op_addsub.h"
6302 /* Unsigned modulo arithmetic. */
6303 #define ADD16(a, b, n) do { \
6305 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
6306 RESULT(sum, n, 16); \
6307 if ((sum >> 16) == 1) \
6308 ge |= 3 << (n * 2); \
6311 #define ADD8(a, b, n) do { \
6313 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
6314 RESULT(sum, n, 8); \
6315 if ((sum >> 8) == 1) \
6319 #define SUB16(a, b, n) do { \
6321 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
6322 RESULT(sum, n, 16); \
6323 if ((sum >> 16) == 0) \
6324 ge |= 3 << (n * 2); \
6327 #define SUB8(a, b, n) do { \
6329 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
6330 RESULT(sum, n, 8); \
6331 if ((sum >> 8) == 0) \
6338 #include "op_addsub.h"
6340 /* Halved signed arithmetic. */
6341 #define ADD16(a, b, n) \
6342 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
6343 #define SUB16(a, b, n) \
6344 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
6345 #define ADD8(a, b, n) \
6346 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
6347 #define SUB8(a, b, n) \
6348 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
6351 #include "op_addsub.h"
6353 /* Halved unsigned arithmetic. */
6354 #define ADD16(a, b, n) \
6355 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6356 #define SUB16(a, b, n) \
6357 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6358 #define ADD8(a, b, n) \
6359 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6360 #define SUB8(a, b, n) \
6361 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6364 #include "op_addsub.h"
6366 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
6374 /* Unsigned sum of absolute byte differences. */
6375 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
6378 sum
= do_usad(a
, b
);
6379 sum
+= do_usad(a
>> 8, b
>> 8);
6380 sum
+= do_usad(a
>> 16, b
>>16);
6381 sum
+= do_usad(a
>> 24, b
>> 24);
6385 /* For ARMv6 SEL instruction. */
6386 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
6399 return (a
& mask
) | (b
& ~mask
);
6402 /* VFP support. We follow the convention used for VFP instructions:
6403 Single precision routines have a "s" suffix, double precision a
6406 /* Convert host exception flags to vfp form. */
6407 static inline int vfp_exceptbits_from_host(int host_bits
)
6409 int target_bits
= 0;
6411 if (host_bits
& float_flag_invalid
)
6413 if (host_bits
& float_flag_divbyzero
)
6415 if (host_bits
& float_flag_overflow
)
6417 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
6419 if (host_bits
& float_flag_inexact
)
6420 target_bits
|= 0x10;
6421 if (host_bits
& float_flag_input_denormal
)
6422 target_bits
|= 0x80;
6426 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
6431 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
6432 | (env
->vfp
.vec_len
<< 16)
6433 | (env
->vfp
.vec_stride
<< 20);
6434 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
6435 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
6436 fpscr
|= vfp_exceptbits_from_host(i
);
6440 uint32_t vfp_get_fpscr(CPUARMState
*env
)
6442 return HELPER(vfp_get_fpscr
)(env
);
6445 /* Convert vfp exception flags to target form. */
6446 static inline int vfp_exceptbits_to_host(int target_bits
)
6450 if (target_bits
& 1)
6451 host_bits
|= float_flag_invalid
;
6452 if (target_bits
& 2)
6453 host_bits
|= float_flag_divbyzero
;
6454 if (target_bits
& 4)
6455 host_bits
|= float_flag_overflow
;
6456 if (target_bits
& 8)
6457 host_bits
|= float_flag_underflow
;
6458 if (target_bits
& 0x10)
6459 host_bits
|= float_flag_inexact
;
6460 if (target_bits
& 0x80)
6461 host_bits
|= float_flag_input_denormal
;
6465 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
6470 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
6471 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
6472 env
->vfp
.vec_len
= (val
>> 16) & 7;
6473 env
->vfp
.vec_stride
= (val
>> 20) & 3;
6476 if (changed
& (3 << 22)) {
6477 i
= (val
>> 22) & 3;
6479 case FPROUNDING_TIEEVEN
:
6480 i
= float_round_nearest_even
;
6482 case FPROUNDING_POSINF
:
6485 case FPROUNDING_NEGINF
:
6486 i
= float_round_down
;
6488 case FPROUNDING_ZERO
:
6489 i
= float_round_to_zero
;
6492 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
6494 if (changed
& (1 << 24)) {
6495 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
6496 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
6498 if (changed
& (1 << 25))
6499 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
6501 i
= vfp_exceptbits_to_host(val
);
6502 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
6503 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
6506 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
6508 HELPER(vfp_set_fpscr
)(env
, val
);
6511 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
6513 #define VFP_BINOP(name) \
6514 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
6516 float_status *fpst = fpstp; \
6517 return float32_ ## name(a, b, fpst); \
6519 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
6521 float_status *fpst = fpstp; \
6522 return float64_ ## name(a, b, fpst); \
6534 float32
VFP_HELPER(neg
, s
)(float32 a
)
6536 return float32_chs(a
);
6539 float64
VFP_HELPER(neg
, d
)(float64 a
)
6541 return float64_chs(a
);
6544 float32
VFP_HELPER(abs
, s
)(float32 a
)
6546 return float32_abs(a
);
6549 float64
VFP_HELPER(abs
, d
)(float64 a
)
6551 return float64_abs(a
);
6554 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
6556 return float32_sqrt(a
, &env
->vfp
.fp_status
);
6559 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
6561 return float64_sqrt(a
, &env
->vfp
.fp_status
);
6564 /* XXX: check quiet/signaling case */
6565 #define DO_VFP_cmp(p, type) \
6566 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
6569 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
6570 case 0: flags = 0x6; break; \
6571 case -1: flags = 0x8; break; \
6572 case 1: flags = 0x2; break; \
6573 default: case 2: flags = 0x3; break; \
6575 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6576 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6578 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
6581 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
6582 case 0: flags = 0x6; break; \
6583 case -1: flags = 0x8; break; \
6584 case 1: flags = 0x2; break; \
6585 default: case 2: flags = 0x3; break; \
6587 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6588 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6590 DO_VFP_cmp(s
, float32
)
6591 DO_VFP_cmp(d
, float64
)
6594 /* Integer to float and float to integer conversions */
6596 #define CONV_ITOF(name, fsz, sign) \
6597 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
6599 float_status *fpst = fpstp; \
6600 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
6603 #define CONV_FTOI(name, fsz, sign, round) \
6604 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
6606 float_status *fpst = fpstp; \
6607 if (float##fsz##_is_any_nan(x)) { \
6608 float_raise(float_flag_invalid, fpst); \
6611 return float##fsz##_to_##sign##int32##round(x, fpst); \
6614 #define FLOAT_CONVS(name, p, fsz, sign) \
6615 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
6616 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
6617 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
6619 FLOAT_CONVS(si
, s
, 32, )
6620 FLOAT_CONVS(si
, d
, 64, )
6621 FLOAT_CONVS(ui
, s
, 32, u
)
6622 FLOAT_CONVS(ui
, d
, 64, u
)
6628 /* floating point conversion */
6629 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
6631 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
6632 /* ARM requires that S<->D conversion of any kind of NaN generates
6633 * a quiet NaN by forcing the most significant frac bit to 1.
6635 return float64_maybe_silence_nan(r
);
6638 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
6640 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
6641 /* ARM requires that S<->D conversion of any kind of NaN generates
6642 * a quiet NaN by forcing the most significant frac bit to 1.
6644 return float32_maybe_silence_nan(r
);
6647 /* VFP3 fixed point conversion. */
6648 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6649 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
6652 float_status *fpst = fpstp; \
6654 tmp = itype##_to_##float##fsz(x, fpst); \
6655 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
6658 /* Notice that we want only input-denormal exception flags from the
6659 * scalbn operation: the other possible flags (overflow+inexact if
6660 * we overflow to infinity, output-denormal) aren't correct for the
6661 * complete scale-and-convert operation.
6663 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
6664 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
6668 float_status *fpst = fpstp; \
6669 int old_exc_flags = get_float_exception_flags(fpst); \
6671 if (float##fsz##_is_any_nan(x)) { \
6672 float_raise(float_flag_invalid, fpst); \
6675 tmp = float##fsz##_scalbn(x, shift, fpst); \
6676 old_exc_flags |= get_float_exception_flags(fpst) \
6677 & float_flag_input_denormal; \
6678 set_float_exception_flags(old_exc_flags, fpst); \
6679 return float##fsz##_to_##itype##round(tmp, fpst); \
6682 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
6683 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6684 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
6685 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6687 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
6688 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6689 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6691 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
6692 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
6693 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
6694 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
6695 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
6696 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
6697 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
6698 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
6699 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
6700 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
6701 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
6702 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
6704 #undef VFP_CONV_FIX_FLOAT
6705 #undef VFP_CONV_FLOAT_FIX_ROUND
6707 /* Set the current fp rounding mode and return the old one.
6708 * The argument is a softfloat float_round_ value.
6710 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
6712 float_status
*fp_status
= &env
->vfp
.fp_status
;
6714 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
6715 set_float_rounding_mode(rmode
, fp_status
);
6720 /* Set the current fp rounding mode in the standard fp status and return
6721 * the old one. This is for NEON instructions that need to change the
6722 * rounding mode but wish to use the standard FPSCR values for everything
6723 * else. Always set the rounding mode back to the correct value after
6725 * The argument is a softfloat float_round_ value.
6727 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
6729 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
6731 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
6732 set_float_rounding_mode(rmode
, fp_status
);
6737 /* Half precision conversions. */
6738 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
6740 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
6741 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
6743 return float32_maybe_silence_nan(r
);
6748 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
6750 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
6751 float16 r
= float32_to_float16(a
, ieee
, s
);
6753 r
= float16_maybe_silence_nan(r
);
6755 return float16_val(r
);
6758 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
6760 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
6763 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
6765 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
6768 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
6770 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
6773 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
6775 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
6778 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
6780 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
6781 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
6783 return float64_maybe_silence_nan(r
);
6788 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
6790 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
6791 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
6793 r
= float16_maybe_silence_nan(r
);
6795 return float16_val(r
);
6798 #define float32_two make_float32(0x40000000)
6799 #define float32_three make_float32(0x40400000)
6800 #define float32_one_point_five make_float32(0x3fc00000)
6802 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
6804 float_status
*s
= &env
->vfp
.standard_fp_status
;
6805 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
6806 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
6807 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
6808 float_raise(float_flag_input_denormal
, s
);
6812 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
6815 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
6817 float_status
*s
= &env
->vfp
.standard_fp_status
;
6819 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
6820 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
6821 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
6822 float_raise(float_flag_input_denormal
, s
);
6824 return float32_one_point_five
;
6826 product
= float32_mul(a
, b
, s
);
6827 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
6832 /* Constants 256 and 512 are used in some helpers; we avoid relying on
6833 * int->float conversions at run-time. */
6834 #define float64_256 make_float64(0x4070000000000000LL)
6835 #define float64_512 make_float64(0x4080000000000000LL)
6836 #define float32_maxnorm make_float32(0x7f7fffff)
6837 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
6839 /* Reciprocal functions
6841 * The algorithm that must be used to calculate the estimate
6842 * is specified by the ARM ARM, see FPRecipEstimate()
6845 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
6847 /* These calculations mustn't set any fp exception flags,
6848 * so we use a local copy of the fp_status.
6850 float_status dummy_status
= *real_fp_status
;
6851 float_status
*s
= &dummy_status
;
6852 /* q = (int)(a * 512.0) */
6853 float64 q
= float64_mul(float64_512
, a
, s
);
6854 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
6856 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
6857 q
= int64_to_float64(q_int
, s
);
6858 q
= float64_add(q
, float64_half
, s
);
6859 q
= float64_div(q
, float64_512
, s
);
6860 q
= float64_div(float64_one
, q
, s
);
6862 /* s = (int)(256.0 * r + 0.5) */
6863 q
= float64_mul(q
, float64_256
, s
);
6864 q
= float64_add(q
, float64_half
, s
);
6865 q_int
= float64_to_int64_round_to_zero(q
, s
);
6867 /* return (double)s / 256.0 */
6868 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
6871 /* Common wrapper to call recip_estimate */
6872 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
6874 uint64_t val64
= float64_val(num
);
6875 uint64_t frac
= extract64(val64
, 0, 52);
6876 int64_t exp
= extract64(val64
, 52, 11);
6878 float64 scaled
, estimate
;
6880 /* Generate the scaled number for the estimate function */
6882 if (extract64(frac
, 51, 1) == 0) {
6884 frac
= extract64(frac
, 0, 50) << 2;
6886 frac
= extract64(frac
, 0, 51) << 1;
6890 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
6891 scaled
= make_float64((0x3feULL
<< 52)
6892 | extract64(frac
, 44, 8) << 44);
6894 estimate
= recip_estimate(scaled
, fpst
);
6896 /* Build new result */
6897 val64
= float64_val(estimate
);
6898 sbit
= 0x8000000000000000ULL
& val64
;
6900 frac
= extract64(val64
, 0, 52);
6903 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
6904 } else if (exp
== -1) {
6905 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
6909 return make_float64(sbit
| (exp
<< 52) | frac
);
6912 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
6914 switch (fpst
->float_rounding_mode
) {
6915 case float_round_nearest_even
: /* Round to Nearest */
6917 case float_round_up
: /* Round to +Inf */
6919 case float_round_down
: /* Round to -Inf */
6921 case float_round_to_zero
: /* Round to Zero */
6925 g_assert_not_reached();
6928 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
6930 float_status
*fpst
= fpstp
;
6931 float32 f32
= float32_squash_input_denormal(input
, fpst
);
6932 uint32_t f32_val
= float32_val(f32
);
6933 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
6934 int32_t f32_exp
= extract32(f32_val
, 23, 8);
6935 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
6941 if (float32_is_any_nan(f32
)) {
6943 if (float32_is_signaling_nan(f32
)) {
6944 float_raise(float_flag_invalid
, fpst
);
6945 nan
= float32_maybe_silence_nan(f32
);
6947 if (fpst
->default_nan_mode
) {
6948 nan
= float32_default_nan
;
6951 } else if (float32_is_infinity(f32
)) {
6952 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
6953 } else if (float32_is_zero(f32
)) {
6954 float_raise(float_flag_divbyzero
, fpst
);
6955 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
6956 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
6957 /* Abs(value) < 2.0^-128 */
6958 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
6959 if (round_to_inf(fpst
, f32_sbit
)) {
6960 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
6962 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
6964 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
6965 float_raise(float_flag_underflow
, fpst
);
6966 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
6970 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
6971 r64
= call_recip_estimate(f64
, 253, fpst
);
6972 r64_val
= float64_val(r64
);
6973 r64_exp
= extract64(r64_val
, 52, 11);
6974 r64_frac
= extract64(r64_val
, 0, 52);
6976 /* result = sign : result_exp<7:0> : fraction<51:29>; */
6977 return make_float32(f32_sbit
|
6978 (r64_exp
& 0xff) << 23 |
6979 extract64(r64_frac
, 29, 24));
6982 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
6984 float_status
*fpst
= fpstp
;
6985 float64 f64
= float64_squash_input_denormal(input
, fpst
);
6986 uint64_t f64_val
= float64_val(f64
);
6987 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
6988 int64_t f64_exp
= extract64(f64_val
, 52, 11);
6994 /* Deal with any special cases */
6995 if (float64_is_any_nan(f64
)) {
6997 if (float64_is_signaling_nan(f64
)) {
6998 float_raise(float_flag_invalid
, fpst
);
6999 nan
= float64_maybe_silence_nan(f64
);
7001 if (fpst
->default_nan_mode
) {
7002 nan
= float64_default_nan
;
7005 } else if (float64_is_infinity(f64
)) {
7006 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
7007 } else if (float64_is_zero(f64
)) {
7008 float_raise(float_flag_divbyzero
, fpst
);
7009 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
7010 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
7011 /* Abs(value) < 2.0^-1024 */
7012 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
7013 if (round_to_inf(fpst
, f64_sbit
)) {
7014 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
7016 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
7018 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
7019 float_raise(float_flag_underflow
, fpst
);
7020 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
7023 r64
= call_recip_estimate(f64
, 2045, fpst
);
7024 r64_val
= float64_val(r64
);
7025 r64_exp
= extract64(r64_val
, 52, 11);
7026 r64_frac
= extract64(r64_val
, 0, 52);
7028 /* result = sign : result_exp<10:0> : fraction<51:0> */
7029 return make_float64(f64_sbit
|
7030 ((r64_exp
& 0x7ff) << 52) |
7034 /* The algorithm that must be used to calculate the estimate
7035 * is specified by the ARM ARM.
7037 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
7039 /* These calculations mustn't set any fp exception flags,
7040 * so we use a local copy of the fp_status.
7042 float_status dummy_status
= *real_fp_status
;
7043 float_status
*s
= &dummy_status
;
7047 if (float64_lt(a
, float64_half
, s
)) {
7048 /* range 0.25 <= a < 0.5 */
7050 /* a in units of 1/512 rounded down */
7051 /* q0 = (int)(a * 512.0); */
7052 q
= float64_mul(float64_512
, a
, s
);
7053 q_int
= float64_to_int64_round_to_zero(q
, s
);
7055 /* reciprocal root r */
7056 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
7057 q
= int64_to_float64(q_int
, s
);
7058 q
= float64_add(q
, float64_half
, s
);
7059 q
= float64_div(q
, float64_512
, s
);
7060 q
= float64_sqrt(q
, s
);
7061 q
= float64_div(float64_one
, q
, s
);
7063 /* range 0.5 <= a < 1.0 */
7065 /* a in units of 1/256 rounded down */
7066 /* q1 = (int)(a * 256.0); */
7067 q
= float64_mul(float64_256
, a
, s
);
7068 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
7070 /* reciprocal root r */
7071 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
7072 q
= int64_to_float64(q_int
, s
);
7073 q
= float64_add(q
, float64_half
, s
);
7074 q
= float64_div(q
, float64_256
, s
);
7075 q
= float64_sqrt(q
, s
);
7076 q
= float64_div(float64_one
, q
, s
);
7078 /* r in units of 1/256 rounded to nearest */
7079 /* s = (int)(256.0 * r + 0.5); */
7081 q
= float64_mul(q
, float64_256
,s
);
7082 q
= float64_add(q
, float64_half
, s
);
7083 q_int
= float64_to_int64_round_to_zero(q
, s
);
7085 /* return (double)s / 256.0;*/
7086 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
7089 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
7091 float_status
*s
= fpstp
;
7092 float32 f32
= float32_squash_input_denormal(input
, s
);
7093 uint32_t val
= float32_val(f32
);
7094 uint32_t f32_sbit
= 0x80000000 & val
;
7095 int32_t f32_exp
= extract32(val
, 23, 8);
7096 uint32_t f32_frac
= extract32(val
, 0, 23);
7102 if (float32_is_any_nan(f32
)) {
7104 if (float32_is_signaling_nan(f32
)) {
7105 float_raise(float_flag_invalid
, s
);
7106 nan
= float32_maybe_silence_nan(f32
);
7108 if (s
->default_nan_mode
) {
7109 nan
= float32_default_nan
;
7112 } else if (float32_is_zero(f32
)) {
7113 float_raise(float_flag_divbyzero
, s
);
7114 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
7115 } else if (float32_is_neg(f32
)) {
7116 float_raise(float_flag_invalid
, s
);
7117 return float32_default_nan
;
7118 } else if (float32_is_infinity(f32
)) {
7119 return float32_zero
;
7122 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
7123 * preserving the parity of the exponent. */
7125 f64_frac
= ((uint64_t) f32_frac
) << 29;
7127 while (extract64(f64_frac
, 51, 1) == 0) {
7128 f64_frac
= f64_frac
<< 1;
7129 f32_exp
= f32_exp
-1;
7131 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
7134 if (extract64(f32_exp
, 0, 1) == 0) {
7135 f64
= make_float64(((uint64_t) f32_sbit
) << 32
7139 f64
= make_float64(((uint64_t) f32_sbit
) << 32
7144 result_exp
= (380 - f32_exp
) / 2;
7146 f64
= recip_sqrt_estimate(f64
, s
);
7148 val64
= float64_val(f64
);
7150 val
= ((result_exp
& 0xff) << 23)
7151 | ((val64
>> 29) & 0x7fffff);
7152 return make_float32(val
);
7155 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
7157 float_status
*s
= fpstp
;
7158 float64 f64
= float64_squash_input_denormal(input
, s
);
7159 uint64_t val
= float64_val(f64
);
7160 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
7161 int64_t f64_exp
= extract64(val
, 52, 11);
7162 uint64_t f64_frac
= extract64(val
, 0, 52);
7164 uint64_t result_frac
;
7166 if (float64_is_any_nan(f64
)) {
7168 if (float64_is_signaling_nan(f64
)) {
7169 float_raise(float_flag_invalid
, s
);
7170 nan
= float64_maybe_silence_nan(f64
);
7172 if (s
->default_nan_mode
) {
7173 nan
= float64_default_nan
;
7176 } else if (float64_is_zero(f64
)) {
7177 float_raise(float_flag_divbyzero
, s
);
7178 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
7179 } else if (float64_is_neg(f64
)) {
7180 float_raise(float_flag_invalid
, s
);
7181 return float64_default_nan
;
7182 } else if (float64_is_infinity(f64
)) {
7183 return float64_zero
;
7186 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
7187 * preserving the parity of the exponent. */
7190 while (extract64(f64_frac
, 51, 1) == 0) {
7191 f64_frac
= f64_frac
<< 1;
7192 f64_exp
= f64_exp
- 1;
7194 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
7197 if (extract64(f64_exp
, 0, 1) == 0) {
7198 f64
= make_float64(f64_sbit
7202 f64
= make_float64(f64_sbit
7207 result_exp
= (3068 - f64_exp
) / 2;
7209 f64
= recip_sqrt_estimate(f64
, s
);
7211 result_frac
= extract64(float64_val(f64
), 0, 52);
7213 return make_float64(f64_sbit
|
7214 ((result_exp
& 0x7ff) << 52) |
7218 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
7220 float_status
*s
= fpstp
;
7223 if ((a
& 0x80000000) == 0) {
7227 f64
= make_float64((0x3feULL
<< 52)
7228 | ((int64_t)(a
& 0x7fffffff) << 21));
7230 f64
= recip_estimate(f64
, s
);
7232 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
7235 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
7237 float_status
*fpst
= fpstp
;
7240 if ((a
& 0xc0000000) == 0) {
7244 if (a
& 0x80000000) {
7245 f64
= make_float64((0x3feULL
<< 52)
7246 | ((uint64_t)(a
& 0x7fffffff) << 21));
7247 } else { /* bits 31-30 == '01' */
7248 f64
= make_float64((0x3fdULL
<< 52)
7249 | ((uint64_t)(a
& 0x3fffffff) << 22));
7252 f64
= recip_sqrt_estimate(f64
, fpst
);
7254 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
7257 /* VFPv4 fused multiply-accumulate */
7258 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
7260 float_status
*fpst
= fpstp
;
7261 return float32_muladd(a
, b
, c
, 0, fpst
);
7264 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
7266 float_status
*fpst
= fpstp
;
7267 return float64_muladd(a
, b
, c
, 0, fpst
);
7270 /* ARMv8 round to integral */
7271 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
7273 return float32_round_to_int(x
, fp_status
);
7276 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
7278 return float64_round_to_int(x
, fp_status
);
7281 float32
HELPER(rints
)(float32 x
, void *fp_status
)
7283 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
7286 ret
= float32_round_to_int(x
, fp_status
);
7288 /* Suppress any inexact exceptions the conversion produced */
7289 if (!(old_flags
& float_flag_inexact
)) {
7290 new_flags
= get_float_exception_flags(fp_status
);
7291 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
7297 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
7299 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
7302 ret
= float64_round_to_int(x
, fp_status
);
7304 new_flags
= get_float_exception_flags(fp_status
);
7306 /* Suppress any inexact exceptions the conversion produced */
7307 if (!(old_flags
& float_flag_inexact
)) {
7308 new_flags
= get_float_exception_flags(fp_status
);
7309 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
7315 /* Convert ARM rounding mode to softfloat */
7316 int arm_rmode_to_sf(int rmode
)
7319 case FPROUNDING_TIEAWAY
:
7320 rmode
= float_round_ties_away
;
7322 case FPROUNDING_ODD
:
7323 /* FIXME: add support for TIEAWAY and ODD */
7324 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
7326 case FPROUNDING_TIEEVEN
:
7328 rmode
= float_round_nearest_even
;
7330 case FPROUNDING_POSINF
:
7331 rmode
= float_round_up
;
7333 case FPROUNDING_NEGINF
:
7334 rmode
= float_round_down
;
7336 case FPROUNDING_ZERO
:
7337 rmode
= float_round_to_zero
;
7344 * The upper bytes of val (above the number specified by 'bytes') must have
7345 * been zeroed out by the caller.
7347 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
7353 /* zlib crc32 converts the accumulator and output to one's complement. */
7354 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
7357 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
7363 /* Linux crc32c converts the output to one's complement. */
7364 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;