target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "cpu.h"
  27 #include "gdbstub.h"
  28 #include "host-utils.h"
  29 #include "hw/pc.h"
  30 #include "hw/apic.h"
  31 #include "ioport.h"
  32 #include "hyperv.h"
  33
  34 //#define DEBUG_KVM
  35
  36 #ifdef DEBUG_KVM
  37 #define DPRINTF(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...) \
  41     do { } while (0)
  42 #endif
  43
  44 #define MSR_KVM_WALL_CLOCK  0x11
  45 #define MSR_KVM_SYSTEM_TIME 0x12
  46
  47 #ifndef BUS_MCEERR_AR
  48 #define BUS_MCEERR_AR 4
  49 #endif
  50 #ifndef BUS_MCEERR_AO
  51 #define BUS_MCEERR_AO 5
  52 #endif
  53
  54 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  55     KVM_CAP_INFO(SET_TSS_ADDR),
  56     KVM_CAP_INFO(EXT_CPUID),
  57     KVM_CAP_INFO(MP_STATE),
  58     KVM_CAP_LAST_INFO
  59 };
  60
  61 static bool has_msr_star;
  62 static bool has_msr_hsave_pa;
  63 static bool has_msr_tsc_deadline;
  64 static bool has_msr_async_pf_en;
  65 static bool has_msr_misc_enable;
  66 static int lm_capable_kernel;
  67
  68 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  69 {
  70     struct kvm_cpuid2 *cpuid;
  71     int r, size;
  72
  73     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  74     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  75     cpuid->nent = max;
  76     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  77     if (r == 0 && cpuid->nent >= max) {
  78         r = -E2BIG;
  79     }
  80     if (r < 0) {
  81         if (r == -E2BIG) {
  82             g_free(cpuid);
  83             return NULL;
  84         } else {
  85             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  86                     strerror(-r));
  87             exit(1);
  88         }
  89     }
  90     return cpuid;
  91 }
  92
  93 struct kvm_para_features {
  94     int cap;
  95     int feature;
  96 } para_features[] = {
  97     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
  98     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
  99     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 100     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 101     { -1, -1 }
 102 };
 103
 104 static int get_para_features(KVMState *s)
 105 {
 106     int i, features = 0;
 107
 108     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 109         if (kvm_check_extension(s, para_features[i].cap)) {
 110             features |= (1 << para_features[i].feature);
 111         }
 112     }
 113
 114     return features;
 115 }
 116
 117
 118 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 119                                       uint32_t index, int reg)
 120 {
 121     struct kvm_cpuid2 *cpuid;
 122     int i, max;
 123     uint32_t ret = 0;
 124     uint32_t cpuid_1_edx;
 125     int has_kvm_features = 0;
 126
 127     max = 1;
 128     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 129         max *= 2;
 130     }
 131
 132     for (i = 0; i < cpuid->nent; ++i) {
 133         if (cpuid->entries[i].function == function &&
 134             cpuid->entries[i].index == index) {
 135             if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
 136                 has_kvm_features = 1;
 137             }
 138             switch (reg) {
 139             case R_EAX:
 140                 ret = cpuid->entries[i].eax;
 141                 break;
 142             case R_EBX:
 143                 ret = cpuid->entries[i].ebx;
 144                 break;
 145             case R_ECX:
 146                 ret = cpuid->entries[i].ecx;
 147                 break;
 148             case R_EDX:
 149                 ret = cpuid->entries[i].edx;
 150                 switch (function) {
 151                 case 1:
 152                     /* KVM before 2.6.30 misreports the following features */
 153                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 154                     break;
 155                 case 0x80000001:
 156                     /* On Intel, kvm returns cpuid according to the Intel spec,
 157                      * so add missing bits according to the AMD spec:
 158                      */
 159                     cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 160                     ret |= cpuid_1_edx & 0x183f7ff;
 161                     break;
 162                 }
 163                 break;
 164             }
 165         }
 166     }
 167
 168     g_free(cpuid);
 169
 170     /* fallback for older kernels */
 171     if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
 172         ret = get_para_features(s);
 173     }
 174
 175     return ret;
 176 }
 177
 178 typedef struct HWPoisonPage {
 179     ram_addr_t ram_addr;
 180     QLIST_ENTRY(HWPoisonPage) list;
 181 } HWPoisonPage;
 182
 183 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 184     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 185
 186 static void kvm_unpoison_all(void *param)
 187 {
 188     HWPoisonPage *page, *next_page;
 189
 190     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 191         QLIST_REMOVE(page, list);
 192         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 193         g_free(page);
 194     }
 195 }
 196
 197 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 198 {
 199     HWPoisonPage *page;
 200
 201     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 202         if (page->ram_addr == ram_addr) {
 203             return;
 204         }
 205     }
 206     page = g_malloc(sizeof(HWPoisonPage));
 207     page->ram_addr = ram_addr;
 208     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 209 }
 210
 211 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 212                                      int *max_banks)
 213 {
 214     int r;
 215
 216     r = kvm_check_extension(s, KVM_CAP_MCE);
 217     if (r > 0) {
 218         *max_banks = r;
 219         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 220     }
 221     return -ENOSYS;
 222 }
 223
 224 static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
 225 {
 226     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 227                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 228     uint64_t mcg_status = MCG_STATUS_MCIP;
 229
 230     if (code == BUS_MCEERR_AR) {
 231         status |= MCI_STATUS_AR | 0x134;
 232         mcg_status |= MCG_STATUS_EIPV;
 233     } else {
 234         status |= 0xc0;
 235         mcg_status |= MCG_STATUS_RIPV;
 236     }
 237     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 238                        (MCM_ADDR_PHYS << 6) | 0xc,
 239                        cpu_x86_support_mca_broadcast(env) ?
 240                        MCE_INJECT_BROADCAST : 0);
 241 }
 242
 243 static void hardware_memory_error(void)
 244 {
 245     fprintf(stderr, "Hardware memory error!\n");
 246     exit(1);
 247 }
 248
 249 int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
 250 {
 251     ram_addr_t ram_addr;
 252     target_phys_addr_t paddr;
 253
 254     if ((env->mcg_cap & MCG_SER_P) && addr
 255         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 256         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 257             !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
 258             fprintf(stderr, "Hardware memory error for memory used by "
 259                     "QEMU itself instead of guest system!\n");
 260             /* Hope we are lucky for AO MCE */
 261             if (code == BUS_MCEERR_AO) {
 262                 return 0;
 263             } else {
 264                 hardware_memory_error();
 265             }
 266         }
 267         kvm_hwpoison_page_add(ram_addr);
 268         kvm_mce_inject(env, paddr, code);
 269     } else {
 270         if (code == BUS_MCEERR_AO) {
 271             return 0;
 272         } else if (code == BUS_MCEERR_AR) {
 273             hardware_memory_error();
 274         } else {
 275             return 1;
 276         }
 277     }
 278     return 0;
 279 }
 280
 281 int kvm_arch_on_sigbus(int code, void *addr)
 282 {
 283     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 284         ram_addr_t ram_addr;
 285         target_phys_addr_t paddr;
 286
 287         /* Hope we are lucky for AO MCE */
 288         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 289             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
 290                                                 &paddr)) {
 291             fprintf(stderr, "Hardware memory error for memory used by "
 292                     "QEMU itself instead of guest system!: %p\n", addr);
 293             return 0;
 294         }
 295         kvm_hwpoison_page_add(ram_addr);
 296         kvm_mce_inject(first_cpu, paddr, code);
 297     } else {
 298         if (code == BUS_MCEERR_AO) {
 299             return 0;
 300         } else if (code == BUS_MCEERR_AR) {
 301             hardware_memory_error();
 302         } else {
 303             return 1;
 304         }
 305     }
 306     return 0;
 307 }
 308
 309 static int kvm_inject_mce_oldstyle(CPUState *env)
 310 {
 311     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 312         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 313         struct kvm_x86_mce mce;
 314
 315         env->exception_injected = -1;
 316
 317         /*
 318          * There must be at least one bank in use if an MCE is pending.
 319          * Find it and use its values for the event injection.
 320          */
 321         for (bank = 0; bank < bank_num; bank++) {
 322             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 323                 break;
 324             }
 325         }
 326         assert(bank < bank_num);
 327
 328         mce.bank = bank;
 329         mce.status = env->mce_banks[bank * 4 + 1];
 330         mce.mcg_status = env->mcg_status;
 331         mce.addr = env->mce_banks[bank * 4 + 2];
 332         mce.misc = env->mce_banks[bank * 4 + 3];
 333
 334         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 335     }
 336     return 0;
 337 }
 338
 339 static void cpu_update_state(void *opaque, int running, RunState state)
 340 {
 341     CPUState *env = opaque;
 342
 343     if (running) {
 344         env->tsc_valid = false;
 345     }
 346 }
 347
 348 int kvm_arch_init_vcpu(CPUState *env)
 349 {
 350     struct {
 351         struct kvm_cpuid2 cpuid;
 352         struct kvm_cpuid_entry2 entries[100];
 353     } QEMU_PACKED cpuid_data;
 354     KVMState *s = env->kvm_state;
 355     uint32_t limit, i, j, cpuid_i;
 356     uint32_t unused;
 357     struct kvm_cpuid_entry2 *c;
 358     uint32_t signature[3];
 359     int r;
 360
 361     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 362
 363     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 364     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 365     env->cpuid_ext_features |= i;
 366
 367     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 368                                                              0, R_EDX);
 369     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 370                                                              0, R_ECX);
 371     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 372                                                              0, R_EDX);
 373
 374     cpuid_i = 0;
 375
 376     /* Paravirtualization CPUIDs */
 377     c = &cpuid_data.entries[cpuid_i++];
 378     memset(c, 0, sizeof(*c));
 379     c->function = KVM_CPUID_SIGNATURE;
 380     if (!hyperv_enabled()) {
 381         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 382         c->eax = 0;
 383     } else {
 384         memcpy(signature, "Microsoft Hv", 12);
 385         c->eax = HYPERV_CPUID_MIN;
 386     }
 387     c->ebx = signature[0];
 388     c->ecx = signature[1];
 389     c->edx = signature[2];
 390
 391     c = &cpuid_data.entries[cpuid_i++];
 392     memset(c, 0, sizeof(*c));
 393     c->function = KVM_CPUID_FEATURES;
 394     c->eax = env->cpuid_kvm_features &
 395         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 396
 397     if (hyperv_enabled()) {
 398         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 399         c->eax = signature[0];
 400
 401         c = &cpuid_data.entries[cpuid_i++];
 402         memset(c, 0, sizeof(*c));
 403         c->function = HYPERV_CPUID_VERSION;
 404         c->eax = 0x00001bbc;
 405         c->ebx = 0x00060001;
 406
 407         c = &cpuid_data.entries[cpuid_i++];
 408         memset(c, 0, sizeof(*c));
 409         c->function = HYPERV_CPUID_FEATURES;
 410         if (hyperv_relaxed_timing_enabled()) {
 411             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 412         }
 413         if (hyperv_vapic_recommended()) {
 414             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 415             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 416         }
 417
 418         c = &cpuid_data.entries[cpuid_i++];
 419         memset(c, 0, sizeof(*c));
 420         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 421         if (hyperv_relaxed_timing_enabled()) {
 422             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 423         }
 424         if (hyperv_vapic_recommended()) {
 425             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 426         }
 427         c->ebx = hyperv_get_spinlock_retries();
 428
 429         c = &cpuid_data.entries[cpuid_i++];
 430         memset(c, 0, sizeof(*c));
 431         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 432         c->eax = 0x40;
 433         c->ebx = 0x40;
 434
 435         c = &cpuid_data.entries[cpuid_i++];
 436         memset(c, 0, sizeof(*c));
 437         c->function = KVM_CPUID_SIGNATURE_NEXT;
 438         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 439         c->eax = 0;
 440         c->ebx = signature[0];
 441         c->ecx = signature[1];
 442         c->edx = signature[2];
 443     }
 444
 445     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 446
 447     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 448
 449     for (i = 0; i <= limit; i++) {
 450         c = &cpuid_data.entries[cpuid_i++];
 451
 452         switch (i) {
 453         case 2: {
 454             /* Keep reading function 2 till all the input is received */
 455             int times;
 456
 457             c->function = i;
 458             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 459                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 460             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 461             times = c->eax & 0xff;
 462
 463             for (j = 1; j < times; ++j) {
 464                 c = &cpuid_data.entries[cpuid_i++];
 465                 c->function = i;
 466                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 467                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 468             }
 469             break;
 470         }
 471         case 4:
 472         case 0xb:
 473         case 0xd:
 474             for (j = 0; ; j++) {
 475                 if (i == 0xd && j == 64) {
 476                     break;
 477                 }
 478                 c->function = i;
 479                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 480                 c->index = j;
 481                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 482
 483                 if (i == 4 && c->eax == 0) {
 484                     break;
 485                 }
 486                 if (i == 0xb && !(c->ecx & 0xff00)) {
 487                     break;
 488                 }
 489                 if (i == 0xd && c->eax == 0) {
 490                     continue;
 491                 }
 492                 c = &cpuid_data.entries[cpuid_i++];
 493             }
 494             break;
 495         default:
 496             c->function = i;
 497             c->flags = 0;
 498             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 499             break;
 500         }
 501     }
 502     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 503
 504     for (i = 0x80000000; i <= limit; i++) {
 505         c = &cpuid_data.entries[cpuid_i++];
 506
 507         c->function = i;
 508         c->flags = 0;
 509         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 510     }
 511
 512     /* Call Centaur's CPUID instructions they are supported. */
 513     if (env->cpuid_xlevel2 > 0) {
 514         env->cpuid_ext4_features &=
 515             kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 516         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 517
 518         for (i = 0xC0000000; i <= limit; i++) {
 519             c = &cpuid_data.entries[cpuid_i++];
 520
 521             c->function = i;
 522             c->flags = 0;
 523             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 524         }
 525     }
 526
 527     cpuid_data.cpuid.nent = cpuid_i;
 528
 529     if (((env->cpuid_version >> 8)&0xF) >= 6
 530         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 531         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 532         uint64_t mcg_cap;
 533         int banks;
 534         int ret;
 535
 536         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 537         if (ret < 0) {
 538             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 539             return ret;
 540         }
 541
 542         if (banks > MCE_BANKS_DEF) {
 543             banks = MCE_BANKS_DEF;
 544         }
 545         mcg_cap &= MCE_CAP_DEF;
 546         mcg_cap |= banks;
 547         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 548         if (ret < 0) {
 549             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 550             return ret;
 551         }
 552
 553         env->mcg_cap = mcg_cap;
 554     }
 555
 556     qemu_add_vm_change_state_handler(cpu_update_state, env);
 557
 558     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 559     if (r) {
 560         return r;
 561     }
 562
 563     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 564     if (r && env->tsc_khz) {
 565         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 566         if (r < 0) {
 567             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 568             return r;
 569         }
 570     }
 571
 572     if (kvm_has_xsave()) {
 573         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 574     }
 575
 576     return 0;
 577 }
 578
 579 void kvm_arch_reset_vcpu(CPUState *env)
 580 {
 581     env->exception_injected = -1;
 582     env->interrupt_injected = -1;
 583     env->xcr0 = 1;
 584     if (kvm_irqchip_in_kernel()) {
 585         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 586                                           KVM_MP_STATE_UNINITIALIZED;
 587     } else {
 588         env->mp_state = KVM_MP_STATE_RUNNABLE;
 589     }
 590 }
 591
 592 static int kvm_get_supported_msrs(KVMState *s)
 593 {
 594     static int kvm_supported_msrs;
 595     int ret = 0;
 596
 597     /* first time */
 598     if (kvm_supported_msrs == 0) {
 599         struct kvm_msr_list msr_list, *kvm_msr_list;
 600
 601         kvm_supported_msrs = -1;
 602
 603         /* Obtain MSR list from KVM.  These are the MSRs that we must
 604          * save/restore */
 605         msr_list.nmsrs = 0;
 606         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 607         if (ret < 0 && ret != -E2BIG) {
 608             return ret;
 609         }
 610         /* Old kernel modules had a bug and could write beyond the provided
 611            memory. Allocate at least a safe amount of 1K. */
 612         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 613                                               msr_list.nmsrs *
 614                                               sizeof(msr_list.indices[0])));
 615
 616         kvm_msr_list->nmsrs = msr_list.nmsrs;
 617         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 618         if (ret >= 0) {
 619             int i;
 620
 621             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 622                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 623                     has_msr_star = true;
 624                     continue;
 625                 }
 626                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 627                     has_msr_hsave_pa = true;
 628                     continue;
 629                 }
 630                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 631                     has_msr_tsc_deadline = true;
 632                     continue;
 633                 }
 634                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 635                     has_msr_misc_enable = true;
 636                     continue;
 637                 }
 638             }
 639         }
 640
 641         g_free(kvm_msr_list);
 642     }
 643
 644     return ret;
 645 }
 646
 647 int kvm_arch_init(KVMState *s)
 648 {
 649     uint64_t identity_base = 0xfffbc000;
 650     int ret;
 651     struct utsname utsname;
 652
 653     ret = kvm_get_supported_msrs(s);
 654     if (ret < 0) {
 655         return ret;
 656     }
 657
 658     uname(&utsname);
 659     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 660
 661     /*
 662      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 663      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 664      * Since these must be part of guest physical memory, we need to allocate
 665      * them, both by setting their start addresses in the kernel and by
 666      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 667      *
 668      * Older KVM versions may not support setting the identity map base. In
 669      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 670      * size.
 671      */
 672     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 673         /* Allows up to 16M BIOSes. */
 674         identity_base = 0xfeffc000;
 675
 676         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 677         if (ret < 0) {
 678             return ret;
 679         }
 680     }
 681
 682     /* Set TSS base one page after EPT identity map. */
 683     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 684     if (ret < 0) {
 685         return ret;
 686     }
 687
 688     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 689     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 690     if (ret < 0) {
 691         fprintf(stderr, "e820_add_entry() table is full\n");
 692         return ret;
 693     }
 694     qemu_register_reset(kvm_unpoison_all, NULL);
 695
 696     return 0;
 697 }
 698
 699 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 700 {
 701     lhs->selector = rhs->selector;
 702     lhs->base = rhs->base;
 703     lhs->limit = rhs->limit;
 704     lhs->type = 3;
 705     lhs->present = 1;
 706     lhs->dpl = 3;
 707     lhs->db = 0;
 708     lhs->s = 1;
 709     lhs->l = 0;
 710     lhs->g = 0;
 711     lhs->avl = 0;
 712     lhs->unusable = 0;
 713 }
 714
 715 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 716 {
 717     unsigned flags = rhs->flags;
 718     lhs->selector = rhs->selector;
 719     lhs->base = rhs->base;
 720     lhs->limit = rhs->limit;
 721     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 722     lhs->present = (flags & DESC_P_MASK) != 0;
 723     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 724     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 725     lhs->s = (flags & DESC_S_MASK) != 0;
 726     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 727     lhs->g = (flags & DESC_G_MASK) != 0;
 728     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 729     lhs->unusable = 0;
 730 }
 731
 732 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 733 {
 734     lhs->selector = rhs->selector;
 735     lhs->base = rhs->base;
 736     lhs->limit = rhs->limit;
 737     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 738                  (rhs->present * DESC_P_MASK) |
 739                  (rhs->dpl << DESC_DPL_SHIFT) |
 740                  (rhs->db << DESC_B_SHIFT) |
 741                  (rhs->s * DESC_S_MASK) |
 742                  (rhs->l << DESC_L_SHIFT) |
 743                  (rhs->g * DESC_G_MASK) |
 744                  (rhs->avl * DESC_AVL_MASK);
 745 }
 746
 747 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 748 {
 749     if (set) {
 750         *kvm_reg = *qemu_reg;
 751     } else {
 752         *qemu_reg = *kvm_reg;
 753     }
 754 }
 755
 756 static int kvm_getput_regs(CPUState *env, int set)
 757 {
 758     struct kvm_regs regs;
 759     int ret = 0;
 760
 761     if (!set) {
 762         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 763         if (ret < 0) {
 764             return ret;
 765         }
 766     }
 767
 768     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 769     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 770     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 771     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 772     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 773     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 774     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 775     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 776 #ifdef TARGET_X86_64
 777     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 778     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 779     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 780     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 781     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 782     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 783     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 784     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 785 #endif
 786
 787     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 788     kvm_getput_reg(&regs.rip, &env->eip, set);
 789
 790     if (set) {
 791         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 792     }
 793
 794     return ret;
 795 }
 796
 797 static int kvm_put_fpu(CPUState *env)
 798 {
 799     struct kvm_fpu fpu;
 800     int i;
 801
 802     memset(&fpu, 0, sizeof fpu);
 803     fpu.fsw = env->fpus & ~(7 << 11);
 804     fpu.fsw |= (env->fpstt & 7) << 11;
 805     fpu.fcw = env->fpuc;
 806     fpu.last_opcode = env->fpop;
 807     fpu.last_ip = env->fpip;
 808     fpu.last_dp = env->fpdp;
 809     for (i = 0; i < 8; ++i) {
 810         fpu.ftwx |= (!env->fptags[i]) << i;
 811     }
 812     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 813     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 814     fpu.mxcsr = env->mxcsr;
 815
 816     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 817 }
 818
 819 #define XSAVE_FCW_FSW     0
 820 #define XSAVE_FTW_FOP     1
 821 #define XSAVE_CWD_RIP     2
 822 #define XSAVE_CWD_RDP     4
 823 #define XSAVE_MXCSR       6
 824 #define XSAVE_ST_SPACE    8
 825 #define XSAVE_XMM_SPACE   40
 826 #define XSAVE_XSTATE_BV   128
 827 #define XSAVE_YMMH_SPACE  144
 828
 829 static int kvm_put_xsave(CPUState *env)
 830 {
 831     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 832     uint16_t cwd, swd, twd;
 833     int i, r;
 834
 835     if (!kvm_has_xsave()) {
 836         return kvm_put_fpu(env);
 837     }
 838
 839     memset(xsave, 0, sizeof(struct kvm_xsave));
 840     twd = 0;
 841     swd = env->fpus & ~(7 << 11);
 842     swd |= (env->fpstt & 7) << 11;
 843     cwd = env->fpuc;
 844     for (i = 0; i < 8; ++i) {
 845         twd |= (!env->fptags[i]) << i;
 846     }
 847     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 848     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 849     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 850     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 851     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 852             sizeof env->fpregs);
 853     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 854             sizeof env->xmm_regs);
 855     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 856     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 857     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 858             sizeof env->ymmh_regs);
 859     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 860     return r;
 861 }
 862
 863 static int kvm_put_xcrs(CPUState *env)
 864 {
 865     struct kvm_xcrs xcrs;
 866
 867     if (!kvm_has_xcrs()) {
 868         return 0;
 869     }
 870
 871     xcrs.nr_xcrs = 1;
 872     xcrs.flags = 0;
 873     xcrs.xcrs[0].xcr = 0;
 874     xcrs.xcrs[0].value = env->xcr0;
 875     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 876 }
 877
 878 static int kvm_put_sregs(CPUState *env)
 879 {
 880     struct kvm_sregs sregs;
 881
 882     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 883     if (env->interrupt_injected >= 0) {
 884         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 885                 (uint64_t)1 << (env->interrupt_injected % 64);
 886     }
 887
 888     if ((env->eflags & VM_MASK)) {
 889         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 890         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 891         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 892         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 893         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 894         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 895     } else {
 896         set_seg(&sregs.cs, &env->segs[R_CS]);
 897         set_seg(&sregs.ds, &env->segs[R_DS]);
 898         set_seg(&sregs.es, &env->segs[R_ES]);
 899         set_seg(&sregs.fs, &env->segs[R_FS]);
 900         set_seg(&sregs.gs, &env->segs[R_GS]);
 901         set_seg(&sregs.ss, &env->segs[R_SS]);
 902     }
 903
 904     set_seg(&sregs.tr, &env->tr);
 905     set_seg(&sregs.ldt, &env->ldt);
 906
 907     sregs.idt.limit = env->idt.limit;
 908     sregs.idt.base = env->idt.base;
 909     sregs.gdt.limit = env->gdt.limit;
 910     sregs.gdt.base = env->gdt.base;
 911
 912     sregs.cr0 = env->cr[0];
 913     sregs.cr2 = env->cr[2];
 914     sregs.cr3 = env->cr[3];
 915     sregs.cr4 = env->cr[4];
 916
 917     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 918     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 919
 920     sregs.efer = env->efer;
 921
 922     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 923 }
 924
 925 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 926                               uint32_t index, uint64_t value)
 927 {
 928     entry->index = index;
 929     entry->data = value;
 930 }
 931
 932 static int kvm_put_msrs(CPUState *env, int level)
 933 {
 934     struct {
 935         struct kvm_msrs info;
 936         struct kvm_msr_entry entries[100];
 937     } msr_data;
 938     struct kvm_msr_entry *msrs = msr_data.entries;
 939     int n = 0;
 940
 941     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 942     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 943     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 944     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 945     if (has_msr_star) {
 946         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 947     }
 948     if (has_msr_hsave_pa) {
 949         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 950     }
 951     if (has_msr_tsc_deadline) {
 952         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
 953     }
 954     if (has_msr_misc_enable) {
 955         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
 956                           env->msr_ia32_misc_enable);
 957     }
 958 #ifdef TARGET_X86_64
 959     if (lm_capable_kernel) {
 960         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 961         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 962         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 963         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 964     }
 965 #endif
 966     if (level == KVM_PUT_FULL_STATE) {
 967         /*
 968          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 969          * writeback. Until this is fixed, we only write the offset to SMP
 970          * guests after migration, desynchronizing the VCPUs, but avoiding
 971          * huge jump-backs that would occur without any writeback at all.
 972          */
 973         if (smp_cpus == 1 || env->tsc != 0) {
 974             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 975         }
 976     }
 977     /*
 978      * The following paravirtual MSRs have side effects on the guest or are
 979      * too heavy for normal writeback. Limit them to reset or full state
 980      * updates.
 981      */
 982     if (level >= KVM_PUT_RESET_STATE) {
 983         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 984                           env->system_time_msr);
 985         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 986         if (has_msr_async_pf_en) {
 987             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
 988                               env->async_pf_en_msr);
 989         }
 990         if (hyperv_hypercall_available()) {
 991             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
 992             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
 993         }
 994         if (hyperv_vapic_recommended()) {
 995             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
 996         }
 997     }
 998     if (env->mcg_cap) {
 999         int i;
1000
1001         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1002         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1003         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1004             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1005         }
1006     }
1007
1008     msr_data.info.nmsrs = n;
1009
1010     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1011
1012 }
1013
1014
1015 static int kvm_get_fpu(CPUState *env)
1016 {
1017     struct kvm_fpu fpu;
1018     int i, ret;
1019
1020     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1021     if (ret < 0) {
1022         return ret;
1023     }
1024
1025     env->fpstt = (fpu.fsw >> 11) & 7;
1026     env->fpus = fpu.fsw;
1027     env->fpuc = fpu.fcw;
1028     env->fpop = fpu.last_opcode;
1029     env->fpip = fpu.last_ip;
1030     env->fpdp = fpu.last_dp;
1031     for (i = 0; i < 8; ++i) {
1032         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1033     }
1034     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1035     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1036     env->mxcsr = fpu.mxcsr;
1037
1038     return 0;
1039 }
1040
1041 static int kvm_get_xsave(CPUState *env)
1042 {
1043     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1044     int ret, i;
1045     uint16_t cwd, swd, twd;
1046
1047     if (!kvm_has_xsave()) {
1048         return kvm_get_fpu(env);
1049     }
1050
1051     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1052     if (ret < 0) {
1053         return ret;
1054     }
1055
1056     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1057     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1058     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1059     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1060     env->fpstt = (swd >> 11) & 7;
1061     env->fpus = swd;
1062     env->fpuc = cwd;
1063     for (i = 0; i < 8; ++i) {
1064         env->fptags[i] = !((twd >> i) & 1);
1065     }
1066     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1067     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1068     env->mxcsr = xsave->region[XSAVE_MXCSR];
1069     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1070             sizeof env->fpregs);
1071     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1072             sizeof env->xmm_regs);
1073     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1074     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1075             sizeof env->ymmh_regs);
1076     return 0;
1077 }
1078
1079 static int kvm_get_xcrs(CPUState *env)
1080 {
1081     int i, ret;
1082     struct kvm_xcrs xcrs;
1083
1084     if (!kvm_has_xcrs()) {
1085         return 0;
1086     }
1087
1088     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1089     if (ret < 0) {
1090         return ret;
1091     }
1092
1093     for (i = 0; i < xcrs.nr_xcrs; i++) {
1094         /* Only support xcr0 now */
1095         if (xcrs.xcrs[0].xcr == 0) {
1096             env->xcr0 = xcrs.xcrs[0].value;
1097             break;
1098         }
1099     }
1100     return 0;
1101 }
1102
1103 static int kvm_get_sregs(CPUState *env)
1104 {
1105     struct kvm_sregs sregs;
1106     uint32_t hflags;
1107     int bit, i, ret;
1108
1109     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1110     if (ret < 0) {
1111         return ret;
1112     }
1113
1114     /* There can only be one pending IRQ set in the bitmap at a time, so try
1115        to find it and save its number instead (-1 for none). */
1116     env->interrupt_injected = -1;
1117     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1118         if (sregs.interrupt_bitmap[i]) {
1119             bit = ctz64(sregs.interrupt_bitmap[i]);
1120             env->interrupt_injected = i * 64 + bit;
1121             break;
1122         }
1123     }
1124
1125     get_seg(&env->segs[R_CS], &sregs.cs);
1126     get_seg(&env->segs[R_DS], &sregs.ds);
1127     get_seg(&env->segs[R_ES], &sregs.es);
1128     get_seg(&env->segs[R_FS], &sregs.fs);
1129     get_seg(&env->segs[R_GS], &sregs.gs);
1130     get_seg(&env->segs[R_SS], &sregs.ss);
1131
1132     get_seg(&env->tr, &sregs.tr);
1133     get_seg(&env->ldt, &sregs.ldt);
1134
1135     env->idt.limit = sregs.idt.limit;
1136     env->idt.base = sregs.idt.base;
1137     env->gdt.limit = sregs.gdt.limit;
1138     env->gdt.base = sregs.gdt.base;
1139
1140     env->cr[0] = sregs.cr0;
1141     env->cr[2] = sregs.cr2;
1142     env->cr[3] = sregs.cr3;
1143     env->cr[4] = sregs.cr4;
1144
1145     env->efer = sregs.efer;
1146
1147     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1148
1149 #define HFLAG_COPY_MASK \
1150     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1151        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1152        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1153        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1154
1155     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1156     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1157     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1158                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1159     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1160     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1161                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1162
1163     if (env->efer & MSR_EFER_LMA) {
1164         hflags |= HF_LMA_MASK;
1165     }
1166
1167     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1168         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1169     } else {
1170         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1171                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1172         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1173                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1174         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1175             !(hflags & HF_CS32_MASK)) {
1176             hflags |= HF_ADDSEG_MASK;
1177         } else {
1178             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1179                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1180         }
1181     }
1182     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1183
1184     return 0;
1185 }
1186
1187 static int kvm_get_msrs(CPUState *env)
1188 {
1189     struct {
1190         struct kvm_msrs info;
1191         struct kvm_msr_entry entries[100];
1192     } msr_data;
1193     struct kvm_msr_entry *msrs = msr_data.entries;
1194     int ret, i, n;
1195
1196     n = 0;
1197     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1198     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1199     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1200     msrs[n++].index = MSR_PAT;
1201     if (has_msr_star) {
1202         msrs[n++].index = MSR_STAR;
1203     }
1204     if (has_msr_hsave_pa) {
1205         msrs[n++].index = MSR_VM_HSAVE_PA;
1206     }
1207     if (has_msr_tsc_deadline) {
1208         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1209     }
1210     if (has_msr_misc_enable) {
1211         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1212     }
1213
1214     if (!env->tsc_valid) {
1215         msrs[n++].index = MSR_IA32_TSC;
1216         env->tsc_valid = !runstate_is_running();
1217     }
1218
1219 #ifdef TARGET_X86_64
1220     if (lm_capable_kernel) {
1221         msrs[n++].index = MSR_CSTAR;
1222         msrs[n++].index = MSR_KERNELGSBASE;
1223         msrs[n++].index = MSR_FMASK;
1224         msrs[n++].index = MSR_LSTAR;
1225     }
1226 #endif
1227     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1228     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1229     if (has_msr_async_pf_en) {
1230         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1231     }
1232
1233     if (env->mcg_cap) {
1234         msrs[n++].index = MSR_MCG_STATUS;
1235         msrs[n++].index = MSR_MCG_CTL;
1236         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1237             msrs[n++].index = MSR_MC0_CTL + i;
1238         }
1239     }
1240
1241     msr_data.info.nmsrs = n;
1242     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1243     if (ret < 0) {
1244         return ret;
1245     }
1246
1247     for (i = 0; i < ret; i++) {
1248         switch (msrs[i].index) {
1249         case MSR_IA32_SYSENTER_CS:
1250             env->sysenter_cs = msrs[i].data;
1251             break;
1252         case MSR_IA32_SYSENTER_ESP:
1253             env->sysenter_esp = msrs[i].data;
1254             break;
1255         case MSR_IA32_SYSENTER_EIP:
1256             env->sysenter_eip = msrs[i].data;
1257             break;
1258         case MSR_PAT:
1259             env->pat = msrs[i].data;
1260             break;
1261         case MSR_STAR:
1262             env->star = msrs[i].data;
1263             break;
1264 #ifdef TARGET_X86_64
1265         case MSR_CSTAR:
1266             env->cstar = msrs[i].data;
1267             break;
1268         case MSR_KERNELGSBASE:
1269             env->kernelgsbase = msrs[i].data;
1270             break;
1271         case MSR_FMASK:
1272             env->fmask = msrs[i].data;
1273             break;
1274         case MSR_LSTAR:
1275             env->lstar = msrs[i].data;
1276             break;
1277 #endif
1278         case MSR_IA32_TSC:
1279             env->tsc = msrs[i].data;
1280             break;
1281         case MSR_IA32_TSCDEADLINE:
1282             env->tsc_deadline = msrs[i].data;
1283             break;
1284         case MSR_VM_HSAVE_PA:
1285             env->vm_hsave = msrs[i].data;
1286             break;
1287         case MSR_KVM_SYSTEM_TIME:
1288             env->system_time_msr = msrs[i].data;
1289             break;
1290         case MSR_KVM_WALL_CLOCK:
1291             env->wall_clock_msr = msrs[i].data;
1292             break;
1293         case MSR_MCG_STATUS:
1294             env->mcg_status = msrs[i].data;
1295             break;
1296         case MSR_MCG_CTL:
1297             env->mcg_ctl = msrs[i].data;
1298             break;
1299         case MSR_IA32_MISC_ENABLE:
1300             env->msr_ia32_misc_enable = msrs[i].data;
1301             break;
1302         default:
1303             if (msrs[i].index >= MSR_MC0_CTL &&
1304                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1305                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1306             }
1307             break;
1308         case MSR_KVM_ASYNC_PF_EN:
1309             env->async_pf_en_msr = msrs[i].data;
1310             break;
1311         }
1312     }
1313
1314     return 0;
1315 }
1316
1317 static int kvm_put_mp_state(CPUState *env)
1318 {
1319     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1320
1321     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1322 }
1323
1324 static int kvm_get_mp_state(CPUState *env)
1325 {
1326     struct kvm_mp_state mp_state;
1327     int ret;
1328
1329     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1330     if (ret < 0) {
1331         return ret;
1332     }
1333     env->mp_state = mp_state.mp_state;
1334     if (kvm_irqchip_in_kernel()) {
1335         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1336     }
1337     return 0;
1338 }
1339
1340 static int kvm_put_vcpu_events(CPUState *env, int level)
1341 {
1342     struct kvm_vcpu_events events;
1343
1344     if (!kvm_has_vcpu_events()) {
1345         return 0;
1346     }
1347
1348     events.exception.injected = (env->exception_injected >= 0);
1349     events.exception.nr = env->exception_injected;
1350     events.exception.has_error_code = env->has_error_code;
1351     events.exception.error_code = env->error_code;
1352
1353     events.interrupt.injected = (env->interrupt_injected >= 0);
1354     events.interrupt.nr = env->interrupt_injected;
1355     events.interrupt.soft = env->soft_interrupt;
1356
1357     events.nmi.injected = env->nmi_injected;
1358     events.nmi.pending = env->nmi_pending;
1359     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1360
1361     events.sipi_vector = env->sipi_vector;
1362
1363     events.flags = 0;
1364     if (level >= KVM_PUT_RESET_STATE) {
1365         events.flags |=
1366             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1367     }
1368
1369     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1370 }
1371
1372 static int kvm_get_vcpu_events(CPUState *env)
1373 {
1374     struct kvm_vcpu_events events;
1375     int ret;
1376
1377     if (!kvm_has_vcpu_events()) {
1378         return 0;
1379     }
1380
1381     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1382     if (ret < 0) {
1383        return ret;
1384     }
1385     env->exception_injected =
1386        events.exception.injected ? events.exception.nr : -1;
1387     env->has_error_code = events.exception.has_error_code;
1388     env->error_code = events.exception.error_code;
1389
1390     env->interrupt_injected =
1391         events.interrupt.injected ? events.interrupt.nr : -1;
1392     env->soft_interrupt = events.interrupt.soft;
1393
1394     env->nmi_injected = events.nmi.injected;
1395     env->nmi_pending = events.nmi.pending;
1396     if (events.nmi.masked) {
1397         env->hflags2 |= HF2_NMI_MASK;
1398     } else {
1399         env->hflags2 &= ~HF2_NMI_MASK;
1400     }
1401
1402     env->sipi_vector = events.sipi_vector;
1403
1404     return 0;
1405 }
1406
1407 static int kvm_guest_debug_workarounds(CPUState *env)
1408 {
1409     int ret = 0;
1410     unsigned long reinject_trap = 0;
1411
1412     if (!kvm_has_vcpu_events()) {
1413         if (env->exception_injected == 1) {
1414             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1415         } else if (env->exception_injected == 3) {
1416             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1417         }
1418         env->exception_injected = -1;
1419     }
1420
1421     /*
1422      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1423      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1424      * by updating the debug state once again if single-stepping is on.
1425      * Another reason to call kvm_update_guest_debug here is a pending debug
1426      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1427      * reinject them via SET_GUEST_DEBUG.
1428      */
1429     if (reinject_trap ||
1430         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1431         ret = kvm_update_guest_debug(env, reinject_trap);
1432     }
1433     return ret;
1434 }
1435
1436 static int kvm_put_debugregs(CPUState *env)
1437 {
1438     struct kvm_debugregs dbgregs;
1439     int i;
1440
1441     if (!kvm_has_debugregs()) {
1442         return 0;
1443     }
1444
1445     for (i = 0; i < 4; i++) {
1446         dbgregs.db[i] = env->dr[i];
1447     }
1448     dbgregs.dr6 = env->dr[6];
1449     dbgregs.dr7 = env->dr[7];
1450     dbgregs.flags = 0;
1451
1452     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1453 }
1454
1455 static int kvm_get_debugregs(CPUState *env)
1456 {
1457     struct kvm_debugregs dbgregs;
1458     int i, ret;
1459
1460     if (!kvm_has_debugregs()) {
1461         return 0;
1462     }
1463
1464     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1465     if (ret < 0) {
1466         return ret;
1467     }
1468     for (i = 0; i < 4; i++) {
1469         env->dr[i] = dbgregs.db[i];
1470     }
1471     env->dr[4] = env->dr[6] = dbgregs.dr6;
1472     env->dr[5] = env->dr[7] = dbgregs.dr7;
1473
1474     return 0;
1475 }
1476
1477 int kvm_arch_put_registers(CPUState *env, int level)
1478 {
1479     int ret;
1480
1481     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1482
1483     ret = kvm_getput_regs(env, 1);
1484     if (ret < 0) {
1485         return ret;
1486     }
1487     ret = kvm_put_xsave(env);
1488     if (ret < 0) {
1489         return ret;
1490     }
1491     ret = kvm_put_xcrs(env);
1492     if (ret < 0) {
1493         return ret;
1494     }
1495     ret = kvm_put_sregs(env);
1496     if (ret < 0) {
1497         return ret;
1498     }
1499     /* must be before kvm_put_msrs */
1500     ret = kvm_inject_mce_oldstyle(env);
1501     if (ret < 0) {
1502         return ret;
1503     }
1504     ret = kvm_put_msrs(env, level);
1505     if (ret < 0) {
1506         return ret;
1507     }
1508     if (level >= KVM_PUT_RESET_STATE) {
1509         ret = kvm_put_mp_state(env);
1510         if (ret < 0) {
1511             return ret;
1512         }
1513     }
1514     ret = kvm_put_vcpu_events(env, level);
1515     if (ret < 0) {
1516         return ret;
1517     }
1518     ret = kvm_put_debugregs(env);
1519     if (ret < 0) {
1520         return ret;
1521     }
1522     /* must be last */
1523     ret = kvm_guest_debug_workarounds(env);
1524     if (ret < 0) {
1525         return ret;
1526     }
1527     return 0;
1528 }
1529
1530 int kvm_arch_get_registers(CPUState *env)
1531 {
1532     int ret;
1533
1534     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1535
1536     ret = kvm_getput_regs(env, 0);
1537     if (ret < 0) {
1538         return ret;
1539     }
1540     ret = kvm_get_xsave(env);
1541     if (ret < 0) {
1542         return ret;
1543     }
1544     ret = kvm_get_xcrs(env);
1545     if (ret < 0) {
1546         return ret;
1547     }
1548     ret = kvm_get_sregs(env);
1549     if (ret < 0) {
1550         return ret;
1551     }
1552     ret = kvm_get_msrs(env);
1553     if (ret < 0) {
1554         return ret;
1555     }
1556     ret = kvm_get_mp_state(env);
1557     if (ret < 0) {
1558         return ret;
1559     }
1560     ret = kvm_get_vcpu_events(env);
1561     if (ret < 0) {
1562         return ret;
1563     }
1564     ret = kvm_get_debugregs(env);
1565     if (ret < 0) {
1566         return ret;
1567     }
1568     return 0;
1569 }
1570
1571 void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1572 {
1573     int ret;
1574
1575     /* Inject NMI */
1576     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1577         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1578         DPRINTF("injected NMI\n");
1579         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1580         if (ret < 0) {
1581             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1582                     strerror(-ret));
1583         }
1584     }
1585
1586     if (!kvm_irqchip_in_kernel()) {
1587         /* Force the VCPU out of its inner loop to process the INIT request */
1588         if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1589             env->exit_request = 1;
1590         }
1591
1592         /* Try to inject an interrupt if the guest can accept it */
1593         if (run->ready_for_interrupt_injection &&
1594             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1595             (env->eflags & IF_MASK)) {
1596             int irq;
1597
1598             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1599             irq = cpu_get_pic_interrupt(env);
1600             if (irq >= 0) {
1601                 struct kvm_interrupt intr;
1602
1603                 intr.irq = irq;
1604                 DPRINTF("injected interrupt %d\n", irq);
1605                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1606                 if (ret < 0) {
1607                     fprintf(stderr,
1608                             "KVM: injection failed, interrupt lost (%s)\n",
1609                             strerror(-ret));
1610                 }
1611             }
1612         }
1613
1614         /* If we have an interrupt but the guest is not ready to receive an
1615          * interrupt, request an interrupt window exit.  This will
1616          * cause a return to userspace as soon as the guest is ready to
1617          * receive interrupts. */
1618         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1619             run->request_interrupt_window = 1;
1620         } else {
1621             run->request_interrupt_window = 0;
1622         }
1623
1624         DPRINTF("setting tpr\n");
1625         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1626     }
1627 }
1628
1629 void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1630 {
1631     if (run->if_flag) {
1632         env->eflags |= IF_MASK;
1633     } else {
1634         env->eflags &= ~IF_MASK;
1635     }
1636     cpu_set_apic_tpr(env->apic_state, run->cr8);
1637     cpu_set_apic_base(env->apic_state, run->apic_base);
1638 }
1639
1640 int kvm_arch_process_async_events(CPUState *env)
1641 {
1642     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1643         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1644         assert(env->mcg_cap);
1645
1646         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1647
1648         kvm_cpu_synchronize_state(env);
1649
1650         if (env->exception_injected == EXCP08_DBLE) {
1651             /* this means triple fault */
1652             qemu_system_reset_request();
1653             env->exit_request = 1;
1654             return 0;
1655         }
1656         env->exception_injected = EXCP12_MCHK;
1657         env->has_error_code = 0;
1658
1659         env->halted = 0;
1660         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1661             env->mp_state = KVM_MP_STATE_RUNNABLE;
1662         }
1663     }
1664
1665     if (kvm_irqchip_in_kernel()) {
1666         return 0;
1667     }
1668
1669     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1670          (env->eflags & IF_MASK)) ||
1671         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1672         env->halted = 0;
1673     }
1674     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1675         kvm_cpu_synchronize_state(env);
1676         do_cpu_init(env);
1677     }
1678     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1679         kvm_cpu_synchronize_state(env);
1680         do_cpu_sipi(env);
1681     }
1682
1683     return env->halted;
1684 }
1685
1686 static int kvm_handle_halt(CPUState *env)
1687 {
1688     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1689           (env->eflags & IF_MASK)) &&
1690         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1691         env->halted = 1;
1692         return EXCP_HLT;
1693     }
1694
1695     return 0;
1696 }
1697
1698 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1699 {
1700     static const uint8_t int3 = 0xcc;
1701
1702     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1703         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1704         return -EINVAL;
1705     }
1706     return 0;
1707 }
1708
1709 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1710 {
1711     uint8_t int3;
1712
1713     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1714         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1715         return -EINVAL;
1716     }
1717     return 0;
1718 }
1719
1720 static struct {
1721     target_ulong addr;
1722     int len;
1723     int type;
1724 } hw_breakpoint[4];
1725
1726 static int nb_hw_breakpoint;
1727
1728 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1729 {
1730     int n;
1731
1732     for (n = 0; n < nb_hw_breakpoint; n++) {
1733         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1734             (hw_breakpoint[n].len == len || len == -1)) {
1735             return n;
1736         }
1737     }
1738     return -1;
1739 }
1740
1741 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1742                                   target_ulong len, int type)
1743 {
1744     switch (type) {
1745     case GDB_BREAKPOINT_HW:
1746         len = 1;
1747         break;
1748     case GDB_WATCHPOINT_WRITE:
1749     case GDB_WATCHPOINT_ACCESS:
1750         switch (len) {
1751         case 1:
1752             break;
1753         case 2:
1754         case 4:
1755         case 8:
1756             if (addr & (len - 1)) {
1757                 return -EINVAL;
1758             }
1759             break;
1760         default:
1761             return -EINVAL;
1762         }
1763         break;
1764     default:
1765         return -ENOSYS;
1766     }
1767
1768     if (nb_hw_breakpoint == 4) {
1769         return -ENOBUFS;
1770     }
1771     if (find_hw_breakpoint(addr, len, type) >= 0) {
1772         return -EEXIST;
1773     }
1774     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1775     hw_breakpoint[nb_hw_breakpoint].len = len;
1776     hw_breakpoint[nb_hw_breakpoint].type = type;
1777     nb_hw_breakpoint++;
1778
1779     return 0;
1780 }
1781
1782 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1783                                   target_ulong len, int type)
1784 {
1785     int n;
1786
1787     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1788     if (n < 0) {
1789         return -ENOENT;
1790     }
1791     nb_hw_breakpoint--;
1792     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1793
1794     return 0;
1795 }
1796
1797 void kvm_arch_remove_all_hw_breakpoints(void)
1798 {
1799     nb_hw_breakpoint = 0;
1800 }
1801
1802 static CPUWatchpoint hw_watchpoint;
1803
1804 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1805 {
1806     int ret = 0;
1807     int n;
1808
1809     if (arch_info->exception == 1) {
1810         if (arch_info->dr6 & (1 << 14)) {
1811             if (cpu_single_env->singlestep_enabled) {
1812                 ret = EXCP_DEBUG;
1813             }
1814         } else {
1815             for (n = 0; n < 4; n++) {
1816                 if (arch_info->dr6 & (1 << n)) {
1817                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1818                     case 0x0:
1819                         ret = EXCP_DEBUG;
1820                         break;
1821                     case 0x1:
1822                         ret = EXCP_DEBUG;
1823                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1824                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1825                         hw_watchpoint.flags = BP_MEM_WRITE;
1826                         break;
1827                     case 0x3:
1828                         ret = EXCP_DEBUG;
1829                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1830                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1831                         hw_watchpoint.flags = BP_MEM_ACCESS;
1832                         break;
1833                     }
1834                 }
1835             }
1836         }
1837     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1838         ret = EXCP_DEBUG;
1839     }
1840     if (ret == 0) {
1841         cpu_synchronize_state(cpu_single_env);
1842         assert(cpu_single_env->exception_injected == -1);
1843
1844         /* pass to guest */
1845         cpu_single_env->exception_injected = arch_info->exception;
1846         cpu_single_env->has_error_code = 0;
1847     }
1848
1849     return ret;
1850 }
1851
1852 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1853 {
1854     const uint8_t type_code[] = {
1855         [GDB_BREAKPOINT_HW] = 0x0,
1856         [GDB_WATCHPOINT_WRITE] = 0x1,
1857         [GDB_WATCHPOINT_ACCESS] = 0x3
1858     };
1859     const uint8_t len_code[] = {
1860         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1861     };
1862     int n;
1863
1864     if (kvm_sw_breakpoints_active(env)) {
1865         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1866     }
1867     if (nb_hw_breakpoint > 0) {
1868         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1869         dbg->arch.debugreg[7] = 0x0600;
1870         for (n = 0; n < nb_hw_breakpoint; n++) {
1871             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1872             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1873                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1874                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1875         }
1876     }
1877 }
1878
1879 static bool host_supports_vmx(void)
1880 {
1881     uint32_t ecx, unused;
1882
1883     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1884     return ecx & CPUID_EXT_VMX;
1885 }
1886
1887 #define VMX_INVALID_GUEST_STATE 0x80000021
1888
1889 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1890 {
1891     uint64_t code;
1892     int ret;
1893
1894     switch (run->exit_reason) {
1895     case KVM_EXIT_HLT:
1896         DPRINTF("handle_hlt\n");
1897         ret = kvm_handle_halt(env);
1898         break;
1899     case KVM_EXIT_SET_TPR:
1900         ret = 0;
1901         break;
1902     case KVM_EXIT_FAIL_ENTRY:
1903         code = run->fail_entry.hardware_entry_failure_reason;
1904         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1905                 code);
1906         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1907             fprintf(stderr,
1908                     "\nIf you're running a guest on an Intel machine without "
1909                         "unrestricted mode\n"
1910                     "support, the failure can be most likely due to the guest "
1911                         "entering an invalid\n"
1912                     "state for Intel VT. For example, the guest maybe running "
1913                         "in big real mode\n"
1914                     "which is not supported on less recent Intel processors."
1915                         "\n\n");
1916         }
1917         ret = -1;
1918         break;
1919     case KVM_EXIT_EXCEPTION:
1920         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1921                 run->ex.exception, run->ex.error_code);
1922         ret = -1;
1923         break;
1924     case KVM_EXIT_DEBUG:
1925         DPRINTF("kvm_exit_debug\n");
1926         ret = kvm_handle_debug(&run->debug.arch);
1927         break;
1928     default:
1929         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1930         ret = -1;
1931         break;
1932     }
1933
1934     return ret;
1935 }
1936
1937 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1938 {
1939     return !(env->cr[0] & CR0_PE_MASK) ||
1940            ((env->segs[R_CS].selector  & 3) != 3);
1941 }