target-lm32/translate.c

   1 /*
   2  *  LatticeMico32 main translation routines.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "disas/disas.h"
  23 #include "exec/helper-proto.h"
  24 #include "tcg-op.h"
  25
  26 #include "exec/cpu_ldst.h"
  27 #include "hw/lm32/lm32_pic.h"
  28
  29 #include "exec/helper-gen.h"
  30
  31 #include "trace-tcg.h"
  32 #include "exec/log.h"
  33
  34
  35 #define DISAS_LM32 1
  36 #if DISAS_LM32
  37 #  define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
  38 #else
  39 #  define LOG_DIS(...) do { } while (0)
  40 #endif
  41
  42 #define EXTRACT_FIELD(src, start, end) \
  43             (((src) >> start) & ((1 << (end - start + 1)) - 1))
  44
  45 #define MEM_INDEX 0
  46
  47 static TCGv_ptr cpu_env;
  48 static TCGv cpu_R[32];
  49 static TCGv cpu_pc;
  50 static TCGv cpu_ie;
  51 static TCGv cpu_icc;
  52 static TCGv cpu_dcc;
  53 static TCGv cpu_cc;
  54 static TCGv cpu_cfg;
  55 static TCGv cpu_eba;
  56 static TCGv cpu_dc;
  57 static TCGv cpu_deba;
  58 static TCGv cpu_bp[4];
  59 static TCGv cpu_wp[4];
  60
  61 #include "exec/gen-icount.h"
  62
  63 enum {
  64     OP_FMT_RI,
  65     OP_FMT_RR,
  66     OP_FMT_CR,
  67     OP_FMT_I
  68 };
  69
  70 /* This is the state at translation time.  */
  71 typedef struct DisasContext {
  72     target_ulong pc;
  73
  74     /* Decoder.  */
  75     int format;
  76     uint32_t ir;
  77     uint8_t opcode;
  78     uint8_t r0, r1, r2, csr;
  79     uint16_t imm5;
  80     uint16_t imm16;
  81     uint32_t imm26;
  82
  83     unsigned int delayed_branch;
  84     unsigned int tb_flags, synced_flags; /* tb dependent flags.  */
  85     int is_jmp;
  86
  87     struct TranslationBlock *tb;
  88     int singlestep_enabled;
  89
  90     uint32_t features;
  91     uint8_t num_breakpoints;
  92     uint8_t num_watchpoints;
  93 } DisasContext;
  94
  95 static const char *regnames[] = {
  96     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  97     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  98     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  99     "r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra",
 100     "r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0",
 101     "wp1", "wp2", "wp3"
 102 };
 103
 104 static inline int zero_extend(unsigned int val, int width)
 105 {
 106     return val & ((1 << width) - 1);
 107 }
 108
 109 static inline int sign_extend(unsigned int val, int width)
 110 {
 111     int sval;
 112
 113     /* LSL.  */
 114     val <<= 32 - width;
 115     sval = val;
 116     /* ASR.  */
 117     sval >>= 32 - width;
 118
 119     return sval;
 120 }
 121
 122 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
 123 {
 124     TCGv_i32 tmp = tcg_const_i32(index);
 125
 126     gen_helper_raise_exception(cpu_env, tmp);
 127     tcg_temp_free_i32(tmp);
 128 }
 129
 130 static inline void t_gen_illegal_insn(DisasContext *dc)
 131 {
 132     tcg_gen_movi_tl(cpu_pc, dc->pc);
 133     gen_helper_ill(cpu_env);
 134 }
 135
 136 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
 137 {
 138     TranslationBlock *tb;
 139
 140     tb = dc->tb;
 141     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
 142             likely(!dc->singlestep_enabled)) {
 143         tcg_gen_goto_tb(n);
 144         tcg_gen_movi_tl(cpu_pc, dest);
 145         tcg_gen_exit_tb((uintptr_t)tb + n);
 146     } else {
 147         tcg_gen_movi_tl(cpu_pc, dest);
 148         if (dc->singlestep_enabled) {
 149             t_gen_raise_exception(dc, EXCP_DEBUG);
 150         }
 151         tcg_gen_exit_tb(0);
 152     }
 153 }
 154
 155 static void dec_add(DisasContext *dc)
 156 {
 157     if (dc->format == OP_FMT_RI) {
 158         if (dc->r0 == R_R0) {
 159             if (dc->r1 == R_R0 && dc->imm16 == 0) {
 160                 LOG_DIS("nop\n");
 161             } else {
 162                 LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16));
 163             }
 164         } else {
 165             LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
 166                     sign_extend(dc->imm16, 16));
 167         }
 168     } else {
 169         LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 170     }
 171
 172     if (dc->format == OP_FMT_RI) {
 173         tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 174                 sign_extend(dc->imm16, 16));
 175     } else {
 176         tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 177     }
 178 }
 179
 180 static void dec_and(DisasContext *dc)
 181 {
 182     if (dc->format == OP_FMT_RI) {
 183         LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
 184                 zero_extend(dc->imm16, 16));
 185     } else {
 186         LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 187     }
 188
 189     if (dc->format == OP_FMT_RI) {
 190         tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 191                 zero_extend(dc->imm16, 16));
 192     } else  {
 193         if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
 194             tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 195             gen_helper_hlt(cpu_env);
 196         } else {
 197             tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 198         }
 199     }
 200 }
 201
 202 static void dec_andhi(DisasContext *dc)
 203 {
 204     LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
 205
 206     tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
 207 }
 208
 209 static void dec_b(DisasContext *dc)
 210 {
 211     if (dc->r0 == R_RA) {
 212         LOG_DIS("ret\n");
 213     } else if (dc->r0 == R_EA) {
 214         LOG_DIS("eret\n");
 215     } else if (dc->r0 == R_BA) {
 216         LOG_DIS("bret\n");
 217     } else {
 218         LOG_DIS("b r%d\n", dc->r0);
 219     }
 220
 221     /* restore IE.IE in case of an eret */
 222     if (dc->r0 == R_EA) {
 223         TCGv t0 = tcg_temp_new();
 224         TCGLabel *l1 = gen_new_label();
 225         tcg_gen_andi_tl(t0, cpu_ie, IE_EIE);
 226         tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
 227         tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1);
 228         tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
 229         gen_set_label(l1);
 230         tcg_temp_free(t0);
 231     } else if (dc->r0 == R_BA) {
 232         TCGv t0 = tcg_temp_new();
 233         TCGLabel *l1 = gen_new_label();
 234         tcg_gen_andi_tl(t0, cpu_ie, IE_BIE);
 235         tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
 236         tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1);
 237         tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
 238         gen_set_label(l1);
 239         tcg_temp_free(t0);
 240     }
 241     tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
 242
 243     dc->is_jmp = DISAS_JUMP;
 244 }
 245
 246 static void dec_bi(DisasContext *dc)
 247 {
 248     LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26));
 249
 250     gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
 251
 252     dc->is_jmp = DISAS_TB_JUMP;
 253 }
 254
 255 static inline void gen_cond_branch(DisasContext *dc, int cond)
 256 {
 257     TCGLabel *l1 = gen_new_label();
 258     tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1);
 259     gen_goto_tb(dc, 0, dc->pc + 4);
 260     gen_set_label(l1);
 261     gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16)));
 262     dc->is_jmp = DISAS_TB_JUMP;
 263 }
 264
 265 static void dec_be(DisasContext *dc)
 266 {
 267     LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
 268             sign_extend(dc->imm16, 16) * 4);
 269
 270     gen_cond_branch(dc, TCG_COND_EQ);
 271 }
 272
 273 static void dec_bg(DisasContext *dc)
 274 {
 275     LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
 276             sign_extend(dc->imm16, 16 * 4));
 277
 278     gen_cond_branch(dc, TCG_COND_GT);
 279 }
 280
 281 static void dec_bge(DisasContext *dc)
 282 {
 283     LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
 284             sign_extend(dc->imm16, 16) * 4);
 285
 286     gen_cond_branch(dc, TCG_COND_GE);
 287 }
 288
 289 static void dec_bgeu(DisasContext *dc)
 290 {
 291     LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
 292             sign_extend(dc->imm16, 16) * 4);
 293
 294     gen_cond_branch(dc, TCG_COND_GEU);
 295 }
 296
 297 static void dec_bgu(DisasContext *dc)
 298 {
 299     LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
 300             sign_extend(dc->imm16, 16) * 4);
 301
 302     gen_cond_branch(dc, TCG_COND_GTU);
 303 }
 304
 305 static void dec_bne(DisasContext *dc)
 306 {
 307     LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
 308             sign_extend(dc->imm16, 16) * 4);
 309
 310     gen_cond_branch(dc, TCG_COND_NE);
 311 }
 312
 313 static void dec_call(DisasContext *dc)
 314 {
 315     LOG_DIS("call r%d\n", dc->r0);
 316
 317     tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
 318     tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
 319
 320     dc->is_jmp = DISAS_JUMP;
 321 }
 322
 323 static void dec_calli(DisasContext *dc)
 324 {
 325     LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4);
 326
 327     tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
 328     gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
 329
 330     dc->is_jmp = DISAS_TB_JUMP;
 331 }
 332
 333 static inline void gen_compare(DisasContext *dc, int cond)
 334 {
 335     int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
 336     int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
 337     int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1;
 338     int i;
 339
 340     if (dc->format == OP_FMT_RI) {
 341         switch (cond) {
 342         case TCG_COND_GEU:
 343         case TCG_COND_GTU:
 344             i = zero_extend(dc->imm16, 16);
 345             break;
 346         default:
 347             i = sign_extend(dc->imm16, 16);
 348             break;
 349         }
 350
 351         tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY], i);
 352     } else {
 353         tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]);
 354     }
 355 }
 356
 357 static void dec_cmpe(DisasContext *dc)
 358 {
 359     if (dc->format == OP_FMT_RI) {
 360         LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
 361                 sign_extend(dc->imm16, 16));
 362     } else {
 363         LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 364     }
 365
 366     gen_compare(dc, TCG_COND_EQ);
 367 }
 368
 369 static void dec_cmpg(DisasContext *dc)
 370 {
 371     if (dc->format == OP_FMT_RI) {
 372         LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
 373                 sign_extend(dc->imm16, 16));
 374     } else {
 375         LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 376     }
 377
 378     gen_compare(dc, TCG_COND_GT);
 379 }
 380
 381 static void dec_cmpge(DisasContext *dc)
 382 {
 383     if (dc->format == OP_FMT_RI) {
 384         LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
 385                 sign_extend(dc->imm16, 16));
 386     } else {
 387         LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 388     }
 389
 390     gen_compare(dc, TCG_COND_GE);
 391 }
 392
 393 static void dec_cmpgeu(DisasContext *dc)
 394 {
 395     if (dc->format == OP_FMT_RI) {
 396         LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
 397                 zero_extend(dc->imm16, 16));
 398     } else {
 399         LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 400     }
 401
 402     gen_compare(dc, TCG_COND_GEU);
 403 }
 404
 405 static void dec_cmpgu(DisasContext *dc)
 406 {
 407     if (dc->format == OP_FMT_RI) {
 408         LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
 409                 zero_extend(dc->imm16, 16));
 410     } else {
 411         LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 412     }
 413
 414     gen_compare(dc, TCG_COND_GTU);
 415 }
 416
 417 static void dec_cmpne(DisasContext *dc)
 418 {
 419     if (dc->format == OP_FMT_RI) {
 420         LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
 421                 sign_extend(dc->imm16, 16));
 422     } else {
 423         LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 424     }
 425
 426     gen_compare(dc, TCG_COND_NE);
 427 }
 428
 429 static void dec_divu(DisasContext *dc)
 430 {
 431     TCGLabel *l1;
 432
 433     LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 434
 435     if (!(dc->features & LM32_FEATURE_DIVIDE)) {
 436         qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
 437         t_gen_illegal_insn(dc);
 438         return;
 439     }
 440
 441     l1 = gen_new_label();
 442     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
 443     tcg_gen_movi_tl(cpu_pc, dc->pc);
 444     t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
 445     gen_set_label(l1);
 446     tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 447 }
 448
 449 static void dec_lb(DisasContext *dc)
 450 {
 451     TCGv t0;
 452
 453     LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 454
 455     t0 = tcg_temp_new();
 456     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 457     tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX);
 458     tcg_temp_free(t0);
 459 }
 460
 461 static void dec_lbu(DisasContext *dc)
 462 {
 463     TCGv t0;
 464
 465     LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 466
 467     t0 = tcg_temp_new();
 468     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 469     tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX);
 470     tcg_temp_free(t0);
 471 }
 472
 473 static void dec_lh(DisasContext *dc)
 474 {
 475     TCGv t0;
 476
 477     LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 478
 479     t0 = tcg_temp_new();
 480     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 481     tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX);
 482     tcg_temp_free(t0);
 483 }
 484
 485 static void dec_lhu(DisasContext *dc)
 486 {
 487     TCGv t0;
 488
 489     LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 490
 491     t0 = tcg_temp_new();
 492     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 493     tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX);
 494     tcg_temp_free(t0);
 495 }
 496
 497 static void dec_lw(DisasContext *dc)
 498 {
 499     TCGv t0;
 500
 501     LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16));
 502
 503     t0 = tcg_temp_new();
 504     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 505     tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX);
 506     tcg_temp_free(t0);
 507 }
 508
 509 static void dec_modu(DisasContext *dc)
 510 {
 511     TCGLabel *l1;
 512
 513     LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
 514
 515     if (!(dc->features & LM32_FEATURE_DIVIDE)) {
 516         qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
 517         t_gen_illegal_insn(dc);
 518         return;
 519     }
 520
 521     l1 = gen_new_label();
 522     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
 523     tcg_gen_movi_tl(cpu_pc, dc->pc);
 524     t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
 525     gen_set_label(l1);
 526     tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 527 }
 528
 529 static void dec_mul(DisasContext *dc)
 530 {
 531     if (dc->format == OP_FMT_RI) {
 532         LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
 533                 sign_extend(dc->imm16, 16));
 534     } else {
 535         LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 536     }
 537
 538     if (!(dc->features & LM32_FEATURE_MULTIPLY)) {
 539         qemu_log_mask(LOG_GUEST_ERROR,
 540                       "hardware multiplier is not available\n");
 541         t_gen_illegal_insn(dc);
 542         return;
 543     }
 544
 545     if (dc->format == OP_FMT_RI) {
 546         tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 547                 sign_extend(dc->imm16, 16));
 548     } else {
 549         tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 550     }
 551 }
 552
 553 static void dec_nor(DisasContext *dc)
 554 {
 555     if (dc->format == OP_FMT_RI) {
 556         LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
 557                 zero_extend(dc->imm16, 16));
 558     } else {
 559         LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 560     }
 561
 562     if (dc->format == OP_FMT_RI) {
 563         TCGv t0 = tcg_temp_new();
 564         tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
 565         tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0);
 566         tcg_temp_free(t0);
 567     } else {
 568         tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 569     }
 570 }
 571
 572 static void dec_or(DisasContext *dc)
 573 {
 574     if (dc->format == OP_FMT_RI) {
 575         LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
 576                 zero_extend(dc->imm16, 16));
 577     } else {
 578         if (dc->r1 == R_R0) {
 579             LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
 580         } else {
 581             LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 582         }
 583     }
 584
 585     if (dc->format == OP_FMT_RI) {
 586         tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 587                 zero_extend(dc->imm16, 16));
 588     } else {
 589         tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 590     }
 591 }
 592
 593 static void dec_orhi(DisasContext *dc)
 594 {
 595     if (dc->r0 == R_R0) {
 596         LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
 597     } else {
 598         LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
 599     }
 600
 601     tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
 602 }
 603
 604 static void dec_scall(DisasContext *dc)
 605 {
 606     switch (dc->imm5) {
 607     case 2:
 608         LOG_DIS("break\n");
 609         tcg_gen_movi_tl(cpu_pc, dc->pc);
 610         t_gen_raise_exception(dc, EXCP_BREAKPOINT);
 611         break;
 612     case 7:
 613         LOG_DIS("scall\n");
 614         tcg_gen_movi_tl(cpu_pc, dc->pc);
 615         t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
 616         break;
 617     default:
 618         qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode @0x%x", dc->pc);
 619         t_gen_illegal_insn(dc);
 620         break;
 621     }
 622 }
 623
 624 static void dec_rcsr(DisasContext *dc)
 625 {
 626     LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
 627
 628     switch (dc->csr) {
 629     case CSR_IE:
 630         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
 631         break;
 632     case CSR_IM:
 633         gen_helper_rcsr_im(cpu_R[dc->r2], cpu_env);
 634         break;
 635     case CSR_IP:
 636         gen_helper_rcsr_ip(cpu_R[dc->r2], cpu_env);
 637         break;
 638     case CSR_CC:
 639         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
 640         break;
 641     case CSR_CFG:
 642         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg);
 643         break;
 644     case CSR_EBA:
 645         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba);
 646         break;
 647     case CSR_DC:
 648         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc);
 649         break;
 650     case CSR_DEBA:
 651         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
 652         break;
 653     case CSR_JTX:
 654         gen_helper_rcsr_jtx(cpu_R[dc->r2], cpu_env);
 655         break;
 656     case CSR_JRX:
 657         gen_helper_rcsr_jrx(cpu_R[dc->r2], cpu_env);
 658         break;
 659     case CSR_ICC:
 660     case CSR_DCC:
 661     case CSR_BP0:
 662     case CSR_BP1:
 663     case CSR_BP2:
 664     case CSR_BP3:
 665     case CSR_WP0:
 666     case CSR_WP1:
 667     case CSR_WP2:
 668     case CSR_WP3:
 669         qemu_log_mask(LOG_GUEST_ERROR, "invalid read access csr=%x\n", dc->csr);
 670         break;
 671     default:
 672         qemu_log_mask(LOG_GUEST_ERROR, "read_csr: unknown csr=%x\n", dc->csr);
 673         break;
 674     }
 675 }
 676
 677 static void dec_sb(DisasContext *dc)
 678 {
 679     TCGv t0;
 680
 681     LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
 682
 683     t0 = tcg_temp_new();
 684     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 685     tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX);
 686     tcg_temp_free(t0);
 687 }
 688
 689 static void dec_sextb(DisasContext *dc)
 690 {
 691     LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
 692
 693     if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
 694         qemu_log_mask(LOG_GUEST_ERROR,
 695                       "hardware sign extender is not available\n");
 696         t_gen_illegal_insn(dc);
 697         return;
 698     }
 699
 700     tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
 701 }
 702
 703 static void dec_sexth(DisasContext *dc)
 704 {
 705     LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
 706
 707     if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
 708         qemu_log_mask(LOG_GUEST_ERROR,
 709                       "hardware sign extender is not available\n");
 710         t_gen_illegal_insn(dc);
 711         return;
 712     }
 713
 714     tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
 715 }
 716
 717 static void dec_sh(DisasContext *dc)
 718 {
 719     TCGv t0;
 720
 721     LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
 722
 723     t0 = tcg_temp_new();
 724     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 725     tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX);
 726     tcg_temp_free(t0);
 727 }
 728
 729 static void dec_sl(DisasContext *dc)
 730 {
 731     if (dc->format == OP_FMT_RI) {
 732         LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
 733     } else {
 734         LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 735     }
 736
 737     if (!(dc->features & LM32_FEATURE_SHIFT)) {
 738         qemu_log_mask(LOG_GUEST_ERROR, "hardware shifter is not available\n");
 739         t_gen_illegal_insn(dc);
 740         return;
 741     }
 742
 743     if (dc->format == OP_FMT_RI) {
 744         tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
 745     } else {
 746         TCGv t0 = tcg_temp_new();
 747         tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
 748         tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
 749         tcg_temp_free(t0);
 750     }
 751 }
 752
 753 static void dec_sr(DisasContext *dc)
 754 {
 755     if (dc->format == OP_FMT_RI) {
 756         LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
 757     } else {
 758         LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 759     }
 760
 761     /* The real CPU (w/o hardware shifter) only supports right shift by exactly
 762      * one bit */
 763     if (dc->format == OP_FMT_RI) {
 764         if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
 765             qemu_log_mask(LOG_GUEST_ERROR,
 766                     "hardware shifter is not available\n");
 767             t_gen_illegal_insn(dc);
 768             return;
 769         }
 770         tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
 771     } else {
 772         TCGLabel *l1 = gen_new_label();
 773         TCGLabel *l2 = gen_new_label();
 774         TCGv t0 = tcg_temp_local_new();
 775         tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
 776
 777         if (!(dc->features & LM32_FEATURE_SHIFT)) {
 778             tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
 779             t_gen_illegal_insn(dc);
 780             tcg_gen_br(l2);
 781         }
 782
 783         gen_set_label(l1);
 784         tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
 785         gen_set_label(l2);
 786
 787         tcg_temp_free(t0);
 788     }
 789 }
 790
 791 static void dec_sru(DisasContext *dc)
 792 {
 793     if (dc->format == OP_FMT_RI) {
 794         LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
 795     } else {
 796         LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 797     }
 798
 799     if (dc->format == OP_FMT_RI) {
 800         if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
 801             qemu_log_mask(LOG_GUEST_ERROR,
 802                     "hardware shifter is not available\n");
 803             t_gen_illegal_insn(dc);
 804             return;
 805         }
 806         tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
 807     } else {
 808         TCGLabel *l1 = gen_new_label();
 809         TCGLabel *l2 = gen_new_label();
 810         TCGv t0 = tcg_temp_local_new();
 811         tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
 812
 813         if (!(dc->features & LM32_FEATURE_SHIFT)) {
 814             tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
 815             t_gen_illegal_insn(dc);
 816             tcg_gen_br(l2);
 817         }
 818
 819         gen_set_label(l1);
 820         tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
 821         gen_set_label(l2);
 822
 823         tcg_temp_free(t0);
 824     }
 825 }
 826
 827 static void dec_sub(DisasContext *dc)
 828 {
 829     LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 830
 831     tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 832 }
 833
 834 static void dec_sw(DisasContext *dc)
 835 {
 836     TCGv t0;
 837
 838     LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1);
 839
 840     t0 = tcg_temp_new();
 841     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 842     tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX);
 843     tcg_temp_free(t0);
 844 }
 845
 846 static void dec_user(DisasContext *dc)
 847 {
 848     LOG_DIS("user");
 849
 850     qemu_log_mask(LOG_GUEST_ERROR, "user instruction undefined\n");
 851     t_gen_illegal_insn(dc);
 852 }
 853
 854 static void dec_wcsr(DisasContext *dc)
 855 {
 856     int no;
 857
 858     LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
 859
 860     switch (dc->csr) {
 861     case CSR_IE:
 862         tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]);
 863         tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 864         dc->is_jmp = DISAS_UPDATE;
 865         break;
 866     case CSR_IM:
 867         /* mark as an io operation because it could cause an interrupt */
 868         if (dc->tb->cflags & CF_USE_ICOUNT) {
 869             gen_io_start();
 870         }
 871         gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
 872         tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 873         if (dc->tb->cflags & CF_USE_ICOUNT) {
 874             gen_io_end();
 875         }
 876         dc->is_jmp = DISAS_UPDATE;
 877         break;
 878     case CSR_IP:
 879         /* mark as an io operation because it could cause an interrupt */
 880         if (dc->tb->cflags & CF_USE_ICOUNT) {
 881             gen_io_start();
 882         }
 883         gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
 884         tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 885         if (dc->tb->cflags & CF_USE_ICOUNT) {
 886             gen_io_end();
 887         }
 888         dc->is_jmp = DISAS_UPDATE;
 889         break;
 890     case CSR_ICC:
 891         /* TODO */
 892         break;
 893     case CSR_DCC:
 894         /* TODO */
 895         break;
 896     case CSR_EBA:
 897         tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]);
 898         break;
 899     case CSR_DEBA:
 900         tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
 901         break;
 902     case CSR_JTX:
 903         gen_helper_wcsr_jtx(cpu_env, cpu_R[dc->r1]);
 904         break;
 905     case CSR_JRX:
 906         gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
 907         break;
 908     case CSR_DC:
 909         gen_helper_wcsr_dc(cpu_env, cpu_R[dc->r1]);
 910         break;
 911     case CSR_BP0:
 912     case CSR_BP1:
 913     case CSR_BP2:
 914     case CSR_BP3:
 915         no = dc->csr - CSR_BP0;
 916         if (dc->num_breakpoints <= no) {
 917             qemu_log_mask(LOG_GUEST_ERROR,
 918                           "breakpoint #%i is not available\n", no);
 919             t_gen_illegal_insn(dc);
 920             break;
 921         }
 922         gen_helper_wcsr_bp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
 923         break;
 924     case CSR_WP0:
 925     case CSR_WP1:
 926     case CSR_WP2:
 927     case CSR_WP3:
 928         no = dc->csr - CSR_WP0;
 929         if (dc->num_watchpoints <= no) {
 930             qemu_log_mask(LOG_GUEST_ERROR,
 931                           "watchpoint #%i is not available\n", no);
 932             t_gen_illegal_insn(dc);
 933             break;
 934         }
 935         gen_helper_wcsr_wp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
 936         break;
 937     case CSR_CC:
 938     case CSR_CFG:
 939         qemu_log_mask(LOG_GUEST_ERROR, "invalid write access csr=%x\n",
 940                       dc->csr);
 941         break;
 942     default:
 943         qemu_log_mask(LOG_GUEST_ERROR, "write_csr: unknown csr=%x\n",
 944                       dc->csr);
 945         break;
 946     }
 947 }
 948
 949 static void dec_xnor(DisasContext *dc)
 950 {
 951     if (dc->format == OP_FMT_RI) {
 952         LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
 953                 zero_extend(dc->imm16, 16));
 954     } else {
 955         if (dc->r1 == R_R0) {
 956             LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
 957         } else {
 958             LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 959         }
 960     }
 961
 962     if (dc->format == OP_FMT_RI) {
 963         tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 964                 zero_extend(dc->imm16, 16));
 965         tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]);
 966     } else {
 967         tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 968     }
 969 }
 970
 971 static void dec_xor(DisasContext *dc)
 972 {
 973     if (dc->format == OP_FMT_RI) {
 974         LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
 975                 zero_extend(dc->imm16, 16));
 976     } else {
 977         LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 978     }
 979
 980     if (dc->format == OP_FMT_RI) {
 981         tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 982                 zero_extend(dc->imm16, 16));
 983     } else {
 984         tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 985     }
 986 }
 987
 988 static void dec_ill(DisasContext *dc)
 989 {
 990     qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode 0x%02x\n", dc->opcode);
 991     t_gen_illegal_insn(dc);
 992 }
 993
 994 typedef void (*DecoderInfo)(DisasContext *dc);
 995 static const DecoderInfo decinfo[] = {
 996     dec_sru, dec_nor, dec_mul, dec_sh, dec_lb, dec_sr, dec_xor, dec_lh,
 997     dec_and, dec_xnor, dec_lw, dec_lhu, dec_sb, dec_add, dec_or, dec_sl,
 998     dec_lbu, dec_be, dec_bg, dec_bge, dec_bgeu, dec_bgu, dec_sw, dec_bne,
 999     dec_andhi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_orhi,
1000     dec_cmpne,
1001     dec_sru, dec_nor, dec_mul, dec_divu, dec_rcsr, dec_sr, dec_xor, dec_ill,
1002     dec_and, dec_xnor, dec_ill, dec_scall, dec_sextb, dec_add, dec_or, dec_sl,
1003     dec_b, dec_modu, dec_sub, dec_user, dec_wcsr, dec_ill, dec_call, dec_sexth,
1004     dec_bi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_calli,
1005     dec_cmpne
1006 };
1007
1008 static inline void decode(DisasContext *dc, uint32_t ir)
1009 {
1010     dc->ir = ir;
1011     LOG_DIS("%8.8x\t", dc->ir);
1012
1013     dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1014
1015     dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
1016     dc->imm16 = EXTRACT_FIELD(ir, 0, 15);
1017     dc->imm26 = EXTRACT_FIELD(ir, 0, 25);
1018
1019     dc->csr = EXTRACT_FIELD(ir, 21, 25);
1020     dc->r0 = EXTRACT_FIELD(ir, 21, 25);
1021     dc->r1 = EXTRACT_FIELD(ir, 16, 20);
1022     dc->r2 = EXTRACT_FIELD(ir, 11, 15);
1023
1024     /* bit 31 seems to indicate insn type.  */
1025     if (ir & (1 << 31)) {
1026         dc->format = OP_FMT_RR;
1027     } else {
1028         dc->format = OP_FMT_RI;
1029     }
1030
1031     assert(ARRAY_SIZE(decinfo) == 64);
1032     assert(dc->opcode < 64);
1033
1034     decinfo[dc->opcode](dc);
1035 }
1036
1037 /* generate intermediate code for basic block 'tb'.  */
1038 void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
1039 {
1040     LM32CPU *cpu = lm32_env_get_cpu(env);
1041     CPUState *cs = CPU(cpu);
1042     struct DisasContext ctx, *dc = &ctx;
1043     uint32_t pc_start;
1044     uint32_t next_page_start;
1045     int num_insns;
1046     int max_insns;
1047
1048     pc_start = tb->pc;
1049     dc->features = cpu->features;
1050     dc->num_breakpoints = cpu->num_breakpoints;
1051     dc->num_watchpoints = cpu->num_watchpoints;
1052     dc->tb = tb;
1053
1054     dc->is_jmp = DISAS_NEXT;
1055     dc->pc = pc_start;
1056     dc->singlestep_enabled = cs->singlestep_enabled;
1057
1058     if (pc_start & 3) {
1059         qemu_log_mask(LOG_GUEST_ERROR,
1060                       "unaligned PC=%x. Ignoring lowest bits.\n", pc_start);
1061         pc_start &= ~3;
1062     }
1063
1064     next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1065     num_insns = 0;
1066     max_insns = tb->cflags & CF_COUNT_MASK;
1067     if (max_insns == 0) {
1068         max_insns = CF_COUNT_MASK;
1069     }
1070     if (max_insns > TCG_MAX_INSNS) {
1071         max_insns = TCG_MAX_INSNS;
1072     }
1073
1074     gen_tb_start(tb);
1075     do {
1076         tcg_gen_insn_start(dc->pc);
1077         num_insns++;
1078
1079         if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
1080             tcg_gen_movi_tl(cpu_pc, dc->pc);
1081             t_gen_raise_exception(dc, EXCP_DEBUG);
1082             dc->is_jmp = DISAS_UPDATE;
1083             /* The address covered by the breakpoint must be included in
1084                [tb->pc, tb->pc + tb->size) in order to for it to be
1085                properly cleared -- thus we increment the PC here so that
1086                the logic setting tb->size below does the right thing.  */
1087             dc->pc += 4;
1088             break;
1089         }
1090
1091         /* Pretty disas.  */
1092         LOG_DIS("%8.8x:\t", dc->pc);
1093
1094         if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
1095             gen_io_start();
1096         }
1097
1098         decode(dc, cpu_ldl_code(env, dc->pc));
1099         dc->pc += 4;
1100     } while (!dc->is_jmp
1101          && !tcg_op_buf_full()
1102          && !cs->singlestep_enabled
1103          && !singlestep
1104          && (dc->pc < next_page_start)
1105          && num_insns < max_insns);
1106
1107     if (tb->cflags & CF_LAST_IO) {
1108         gen_io_end();
1109     }
1110
1111     if (unlikely(cs->singlestep_enabled)) {
1112         if (dc->is_jmp == DISAS_NEXT) {
1113             tcg_gen_movi_tl(cpu_pc, dc->pc);
1114         }
1115         t_gen_raise_exception(dc, EXCP_DEBUG);
1116     } else {
1117         switch (dc->is_jmp) {
1118         case DISAS_NEXT:
1119             gen_goto_tb(dc, 1, dc->pc);
1120             break;
1121         default:
1122         case DISAS_JUMP:
1123         case DISAS_UPDATE:
1124             /* indicate that the hash table must be used
1125                to find the next TB */
1126             tcg_gen_exit_tb(0);
1127             break;
1128         case DISAS_TB_JUMP:
1129             /* nothing more to generate */
1130             break;
1131         }
1132     }
1133
1134     gen_tb_end(tb, num_insns);
1135
1136     tb->size = dc->pc - pc_start;
1137     tb->icount = num_insns;
1138
1139 #ifdef DEBUG_DISAS
1140     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1141         qemu_log("\n");
1142         log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
1143         qemu_log("\nisize=%d osize=%d\n",
1144                  dc->pc - pc_start, tcg_op_buf_count());
1145     }
1146 #endif
1147 }
1148
1149 void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1150                          int flags)
1151 {
1152     LM32CPU *cpu = LM32_CPU(cs);
1153     CPULM32State *env = &cpu->env;
1154     int i;
1155
1156     if (!env || !f) {
1157         return;
1158     }
1159
1160     cpu_fprintf(f, "IN: PC=%x %s\n",
1161                 env->pc, lookup_symbol(env->pc));
1162
1163     cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
1164              env->ie,
1165              (env->ie & IE_IE) ? 1 : 0,
1166              (env->ie & IE_EIE) ? 1 : 0,
1167              (env->ie & IE_BIE) ? 1 : 0,
1168              lm32_pic_get_im(env->pic_state),
1169              lm32_pic_get_ip(env->pic_state));
1170     cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
1171              env->eba,
1172              env->deba);
1173
1174     for (i = 0; i < 32; i++) {
1175         cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1176         if ((i + 1) % 4 == 0) {
1177             cpu_fprintf(f, "\n");
1178         }
1179     }
1180     cpu_fprintf(f, "\n\n");
1181 }
1182
1183 void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb,
1184                           target_ulong *data)
1185 {
1186     env->pc = data[0];
1187 }
1188
1189 void lm32_translate_init(void)
1190 {
1191     int i;
1192
1193     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1194
1195     for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1196         cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1197                           offsetof(CPULM32State, regs[i]),
1198                           regnames[i]);
1199     }
1200
1201     for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
1202         cpu_bp[i] = tcg_global_mem_new(TCG_AREG0,
1203                           offsetof(CPULM32State, bp[i]),
1204                           regnames[32+i]);
1205     }
1206
1207     for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
1208         cpu_wp[i] = tcg_global_mem_new(TCG_AREG0,
1209                           offsetof(CPULM32State, wp[i]),
1210                           regnames[36+i]);
1211     }
1212
1213     cpu_pc = tcg_global_mem_new(TCG_AREG0,
1214                     offsetof(CPULM32State, pc),
1215                     "pc");
1216     cpu_ie = tcg_global_mem_new(TCG_AREG0,
1217                     offsetof(CPULM32State, ie),
1218                     "ie");
1219     cpu_icc = tcg_global_mem_new(TCG_AREG0,
1220                     offsetof(CPULM32State, icc),
1221                     "icc");
1222     cpu_dcc = tcg_global_mem_new(TCG_AREG0,
1223                     offsetof(CPULM32State, dcc),
1224                     "dcc");
1225     cpu_cc = tcg_global_mem_new(TCG_AREG0,
1226                     offsetof(CPULM32State, cc),
1227                     "cc");
1228     cpu_cfg = tcg_global_mem_new(TCG_AREG0,
1229                     offsetof(CPULM32State, cfg),
1230                     "cfg");
1231     cpu_eba = tcg_global_mem_new(TCG_AREG0,
1232                     offsetof(CPULM32State, eba),
1233                     "eba");
1234     cpu_dc = tcg_global_mem_new(TCG_AREG0,
1235                     offsetof(CPULM32State, dc),
1236                     "dc");
1237     cpu_deba = tcg_global_mem_new(TCG_AREG0,
1238                     offsetof(CPULM32State, deba),
1239                     "deba");
1240 }
1241