4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 #ifndef QEMU_I386_CPU_QOM_H
21 #define QEMU_I386_CPU_QOM_H
25 #include "qapi/error.h"
26 #include "qemu/notify.h"
29 #define TYPE_X86_CPU "x86_64-cpu"
31 #define TYPE_X86_CPU "i386-cpu"
34 #define X86_CPU_CLASS(klass) \
35 OBJECT_CLASS_CHECK(X86CPUClass, (klass), TYPE_X86_CPU)
36 #define X86_CPU(obj) \
37 OBJECT_CHECK(X86CPU, (obj), TYPE_X86_CPU)
38 #define X86_CPU_GET_CLASS(obj) \
39 OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU)
44 * CPU model definition data that was not converted to QOM per-subclass
45 * property defaults yet.
47 typedef struct X86CPUDefinition X86CPUDefinition
;
51 * @cpu_def: CPU model definition
52 * @kvm_required: Whether CPU model requires KVM to be enabled.
53 * @parent_realize: The parent class' realize handler.
54 * @parent_reset: The parent class' reset handler.
56 * An x86 CPU model or family.
58 typedef struct X86CPUClass
{
60 CPUClass parent_class
;
63 /* Should be eventually replaced by subclass-specific property defaults. */
64 X86CPUDefinition
*cpu_def
;
68 DeviceRealize parent_realize
;
69 void (*parent_reset
)(CPUState
*cpu
);
75 * @migratable: If set, only migratable flags will be accepted when "enforce"
76 * mode is used, and only migratable flags will be included in the "host"
81 typedef struct X86CPU
{
89 bool hyperv_relaxed_timing
;
90 int hyperv_spinlock_attempts
;
103 /* if true the CPUID code directly forward host cache leaves to the guest */
104 bool cache_info_passthrough
;
106 /* Features that were filtered out because of missing host capabilities */
107 uint32_t filtered_features
[FEATURE_WORDS
];
109 /* Enable PMU CPUID bits. This can't be enabled by default yet because
110 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
111 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
112 * capabilities) directly to the guest.
116 /* in order to simplify APIC support, we leave this pointer to the
118 struct DeviceState
*apic_state
;
119 struct MemoryRegion
*cpu_as_root
, *cpu_as_mem
, *smram
;
120 Notifier machine_done
;
123 static inline X86CPU
*x86_env_get_cpu(CPUX86State
*env
)
125 return container_of(env
, X86CPU
, env
);
128 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
130 #define ENV_OFFSET offsetof(X86CPU, env)
132 #ifndef CONFIG_USER_ONLY
133 extern struct VMStateDescription vmstate_x86_cpu
;
137 * x86_cpu_do_interrupt:
138 * @cpu: vCPU the interrupt is to be handled by.
140 void x86_cpu_do_interrupt(CPUState
*cpu
);
141 bool x86_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
143 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
144 int cpuid
, void *opaque
);
145 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
146 int cpuid
, void *opaque
);
147 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
149 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
152 void x86_cpu_get_memory_mapping(CPUState
*cpu
, MemoryMappingList
*list
,
155 void x86_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
158 hwaddr
x86_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
160 int x86_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
161 int x86_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
163 void x86_cpu_exec_enter(CPUState
*cpu
);
164 void x86_cpu_exec_exit(CPUState
*cpu
);