2 * ARM Generic Interrupt Controller using KVM in-kernel support
4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
6 * Save/Restore logic added by Christoffer Dall.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "hw/sysbus.h"
23 #include "migration/migration.h"
24 #include "sysemu/kvm.h"
26 #include "gic_internal.h"
27 #include "vgic_common.h"
29 //#define DEBUG_GIC_KVM
32 static const int debug_gic_kvm
= 1;
34 static const int debug_gic_kvm
= 0;
37 #define DPRINTF(fmt, ...) do { \
38 if (debug_gic_kvm) { \
39 printf("arm_gic: " fmt , ## __VA_ARGS__); \
43 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
44 #define KVM_ARM_GIC(obj) \
45 OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
46 #define KVM_ARM_GIC_CLASS(klass) \
47 OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
48 #define KVM_ARM_GIC_GET_CLASS(obj) \
49 OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
51 typedef struct KVMARMGICClass
{
52 ARMGICCommonClass parent_class
;
53 DeviceRealize parent_realize
;
54 void (*parent_reset
)(DeviceState
*dev
);
57 void kvm_arm_gic_set_irq(uint32_t num_irq
, int irq
, int level
)
59 /* Meaning of the 'irq' parameter:
60 * [0..N-1] : external interrupts
61 * [N..N+31] : PPI (internal) interrupts for CPU 0
62 * [N+32..N+63] : PPI (internal interrupts for CPU 1
64 * Convert this to the kernel's desired encoding, which
65 * has separate fields in the irq number for type,
66 * CPU number and interrupt number.
68 int kvm_irq
, irqtype
, cpu
;
70 if (irq
< (num_irq
- GIC_INTERNAL
)) {
71 /* External interrupt. The kernel numbers these like the GIC
72 * hardware, with external interrupt IDs starting after the
75 irqtype
= KVM_ARM_IRQ_TYPE_SPI
;
79 /* Internal interrupt: decode into (cpu, interrupt id) */
80 irqtype
= KVM_ARM_IRQ_TYPE_PPI
;
81 irq
-= (num_irq
- GIC_INTERNAL
);
82 cpu
= irq
/ GIC_INTERNAL
;
85 kvm_irq
= (irqtype
<< KVM_ARM_IRQ_TYPE_SHIFT
)
86 | (cpu
<< KVM_ARM_IRQ_VCPU_SHIFT
) | irq
;
88 kvm_set_irq(kvm_state
, kvm_irq
, !!level
);
91 static void kvm_arm_gicv2_set_irq(void *opaque
, int irq
, int level
)
93 GICState
*s
= (GICState
*)opaque
;
95 kvm_arm_gic_set_irq(s
->num_irq
, irq
, level
);
98 static bool kvm_arm_gic_can_save_restore(GICState
*s
)
100 return s
->dev_fd
>= 0;
103 #define KVM_VGIC_ATTR(offset, cpu) \
104 ((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \
105 KVM_DEV_ARM_VGIC_CPUID_MASK) | \
106 (((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \
107 KVM_DEV_ARM_VGIC_OFFSET_MASK))
109 static void kvm_gicd_access(GICState
*s
, int offset
, int cpu
,
110 uint32_t *val
, bool write
)
112 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_DIST_REGS
,
113 KVM_VGIC_ATTR(offset
, cpu
), val
, write
);
116 static void kvm_gicc_access(GICState
*s
, int offset
, int cpu
,
117 uint32_t *val
, bool write
)
119 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CPU_REGS
,
120 KVM_VGIC_ATTR(offset
, cpu
), val
, write
);
123 #define for_each_irq_reg(_ctr, _max_irq, _field_width) \
124 for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
127 * Translate from the in-kernel field for an IRQ value to/from the qemu
130 typedef void (*vgic_translate_fn
)(GICState
*s
, int irq
, int cpu
,
131 uint32_t *field
, bool to_kernel
);
133 /* synthetic translate function used for clear/set registers to completely
134 * clear a setting using a clear-register before setting the remaining bits
135 * using a set-register */
136 static void translate_clear(GICState
*s
, int irq
, int cpu
,
137 uint32_t *field
, bool to_kernel
)
142 /* does not make sense: qemu model doesn't use set/clear regs */
147 static void translate_group(GICState
*s
, int irq
, int cpu
,
148 uint32_t *field
, bool to_kernel
)
150 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
153 *field
= GIC_TEST_GROUP(irq
, cm
);
156 GIC_SET_GROUP(irq
, cm
);
161 static void translate_enabled(GICState
*s
, int irq
, int cpu
,
162 uint32_t *field
, bool to_kernel
)
164 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
167 *field
= GIC_TEST_ENABLED(irq
, cm
);
170 GIC_SET_ENABLED(irq
, cm
);
175 static void translate_pending(GICState
*s
, int irq
, int cpu
,
176 uint32_t *field
, bool to_kernel
)
178 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
181 *field
= gic_test_pending(s
, irq
, cm
);
184 GIC_SET_PENDING(irq
, cm
);
185 /* TODO: Capture is level-line is held high in the kernel */
190 static void translate_active(GICState
*s
, int irq
, int cpu
,
191 uint32_t *field
, bool to_kernel
)
193 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
196 *field
= GIC_TEST_ACTIVE(irq
, cm
);
199 GIC_SET_ACTIVE(irq
, cm
);
204 static void translate_trigger(GICState
*s
, int irq
, int cpu
,
205 uint32_t *field
, bool to_kernel
)
208 *field
= (GIC_TEST_EDGE_TRIGGER(irq
)) ? 0x2 : 0x0;
211 GIC_SET_EDGE_TRIGGER(irq
);
216 static void translate_priority(GICState
*s
, int irq
, int cpu
,
217 uint32_t *field
, bool to_kernel
)
220 *field
= GIC_GET_PRIORITY(irq
, cpu
) & 0xff;
222 gic_set_priority(s
, cpu
, irq
, *field
& 0xff, MEMTXATTRS_UNSPECIFIED
);
226 static void translate_targets(GICState
*s
, int irq
, int cpu
,
227 uint32_t *field
, bool to_kernel
)
230 *field
= s
->irq_target
[irq
] & 0xff;
232 s
->irq_target
[irq
] = *field
& 0xff;
236 static void translate_sgisource(GICState
*s
, int irq
, int cpu
,
237 uint32_t *field
, bool to_kernel
)
240 *field
= s
->sgi_pending
[irq
][cpu
] & 0xff;
242 s
->sgi_pending
[irq
][cpu
] = *field
& 0xff;
246 /* Read a register group from the kernel VGIC */
247 static void kvm_dist_get(GICState
*s
, uint32_t offset
, int width
,
248 int maxirq
, vgic_translate_fn translate_fn
)
255 int regsz
= 32 / width
; /* irqs per kernel register */
258 for_each_irq_reg(i
, maxirq
, width
) {
261 while ((cpu
< s
->num_cpu
&& irq
< GIC_INTERNAL
) || cpu
== 0) {
262 kvm_gicd_access(s
, offset
, cpu
, ®
, false);
263 for (j
= 0; j
< regsz
; j
++) {
264 field
= extract32(reg
, j
* width
, width
);
265 translate_fn(s
, irq
+ j
, cpu
, &field
, false);
274 /* Write a register group to the kernel VGIC */
275 static void kvm_dist_put(GICState
*s
, uint32_t offset
, int width
,
276 int maxirq
, vgic_translate_fn translate_fn
)
283 int regsz
= 32 / width
; /* irqs per kernel register */
286 for_each_irq_reg(i
, maxirq
, width
) {
289 while ((cpu
< s
->num_cpu
&& irq
< GIC_INTERNAL
) || cpu
== 0) {
291 for (j
= 0; j
< regsz
; j
++) {
292 translate_fn(s
, irq
+ j
, cpu
, &field
, true);
293 reg
= deposit32(reg
, j
* width
, width
, field
);
295 kvm_gicd_access(s
, offset
, cpu
, ®
, true);
303 static void kvm_arm_gic_put(GICState
*s
)
311 /* Note: We do the restore in a slightly different order than the save
312 * (where the order doesn't matter and is simply ordered according to the
313 * register offset values */
315 /*****************************************************************
319 /* s->ctlr -> GICD_CTLR */
321 kvm_gicd_access(s
, 0x0, 0, ®
, true);
323 /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
324 kvm_gicd_access(s
, 0x4, 0, ®
, false);
325 num_irq
= ((reg
& 0x1f) + 1) * 32;
326 num_cpu
= ((reg
& 0xe0) >> 5) + 1;
328 if (num_irq
< s
->num_irq
) {
329 fprintf(stderr
, "Restoring %u IRQs, but kernel supports max %d\n",
330 s
->num_irq
, num_irq
);
332 } else if (num_cpu
!= s
->num_cpu
) {
333 fprintf(stderr
, "Restoring %u CPU interfaces, kernel only has %d\n",
334 s
->num_cpu
, num_cpu
);
335 /* Did we not create the VCPUs in the kernel yet? */
339 /* TODO: Consider checking compatibility with the IIDR ? */
341 /* irq_state[n].enabled -> GICD_ISENABLERn */
342 kvm_dist_put(s
, 0x180, 1, s
->num_irq
, translate_clear
);
343 kvm_dist_put(s
, 0x100, 1, s
->num_irq
, translate_enabled
);
345 /* irq_state[n].group -> GICD_IGROUPRn */
346 kvm_dist_put(s
, 0x80, 1, s
->num_irq
, translate_group
);
348 /* s->irq_target[irq] -> GICD_ITARGETSRn
349 * (restore targets before pending to ensure the pending state is set on
350 * the appropriate CPU interfaces in the kernel) */
351 kvm_dist_put(s
, 0x800, 8, s
->num_irq
, translate_targets
);
353 /* irq_state[n].trigger -> GICD_ICFGRn
354 * (restore configuration registers before pending IRQs so we treat
355 * level/edge correctly) */
356 kvm_dist_put(s
, 0xc00, 2, s
->num_irq
, translate_trigger
);
358 /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
359 kvm_dist_put(s
, 0x280, 1, s
->num_irq
, translate_clear
);
360 kvm_dist_put(s
, 0x200, 1, s
->num_irq
, translate_pending
);
362 /* irq_state[n].active -> GICD_ISACTIVERn */
363 kvm_dist_put(s
, 0x380, 1, s
->num_irq
, translate_clear
);
364 kvm_dist_put(s
, 0x300, 1, s
->num_irq
, translate_active
);
367 /* s->priorityX[irq] -> ICD_IPRIORITYRn */
368 kvm_dist_put(s
, 0x400, 8, s
->num_irq
, translate_priority
);
370 /* s->sgi_pending -> ICD_CPENDSGIRn */
371 kvm_dist_put(s
, 0xf10, 8, GIC_NR_SGIS
, translate_clear
);
372 kvm_dist_put(s
, 0xf20, 8, GIC_NR_SGIS
, translate_sgisource
);
375 /*****************************************************************
376 * CPU Interface(s) State
379 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
380 /* s->cpu_ctlr[cpu] -> GICC_CTLR */
381 reg
= s
->cpu_ctlr
[cpu
];
382 kvm_gicc_access(s
, 0x00, cpu
, ®
, true);
384 /* s->priority_mask[cpu] -> GICC_PMR */
385 reg
= (s
->priority_mask
[cpu
] & 0xff);
386 kvm_gicc_access(s
, 0x04, cpu
, ®
, true);
388 /* s->bpr[cpu] -> GICC_BPR */
389 reg
= (s
->bpr
[cpu
] & 0x7);
390 kvm_gicc_access(s
, 0x08, cpu
, ®
, true);
392 /* s->abpr[cpu] -> GICC_ABPR */
393 reg
= (s
->abpr
[cpu
] & 0x7);
394 kvm_gicc_access(s
, 0x1c, cpu
, ®
, true);
396 /* s->apr[n][cpu] -> GICC_APRn */
397 for (i
= 0; i
< 4; i
++) {
398 reg
= s
->apr
[i
][cpu
];
399 kvm_gicc_access(s
, 0xd0 + i
* 4, cpu
, ®
, true);
404 static void kvm_arm_gic_get(GICState
*s
)
410 /*****************************************************************
414 /* GICD_CTLR -> s->ctlr */
415 kvm_gicd_access(s
, 0x0, 0, ®
, false);
418 /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
419 kvm_gicd_access(s
, 0x4, 0, ®
, false);
420 s
->num_irq
= ((reg
& 0x1f) + 1) * 32;
421 s
->num_cpu
= ((reg
& 0xe0) >> 5) + 1;
423 if (s
->num_irq
> GIC_MAXIRQ
) {
424 fprintf(stderr
, "Too many IRQs reported from the kernel: %d\n",
430 kvm_gicd_access(s
, 0x8, 0, ®
, false);
432 /* Clear all the IRQ settings */
433 for (i
= 0; i
< s
->num_irq
; i
++) {
434 memset(&s
->irq_state
[i
], 0, sizeof(s
->irq_state
[0]));
437 /* GICD_IGROUPRn -> irq_state[n].group */
438 kvm_dist_get(s
, 0x80, 1, s
->num_irq
, translate_group
);
440 /* GICD_ISENABLERn -> irq_state[n].enabled */
441 kvm_dist_get(s
, 0x100, 1, s
->num_irq
, translate_enabled
);
443 /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
444 kvm_dist_get(s
, 0x200, 1, s
->num_irq
, translate_pending
);
446 /* GICD_ISACTIVERn -> irq_state[n].active */
447 kvm_dist_get(s
, 0x300, 1, s
->num_irq
, translate_active
);
449 /* GICD_ICFRn -> irq_state[n].trigger */
450 kvm_dist_get(s
, 0xc00, 2, s
->num_irq
, translate_trigger
);
452 /* GICD_IPRIORITYRn -> s->priorityX[irq] */
453 kvm_dist_get(s
, 0x400, 8, s
->num_irq
, translate_priority
);
455 /* GICD_ITARGETSRn -> s->irq_target[irq] */
456 kvm_dist_get(s
, 0x800, 8, s
->num_irq
, translate_targets
);
458 /* GICD_CPENDSGIRn -> s->sgi_pending */
459 kvm_dist_get(s
, 0xf10, 8, GIC_NR_SGIS
, translate_sgisource
);
462 /*****************************************************************
463 * CPU Interface(s) State
466 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
467 /* GICC_CTLR -> s->cpu_ctlr[cpu] */
468 kvm_gicc_access(s
, 0x00, cpu
, ®
, false);
469 s
->cpu_ctlr
[cpu
] = reg
;
471 /* GICC_PMR -> s->priority_mask[cpu] */
472 kvm_gicc_access(s
, 0x04, cpu
, ®
, false);
473 s
->priority_mask
[cpu
] = (reg
& 0xff);
475 /* GICC_BPR -> s->bpr[cpu] */
476 kvm_gicc_access(s
, 0x08, cpu
, ®
, false);
477 s
->bpr
[cpu
] = (reg
& 0x7);
479 /* GICC_ABPR -> s->abpr[cpu] */
480 kvm_gicc_access(s
, 0x1c, cpu
, ®
, false);
481 s
->abpr
[cpu
] = (reg
& 0x7);
483 /* GICC_APRn -> s->apr[n][cpu] */
484 for (i
= 0; i
< 4; i
++) {
485 kvm_gicc_access(s
, 0xd0 + i
* 4, cpu
, ®
, false);
486 s
->apr
[i
][cpu
] = reg
;
491 static void kvm_arm_gic_reset(DeviceState
*dev
)
493 GICState
*s
= ARM_GIC_COMMON(dev
);
494 KVMARMGICClass
*kgc
= KVM_ARM_GIC_GET_CLASS(s
);
496 kgc
->parent_reset(dev
);
498 if (kvm_arm_gic_can_save_restore(s
)) {
503 static void kvm_arm_gic_realize(DeviceState
*dev
, Error
**errp
)
506 GICState
*s
= KVM_ARM_GIC(dev
);
507 KVMARMGICClass
*kgc
= KVM_ARM_GIC_GET_CLASS(s
);
508 Error
*local_err
= NULL
;
511 kgc
->parent_realize(dev
, &local_err
);
513 error_propagate(errp
, local_err
);
517 if (s
->security_extn
) {
518 error_setg(errp
, "the in-kernel VGIC does not implement the "
519 "security extensions");
523 gic_init_irqs_and_mmio(s
, kvm_arm_gicv2_set_irq
, NULL
);
525 for (i
= 0; i
< s
->num_irq
- GIC_INTERNAL
; i
++) {
526 qemu_irq irq
= qdev_get_gpio_in(dev
, i
);
527 kvm_irqchip_set_qemuirq_gsi(kvm_state
, irq
, i
);
530 /* Try to create the device via the device control API */
532 ret
= kvm_create_device(kvm_state
, KVM_DEV_TYPE_ARM_VGIC_V2
, false);
536 /* Newstyle API is used, we may have attributes */
537 if (kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_NR_IRQS
, 0)) {
538 uint32_t numirqs
= s
->num_irq
;
539 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_NR_IRQS
, 0,
542 /* Tell the kernel to complete VGIC initialization now */
543 if (kvm_device_check_attr(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
544 KVM_DEV_ARM_VGIC_CTRL_INIT
)) {
545 kvm_device_access(s
->dev_fd
, KVM_DEV_ARM_VGIC_GRP_CTRL
,
546 KVM_DEV_ARM_VGIC_CTRL_INIT
, NULL
, true);
548 } else if (ret
!= -ENODEV
&& ret
!= -ENOTSUP
) {
549 error_setg_errno(errp
, -ret
, "error creating in-kernel VGIC");
554 kvm_arm_register_device(&s
->iomem
,
555 (KVM_ARM_DEVICE_VGIC_V2
<< KVM_ARM_DEVICE_ID_SHIFT
)
556 | KVM_VGIC_V2_ADDR_TYPE_DIST
,
557 KVM_DEV_ARM_VGIC_GRP_ADDR
,
558 KVM_VGIC_V2_ADDR_TYPE_DIST
,
560 /* CPU interface for current core. Unlike arm_gic, we don't
561 * provide the "interface for core #N" memory regions, because
562 * cores with a VGIC don't have those.
564 kvm_arm_register_device(&s
->cpuiomem
[0],
565 (KVM_ARM_DEVICE_VGIC_V2
<< KVM_ARM_DEVICE_ID_SHIFT
)
566 | KVM_VGIC_V2_ADDR_TYPE_CPU
,
567 KVM_DEV_ARM_VGIC_GRP_ADDR
,
568 KVM_VGIC_V2_ADDR_TYPE_CPU
,
571 if (!kvm_arm_gic_can_save_restore(s
)) {
572 error_setg(&s
->migration_blocker
, "This operating system kernel does "
573 "not support vGICv2 migration");
574 migrate_add_blocker(s
->migration_blocker
);
578 static void kvm_arm_gic_class_init(ObjectClass
*klass
, void *data
)
580 DeviceClass
*dc
= DEVICE_CLASS(klass
);
581 ARMGICCommonClass
*agcc
= ARM_GIC_COMMON_CLASS(klass
);
582 KVMARMGICClass
*kgc
= KVM_ARM_GIC_CLASS(klass
);
584 agcc
->pre_save
= kvm_arm_gic_get
;
585 agcc
->post_load
= kvm_arm_gic_put
;
586 kgc
->parent_realize
= dc
->realize
;
587 kgc
->parent_reset
= dc
->reset
;
588 dc
->realize
= kvm_arm_gic_realize
;
589 dc
->reset
= kvm_arm_gic_reset
;
592 static const TypeInfo kvm_arm_gic_info
= {
593 .name
= TYPE_KVM_ARM_GIC
,
594 .parent
= TYPE_ARM_GIC_COMMON
,
595 .instance_size
= sizeof(GICState
),
596 .class_init
= kvm_arm_gic_class_init
,
597 .class_size
= sizeof(KVMARMGICClass
),
600 static void kvm_arm_gic_register_types(void)
602 type_register_static(&kvm_arm_gic_info
);
605 type_init(kvm_arm_gic_register_types
)