?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-arm: implement BE32 mode in system emulation
[qemu/cris-port.git] / target-arm / translate.c
blob25db09e9f58a0b431de00e7b23527078466d4f33
1 /*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "qemu/osdep.h"
22
23 #include "cpu.h"
24 #include "internals.h"
25 #include "disas/disas.h"
26 #include "tcg-op.h"
27 #include "qemu/log.h"
28 #include "qemu/bitops.h"
29 #include "arm_ldst.h"
30
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
33
34 #include "trace-tcg.h"
35 #include "exec/log.h"
36
37
38 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T)
39 #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
40 /* currently all emulated v5 cores are also v5TE, so don't bother */
41 #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
42 #define ENABLE_ARCH_5J 0
43 #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
44 #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
45 #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
46 #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7)
47 #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8)
48
49 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
50
51 #include "translate.h"
52
53 #if defined(CONFIG_USER_ONLY)
54 #define IS_USER(s) 1
55 #else
56 #define IS_USER(s) (s->user)
57 #endif
58
59 TCGv_env cpu_env;
60 /* We reuse the same 64-bit temporaries for efficiency. */
61 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
62 static TCGv_i32 cpu_R[16];
63 TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
64 TCGv_i64 cpu_exclusive_addr;
65 TCGv_i64 cpu_exclusive_val;
66 #ifdef CONFIG_USER_ONLY
67 TCGv_i64 cpu_exclusive_test;
68 TCGv_i32 cpu_exclusive_info;
69 #endif
70
71 /* FIXME: These should be removed. */
72 static TCGv_i32 cpu_F0s, cpu_F1s;
73 static TCGv_i64 cpu_F0d, cpu_F1d;
74
75 #include "exec/gen-icount.h"
76
77 static const char *regnames[] =
78 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
79 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
80
81 /* initialize TCG globals. */
82 void arm_translate_init(void)
83 {
84 int i;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 for (i = 0; i < 16; i++) {
89 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
90 offsetof(CPUARMState, regs[i]),
91 regnames[i]);
92 }
93 cpu_CF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, CF), "CF");
94 cpu_NF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, NF), "NF");
95 cpu_VF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, VF), "VF");
96 cpu_ZF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, ZF), "ZF");
97
98 cpu_exclusive_addr = tcg_global_mem_new_i64(cpu_env,
99 offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
100 cpu_exclusive_val = tcg_global_mem_new_i64(cpu_env,
101 offsetof(CPUARMState, exclusive_val), "exclusive_val");
102 #ifdef CONFIG_USER_ONLY
103 cpu_exclusive_test = tcg_global_mem_new_i64(cpu_env,
104 offsetof(CPUARMState, exclusive_test), "exclusive_test");
105 cpu_exclusive_info = tcg_global_mem_new_i32(cpu_env,
106 offsetof(CPUARMState, exclusive_info), "exclusive_info");
107 #endif
108
109 a64_translate_init();
110 }
111
112 static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
113 {
114 /* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
115 * insns:
116 * if PL2, UNPREDICTABLE (we choose to implement as if PL0)
117 * otherwise, access as if at PL0.
118 */
119 switch (s->mmu_idx) {
120 case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */
121 case ARMMMUIdx_S12NSE0:
122 case ARMMMUIdx_S12NSE1:
123 return ARMMMUIdx_S12NSE0;
124 case ARMMMUIdx_S1E3:
125 case ARMMMUIdx_S1SE0:
126 case ARMMMUIdx_S1SE1:
127 return ARMMMUIdx_S1SE0;
128 case ARMMMUIdx_S2NS:
129 default:
130 g_assert_not_reached();
131 }
132 }
133
134 static inline TCGv_i32 load_cpu_offset(int offset)
135 {
136 TCGv_i32 tmp = tcg_temp_new_i32();
137 tcg_gen_ld_i32(tmp, cpu_env, offset);
138 return tmp;
139 }
140
141 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
142
143 static inline void store_cpu_offset(TCGv_i32 var, int offset)
144 {
145 tcg_gen_st_i32(var, cpu_env, offset);
146 tcg_temp_free_i32(var);
147 }
148
149 #define store_cpu_field(var, name) \
150 store_cpu_offset(var, offsetof(CPUARMState, name))
151
152 /* Set a variable to the value of a CPU register. */
153 static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
154 {
155 if (reg == 15) {
156 uint32_t addr;
157 /* normally, since we updated PC, we need only to add one insn */
158 if (s->thumb)
159 addr = (long)s->pc + 2;
160 else
161 addr = (long)s->pc + 4;
162 tcg_gen_movi_i32(var, addr);
163 } else {
164 tcg_gen_mov_i32(var, cpu_R[reg]);
165 }
166 }
167
168 /* Create a new temporary and set it to the value of a CPU register. */
169 static inline TCGv_i32 load_reg(DisasContext *s, int reg)
170 {
171 TCGv_i32 tmp = tcg_temp_new_i32();
172 load_reg_var(s, tmp, reg);
173 return tmp;
174 }
175
176 /* Set a CPU register. The source must be a temporary and will be
177 marked as dead. */
178 static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
179 {
180 if (reg == 15) {
181 tcg_gen_andi_i32(var, var, ~1);
182 s->is_jmp = DISAS_JUMP;
183 }
184 tcg_gen_mov_i32(cpu_R[reg], var);
185 tcg_temp_free_i32(var);
186 }
187
188 /* Value extensions. */
189 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
190 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
191 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
192 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
193
194 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
195 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
196
197
198 static inline void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
199 {
200 TCGv_i32 tmp_mask = tcg_const_i32(mask);
201 gen_helper_cpsr_write(cpu_env, var, tmp_mask);
202 tcg_temp_free_i32(tmp_mask);
203 }
204 /* Set NZCV flags from the high 4 bits of var. */
205 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
206
207 static void gen_exception_internal(int excp)
208 {
209 TCGv_i32 tcg_excp = tcg_const_i32(excp);
210
211 assert(excp_is_internal(excp));
212 gen_helper_exception_internal(cpu_env, tcg_excp);
213 tcg_temp_free_i32(tcg_excp);
214 }
215
216 static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
217 {
218 TCGv_i32 tcg_excp = tcg_const_i32(excp);
219 TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
220 TCGv_i32 tcg_el = tcg_const_i32(target_el);
221
222 gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
223 tcg_syn, tcg_el);
224
225 tcg_temp_free_i32(tcg_el);
226 tcg_temp_free_i32(tcg_syn);
227 tcg_temp_free_i32(tcg_excp);
228 }
229
230 static void gen_ss_advance(DisasContext *s)
231 {
232 /* If the singlestep state is Active-not-pending, advance to
233 * Active-pending.
234 */
235 if (s->ss_active) {
236 s->pstate_ss = 0;
237 gen_helper_clear_pstate_ss(cpu_env);
238 }
239 }
240
241 static void gen_step_complete_exception(DisasContext *s)
242 {
243 /* We just completed step of an insn. Move from Active-not-pending
244 * to Active-pending, and then also take the swstep exception.
245 * This corresponds to making the (IMPDEF) choice to prioritize
246 * swstep exceptions over asynchronous exceptions taken to an exception
247 * level where debug is disabled. This choice has the advantage that
248 * we do not need to maintain internal state corresponding to the
249 * ISV/EX syndrome bits between completion of the step and generation
250 * of the exception, and our syndrome information is always correct.
251 */
252 gen_ss_advance(s);
253 gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),
254 default_exception_el(s));
255 s->is_jmp = DISAS_EXC;
256 }
257
258 static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
259 {
260 TCGv_i32 tmp1 = tcg_temp_new_i32();
261 TCGv_i32 tmp2 = tcg_temp_new_i32();
262 tcg_gen_ext16s_i32(tmp1, a);
263 tcg_gen_ext16s_i32(tmp2, b);
264 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
265 tcg_temp_free_i32(tmp2);
266 tcg_gen_sari_i32(a, a, 16);
267 tcg_gen_sari_i32(b, b, 16);
268 tcg_gen_mul_i32(b, b, a);
269 tcg_gen_mov_i32(a, tmp1);
270 tcg_temp_free_i32(tmp1);
271 }
272
273 /* Byteswap each halfword. */
274 static void gen_rev16(TCGv_i32 var)
275 {
276 TCGv_i32 tmp = tcg_temp_new_i32();
277 tcg_gen_shri_i32(tmp, var, 8);
278 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
279 tcg_gen_shli_i32(var, var, 8);
280 tcg_gen_andi_i32(var, var, 0xff00ff00);
281 tcg_gen_or_i32(var, var, tmp);
282 tcg_temp_free_i32(tmp);
283 }
284
285 /* Byteswap low halfword and sign extend. */
286 static void gen_revsh(TCGv_i32 var)
287 {
288 tcg_gen_ext16u_i32(var, var);
289 tcg_gen_bswap16_i32(var, var);
290 tcg_gen_ext16s_i32(var, var);
291 }
292
293 /* Unsigned bitfield extract. */
294 static void gen_ubfx(TCGv_i32 var, int shift, uint32_t mask)
295 {
296 if (shift)
297 tcg_gen_shri_i32(var, var, shift);
298 tcg_gen_andi_i32(var, var, mask);
299 }
300
301 /* Signed bitfield extract. */
302 static void gen_sbfx(TCGv_i32 var, int shift, int width)
303 {
304 uint32_t signbit;
305
306 if (shift)
307 tcg_gen_sari_i32(var, var, shift);
308 if (shift + width < 32) {
309 signbit = 1u << (width - 1);
310 tcg_gen_andi_i32(var, var, (1u << width) - 1);
311 tcg_gen_xori_i32(var, var, signbit);
312 tcg_gen_subi_i32(var, var, signbit);
313 }
314 }
315
316 /* Return (b << 32) + a. Mark inputs as dead */
317 static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv_i32 b)
318 {
319 TCGv_i64 tmp64 = tcg_temp_new_i64();
320
321 tcg_gen_extu_i32_i64(tmp64, b);
322 tcg_temp_free_i32(b);
323 tcg_gen_shli_i64(tmp64, tmp64, 32);
324 tcg_gen_add_i64(a, tmp64, a);
325
326 tcg_temp_free_i64(tmp64);
327 return a;
328 }
329
330 /* Return (b << 32) - a. Mark inputs as dead. */
331 static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv_i32 b)
332 {
333 TCGv_i64 tmp64 = tcg_temp_new_i64();
334
335 tcg_gen_extu_i32_i64(tmp64, b);
336 tcg_temp_free_i32(b);
337 tcg_gen_shli_i64(tmp64, tmp64, 32);
338 tcg_gen_sub_i64(a, tmp64, a);
339
340 tcg_temp_free_i64(tmp64);
341 return a;
342 }
343
344 /* 32x32->64 multiply. Marks inputs as dead. */
345 static TCGv_i64 gen_mulu_i64_i32(TCGv_i32 a, TCGv_i32 b)
346 {
347 TCGv_i32 lo = tcg_temp_new_i32();
348 TCGv_i32 hi = tcg_temp_new_i32();
349 TCGv_i64 ret;
350
351 tcg_gen_mulu2_i32(lo, hi, a, b);
352 tcg_temp_free_i32(a);
353 tcg_temp_free_i32(b);
354
355 ret = tcg_temp_new_i64();
356 tcg_gen_concat_i32_i64(ret, lo, hi);
357 tcg_temp_free_i32(lo);
358 tcg_temp_free_i32(hi);
359
360 return ret;
361 }
362
363 static TCGv_i64 gen_muls_i64_i32(TCGv_i32 a, TCGv_i32 b)
364 {
365 TCGv_i32 lo = tcg_temp_new_i32();
366 TCGv_i32 hi = tcg_temp_new_i32();
367 TCGv_i64 ret;
368
369 tcg_gen_muls2_i32(lo, hi, a, b);
370 tcg_temp_free_i32(a);
371 tcg_temp_free_i32(b);
372
373 ret = tcg_temp_new_i64();
374 tcg_gen_concat_i32_i64(ret, lo, hi);
375 tcg_temp_free_i32(lo);
376 tcg_temp_free_i32(hi);
377
378 return ret;
379 }
380
381 /* Swap low and high halfwords. */
382 static void gen_swap_half(TCGv_i32 var)
383 {
384 TCGv_i32 tmp = tcg_temp_new_i32();
385 tcg_gen_shri_i32(tmp, var, 16);
386 tcg_gen_shli_i32(var, var, 16);
387 tcg_gen_or_i32(var, var, tmp);
388 tcg_temp_free_i32(tmp);
389 }
390
391 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
392 tmp = (t0 ^ t1) & 0x8000;
393 t0 &= ~0x8000;
394 t1 &= ~0x8000;
395 t0 = (t0 + t1) ^ tmp;
396 */
397
398 static void gen_add16(TCGv_i32 t0, TCGv_i32 t1)
399 {
400 TCGv_i32 tmp = tcg_temp_new_i32();
401 tcg_gen_xor_i32(tmp, t0, t1);
402 tcg_gen_andi_i32(tmp, tmp, 0x8000);
403 tcg_gen_andi_i32(t0, t0, ~0x8000);
404 tcg_gen_andi_i32(t1, t1, ~0x8000);
405 tcg_gen_add_i32(t0, t0, t1);
406 tcg_gen_xor_i32(t0, t0, tmp);
407 tcg_temp_free_i32(tmp);
408 tcg_temp_free_i32(t1);
409 }
410
411 /* Set CF to the top bit of var. */
412 static void gen_set_CF_bit31(TCGv_i32 var)
413 {
414 tcg_gen_shri_i32(cpu_CF, var, 31);
415 }
416
417 /* Set N and Z flags from var. */
418 static inline void gen_logic_CC(TCGv_i32 var)
419 {
420 tcg_gen_mov_i32(cpu_NF, var);
421 tcg_gen_mov_i32(cpu_ZF, var);
422 }
423
424 /* T0 += T1 + CF. */
425 static void gen_adc(TCGv_i32 t0, TCGv_i32 t1)
426 {
427 tcg_gen_add_i32(t0, t0, t1);
428 tcg_gen_add_i32(t0, t0, cpu_CF);
429 }
430
431 /* dest = T0 + T1 + CF. */
432 static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
433 {
434 tcg_gen_add_i32(dest, t0, t1);
435 tcg_gen_add_i32(dest, dest, cpu_CF);
436 }
437
438 /* dest = T0 - T1 + CF - 1. */
439 static void gen_sub_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
440 {
441 tcg_gen_sub_i32(dest, t0, t1);
442 tcg_gen_add_i32(dest, dest, cpu_CF);
443 tcg_gen_subi_i32(dest, dest, 1);
444 }
445
446 /* dest = T0 + T1. Compute C, N, V and Z flags */
447 static void gen_add_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
448 {
449 TCGv_i32 tmp = tcg_temp_new_i32();
450 tcg_gen_movi_i32(tmp, 0);
451 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, t1, tmp);
452 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
453 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
454 tcg_gen_xor_i32(tmp, t0, t1);
455 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
456 tcg_temp_free_i32(tmp);
457 tcg_gen_mov_i32(dest, cpu_NF);
458 }
459
460 /* dest = T0 + T1 + CF. Compute C, N, V and Z flags */
461 static void gen_adc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
462 {
463 TCGv_i32 tmp = tcg_temp_new_i32();
464 if (TCG_TARGET_HAS_add2_i32) {
465 tcg_gen_movi_i32(tmp, 0);
466 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp);
467 tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp);
468 } else {
469 TCGv_i64 q0 = tcg_temp_new_i64();
470 TCGv_i64 q1 = tcg_temp_new_i64();
471 tcg_gen_extu_i32_i64(q0, t0);
472 tcg_gen_extu_i32_i64(q1, t1);
473 tcg_gen_add_i64(q0, q0, q1);
474 tcg_gen_extu_i32_i64(q1, cpu_CF);
475 tcg_gen_add_i64(q0, q0, q1);
476 tcg_gen_extr_i64_i32(cpu_NF, cpu_CF, q0);
477 tcg_temp_free_i64(q0);
478 tcg_temp_free_i64(q1);
479 }
480 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
481 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
482 tcg_gen_xor_i32(tmp, t0, t1);
483 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
484 tcg_temp_free_i32(tmp);
485 tcg_gen_mov_i32(dest, cpu_NF);
486 }
487
488 /* dest = T0 - T1. Compute C, N, V and Z flags */
489 static void gen_sub_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
490 {
491 TCGv_i32 tmp;
492 tcg_gen_sub_i32(cpu_NF, t0, t1);
493 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
494 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0, t1);
495 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
496 tmp = tcg_temp_new_i32();
497 tcg_gen_xor_i32(tmp, t0, t1);
498 tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
499 tcg_temp_free_i32(tmp);
500 tcg_gen_mov_i32(dest, cpu_NF);
501 }
502
503 /* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */
504 static void gen_sbc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
505 {
506 TCGv_i32 tmp = tcg_temp_new_i32();
507 tcg_gen_not_i32(tmp, t1);
508 gen_adc_CC(dest, t0, tmp);
509 tcg_temp_free_i32(tmp);
510 }
511
512 #define GEN_SHIFT(name) \
513 static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \
514 { \
515 TCGv_i32 tmp1, tmp2, tmp3; \
516 tmp1 = tcg_temp_new_i32(); \
517 tcg_gen_andi_i32(tmp1, t1, 0xff); \
518 tmp2 = tcg_const_i32(0); \
519 tmp3 = tcg_const_i32(0x1f); \
520 tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0); \
521 tcg_temp_free_i32(tmp3); \
522 tcg_gen_andi_i32(tmp1, tmp1, 0x1f); \
523 tcg_gen_##name##_i32(dest, tmp2, tmp1); \
524 tcg_temp_free_i32(tmp2); \
525 tcg_temp_free_i32(tmp1); \
526 }
527 GEN_SHIFT(shl)
528 GEN_SHIFT(shr)
529 #undef GEN_SHIFT
530
531 static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
532 {
533 TCGv_i32 tmp1, tmp2;
534 tmp1 = tcg_temp_new_i32();
535 tcg_gen_andi_i32(tmp1, t1, 0xff);
536 tmp2 = tcg_const_i32(0x1f);
537 tcg_gen_movcond_i32(TCG_COND_GTU, tmp1, tmp1, tmp2, tmp2, tmp1);
538 tcg_temp_free_i32(tmp2);
539 tcg_gen_sar_i32(dest, t0, tmp1);
540 tcg_temp_free_i32(tmp1);
541 }
542
543 static void tcg_gen_abs_i32(TCGv_i32 dest, TCGv_i32 src)
544 {
545 TCGv_i32 c0 = tcg_const_i32(0);
546 TCGv_i32 tmp = tcg_temp_new_i32();
547 tcg_gen_neg_i32(tmp, src);
548 tcg_gen_movcond_i32(TCG_COND_GT, dest, src, c0, src, tmp);
549 tcg_temp_free_i32(c0);
550 tcg_temp_free_i32(tmp);
551 }
552
553 static void shifter_out_im(TCGv_i32 var, int shift)
554 {
555 if (shift == 0) {
556 tcg_gen_andi_i32(cpu_CF, var, 1);
557 } else {
558 tcg_gen_shri_i32(cpu_CF, var, shift);
559 if (shift != 31) {
560 tcg_gen_andi_i32(cpu_CF, cpu_CF, 1);
561 }
562 }
563 }
564
565 /* Shift by immediate. Includes special handling for shift == 0. */
566 static inline void gen_arm_shift_im(TCGv_i32 var, int shiftop,
567 int shift, int flags)
568 {
569 switch (shiftop) {
570 case 0: /* LSL */
571 if (shift != 0) {
572 if (flags)
573 shifter_out_im(var, 32 - shift);
574 tcg_gen_shli_i32(var, var, shift);
575 }
576 break;
577 case 1: /* LSR */
578 if (shift == 0) {
579 if (flags) {
580 tcg_gen_shri_i32(cpu_CF, var, 31);
581 }
582 tcg_gen_movi_i32(var, 0);
583 } else {
584 if (flags)
585 shifter_out_im(var, shift - 1);
586 tcg_gen_shri_i32(var, var, shift);
587 }
588 break;
589 case 2: /* ASR */
590 if (shift == 0)
591 shift = 32;
592 if (flags)
593 shifter_out_im(var, shift - 1);
594 if (shift == 32)
595 shift = 31;
596 tcg_gen_sari_i32(var, var, shift);
597 break;
598 case 3: /* ROR/RRX */
599 if (shift != 0) {
600 if (flags)
601 shifter_out_im(var, shift - 1);
602 tcg_gen_rotri_i32(var, var, shift); break;
603 } else {
604 TCGv_i32 tmp = tcg_temp_new_i32();
605 tcg_gen_shli_i32(tmp, cpu_CF, 31);
606 if (flags)
607 shifter_out_im(var, 0);
608 tcg_gen_shri_i32(var, var, 1);
609 tcg_gen_or_i32(var, var, tmp);
610 tcg_temp_free_i32(tmp);
611 }
612 }
613 };
614
615 static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop,
616 TCGv_i32 shift, int flags)
617 {
618 if (flags) {
619 switch (shiftop) {
620 case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
621 case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
622 case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
623 case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
624 }
625 } else {
626 switch (shiftop) {
627 case 0:
628 gen_shl(var, var, shift);
629 break;
630 case 1:
631 gen_shr(var, var, shift);
632 break;
633 case 2:
634 gen_sar(var, var, shift);
635 break;
636 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
637 tcg_gen_rotr_i32(var, var, shift); break;
638 }
639 }
640 tcg_temp_free_i32(shift);
641 }
642
643 #define PAS_OP(pfx) \
644 switch (op2) { \
645 case 0: gen_pas_helper(glue(pfx,add16)); break; \
646 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
647 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
648 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
649 case 4: gen_pas_helper(glue(pfx,add8)); break; \
650 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
651 }
652 static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
653 {
654 TCGv_ptr tmp;
655
656 switch (op1) {
657 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
658 case 1:
659 tmp = tcg_temp_new_ptr();
660 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
661 PAS_OP(s)
662 tcg_temp_free_ptr(tmp);
663 break;
664 case 5:
665 tmp = tcg_temp_new_ptr();
666 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
667 PAS_OP(u)
668 tcg_temp_free_ptr(tmp);
669 break;
670 #undef gen_pas_helper
671 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
672 case 2:
673 PAS_OP(q);
674 break;
675 case 3:
676 PAS_OP(sh);
677 break;
678 case 6:
679 PAS_OP(uq);
680 break;
681 case 7:
682 PAS_OP(uh);
683 break;
684 #undef gen_pas_helper
685 }
686 }
687 #undef PAS_OP
688
689 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
690 #define PAS_OP(pfx) \
691 switch (op1) { \
692 case 0: gen_pas_helper(glue(pfx,add8)); break; \
693 case 1: gen_pas_helper(glue(pfx,add16)); break; \
694 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
695 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
696 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
697 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
698 }
699 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
700 {
701 TCGv_ptr tmp;
702
703 switch (op2) {
704 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
705 case 0:
706 tmp = tcg_temp_new_ptr();
707 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
708 PAS_OP(s)
709 tcg_temp_free_ptr(tmp);
710 break;
711 case 4:
712 tmp = tcg_temp_new_ptr();
713 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
714 PAS_OP(u)
715 tcg_temp_free_ptr(tmp);
716 break;
717 #undef gen_pas_helper
718 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
719 case 1:
720 PAS_OP(q);
721 break;
722 case 2:
723 PAS_OP(sh);
724 break;
725 case 5:
726 PAS_OP(uq);
727 break;
728 case 6:
729 PAS_OP(uh);
730 break;
731 #undef gen_pas_helper
732 }
733 }
734 #undef PAS_OP
735
736 /*
737 * Generate a conditional based on ARM condition code cc.
738 * This is common between ARM and Aarch64 targets.
739 */
740 void arm_test_cc(DisasCompare *cmp, int cc)
741 {
742 TCGv_i32 value;
743 TCGCond cond;
744 bool global = true;
745
746 switch (cc) {
747 case 0: /* eq: Z */
748 case 1: /* ne: !Z */
749 cond = TCG_COND_EQ;
750 value = cpu_ZF;
751 break;
752
753 case 2: /* cs: C */
754 case 3: /* cc: !C */
755 cond = TCG_COND_NE;
756 value = cpu_CF;
757 break;
758
759 case 4: /* mi: N */
760 case 5: /* pl: !N */
761 cond = TCG_COND_LT;
762 value = cpu_NF;
763 break;
764
765 case 6: /* vs: V */
766 case 7: /* vc: !V */
767 cond = TCG_COND_LT;
768 value = cpu_VF;
769 break;
770
771 case 8: /* hi: C && !Z */
772 case 9: /* ls: !C || Z -> !(C && !Z) */
773 cond = TCG_COND_NE;
774 value = tcg_temp_new_i32();
775 global = false;
776 /* CF is 1 for C, so -CF is an all-bits-set mask for C;
777 ZF is non-zero for !Z; so AND the two subexpressions. */
778 tcg_gen_neg_i32(value, cpu_CF);
779 tcg_gen_and_i32(value, value, cpu_ZF);
780 break;
781
782 case 10: /* ge: N == V -> N ^ V == 0 */
783 case 11: /* lt: N != V -> N ^ V != 0 */
784 /* Since we're only interested in the sign bit, == 0 is >= 0. */
785 cond = TCG_COND_GE;
786 value = tcg_temp_new_i32();
787 global = false;
788 tcg_gen_xor_i32(value, cpu_VF, cpu_NF);
789 break;
790
791 case 12: /* gt: !Z && N == V */
792 case 13: /* le: Z || N != V */
793 cond = TCG_COND_NE;
794 value = tcg_temp_new_i32();
795 global = false;
796 /* (N == V) is equal to the sign bit of ~(NF ^ VF). Propagate
797 * the sign bit then AND with ZF to yield the result. */
798 tcg_gen_xor_i32(value, cpu_VF, cpu_NF);
799 tcg_gen_sari_i32(value, value, 31);
800 tcg_gen_andc_i32(value, cpu_ZF, value);
801 break;
802
803 case 14: /* always */
804 case 15: /* always */
805 /* Use the ALWAYS condition, which will fold early.
806 * It doesn't matter what we use for the value. */
807 cond = TCG_COND_ALWAYS;
808 value = cpu_ZF;
809 goto no_invert;
810
811 default:
812 fprintf(stderr, "Bad condition code 0x%x\n", cc);
813 abort();
814 }
815
816 if (cc & 1) {
817 cond = tcg_invert_cond(cond);
818 }
819
820 no_invert:
821 cmp->cond = cond;
822 cmp->value = value;
823 cmp->value_global = global;
824 }
825
826 void arm_free_cc(DisasCompare *cmp)
827 {
828 if (!cmp->value_global) {
829 tcg_temp_free_i32(cmp->value);
830 }
831 }
832
833 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label)
834 {
835 tcg_gen_brcondi_i32(cmp->cond, cmp->value, 0, label);
836 }
837
838 void arm_gen_test_cc(int cc, TCGLabel *label)
839 {
840 DisasCompare cmp;
841 arm_test_cc(&cmp, cc);
842 arm_jump_cc(&cmp, label);
843 arm_free_cc(&cmp);
844 }
845
846 static const uint8_t table_logic_cc[16] = {
847 1, /* and */
848 1, /* xor */
849 0, /* sub */
850 0, /* rsb */
851 0, /* add */
852 0, /* adc */
853 0, /* sbc */
854 0, /* rsc */
855 1, /* andl */
856 1, /* xorl */
857 0, /* cmp */
858 0, /* cmn */
859 1, /* orr */
860 1, /* mov */
861 1, /* bic */
862 1, /* mvn */
863 };
864
865 /* Set PC and Thumb state from an immediate address. */
866 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
867 {
868 TCGv_i32 tmp;
869
870 s->is_jmp = DISAS_JUMP;
871 if (s->thumb != (addr & 1)) {
872 tmp = tcg_temp_new_i32();
873 tcg_gen_movi_i32(tmp, addr & 1);
874 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));
875 tcg_temp_free_i32(tmp);
876 }
877 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
878 }
879
880 /* Set PC and Thumb state from var. var is marked as dead. */
881 static inline void gen_bx(DisasContext *s, TCGv_i32 var)
882 {
883 s->is_jmp = DISAS_JUMP;
884 tcg_gen_andi_i32(cpu_R[15], var, ~1);
885 tcg_gen_andi_i32(var, var, 1);
886 store_cpu_field(var, thumb);
887 }
888
889 /* Variant of store_reg which uses branch&exchange logic when storing
890 to r15 in ARM architecture v7 and above. The source must be a temporary
891 and will be marked as dead. */
892 static inline void store_reg_bx(DisasContext *s, int reg, TCGv_i32 var)
893 {
894 if (reg == 15 && ENABLE_ARCH_7) {
895 gen_bx(s, var);
896 } else {
897 store_reg(s, reg, var);
898 }
899 }
900
901 /* Variant of store_reg which uses branch&exchange logic when storing
902 * to r15 in ARM architecture v5T and above. This is used for storing
903 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
904 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
905 static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
906 {
907 if (reg == 15 && ENABLE_ARCH_5) {
908 gen_bx(s, var);
909 } else {
910 store_reg(s, reg, var);
911 }
912 }
913
914 #ifdef CONFIG_USER_ONLY
915 #define IS_USER_ONLY 1
916 #else
917 #define IS_USER_ONLY 0
918 #endif
919
920 /* Abstractions of "generate code to do a guest load/store for
921 * AArch32", where a vaddr is always 32 bits (and is zero
922 * extended if we're a 64 bit core) and data is also
923 * 32 bits unless specifically doing a 64 bit access.
924 * These functions work like tcg_gen_qemu_{ld,st}* except
925 * that the address argument is TCGv_i32 rather than TCGv.
926 */
927 #if TARGET_LONG_BITS == 32
928
929 #define DO_GEN_LD(SUFF, OPC, BE32_XOR) \
930 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
931 TCGv_i32 addr, int index) \
932 { \
933 TCGMemOp opc = (OPC) | s->be_data; \
934 /* Not needed for user-mode BE32, where we use MO_BE instead. */ \
935 if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
936 TCGv addr_be = tcg_temp_new(); \
937 tcg_gen_xori_i32(addr_be, addr, BE32_XOR); \
938 tcg_gen_qemu_ld_i32(val, addr_be, index, opc); \
939 tcg_temp_free(addr_be); \
940 return; \
941 } \
942 tcg_gen_qemu_ld_i32(val, addr, index, opc); \
943 }
944
945 #define DO_GEN_ST(SUFF, OPC, BE32_XOR) \
946 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
947 TCGv_i32 addr, int index) \
948 { \
949 TCGMemOp opc = (OPC) | s->be_data; \
950 /* Not needed for user-mode BE32, where we use MO_BE instead. */ \
951 if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
952 TCGv addr_be = tcg_temp_new(); \
953 tcg_gen_xori_i32(addr_be, addr, BE32_XOR); \
954 tcg_gen_qemu_st_i32(val, addr_be, index, opc); \
955 tcg_temp_free(addr_be); \
956 return; \
957 } \
958 tcg_gen_qemu_st_i32(val, addr, index, opc); \
959 }
960
961 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
962 TCGv_i32 addr, int index)
963 {
964 TCGMemOp opc = MO_Q | s->be_data;
965 tcg_gen_qemu_ld_i64(val, addr, index, opc);
966 /* Not needed for user-mode BE32, where we use MO_BE instead. */
967 if (!IS_USER_ONLY && s->sctlr_b) {
968 tcg_gen_rotri_i64(val, val, 32);
969 }
970 }
971
972 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
973 TCGv_i32 addr, int index)
974 {
975 TCGMemOp opc = MO_Q | s->be_data;
976 /* Not needed for user-mode BE32, where we use MO_BE instead. */
977 if (!IS_USER_ONLY && s->sctlr_b) {
978 TCGv_i64 tmp = tcg_temp_new_i64();
979 tcg_gen_rotri_i64(tmp, val, 32);
980 tcg_gen_qemu_st_i64(tmp, addr, index, opc);
981 tcg_temp_free_i64(tmp);
982 return;
983 }
984 tcg_gen_qemu_st_i64(val, addr, index, opc);
985 }
986
987 #else
988
989 #define DO_GEN_LD(SUFF, OPC, BE32_XOR) \
990 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
991 TCGv_i32 addr, int index) \
992 { \
993 TCGMemOp opc = (OPC) | s->be_data; \
994 TCGv addr64 = tcg_temp_new(); \
995 tcg_gen_extu_i32_i64(addr64, addr); \
996 /* Not needed for user-mode BE32, where we use MO_BE instead. */ \
997 if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
998 tcg_gen_xori_i64(addr64, addr64, BE32_XOR); \
999 } \
1000 tcg_gen_qemu_ld_i32(val, addr64, index, opc); \
1001 tcg_temp_free(addr64); \
1002 }
1003
1004 #define DO_GEN_ST(SUFF, OPC, BE32_XOR) \
1005 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
1006 TCGv_i32 addr, int index) \
1007 { \
1008 TCGMemOp opc = (OPC) | s->be_data; \
1009 TCGv addr64 = tcg_temp_new(); \
1010 tcg_gen_extu_i32_i64(addr64, addr); \
1011 /* Not needed for user-mode BE32, where we use MO_BE instead. */ \
1012 if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
1013 tcg_gen_xori_i64(addr64, addr64, BE32_XOR); \
1014 } \
1015 tcg_gen_qemu_st_i32(val, addr64, index, opc); \
1016 tcg_temp_free(addr64); \
1017 }
1018
1019 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
1020 TCGv_i32 addr, int index)
1021 {
1022 TCGMemOp opc = MO_Q | s->be_data;
1023 TCGv addr64 = tcg_temp_new();
1024 tcg_gen_extu_i32_i64(addr64, addr);
1025 tcg_gen_qemu_ld_i64(val, addr64, index, opc);
1026
1027 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1028 if (!IS_USER_ONLY && s->sctlr_b) {
1029 tcg_gen_rotri_i64(val, val, 32);
1030 }
1031 tcg_temp_free(addr64);
1032 }
1033
1034 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
1035 TCGv_i32 addr, int index)
1036 {
1037 TCGMemOp opc = MO_Q | s->be_data;
1038 TCGv addr64 = tcg_temp_new();
1039 tcg_gen_extu_i32_i64(addr64, addr);
1040
1041 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1042 if (!IS_USER_ONLY && s->sctlr_b) {
1043 TCGv tmp = tcg_temp_new();
1044 tcg_gen_rotri_i64(tmp, val, 32);
1045 tcg_gen_qemu_st_i64(tmp, addr64, index, opc);
1046 tcg_temp_free(tmp);
1047 } else {
1048 tcg_gen_qemu_st_i64(val, addr64, index, opc);
1049 }
1050 tcg_temp_free(addr64);
1051 }
1052
1053 #endif
1054
1055 DO_GEN_LD(8s, MO_SB, 3)
1056 DO_GEN_LD(8u, MO_UB, 3)
1057 DO_GEN_LD(16s, MO_SW, 2)
1058 DO_GEN_LD(16u, MO_UW, 2)
1059 DO_GEN_LD(32u, MO_UL, 0)
1060 /* 'a' variants include an alignment check */
1061 DO_GEN_LD(16ua, MO_UW | MO_ALIGN, 2)
1062 DO_GEN_LD(32ua, MO_UL | MO_ALIGN, 0)
1063 DO_GEN_ST(8, MO_UB, 3)
1064 DO_GEN_ST(16, MO_UW, 2)
1065 DO_GEN_ST(32, MO_UL, 0)
1066
1067 static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
1068 {
1069 tcg_gen_movi_i32(cpu_R[15], val);
1070 }
1071
1072 static inline void gen_hvc(DisasContext *s, int imm16)
1073 {
1074 /* The pre HVC helper handles cases when HVC gets trapped
1075 * as an undefined insn by runtime configuration (ie before
1076 * the insn really executes).
1077 */
1078 gen_set_pc_im(s, s->pc - 4);
1079 gen_helper_pre_hvc(cpu_env);
1080 /* Otherwise we will treat this as a real exception which
1081 * happens after execution of the insn. (The distinction matters
1082 * for the PC value reported to the exception handler and also
1083 * for single stepping.)
1084 */
1085 s->svc_imm = imm16;
1086 gen_set_pc_im(s, s->pc);
1087 s->is_jmp = DISAS_HVC;
1088 }
1089
1090 static inline void gen_smc(DisasContext *s)
1091 {
1092 /* As with HVC, we may take an exception either before or after
1093 * the insn executes.
1094 */
1095 TCGv_i32 tmp;
1096
1097 gen_set_pc_im(s, s->pc - 4);
1098 tmp = tcg_const_i32(syn_aa32_smc());
1099 gen_helper_pre_smc(cpu_env, tmp);
1100 tcg_temp_free_i32(tmp);
1101 gen_set_pc_im(s, s->pc);
1102 s->is_jmp = DISAS_SMC;
1103 }
1104
1105 static inline void
1106 gen_set_condexec (DisasContext *s)
1107 {
1108 if (s->condexec_mask) {
1109 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
1110 TCGv_i32 tmp = tcg_temp_new_i32();
1111 tcg_gen_movi_i32(tmp, val);
1112 store_cpu_field(tmp, condexec_bits);
1113 }
1114 }
1115
1116 static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
1117 {
1118 gen_set_condexec(s);
1119 gen_set_pc_im(s, s->pc - offset);
1120 gen_exception_internal(excp);
1121 s->is_jmp = DISAS_JUMP;
1122 }
1123
1124 static void gen_exception_insn(DisasContext *s, int offset, int excp,
1125 int syn, uint32_t target_el)
1126 {
1127 gen_set_condexec(s);
1128 gen_set_pc_im(s, s->pc - offset);
1129 gen_exception(excp, syn, target_el);
1130 s->is_jmp = DISAS_JUMP;
1131 }
1132
1133 /* Force a TB lookup after an instruction that changes the CPU state. */
1134 static inline void gen_lookup_tb(DisasContext *s)
1135 {
1136 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
1137 s->is_jmp = DISAS_JUMP;
1138 }
1139
1140 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
1141 TCGv_i32 var)
1142 {
1143 int val, rm, shift, shiftop;
1144 TCGv_i32 offset;
1145
1146 if (!(insn & (1 << 25))) {
1147 /* immediate */
1148 val = insn & 0xfff;
1149 if (!(insn & (1 << 23)))
1150 val = -val;
1151 if (val != 0)
1152 tcg_gen_addi_i32(var, var, val);
1153 } else {
1154 /* shift/register */
1155 rm = (insn) & 0xf;
1156 shift = (insn >> 7) & 0x1f;
1157 shiftop = (insn >> 5) & 3;
1158 offset = load_reg(s, rm);
1159 gen_arm_shift_im(offset, shiftop, shift, 0);
1160 if (!(insn & (1 << 23)))
1161 tcg_gen_sub_i32(var, var, offset);
1162 else
1163 tcg_gen_add_i32(var, var, offset);
1164 tcg_temp_free_i32(offset);
1165 }
1166 }
1167
1168 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
1169 int extra, TCGv_i32 var)
1170 {
1171 int val, rm;
1172 TCGv_i32 offset;
1173
1174 if (insn & (1 << 22)) {
1175 /* immediate */
1176 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
1177 if (!(insn & (1 << 23)))
1178 val = -val;
1179 val += extra;
1180 if (val != 0)
1181 tcg_gen_addi_i32(var, var, val);
1182 } else {
1183 /* register */
1184 if (extra)
1185 tcg_gen_addi_i32(var, var, extra);
1186 rm = (insn) & 0xf;
1187 offset = load_reg(s, rm);
1188 if (!(insn & (1 << 23)))
1189 tcg_gen_sub_i32(var, var, offset);
1190 else
1191 tcg_gen_add_i32(var, var, offset);
1192 tcg_temp_free_i32(offset);
1193 }
1194 }
1195
1196 static TCGv_ptr get_fpstatus_ptr(int neon)
1197 {
1198 TCGv_ptr statusptr = tcg_temp_new_ptr();
1199 int offset;
1200 if (neon) {
1201 offset = offsetof(CPUARMState, vfp.standard_fp_status);
1202 } else {
1203 offset = offsetof(CPUARMState, vfp.fp_status);
1204 }
1205 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
1206 return statusptr;
1207 }
1208
1209 #define VFP_OP2(name) \
1210 static inline void gen_vfp_##name(int dp) \
1211 { \
1212 TCGv_ptr fpst = get_fpstatus_ptr(0); \
1213 if (dp) { \
1214 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, fpst); \
1215 } else { \
1216 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, fpst); \
1217 } \
1218 tcg_temp_free_ptr(fpst); \
1219 }
1220
1221 VFP_OP2(add)
1222 VFP_OP2(sub)
1223 VFP_OP2(mul)
1224 VFP_OP2(div)
1225
1226 #undef VFP_OP2
1227
1228 static inline void gen_vfp_F1_mul(int dp)
1229 {
1230 /* Like gen_vfp_mul() but put result in F1 */
1231 TCGv_ptr fpst = get_fpstatus_ptr(0);
1232 if (dp) {
1233 gen_helper_vfp_muld(cpu_F1d, cpu_F0d, cpu_F1d, fpst);
1234 } else {
1235 gen_helper_vfp_muls(cpu_F1s, cpu_F0s, cpu_F1s, fpst);
1236 }
1237 tcg_temp_free_ptr(fpst);
1238 }
1239
1240 static inline void gen_vfp_F1_neg(int dp)
1241 {
1242 /* Like gen_vfp_neg() but put result in F1 */
1243 if (dp) {
1244 gen_helper_vfp_negd(cpu_F1d, cpu_F0d);
1245 } else {
1246 gen_helper_vfp_negs(cpu_F1s, cpu_F0s);
1247 }
1248 }
1249
1250 static inline void gen_vfp_abs(int dp)
1251 {
1252 if (dp)
1253 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
1254 else
1255 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
1256 }
1257
1258 static inline void gen_vfp_neg(int dp)
1259 {
1260 if (dp)
1261 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
1262 else
1263 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
1264 }
1265
1266 static inline void gen_vfp_sqrt(int dp)
1267 {
1268 if (dp)
1269 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
1270 else
1271 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
1272 }
1273
1274 static inline void gen_vfp_cmp(int dp)
1275 {
1276 if (dp)
1277 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
1278 else
1279 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
1280 }
1281
1282 static inline void gen_vfp_cmpe(int dp)
1283 {
1284 if (dp)
1285 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
1286 else
1287 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
1288 }
1289
1290 static inline void gen_vfp_F1_ld0(int dp)
1291 {
1292 if (dp)
1293 tcg_gen_movi_i64(cpu_F1d, 0);
1294 else
1295 tcg_gen_movi_i32(cpu_F1s, 0);
1296 }
1297
1298 #define VFP_GEN_ITOF(name) \
1299 static inline void gen_vfp_##name(int dp, int neon) \
1300 { \
1301 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1302 if (dp) { \
1303 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0s, statusptr); \
1304 } else { \
1305 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1306 } \
1307 tcg_temp_free_ptr(statusptr); \
1308 }
1309
1310 VFP_GEN_ITOF(uito)
1311 VFP_GEN_ITOF(sito)
1312 #undef VFP_GEN_ITOF
1313
1314 #define VFP_GEN_FTOI(name) \
1315 static inline void gen_vfp_##name(int dp, int neon) \
1316 { \
1317 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1318 if (dp) { \
1319 gen_helper_vfp_##name##d(cpu_F0s, cpu_F0d, statusptr); \
1320 } else { \
1321 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1322 } \
1323 tcg_temp_free_ptr(statusptr); \
1324 }
1325
1326 VFP_GEN_FTOI(toui)
1327 VFP_GEN_FTOI(touiz)
1328 VFP_GEN_FTOI(tosi)
1329 VFP_GEN_FTOI(tosiz)
1330 #undef VFP_GEN_FTOI
1331
1332 #define VFP_GEN_FIX(name, round) \
1333 static inline void gen_vfp_##name(int dp, int shift, int neon) \
1334 { \
1335 TCGv_i32 tmp_shift = tcg_const_i32(shift); \
1336 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1337 if (dp) { \
1338 gen_helper_vfp_##name##d##round(cpu_F0d, cpu_F0d, tmp_shift, \
1339 statusptr); \
1340 } else { \
1341 gen_helper_vfp_##name##s##round(cpu_F0s, cpu_F0s, tmp_shift, \
1342 statusptr); \
1343 } \
1344 tcg_temp_free_i32(tmp_shift); \
1345 tcg_temp_free_ptr(statusptr); \
1346 }
1347 VFP_GEN_FIX(tosh, _round_to_zero)
1348 VFP_GEN_FIX(tosl, _round_to_zero)
1349 VFP_GEN_FIX(touh, _round_to_zero)
1350 VFP_GEN_FIX(toul, _round_to_zero)
1351 VFP_GEN_FIX(shto, )
1352 VFP_GEN_FIX(slto, )
1353 VFP_GEN_FIX(uhto, )
1354 VFP_GEN_FIX(ulto, )
1355 #undef VFP_GEN_FIX
1356
1357 static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr)
1358 {
1359 if (dp) {
1360 gen_aa32_ld64(s, cpu_F0d, addr, get_mem_index(s));
1361 } else {
1362 gen_aa32_ld32u(s, cpu_F0s, addr, get_mem_index(s));
1363 }
1364 }
1365
1366 static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr)
1367 {
1368 if (dp) {
1369 gen_aa32_st64(s, cpu_F0d, addr, get_mem_index(s));
1370 } else {
1371 gen_aa32_st32(s, cpu_F0s, addr, get_mem_index(s));
1372 }
1373 }
1374
1375 static inline long
1376 vfp_reg_offset (int dp, int reg)
1377 {
1378 if (dp)
1379 return offsetof(CPUARMState, vfp.regs[reg]);
1380 else if (reg & 1) {
1381 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1382 + offsetof(CPU_DoubleU, l.upper);
1383 } else {
1384 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1385 + offsetof(CPU_DoubleU, l.lower);
1386 }
1387 }
1388
1389 /* Return the offset of a 32-bit piece of a NEON register.
1390 zero is the least significant end of the register. */
1391 static inline long
1392 neon_reg_offset (int reg, int n)
1393 {
1394 int sreg;
1395 sreg = reg * 2 + n;
1396 return vfp_reg_offset(0, sreg);
1397 }
1398
1399 static TCGv_i32 neon_load_reg(int reg, int pass)
1400 {
1401 TCGv_i32 tmp = tcg_temp_new_i32();
1402 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1403 return tmp;
1404 }
1405
1406 static void neon_store_reg(int reg, int pass, TCGv_i32 var)
1407 {
1408 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1409 tcg_temp_free_i32(var);
1410 }
1411
1412 static inline void neon_load_reg64(TCGv_i64 var, int reg)
1413 {
1414 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1415 }
1416
1417 static inline void neon_store_reg64(TCGv_i64 var, int reg)
1418 {
1419 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1420 }
1421
1422 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1423 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1424 #define tcg_gen_st_f32 tcg_gen_st_i32
1425 #define tcg_gen_st_f64 tcg_gen_st_i64
1426
1427 static inline void gen_mov_F0_vreg(int dp, int reg)
1428 {
1429 if (dp)
1430 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1431 else
1432 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1433 }
1434
1435 static inline void gen_mov_F1_vreg(int dp, int reg)
1436 {
1437 if (dp)
1438 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1439 else
1440 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1441 }
1442
1443 static inline void gen_mov_vreg_F0(int dp, int reg)
1444 {
1445 if (dp)
1446 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1447 else
1448 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1449 }
1450
1451 #define ARM_CP_RW_BIT (1 << 20)
1452
1453 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
1454 {
1455 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
1456 }
1457
1458 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
1459 {
1460 tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
1461 }
1462
1463 static inline TCGv_i32 iwmmxt_load_creg(int reg)
1464 {
1465 TCGv_i32 var = tcg_temp_new_i32();
1466 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
1467 return var;
1468 }
1469
1470 static inline void iwmmxt_store_creg(int reg, TCGv_i32 var)
1471 {
1472 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
1473 tcg_temp_free_i32(var);
1474 }
1475
1476 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1477 {
1478 iwmmxt_store_reg(cpu_M0, rn);
1479 }
1480
1481 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1482 {
1483 iwmmxt_load_reg(cpu_M0, rn);
1484 }
1485
1486 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1487 {
1488 iwmmxt_load_reg(cpu_V1, rn);
1489 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1490 }
1491
1492 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1493 {
1494 iwmmxt_load_reg(cpu_V1, rn);
1495 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1496 }
1497
1498 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1499 {
1500 iwmmxt_load_reg(cpu_V1, rn);
1501 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1502 }
1503
1504 #define IWMMXT_OP(name) \
1505 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1506 { \
1507 iwmmxt_load_reg(cpu_V1, rn); \
1508 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1509 }
1510
1511 #define IWMMXT_OP_ENV(name) \
1512 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1513 { \
1514 iwmmxt_load_reg(cpu_V1, rn); \
1515 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1516 }
1517
1518 #define IWMMXT_OP_ENV_SIZE(name) \
1519 IWMMXT_OP_ENV(name##b) \
1520 IWMMXT_OP_ENV(name##w) \
1521 IWMMXT_OP_ENV(name##l)
1522
1523 #define IWMMXT_OP_ENV1(name) \
1524 static inline void gen_op_iwmmxt_##name##_M0(void) \
1525 { \
1526 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1527 }
1528
1529 IWMMXT_OP(maddsq)
1530 IWMMXT_OP(madduq)
1531 IWMMXT_OP(sadb)
1532 IWMMXT_OP(sadw)
1533 IWMMXT_OP(mulslw)
1534 IWMMXT_OP(mulshw)
1535 IWMMXT_OP(mululw)
1536 IWMMXT_OP(muluhw)
1537 IWMMXT_OP(macsw)
1538 IWMMXT_OP(macuw)
1539
1540 IWMMXT_OP_ENV_SIZE(unpackl)
1541 IWMMXT_OP_ENV_SIZE(unpackh)
1542
1543 IWMMXT_OP_ENV1(unpacklub)
1544 IWMMXT_OP_ENV1(unpackluw)
1545 IWMMXT_OP_ENV1(unpacklul)
1546 IWMMXT_OP_ENV1(unpackhub)
1547 IWMMXT_OP_ENV1(unpackhuw)
1548 IWMMXT_OP_ENV1(unpackhul)
1549 IWMMXT_OP_ENV1(unpacklsb)
1550 IWMMXT_OP_ENV1(unpacklsw)
1551 IWMMXT_OP_ENV1(unpacklsl)
1552 IWMMXT_OP_ENV1(unpackhsb)
1553 IWMMXT_OP_ENV1(unpackhsw)
1554 IWMMXT_OP_ENV1(unpackhsl)
1555
1556 IWMMXT_OP_ENV_SIZE(cmpeq)
1557 IWMMXT_OP_ENV_SIZE(cmpgtu)
1558 IWMMXT_OP_ENV_SIZE(cmpgts)
1559
1560 IWMMXT_OP_ENV_SIZE(mins)
1561 IWMMXT_OP_ENV_SIZE(minu)
1562 IWMMXT_OP_ENV_SIZE(maxs)
1563 IWMMXT_OP_ENV_SIZE(maxu)
1564
1565 IWMMXT_OP_ENV_SIZE(subn)
1566 IWMMXT_OP_ENV_SIZE(addn)
1567 IWMMXT_OP_ENV_SIZE(subu)
1568 IWMMXT_OP_ENV_SIZE(addu)
1569 IWMMXT_OP_ENV_SIZE(subs)
1570 IWMMXT_OP_ENV_SIZE(adds)
1571
1572 IWMMXT_OP_ENV(avgb0)
1573 IWMMXT_OP_ENV(avgb1)
1574 IWMMXT_OP_ENV(avgw0)
1575 IWMMXT_OP_ENV(avgw1)
1576
1577 IWMMXT_OP_ENV(packuw)
1578 IWMMXT_OP_ENV(packul)
1579 IWMMXT_OP_ENV(packuq)
1580 IWMMXT_OP_ENV(packsw)
1581 IWMMXT_OP_ENV(packsl)
1582 IWMMXT_OP_ENV(packsq)
1583
1584 static void gen_op_iwmmxt_set_mup(void)
1585 {
1586 TCGv_i32 tmp;
1587 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1588 tcg_gen_ori_i32(tmp, tmp, 2);
1589 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1590 }
1591
1592 static void gen_op_iwmmxt_set_cup(void)
1593 {
1594 TCGv_i32 tmp;
1595 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1596 tcg_gen_ori_i32(tmp, tmp, 1);
1597 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1598 }
1599
1600 static void gen_op_iwmmxt_setpsr_nz(void)
1601 {
1602 TCGv_i32 tmp = tcg_temp_new_i32();
1603 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1604 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1605 }
1606
1607 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1608 {
1609 iwmmxt_load_reg(cpu_V1, rn);
1610 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
1611 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1612 }
1613
1614 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn,
1615 TCGv_i32 dest)
1616 {
1617 int rd;
1618 uint32_t offset;
1619 TCGv_i32 tmp;
1620
1621 rd = (insn >> 16) & 0xf;
1622 tmp = load_reg(s, rd);
1623
1624 offset = (insn & 0xff) << ((insn >> 7) & 2);
1625 if (insn & (1 << 24)) {
1626 /* Pre indexed */
1627 if (insn & (1 << 23))
1628 tcg_gen_addi_i32(tmp, tmp, offset);
1629 else
1630 tcg_gen_addi_i32(tmp, tmp, -offset);
1631 tcg_gen_mov_i32(dest, tmp);
1632 if (insn & (1 << 21))
1633 store_reg(s, rd, tmp);
1634 else
1635 tcg_temp_free_i32(tmp);
1636 } else if (insn & (1 << 21)) {
1637 /* Post indexed */
1638 tcg_gen_mov_i32(dest, tmp);
1639 if (insn & (1 << 23))
1640 tcg_gen_addi_i32(tmp, tmp, offset);
1641 else
1642 tcg_gen_addi_i32(tmp, tmp, -offset);
1643 store_reg(s, rd, tmp);
1644 } else if (!(insn & (1 << 23)))
1645 return 1;
1646 return 0;
1647 }
1648
1649 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 dest)
1650 {
1651 int rd = (insn >> 0) & 0xf;
1652 TCGv_i32 tmp;
1653
1654 if (insn & (1 << 8)) {
1655 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
1656 return 1;
1657 } else {
1658 tmp = iwmmxt_load_creg(rd);
1659 }
1660 } else {
1661 tmp = tcg_temp_new_i32();
1662 iwmmxt_load_reg(cpu_V0, rd);
1663 tcg_gen_extrl_i64_i32(tmp, cpu_V0);
1664 }
1665 tcg_gen_andi_i32(tmp, tmp, mask);
1666 tcg_gen_mov_i32(dest, tmp);
1667 tcg_temp_free_i32(tmp);
1668 return 0;
1669 }
1670
1671 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
1672 (ie. an undefined instruction). */
1673 static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
1674 {
1675 int rd, wrd;
1676 int rdhi, rdlo, rd0, rd1, i;
1677 TCGv_i32 addr;
1678 TCGv_i32 tmp, tmp2, tmp3;
1679
1680 if ((insn & 0x0e000e00) == 0x0c000000) {
1681 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1682 wrd = insn & 0xf;
1683 rdlo = (insn >> 12) & 0xf;
1684 rdhi = (insn >> 16) & 0xf;
1685 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1686 iwmmxt_load_reg(cpu_V0, wrd);
1687 tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
1688 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1689 tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);
1690 } else { /* TMCRR */
1691 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1692 iwmmxt_store_reg(cpu_V0, wrd);
1693 gen_op_iwmmxt_set_mup();
1694 }
1695 return 0;
1696 }
1697
1698 wrd = (insn >> 12) & 0xf;
1699 addr = tcg_temp_new_i32();
1700 if (gen_iwmmxt_address(s, insn, addr)) {
1701 tcg_temp_free_i32(addr);
1702 return 1;
1703 }
1704 if (insn & ARM_CP_RW_BIT) {
1705 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1706 tmp = tcg_temp_new_i32();
1707 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
1708 iwmmxt_store_creg(wrd, tmp);
1709 } else {
1710 i = 1;
1711 if (insn & (1 << 8)) {
1712 if (insn & (1 << 22)) { /* WLDRD */
1713 gen_aa32_ld64(s, cpu_M0, addr, get_mem_index(s));
1714 i = 0;
1715 } else { /* WLDRW wRd */
1716 tmp = tcg_temp_new_i32();
1717 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
1718 }
1719 } else {
1720 tmp = tcg_temp_new_i32();
1721 if (insn & (1 << 22)) { /* WLDRH */
1722 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
1723 } else { /* WLDRB */
1724 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
1725 }
1726 }
1727 if (i) {
1728 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1729 tcg_temp_free_i32(tmp);
1730 }
1731 gen_op_iwmmxt_movq_wRn_M0(wrd);
1732 }
1733 } else {
1734 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1735 tmp = iwmmxt_load_creg(wrd);
1736 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
1737 } else {
1738 gen_op_iwmmxt_movq_M0_wRn(wrd);
1739 tmp = tcg_temp_new_i32();
1740 if (insn & (1 << 8)) {
1741 if (insn & (1 << 22)) { /* WSTRD */
1742 gen_aa32_st64(s, cpu_M0, addr, get_mem_index(s));
1743 } else { /* WSTRW wRd */
1744 tcg_gen_extrl_i64_i32(tmp, cpu_M0);
1745 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
1746 }
1747 } else {
1748 if (insn & (1 << 22)) { /* WSTRH */
1749 tcg_gen_extrl_i64_i32(tmp, cpu_M0);
1750 gen_aa32_st16(s, tmp, addr, get_mem_index(s));
1751 } else { /* WSTRB */
1752 tcg_gen_extrl_i64_i32(tmp, cpu_M0);
1753 gen_aa32_st8(s, tmp, addr, get_mem_index(s));
1754 }
1755 }
1756 }
1757 tcg_temp_free_i32(tmp);
1758 }
1759 tcg_temp_free_i32(addr);
1760 return 0;
1761 }
1762
1763 if ((insn & 0x0f000000) != 0x0e000000)
1764 return 1;
1765
1766 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1767 case 0x000: /* WOR */
1768 wrd = (insn >> 12) & 0xf;
1769 rd0 = (insn >> 0) & 0xf;
1770 rd1 = (insn >> 16) & 0xf;
1771 gen_op_iwmmxt_movq_M0_wRn(rd0);
1772 gen_op_iwmmxt_orq_M0_wRn(rd1);
1773 gen_op_iwmmxt_setpsr_nz();
1774 gen_op_iwmmxt_movq_wRn_M0(wrd);
1775 gen_op_iwmmxt_set_mup();
1776 gen_op_iwmmxt_set_cup();
1777 break;
1778 case 0x011: /* TMCR */
1779 if (insn & 0xf)
1780 return 1;
1781 rd = (insn >> 12) & 0xf;
1782 wrd = (insn >> 16) & 0xf;
1783 switch (wrd) {
1784 case ARM_IWMMXT_wCID:
1785 case ARM_IWMMXT_wCASF:
1786 break;
1787 case ARM_IWMMXT_wCon:
1788 gen_op_iwmmxt_set_cup();
1789 /* Fall through. */
1790 case ARM_IWMMXT_wCSSF:
1791 tmp = iwmmxt_load_creg(wrd);
1792 tmp2 = load_reg(s, rd);
1793 tcg_gen_andc_i32(tmp, tmp, tmp2);
1794 tcg_temp_free_i32(tmp2);
1795 iwmmxt_store_creg(wrd, tmp);
1796 break;
1797 case ARM_IWMMXT_wCGR0:
1798 case ARM_IWMMXT_wCGR1:
1799 case ARM_IWMMXT_wCGR2:
1800 case ARM_IWMMXT_wCGR3:
1801 gen_op_iwmmxt_set_cup();
1802 tmp = load_reg(s, rd);
1803 iwmmxt_store_creg(wrd, tmp);
1804 break;
1805 default:
1806 return 1;
1807 }
1808 break;
1809 case 0x100: /* WXOR */
1810 wrd = (insn >> 12) & 0xf;
1811 rd0 = (insn >> 0) & 0xf;
1812 rd1 = (insn >> 16) & 0xf;
1813 gen_op_iwmmxt_movq_M0_wRn(rd0);
1814 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1815 gen_op_iwmmxt_setpsr_nz();
1816 gen_op_iwmmxt_movq_wRn_M0(wrd);
1817 gen_op_iwmmxt_set_mup();
1818 gen_op_iwmmxt_set_cup();
1819 break;
1820 case 0x111: /* TMRC */
1821 if (insn & 0xf)
1822 return 1;
1823 rd = (insn >> 12) & 0xf;
1824 wrd = (insn >> 16) & 0xf;
1825 tmp = iwmmxt_load_creg(wrd);
1826 store_reg(s, rd, tmp);
1827 break;
1828 case 0x300: /* WANDN */
1829 wrd = (insn >> 12) & 0xf;
1830 rd0 = (insn >> 0) & 0xf;
1831 rd1 = (insn >> 16) & 0xf;
1832 gen_op_iwmmxt_movq_M0_wRn(rd0);
1833 tcg_gen_neg_i64(cpu_M0, cpu_M0);
1834 gen_op_iwmmxt_andq_M0_wRn(rd1);
1835 gen_op_iwmmxt_setpsr_nz();
1836 gen_op_iwmmxt_movq_wRn_M0(wrd);
1837 gen_op_iwmmxt_set_mup();
1838 gen_op_iwmmxt_set_cup();
1839 break;
1840 case 0x200: /* WAND */
1841 wrd = (insn >> 12) & 0xf;
1842 rd0 = (insn >> 0) & 0xf;
1843 rd1 = (insn >> 16) & 0xf;
1844 gen_op_iwmmxt_movq_M0_wRn(rd0);
1845 gen_op_iwmmxt_andq_M0_wRn(rd1);
1846 gen_op_iwmmxt_setpsr_nz();
1847 gen_op_iwmmxt_movq_wRn_M0(wrd);
1848 gen_op_iwmmxt_set_mup();
1849 gen_op_iwmmxt_set_cup();
1850 break;
1851 case 0x810: case 0xa10: /* WMADD */
1852 wrd = (insn >> 12) & 0xf;
1853 rd0 = (insn >> 0) & 0xf;
1854 rd1 = (insn >> 16) & 0xf;
1855 gen_op_iwmmxt_movq_M0_wRn(rd0);
1856 if (insn & (1 << 21))
1857 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1858 else
1859 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1860 gen_op_iwmmxt_movq_wRn_M0(wrd);
1861 gen_op_iwmmxt_set_mup();
1862 break;
1863 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1864 wrd = (insn >> 12) & 0xf;
1865 rd0 = (insn >> 16) & 0xf;
1866 rd1 = (insn >> 0) & 0xf;
1867 gen_op_iwmmxt_movq_M0_wRn(rd0);
1868 switch ((insn >> 22) & 3) {
1869 case 0:
1870 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1871 break;
1872 case 1:
1873 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1874 break;
1875 case 2:
1876 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1877 break;
1878 case 3:
1879 return 1;
1880 }
1881 gen_op_iwmmxt_movq_wRn_M0(wrd);
1882 gen_op_iwmmxt_set_mup();
1883 gen_op_iwmmxt_set_cup();
1884 break;
1885 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1886 wrd = (insn >> 12) & 0xf;
1887 rd0 = (insn >> 16) & 0xf;
1888 rd1 = (insn >> 0) & 0xf;
1889 gen_op_iwmmxt_movq_M0_wRn(rd0);
1890 switch ((insn >> 22) & 3) {
1891 case 0:
1892 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1893 break;
1894 case 1:
1895 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1896 break;
1897 case 2:
1898 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1899 break;
1900 case 3:
1901 return 1;
1902 }
1903 gen_op_iwmmxt_movq_wRn_M0(wrd);
1904 gen_op_iwmmxt_set_mup();
1905 gen_op_iwmmxt_set_cup();
1906 break;
1907 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1908 wrd = (insn >> 12) & 0xf;
1909 rd0 = (insn >> 16) & 0xf;
1910 rd1 = (insn >> 0) & 0xf;
1911 gen_op_iwmmxt_movq_M0_wRn(rd0);
1912 if (insn & (1 << 22))
1913 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1914 else
1915 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1916 if (!(insn & (1 << 20)))
1917 gen_op_iwmmxt_addl_M0_wRn(wrd);
1918 gen_op_iwmmxt_movq_wRn_M0(wrd);
1919 gen_op_iwmmxt_set_mup();
1920 break;
1921 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1922 wrd = (insn >> 12) & 0xf;
1923 rd0 = (insn >> 16) & 0xf;
1924 rd1 = (insn >> 0) & 0xf;
1925 gen_op_iwmmxt_movq_M0_wRn(rd0);
1926 if (insn & (1 << 21)) {
1927 if (insn & (1 << 20))
1928 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1929 else
1930 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1931 } else {
1932 if (insn & (1 << 20))
1933 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1934 else
1935 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1936 }
1937 gen_op_iwmmxt_movq_wRn_M0(wrd);
1938 gen_op_iwmmxt_set_mup();
1939 break;
1940 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1941 wrd = (insn >> 12) & 0xf;
1942 rd0 = (insn >> 16) & 0xf;
1943 rd1 = (insn >> 0) & 0xf;
1944 gen_op_iwmmxt_movq_M0_wRn(rd0);
1945 if (insn & (1 << 21))
1946 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1947 else
1948 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1949 if (!(insn & (1 << 20))) {
1950 iwmmxt_load_reg(cpu_V1, wrd);
1951 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1952 }
1953 gen_op_iwmmxt_movq_wRn_M0(wrd);
1954 gen_op_iwmmxt_set_mup();
1955 break;
1956 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1957 wrd = (insn >> 12) & 0xf;
1958 rd0 = (insn >> 16) & 0xf;
1959 rd1 = (insn >> 0) & 0xf;
1960 gen_op_iwmmxt_movq_M0_wRn(rd0);
1961 switch ((insn >> 22) & 3) {
1962 case 0:
1963 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1964 break;
1965 case 1:
1966 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1967 break;
1968 case 2:
1969 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1970 break;
1971 case 3:
1972 return 1;
1973 }
1974 gen_op_iwmmxt_movq_wRn_M0(wrd);
1975 gen_op_iwmmxt_set_mup();
1976 gen_op_iwmmxt_set_cup();
1977 break;
1978 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1979 wrd = (insn >> 12) & 0xf;
1980 rd0 = (insn >> 16) & 0xf;
1981 rd1 = (insn >> 0) & 0xf;
1982 gen_op_iwmmxt_movq_M0_wRn(rd0);
1983 if (insn & (1 << 22)) {
1984 if (insn & (1 << 20))
1985 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1986 else
1987 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1988 } else {
1989 if (insn & (1 << 20))
1990 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1991 else
1992 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1993 }
1994 gen_op_iwmmxt_movq_wRn_M0(wrd);
1995 gen_op_iwmmxt_set_mup();
1996 gen_op_iwmmxt_set_cup();
1997 break;
1998 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1999 wrd = (insn >> 12) & 0xf;
2000 rd0 = (insn >> 16) & 0xf;
2001 rd1 = (insn >> 0) & 0xf;
2002 gen_op_iwmmxt_movq_M0_wRn(rd0);
2003 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
2004 tcg_gen_andi_i32(tmp, tmp, 7);
2005 iwmmxt_load_reg(cpu_V1, rd1);
2006 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2007 tcg_temp_free_i32(tmp);
2008 gen_op_iwmmxt_movq_wRn_M0(wrd);
2009 gen_op_iwmmxt_set_mup();
2010 break;
2011 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
2012 if (((insn >> 6) & 3) == 3)
2013 return 1;
2014 rd = (insn >> 12) & 0xf;
2015 wrd = (insn >> 16) & 0xf;
2016 tmp = load_reg(s, rd);
2017 gen_op_iwmmxt_movq_M0_wRn(wrd);
2018 switch ((insn >> 6) & 3) {
2019 case 0:
2020 tmp2 = tcg_const_i32(0xff);
2021 tmp3 = tcg_const_i32((insn & 7) << 3);
2022 break;
2023 case 1:
2024 tmp2 = tcg_const_i32(0xffff);
2025 tmp3 = tcg_const_i32((insn & 3) << 4);
2026 break;
2027 case 2:
2028 tmp2 = tcg_const_i32(0xffffffff);
2029 tmp3 = tcg_const_i32((insn & 1) << 5);
2030 break;
2031 default:
2032 TCGV_UNUSED_I32(tmp2);
2033 TCGV_UNUSED_I32(tmp3);
2034 }
2035 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
2036 tcg_temp_free_i32(tmp3);
2037 tcg_temp_free_i32(tmp2);
2038 tcg_temp_free_i32(tmp);
2039 gen_op_iwmmxt_movq_wRn_M0(wrd);
2040 gen_op_iwmmxt_set_mup();
2041 break;
2042 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
2043 rd = (insn >> 12) & 0xf;
2044 wrd = (insn >> 16) & 0xf;
2045 if (rd == 15 || ((insn >> 22) & 3) == 3)
2046 return 1;
2047 gen_op_iwmmxt_movq_M0_wRn(wrd);
2048 tmp = tcg_temp_new_i32();
2049 switch ((insn >> 22) & 3) {
2050 case 0:
2051 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
2052 tcg_gen_extrl_i64_i32(tmp, cpu_M0);
2053 if (insn & 8) {
2054 tcg_gen_ext8s_i32(tmp, tmp);
2055 } else {
2056 tcg_gen_andi_i32(tmp, tmp, 0xff);
2057 }
2058 break;
2059 case 1:
2060 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
2061 tcg_gen_extrl_i64_i32(tmp, cpu_M0);
2062 if (insn & 8) {
2063 tcg_gen_ext16s_i32(tmp, tmp);
2064 } else {
2065 tcg_gen_andi_i32(tmp, tmp, 0xffff);
2066 }
2067 break;
2068 case 2:
2069 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
2070 tcg_gen_extrl_i64_i32(tmp, cpu_M0);
2071 break;
2072 }
2073 store_reg(s, rd, tmp);
2074 break;
2075 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
2076 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
2077 return 1;
2078 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
2079 switch ((insn >> 22) & 3) {
2080 case 0:
2081 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
2082 break;
2083 case 1:
2084 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
2085 break;
2086 case 2:
2087 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
2088 break;
2089 }
2090 tcg_gen_shli_i32(tmp, tmp, 28);
2091 gen_set_nzcv(tmp);
2092 tcg_temp_free_i32(tmp);
2093 break;
2094 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
2095 if (((insn >> 6) & 3) == 3)
2096 return 1;
2097 rd = (insn >> 12) & 0xf;
2098 wrd = (insn >> 16) & 0xf;
2099 tmp = load_reg(s, rd);
2100 switch ((insn >> 6) & 3) {
2101 case 0:
2102 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
2103 break;
2104 case 1:
2105 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
2106 break;
2107 case 2:
2108 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
2109 break;
2110 }
2111 tcg_temp_free_i32(tmp);
2112 gen_op_iwmmxt_movq_wRn_M0(wrd);
2113 gen_op_iwmmxt_set_mup();
2114 break;
2115 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
2116 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
2117 return 1;
2118 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
2119 tmp2 = tcg_temp_new_i32();
2120 tcg_gen_mov_i32(tmp2, tmp);
2121 switch ((insn >> 22) & 3) {
2122 case 0:
2123 for (i = 0; i < 7; i ++) {
2124 tcg_gen_shli_i32(tmp2, tmp2, 4);
2125 tcg_gen_and_i32(tmp, tmp, tmp2);
2126 }
2127 break;
2128 case 1:
2129 for (i = 0; i < 3; i ++) {
2130 tcg_gen_shli_i32(tmp2, tmp2, 8);
2131 tcg_gen_and_i32(tmp, tmp, tmp2);
2132 }
2133 break;
2134 case 2:
2135 tcg_gen_shli_i32(tmp2, tmp2, 16);
2136 tcg_gen_and_i32(tmp, tmp, tmp2);
2137 break;
2138 }
2139 gen_set_nzcv(tmp);
2140 tcg_temp_free_i32(tmp2);
2141 tcg_temp_free_i32(tmp);
2142 break;
2143 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
2144 wrd = (insn >> 12) & 0xf;
2145 rd0 = (insn >> 16) & 0xf;
2146 gen_op_iwmmxt_movq_M0_wRn(rd0);
2147 switch ((insn >> 22) & 3) {
2148 case 0:
2149 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
2150 break;
2151 case 1:
2152 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
2153 break;
2154 case 2:
2155 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
2156 break;
2157 case 3:
2158 return 1;
2159 }
2160 gen_op_iwmmxt_movq_wRn_M0(wrd);
2161 gen_op_iwmmxt_set_mup();
2162 break;
2163 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
2164 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
2165 return 1;
2166 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
2167 tmp2 = tcg_temp_new_i32();
2168 tcg_gen_mov_i32(tmp2, tmp);
2169 switch ((insn >> 22) & 3) {
2170 case 0:
2171 for (i = 0; i < 7; i ++) {
2172 tcg_gen_shli_i32(tmp2, tmp2, 4);
2173 tcg_gen_or_i32(tmp, tmp, tmp2);
2174 }
2175 break;
2176 case 1:
2177 for (i = 0; i < 3; i ++) {
2178 tcg_gen_shli_i32(tmp2, tmp2, 8);
2179 tcg_gen_or_i32(tmp, tmp, tmp2);
2180 }
2181 break;
2182 case 2:
2183 tcg_gen_shli_i32(tmp2, tmp2, 16);
2184 tcg_gen_or_i32(tmp, tmp, tmp2);
2185 break;
2186 }
2187 gen_set_nzcv(tmp);
2188 tcg_temp_free_i32(tmp2);
2189 tcg_temp_free_i32(tmp);
2190 break;
2191 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
2192 rd = (insn >> 12) & 0xf;
2193 rd0 = (insn >> 16) & 0xf;
2194 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
2195 return 1;
2196 gen_op_iwmmxt_movq_M0_wRn(rd0);
2197 tmp = tcg_temp_new_i32();
2198 switch ((insn >> 22) & 3) {
2199 case 0:
2200 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
2201 break;
2202 case 1:
2203 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
2204 break;
2205 case 2:
2206 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
2207 break;
2208 }
2209 store_reg(s, rd, tmp);
2210 break;
2211 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
2212 case 0x906: case 0xb06: case 0xd06: case 0xf06:
2213 wrd = (insn >> 12) & 0xf;
2214 rd0 = (insn >> 16) & 0xf;
2215 rd1 = (insn >> 0) & 0xf;
2216 gen_op_iwmmxt_movq_M0_wRn(rd0);
2217 switch ((insn >> 22) & 3) {
2218 case 0:
2219 if (insn & (1 << 21))
2220 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
2221 else
2222 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
2223 break;
2224 case 1:
2225 if (insn & (1 << 21))
2226 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
2227 else
2228 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
2229 break;
2230 case 2:
2231 if (insn & (1 << 21))
2232 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
2233 else
2234 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
2235 break;
2236 case 3:
2237 return 1;
2238 }
2239 gen_op_iwmmxt_movq_wRn_M0(wrd);
2240 gen_op_iwmmxt_set_mup();
2241 gen_op_iwmmxt_set_cup();
2242 break;
2243 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2244 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2245 wrd = (insn >> 12) & 0xf;
2246 rd0 = (insn >> 16) & 0xf;
2247 gen_op_iwmmxt_movq_M0_wRn(rd0);
2248 switch ((insn >> 22) & 3) {
2249 case 0:
2250 if (insn & (1 << 21))
2251 gen_op_iwmmxt_unpacklsb_M0();
2252 else
2253 gen_op_iwmmxt_unpacklub_M0();
2254 break;
2255 case 1:
2256 if (insn & (1 << 21))
2257 gen_op_iwmmxt_unpacklsw_M0();
2258 else
2259 gen_op_iwmmxt_unpackluw_M0();
2260 break;
2261 case 2:
2262 if (insn & (1 << 21))
2263 gen_op_iwmmxt_unpacklsl_M0();
2264 else
2265 gen_op_iwmmxt_unpacklul_M0();
2266 break;
2267 case 3:
2268 return 1;
2269 }
2270 gen_op_iwmmxt_movq_wRn_M0(wrd);
2271 gen_op_iwmmxt_set_mup();
2272 gen_op_iwmmxt_set_cup();
2273 break;
2274 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2275 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2276 wrd = (insn >> 12) & 0xf;
2277 rd0 = (insn >> 16) & 0xf;
2278 gen_op_iwmmxt_movq_M0_wRn(rd0);
2279 switch ((insn >> 22) & 3) {
2280 case 0:
2281 if (insn & (1 << 21))
2282 gen_op_iwmmxt_unpackhsb_M0();
2283 else
2284 gen_op_iwmmxt_unpackhub_M0();
2285 break;
2286 case 1:
2287 if (insn & (1 << 21))
2288 gen_op_iwmmxt_unpackhsw_M0();
2289 else
2290 gen_op_iwmmxt_unpackhuw_M0();
2291 break;
2292 case 2:
2293 if (insn & (1 << 21))
2294 gen_op_iwmmxt_unpackhsl_M0();
2295 else
2296 gen_op_iwmmxt_unpackhul_M0();
2297 break;
2298 case 3:
2299 return 1;
2300 }
2301 gen_op_iwmmxt_movq_wRn_M0(wrd);
2302 gen_op_iwmmxt_set_mup();
2303 gen_op_iwmmxt_set_cup();
2304 break;
2305 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2306 case 0x214: case 0x614: case 0xa14: case 0xe14:
2307 if (((insn >> 22) & 3) == 0)
2308 return 1;
2309 wrd = (insn >> 12) & 0xf;
2310 rd0 = (insn >> 16) & 0xf;
2311 gen_op_iwmmxt_movq_M0_wRn(rd0);
2312 tmp = tcg_temp_new_i32();
2313 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2314 tcg_temp_free_i32(tmp);
2315 return 1;
2316 }
2317 switch ((insn >> 22) & 3) {
2318 case 1:
2319 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
2320 break;
2321 case 2:
2322 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
2323 break;
2324 case 3:
2325 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
2326 break;
2327 }
2328 tcg_temp_free_i32(tmp);
2329 gen_op_iwmmxt_movq_wRn_M0(wrd);
2330 gen_op_iwmmxt_set_mup();
2331 gen_op_iwmmxt_set_cup();
2332 break;
2333 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2334 case 0x014: case 0x414: case 0x814: case 0xc14:
2335 if (((insn >> 22) & 3) == 0)
2336 return 1;
2337 wrd = (insn >> 12) & 0xf;
2338 rd0 = (insn >> 16) & 0xf;
2339 gen_op_iwmmxt_movq_M0_wRn(rd0);
2340 tmp = tcg_temp_new_i32();
2341 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2342 tcg_temp_free_i32(tmp);
2343 return 1;
2344 }
2345 switch ((insn >> 22) & 3) {
2346 case 1:
2347 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
2348 break;
2349 case 2:
2350 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
2351 break;
2352 case 3:
2353 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
2354 break;
2355 }
2356 tcg_temp_free_i32(tmp);
2357 gen_op_iwmmxt_movq_wRn_M0(wrd);
2358 gen_op_iwmmxt_set_mup();
2359 gen_op_iwmmxt_set_cup();
2360 break;
2361 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2362 case 0x114: case 0x514: case 0x914: case 0xd14:
2363 if (((insn >> 22) & 3) == 0)
2364 return 1;
2365 wrd = (insn >> 12) & 0xf;
2366 rd0 = (insn >> 16) & 0xf;
2367 gen_op_iwmmxt_movq_M0_wRn(rd0);
2368 tmp = tcg_temp_new_i32();
2369 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2370 tcg_temp_free_i32(tmp);
2371 return 1;
2372 }
2373 switch ((insn >> 22) & 3) {
2374 case 1:
2375 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
2376 break;
2377 case 2:
2378 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
2379 break;
2380 case 3:
2381 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
2382 break;
2383 }
2384 tcg_temp_free_i32(tmp);
2385 gen_op_iwmmxt_movq_wRn_M0(wrd);
2386 gen_op_iwmmxt_set_mup();
2387 gen_op_iwmmxt_set_cup();
2388 break;
2389 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2390 case 0x314: case 0x714: case 0xb14: case 0xf14:
2391 if (((insn >> 22) & 3) == 0)
2392 return 1;
2393 wrd = (insn >> 12) & 0xf;
2394 rd0 = (insn >> 16) & 0xf;
2395 gen_op_iwmmxt_movq_M0_wRn(rd0);
2396 tmp = tcg_temp_new_i32();
2397 switch ((insn >> 22) & 3) {
2398 case 1:
2399 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2400 tcg_temp_free_i32(tmp);
2401 return 1;
2402 }
2403 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
2404 break;
2405 case 2:
2406 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2407 tcg_temp_free_i32(tmp);
2408 return 1;
2409 }
2410 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
2411 break;
2412 case 3:
2413 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2414 tcg_temp_free_i32(tmp);
2415 return 1;
2416 }
2417 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
2418 break;
2419 }
2420 tcg_temp_free_i32(tmp);
2421 gen_op_iwmmxt_movq_wRn_M0(wrd);
2422 gen_op_iwmmxt_set_mup();
2423 gen_op_iwmmxt_set_cup();
2424 break;
2425 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2426 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2427 wrd = (insn >> 12) & 0xf;
2428 rd0 = (insn >> 16) & 0xf;
2429 rd1 = (insn >> 0) & 0xf;
2430 gen_op_iwmmxt_movq_M0_wRn(rd0);
2431 switch ((insn >> 22) & 3) {
2432 case 0:
2433 if (insn & (1 << 21))
2434 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2435 else
2436 gen_op_iwmmxt_minub_M0_wRn(rd1);
2437 break;
2438 case 1:
2439 if (insn & (1 << 21))
2440 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2441 else
2442 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2443 break;
2444 case 2:
2445 if (insn & (1 << 21))
2446 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2447 else
2448 gen_op_iwmmxt_minul_M0_wRn(rd1);
2449 break;
2450 case 3:
2451 return 1;
2452 }
2453 gen_op_iwmmxt_movq_wRn_M0(wrd);
2454 gen_op_iwmmxt_set_mup();
2455 break;
2456 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2457 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2458 wrd = (insn >> 12) & 0xf;
2459 rd0 = (insn >> 16) & 0xf;
2460 rd1 = (insn >> 0) & 0xf;
2461 gen_op_iwmmxt_movq_M0_wRn(rd0);
2462 switch ((insn >> 22) & 3) {
2463 case 0:
2464 if (insn & (1 << 21))
2465 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2466 else
2467 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2468 break;
2469 case 1:
2470 if (insn & (1 << 21))
2471 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2472 else
2473 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2474 break;
2475 case 2:
2476 if (insn & (1 << 21))
2477 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2478 else
2479 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2480 break;
2481 case 3:
2482 return 1;
2483 }
2484 gen_op_iwmmxt_movq_wRn_M0(wrd);
2485 gen_op_iwmmxt_set_mup();
2486 break;
2487 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2488 case 0x402: case 0x502: case 0x602: case 0x702:
2489 wrd = (insn >> 12) & 0xf;
2490 rd0 = (insn >> 16) & 0xf;
2491 rd1 = (insn >> 0) & 0xf;
2492 gen_op_iwmmxt_movq_M0_wRn(rd0);
2493 tmp = tcg_const_i32((insn >> 20) & 3);
2494 iwmmxt_load_reg(cpu_V1, rd1);
2495 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2496 tcg_temp_free_i32(tmp);
2497 gen_op_iwmmxt_movq_wRn_M0(wrd);
2498 gen_op_iwmmxt_set_mup();
2499 break;
2500 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2501 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2502 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2503 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2504 wrd = (insn >> 12) & 0xf;
2505 rd0 = (insn >> 16) & 0xf;
2506 rd1 = (insn >> 0) & 0xf;
2507 gen_op_iwmmxt_movq_M0_wRn(rd0);
2508 switch ((insn >> 20) & 0xf) {
2509 case 0x0:
2510 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2511 break;
2512 case 0x1:
2513 gen_op_iwmmxt_subub_M0_wRn(rd1);
2514 break;
2515 case 0x3:
2516 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2517 break;
2518 case 0x4:
2519 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2520 break;
2521 case 0x5:
2522 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2523 break;
2524 case 0x7:
2525 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2526 break;
2527 case 0x8:
2528 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2529 break;
2530 case 0x9:
2531 gen_op_iwmmxt_subul_M0_wRn(rd1);
2532 break;
2533 case 0xb:
2534 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2535 break;
2536 default:
2537 return 1;
2538 }
2539 gen_op_iwmmxt_movq_wRn_M0(wrd);
2540 gen_op_iwmmxt_set_mup();
2541 gen_op_iwmmxt_set_cup();
2542 break;
2543 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2544 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2545 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2546 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2547 wrd = (insn >> 12) & 0xf;
2548 rd0 = (insn >> 16) & 0xf;
2549 gen_op_iwmmxt_movq_M0_wRn(rd0);
2550 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2551 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2552 tcg_temp_free_i32(tmp);
2553 gen_op_iwmmxt_movq_wRn_M0(wrd);
2554 gen_op_iwmmxt_set_mup();
2555 gen_op_iwmmxt_set_cup();
2556 break;
2557 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2558 case 0x418: case 0x518: case 0x618: case 0x718:
2559 case 0x818: case 0x918: case 0xa18: case 0xb18:
2560 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2561 wrd = (insn >> 12) & 0xf;
2562 rd0 = (insn >> 16) & 0xf;
2563 rd1 = (insn >> 0) & 0xf;
2564 gen_op_iwmmxt_movq_M0_wRn(rd0);
2565 switch ((insn >> 20) & 0xf) {
2566 case 0x0:
2567 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2568 break;
2569 case 0x1:
2570 gen_op_iwmmxt_addub_M0_wRn(rd1);
2571 break;
2572 case 0x3:
2573 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2574 break;
2575 case 0x4:
2576 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2577 break;
2578 case 0x5:
2579 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2580 break;
2581 case 0x7:
2582 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2583 break;
2584 case 0x8:
2585 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2586 break;
2587 case 0x9:
2588 gen_op_iwmmxt_addul_M0_wRn(rd1);
2589 break;
2590 case 0xb:
2591 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2592 break;
2593 default:
2594 return 1;
2595 }
2596 gen_op_iwmmxt_movq_wRn_M0(wrd);
2597 gen_op_iwmmxt_set_mup();
2598 gen_op_iwmmxt_set_cup();
2599 break;
2600 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2601 case 0x408: case 0x508: case 0x608: case 0x708:
2602 case 0x808: case 0x908: case 0xa08: case 0xb08:
2603 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2604 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2605 return 1;
2606 wrd = (insn >> 12) & 0xf;
2607 rd0 = (insn >> 16) & 0xf;
2608 rd1 = (insn >> 0) & 0xf;
2609 gen_op_iwmmxt_movq_M0_wRn(rd0);
2610 switch ((insn >> 22) & 3) {
2611 case 1:
2612 if (insn & (1 << 21))
2613 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2614 else
2615 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2616 break;
2617 case 2:
2618 if (insn & (1 << 21))
2619 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2620 else
2621 gen_op_iwmmxt_packul_M0_wRn(rd1);
2622 break;
2623 case 3:
2624 if (insn & (1 << 21))
2625 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2626 else
2627 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2628 break;
2629 }
2630 gen_op_iwmmxt_movq_wRn_M0(wrd);
2631 gen_op_iwmmxt_set_mup();
2632 gen_op_iwmmxt_set_cup();
2633 break;
2634 case 0x201: case 0x203: case 0x205: case 0x207:
2635 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2636 case 0x211: case 0x213: case 0x215: case 0x217:
2637 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2638 wrd = (insn >> 5) & 0xf;
2639 rd0 = (insn >> 12) & 0xf;
2640 rd1 = (insn >> 0) & 0xf;
2641 if (rd0 == 0xf || rd1 == 0xf)
2642 return 1;
2643 gen_op_iwmmxt_movq_M0_wRn(wrd);
2644 tmp = load_reg(s, rd0);
2645 tmp2 = load_reg(s, rd1);
2646 switch ((insn >> 16) & 0xf) {
2647 case 0x0: /* TMIA */
2648 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2649 break;
2650 case 0x8: /* TMIAPH */
2651 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2652 break;
2653 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2654 if (insn & (1 << 16))
2655 tcg_gen_shri_i32(tmp, tmp, 16);
2656 if (insn & (1 << 17))
2657 tcg_gen_shri_i32(tmp2, tmp2, 16);
2658 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2659 break;
2660 default:
2661 tcg_temp_free_i32(tmp2);
2662 tcg_temp_free_i32(tmp);
2663 return 1;
2664 }
2665 tcg_temp_free_i32(tmp2);
2666 tcg_temp_free_i32(tmp);
2667 gen_op_iwmmxt_movq_wRn_M0(wrd);
2668 gen_op_iwmmxt_set_mup();
2669 break;
2670 default:
2671 return 1;
2672 }
2673
2674 return 0;
2675 }
2676
2677 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
2678 (ie. an undefined instruction). */
2679 static int disas_dsp_insn(DisasContext *s, uint32_t insn)
2680 {
2681 int acc, rd0, rd1, rdhi, rdlo;
2682 TCGv_i32 tmp, tmp2;
2683
2684 if ((insn & 0x0ff00f10) == 0x0e200010) {
2685 /* Multiply with Internal Accumulate Format */
2686 rd0 = (insn >> 12) & 0xf;
2687 rd1 = insn & 0xf;
2688 acc = (insn >> 5) & 7;
2689
2690 if (acc != 0)
2691 return 1;
2692
2693 tmp = load_reg(s, rd0);
2694 tmp2 = load_reg(s, rd1);
2695 switch ((insn >> 16) & 0xf) {
2696 case 0x0: /* MIA */
2697 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2698 break;
2699 case 0x8: /* MIAPH */
2700 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2701 break;
2702 case 0xc: /* MIABB */
2703 case 0xd: /* MIABT */
2704 case 0xe: /* MIATB */
2705 case 0xf: /* MIATT */
2706 if (insn & (1 << 16))
2707 tcg_gen_shri_i32(tmp, tmp, 16);
2708 if (insn & (1 << 17))
2709 tcg_gen_shri_i32(tmp2, tmp2, 16);
2710 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2711 break;
2712 default:
2713 return 1;
2714 }
2715 tcg_temp_free_i32(tmp2);
2716 tcg_temp_free_i32(tmp);
2717
2718 gen_op_iwmmxt_movq_wRn_M0(acc);
2719 return 0;
2720 }
2721
2722 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2723 /* Internal Accumulator Access Format */
2724 rdhi = (insn >> 16) & 0xf;
2725 rdlo = (insn >> 12) & 0xf;
2726 acc = insn & 7;
2727
2728 if (acc != 0)
2729 return 1;
2730
2731 if (insn & ARM_CP_RW_BIT) { /* MRA */
2732 iwmmxt_load_reg(cpu_V0, acc);
2733 tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
2734 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2735 tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);
2736 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
2737 } else { /* MAR */
2738 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2739 iwmmxt_store_reg(cpu_V0, acc);
2740 }
2741 return 0;
2742 }
2743
2744 return 1;
2745 }
2746
2747 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2748 #define VFP_SREG(insn, bigbit, smallbit) \
2749 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2750 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2751 if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
2752 reg = (((insn) >> (bigbit)) & 0x0f) \
2753 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2754 } else { \
2755 if (insn & (1 << (smallbit))) \
2756 return 1; \
2757 reg = ((insn) >> (bigbit)) & 0x0f; \
2758 }} while (0)
2759
2760 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2761 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2762 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2763 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2764 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2765 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2766
2767 /* Move between integer and VFP cores. */
2768 static TCGv_i32 gen_vfp_mrs(void)
2769 {
2770 TCGv_i32 tmp = tcg_temp_new_i32();
2771 tcg_gen_mov_i32(tmp, cpu_F0s);
2772 return tmp;
2773 }
2774
2775 static void gen_vfp_msr(TCGv_i32 tmp)
2776 {
2777 tcg_gen_mov_i32(cpu_F0s, tmp);
2778 tcg_temp_free_i32(tmp);
2779 }
2780
2781 static void gen_neon_dup_u8(TCGv_i32 var, int shift)
2782 {
2783 TCGv_i32 tmp = tcg_temp_new_i32();
2784 if (shift)
2785 tcg_gen_shri_i32(var, var, shift);
2786 tcg_gen_ext8u_i32(var, var);
2787 tcg_gen_shli_i32(tmp, var, 8);
2788 tcg_gen_or_i32(var, var, tmp);
2789 tcg_gen_shli_i32(tmp, var, 16);
2790 tcg_gen_or_i32(var, var, tmp);
2791 tcg_temp_free_i32(tmp);
2792 }
2793
2794 static void gen_neon_dup_low16(TCGv_i32 var)
2795 {
2796 TCGv_i32 tmp = tcg_temp_new_i32();
2797 tcg_gen_ext16u_i32(var, var);
2798 tcg_gen_shli_i32(tmp, var, 16);
2799 tcg_gen_or_i32(var, var, tmp);
2800 tcg_temp_free_i32(tmp);
2801 }
2802
2803 static void gen_neon_dup_high16(TCGv_i32 var)
2804 {
2805 TCGv_i32 tmp = tcg_temp_new_i32();
2806 tcg_gen_andi_i32(var, var, 0xffff0000);
2807 tcg_gen_shri_i32(tmp, var, 16);
2808 tcg_gen_or_i32(var, var, tmp);
2809 tcg_temp_free_i32(tmp);
2810 }
2811
2812 static TCGv_i32 gen_load_and_replicate(DisasContext *s, TCGv_i32 addr, int size)
2813 {
2814 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2815 TCGv_i32 tmp = tcg_temp_new_i32();
2816 switch (size) {
2817 case 0:
2818 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
2819 gen_neon_dup_u8(tmp, 0);
2820 break;
2821 case 1:
2822 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
2823 gen_neon_dup_low16(tmp);
2824 break;
2825 case 2:
2826 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
2827 break;
2828 default: /* Avoid compiler warnings. */
2829 abort();
2830 }
2831 return tmp;
2832 }
2833
2834 static int handle_vsel(uint32_t insn, uint32_t rd, uint32_t rn, uint32_t rm,
2835 uint32_t dp)
2836 {
2837 uint32_t cc = extract32(insn, 20, 2);
2838
2839 if (dp) {
2840 TCGv_i64 frn, frm, dest;
2841 TCGv_i64 tmp, zero, zf, nf, vf;
2842
2843 zero = tcg_const_i64(0);
2844
2845 frn = tcg_temp_new_i64();
2846 frm = tcg_temp_new_i64();
2847 dest = tcg_temp_new_i64();
2848
2849 zf = tcg_temp_new_i64();
2850 nf = tcg_temp_new_i64();
2851 vf = tcg_temp_new_i64();
2852
2853 tcg_gen_extu_i32_i64(zf, cpu_ZF);
2854 tcg_gen_ext_i32_i64(nf, cpu_NF);
2855 tcg_gen_ext_i32_i64(vf, cpu_VF);
2856
2857 tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn));
2858 tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm));
2859 switch (cc) {
2860 case 0: /* eq: Z */
2861 tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
2862 frn, frm);
2863 break;
2864 case 1: /* vs: V */
2865 tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero,
2866 frn, frm);
2867 break;
2868 case 2: /* ge: N == V -> N ^ V == 0 */
2869 tmp = tcg_temp_new_i64();
2870 tcg_gen_xor_i64(tmp, vf, nf);
2871 tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
2872 frn, frm);
2873 tcg_temp_free_i64(tmp);
2874 break;
2875 case 3: /* gt: !Z && N == V */
2876 tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero,
2877 frn, frm);
2878 tmp = tcg_temp_new_i64();
2879 tcg_gen_xor_i64(tmp, vf, nf);
2880 tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
2881 dest, frm);
2882 tcg_temp_free_i64(tmp);
2883 break;
2884 }
2885 tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd));
2886 tcg_temp_free_i64(frn);
2887 tcg_temp_free_i64(frm);
2888 tcg_temp_free_i64(dest);
2889
2890 tcg_temp_free_i64(zf);
2891 tcg_temp_free_i64(nf);
2892 tcg_temp_free_i64(vf);
2893
2894 tcg_temp_free_i64(zero);
2895 } else {
2896 TCGv_i32 frn, frm, dest;
2897 TCGv_i32 tmp, zero;
2898
2899 zero = tcg_const_i32(0);
2900
2901 frn = tcg_temp_new_i32();
2902 frm = tcg_temp_new_i32();
2903 dest = tcg_temp_new_i32();
2904 tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn));
2905 tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm));
2906 switch (cc) {
2907 case 0: /* eq: Z */
2908 tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
2909 frn, frm);
2910 break;
2911 case 1: /* vs: V */
2912 tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero,
2913 frn, frm);
2914 break;
2915 case 2: /* ge: N == V -> N ^ V == 0 */
2916 tmp = tcg_temp_new_i32();
2917 tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
2918 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
2919 frn, frm);
2920 tcg_temp_free_i32(tmp);
2921 break;
2922 case 3: /* gt: !Z && N == V */
2923 tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero,
2924 frn, frm);
2925 tmp = tcg_temp_new_i32();
2926 tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
2927 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
2928 dest, frm);
2929 tcg_temp_free_i32(tmp);
2930 break;
2931 }
2932 tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd));
2933 tcg_temp_free_i32(frn);
2934 tcg_temp_free_i32(frm);
2935 tcg_temp_free_i32(dest);
2936
2937 tcg_temp_free_i32(zero);
2938 }
2939
2940 return 0;
2941 }
2942
2943 static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn,
2944 uint32_t rm, uint32_t dp)
2945 {
2946 uint32_t vmin = extract32(insn, 6, 1);
2947 TCGv_ptr fpst = get_fpstatus_ptr(0);
2948
2949 if (dp) {
2950 TCGv_i64 frn, frm, dest;
2951
2952 frn = tcg_temp_new_i64();
2953 frm = tcg_temp_new_i64();
2954 dest = tcg_temp_new_i64();
2955
2956 tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn));
2957 tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm));
2958 if (vmin) {
2959 gen_helper_vfp_minnumd(dest, frn, frm, fpst);
2960 } else {
2961 gen_helper_vfp_maxnumd(dest, frn, frm, fpst);
2962 }
2963 tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd));
2964 tcg_temp_free_i64(frn);
2965 tcg_temp_free_i64(frm);
2966 tcg_temp_free_i64(dest);
2967 } else {
2968 TCGv_i32 frn, frm, dest;
2969
2970 frn = tcg_temp_new_i32();
2971 frm = tcg_temp_new_i32();
2972 dest = tcg_temp_new_i32();
2973
2974 tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn));
2975 tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm));
2976 if (vmin) {
2977 gen_helper_vfp_minnums(dest, frn, frm, fpst);
2978 } else {
2979 gen_helper_vfp_maxnums(dest, frn, frm, fpst);
2980 }
2981 tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd));
2982 tcg_temp_free_i32(frn);
2983 tcg_temp_free_i32(frm);
2984 tcg_temp_free_i32(dest);
2985 }
2986
2987 tcg_temp_free_ptr(fpst);
2988 return 0;
2989 }
2990
2991 static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
2992 int rounding)
2993 {
2994 TCGv_ptr fpst = get_fpstatus_ptr(0);
2995 TCGv_i32 tcg_rmode;
2996
2997 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
2998 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
2999
3000 if (dp) {
3001 TCGv_i64 tcg_op;
3002 TCGv_i64 tcg_res;
3003 tcg_op = tcg_temp_new_i64();
3004 tcg_res = tcg_temp_new_i64();
3005 tcg_gen_ld_f64(tcg_op, cpu_env, vfp_reg_offset(dp, rm));
3006 gen_helper_rintd(tcg_res, tcg_op, fpst);
3007 tcg_gen_st_f64(tcg_res, cpu_env, vfp_reg_offset(dp, rd));
3008 tcg_temp_free_i64(tcg_op);
3009 tcg_temp_free_i64(tcg_res);
3010 } else {
3011 TCGv_i32 tcg_op;
3012 TCGv_i32 tcg_res;
3013 tcg_op = tcg_temp_new_i32();
3014 tcg_res = tcg_temp_new_i32();
3015 tcg_gen_ld_f32(tcg_op, cpu_env, vfp_reg_offset(dp, rm));
3016 gen_helper_rints(tcg_res, tcg_op, fpst);
3017 tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(dp, rd));
3018 tcg_temp_free_i32(tcg_op);
3019 tcg_temp_free_i32(tcg_res);
3020 }
3021
3022 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
3023 tcg_temp_free_i32(tcg_rmode);
3024
3025 tcg_temp_free_ptr(fpst);
3026 return 0;
3027 }
3028
3029 static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
3030 int rounding)
3031 {
3032 bool is_signed = extract32(insn, 7, 1);
3033 TCGv_ptr fpst = get_fpstatus_ptr(0);
3034 TCGv_i32 tcg_rmode, tcg_shift;
3035
3036 tcg_shift = tcg_const_i32(0);
3037
3038 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
3039 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
3040
3041 if (dp) {
3042 TCGv_i64 tcg_double, tcg_res;
3043 TCGv_i32 tcg_tmp;
3044 /* Rd is encoded as a single precision register even when the source
3045 * is double precision.
3046 */
3047 rd = ((rd << 1) & 0x1e) | ((rd >> 4) & 0x1);
3048 tcg_double = tcg_temp_new_i64();
3049 tcg_res = tcg_temp_new_i64();
3050 tcg_tmp = tcg_temp_new_i32();
3051 tcg_gen_ld_f64(tcg_double, cpu_env, vfp_reg_offset(1, rm));
3052 if (is_signed) {
3053 gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
3054 } else {
3055 gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
3056 }
3057 tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res);
3058 tcg_gen_st_f32(tcg_tmp, cpu_env, vfp_reg_offset(0, rd));
3059 tcg_temp_free_i32(tcg_tmp);
3060 tcg_temp_free_i64(tcg_res);
3061 tcg_temp_free_i64(tcg_double);
3062 } else {
3063 TCGv_i32 tcg_single, tcg_res;
3064 tcg_single = tcg_temp_new_i32();
3065 tcg_res = tcg_temp_new_i32();
3066 tcg_gen_ld_f32(tcg_single, cpu_env, vfp_reg_offset(0, rm));
3067 if (is_signed) {
3068 gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst);
3069 } else {
3070 gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
3071 }
3072 tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(0, rd));
3073 tcg_temp_free_i32(tcg_res);
3074 tcg_temp_free_i32(tcg_single);
3075 }
3076
3077 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
3078 tcg_temp_free_i32(tcg_rmode);
3079
3080 tcg_temp_free_i32(tcg_shift);
3081
3082 tcg_temp_free_ptr(fpst);
3083
3084 return 0;
3085 }
3086
3087 /* Table for converting the most common AArch32 encoding of
3088 * rounding mode to arm_fprounding order (which matches the
3089 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
3090 */
3091 static const uint8_t fp_decode_rm[] = {
3092 FPROUNDING_TIEAWAY,
3093 FPROUNDING_TIEEVEN,
3094 FPROUNDING_POSINF,
3095 FPROUNDING_NEGINF,
3096 };
3097
3098 static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
3099 {
3100 uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
3101
3102 if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
3103 return 1;
3104 }
3105
3106 if (dp) {
3107 VFP_DREG_D(rd, insn);
3108 VFP_DREG_N(rn, insn);
3109 VFP_DREG_M(rm, insn);
3110 } else {
3111 rd = VFP_SREG_D(insn);
3112 rn = VFP_SREG_N(insn);
3113 rm = VFP_SREG_M(insn);
3114 }
3115
3116 if ((insn & 0x0f800e50) == 0x0e000a00) {
3117 return handle_vsel(insn, rd, rn, rm, dp);
3118 } else if ((insn & 0x0fb00e10) == 0x0e800a00) {
3119 return handle_vminmaxnm(insn, rd, rn, rm, dp);
3120 } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40) {
3121 /* VRINTA, VRINTN, VRINTP, VRINTM */
3122 int rounding = fp_decode_rm[extract32(insn, 16, 2)];
3123 return handle_vrint(insn, rd, rm, dp, rounding);
3124 } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40) {
3125 /* VCVTA, VCVTN, VCVTP, VCVTM */
3126 int rounding = fp_decode_rm[extract32(insn, 16, 2)];
3127 return handle_vcvt(insn, rd, rm, dp, rounding);
3128 }
3129 return 1;
3130 }
3131
3132 /* Disassemble a VFP instruction. Returns nonzero if an error occurred
3133 (ie. an undefined instruction). */
3134 static int disas_vfp_insn(DisasContext *s, uint32_t insn)
3135 {
3136 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
3137 int dp, veclen;
3138 TCGv_i32 addr;
3139 TCGv_i32 tmp;
3140 TCGv_i32 tmp2;
3141
3142 if (!arm_dc_feature(s, ARM_FEATURE_VFP)) {
3143 return 1;
3144 }
3145
3146 /* FIXME: this access check should not take precedence over UNDEF
3147 * for invalid encodings; we will generate incorrect syndrome information
3148 * for attempts to execute invalid vfp/neon encodings with FP disabled.
3149 */
3150 if (s->fp_excp_el) {
3151 gen_exception_insn(s, 4, EXCP_UDEF,
3152 syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
3153 return 0;
3154 }
3155
3156 if (!s->vfp_enabled) {
3157 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
3158 if ((insn & 0x0fe00fff) != 0x0ee00a10)
3159 return 1;
3160 rn = (insn >> 16) & 0xf;
3161 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC && rn != ARM_VFP_MVFR2
3162 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0) {
3163 return 1;
3164 }
3165 }
3166
3167 if (extract32(insn, 28, 4) == 0xf) {
3168 /* Encodings with T=1 (Thumb) or unconditional (ARM):
3169 * only used in v8 and above.
3170 */
3171 return disas_vfp_v8_insn(s, insn);
3172 }
3173
3174 dp = ((insn & 0xf00) == 0xb00);
3175 switch ((insn >> 24) & 0xf) {
3176 case 0xe:
3177 if (insn & (1 << 4)) {
3178 /* single register transfer */
3179 rd = (insn >> 12) & 0xf;
3180 if (dp) {
3181 int size;
3182 int pass;
3183
3184 VFP_DREG_N(rn, insn);
3185 if (insn & 0xf)
3186 return 1;
3187 if (insn & 0x00c00060
3188 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
3189 return 1;
3190 }
3191
3192 pass = (insn >> 21) & 1;
3193 if (insn & (1 << 22)) {
3194 size = 0;
3195 offset = ((insn >> 5) & 3) * 8;
3196 } else if (insn & (1 << 5)) {
3197 size = 1;
3198 offset = (insn & (1 << 6)) ? 16 : 0;
3199 } else {
3200 size = 2;
3201 offset = 0;
3202 }
3203 if (insn & ARM_CP_RW_BIT) {
3204 /* vfp->arm */
3205 tmp = neon_load_reg(rn, pass);
3206 switch (size) {
3207 case 0:
3208 if (offset)
3209 tcg_gen_shri_i32(tmp, tmp, offset);
3210 if (insn & (1 << 23))
3211 gen_uxtb(tmp);
3212 else
3213 gen_sxtb(tmp);
3214 break;
3215 case 1:
3216 if (insn & (1 << 23)) {
3217 if (offset) {
3218 tcg_gen_shri_i32(tmp, tmp, 16);
3219 } else {
3220 gen_uxth(tmp);
3221 }
3222 } else {
3223 if (offset) {
3224 tcg_gen_sari_i32(tmp, tmp, 16);
3225 } else {
3226 gen_sxth(tmp);
3227 }
3228 }
3229 break;
3230 case 2:
3231 break;
3232 }
3233 store_reg(s, rd, tmp);
3234 } else {
3235 /* arm->vfp */
3236 tmp = load_reg(s, rd);
3237 if (insn & (1 << 23)) {
3238 /* VDUP */
3239 if (size == 0) {
3240 gen_neon_dup_u8(tmp, 0);
3241 } else if (size == 1) {
3242 gen_neon_dup_low16(tmp);
3243 }
3244 for (n = 0; n <= pass * 2; n++) {
3245 tmp2 = tcg_temp_new_i32();
3246 tcg_gen_mov_i32(tmp2, tmp);
3247 neon_store_reg(rn, n, tmp2);
3248 }
3249 neon_store_reg(rn, n, tmp);
3250 } else {
3251 /* VMOV */
3252 switch (size) {
3253 case 0:
3254 tmp2 = neon_load_reg(rn, pass);
3255 tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
3256 tcg_temp_free_i32(tmp2);
3257 break;
3258 case 1:
3259 tmp2 = neon_load_reg(rn, pass);
3260 tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
3261 tcg_temp_free_i32(tmp2);
3262 break;
3263 case 2:
3264 break;
3265 }
3266 neon_store_reg(rn, pass, tmp);
3267 }
3268 }
3269 } else { /* !dp */
3270 if ((insn & 0x6f) != 0x00)
3271 return 1;
3272 rn = VFP_SREG_N(insn);
3273 if (insn & ARM_CP_RW_BIT) {
3274 /* vfp->arm */
3275 if (insn & (1 << 21)) {
3276 /* system register */
3277 rn >>= 1;
3278
3279 switch (rn) {
3280 case ARM_VFP_FPSID:
3281 /* VFP2 allows access to FSID from userspace.
3282 VFP3 restricts all id registers to privileged
3283 accesses. */
3284 if (IS_USER(s)
3285 && arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3286 return 1;
3287 }
3288 tmp = load_cpu_field(vfp.xregs[rn]);
3289 break;
3290 case ARM_VFP_FPEXC:
3291 if (IS_USER(s))
3292 return 1;
3293 tmp = load_cpu_field(vfp.xregs[rn]);
3294 break;
3295 case ARM_VFP_FPINST:
3296 case ARM_VFP_FPINST2:
3297 /* Not present in VFP3. */
3298 if (IS_USER(s)
3299 || arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3300 return 1;
3301 }
3302 tmp = load_cpu_field(vfp.xregs[rn]);
3303 break;
3304 case ARM_VFP_FPSCR:
3305 if (rd == 15) {
3306 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
3307 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
3308 } else {
3309 tmp = tcg_temp_new_i32();
3310 gen_helper_vfp_get_fpscr(tmp, cpu_env);
3311 }
3312 break;
3313 case ARM_VFP_MVFR2:
3314 if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
3315 return 1;
3316 }
3317 /* fall through */
3318 case ARM_VFP_MVFR0:
3319 case ARM_VFP_MVFR1:
3320 if (IS_USER(s)
3321 || !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
3322 return 1;
3323 }
3324 tmp = load_cpu_field(vfp.xregs[rn]);
3325 break;
3326 default:
3327 return 1;
3328 }
3329 } else {
3330 gen_mov_F0_vreg(0, rn);
3331 tmp = gen_vfp_mrs();
3332 }
3333 if (rd == 15) {
3334 /* Set the 4 flag bits in the CPSR. */
3335 gen_set_nzcv(tmp);
3336 tcg_temp_free_i32(tmp);
3337 } else {
3338 store_reg(s, rd, tmp);
3339 }
3340 } else {
3341 /* arm->vfp */
3342 if (insn & (1 << 21)) {
3343 rn >>= 1;
3344 /* system register */
3345 switch (rn) {
3346 case ARM_VFP_FPSID:
3347 case ARM_VFP_MVFR0:
3348 case ARM_VFP_MVFR1:
3349 /* Writes are ignored. */
3350 break;
3351 case ARM_VFP_FPSCR:
3352 tmp = load_reg(s, rd);
3353 gen_helper_vfp_set_fpscr(cpu_env, tmp);
3354 tcg_temp_free_i32(tmp);
3355 gen_lookup_tb(s);
3356 break;
3357 case ARM_VFP_FPEXC:
3358 if (IS_USER(s))
3359 return 1;
3360 /* TODO: VFP subarchitecture support.
3361 * For now, keep the EN bit only */
3362 tmp = load_reg(s, rd);
3363 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
3364 store_cpu_field(tmp, vfp.xregs[rn]);
3365 gen_lookup_tb(s);
3366 break;
3367 case ARM_VFP_FPINST:
3368 case ARM_VFP_FPINST2:
3369 if (IS_USER(s)) {
3370 return 1;
3371 }
3372 tmp = load_reg(s, rd);
3373 store_cpu_field(tmp, vfp.xregs[rn]);
3374 break;
3375 default:
3376 return 1;
3377 }
3378 } else {
3379 tmp = load_reg(s, rd);
3380 gen_vfp_msr(tmp);
3381 gen_mov_vreg_F0(0, rn);
3382 }
3383 }
3384 }
3385 } else {
3386 /* data processing */
3387 /* The opcode is in bits 23, 21, 20 and 6. */
3388 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
3389 if (dp) {
3390 if (op == 15) {
3391 /* rn is opcode */
3392 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
3393 } else {
3394 /* rn is register number */
3395 VFP_DREG_N(rn, insn);
3396 }
3397
3398 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18) ||
3399 ((rn & 0x1e) == 0x6))) {
3400 /* Integer or single/half precision destination. */
3401 rd = VFP_SREG_D(insn);
3402 } else {
3403 VFP_DREG_D(rd, insn);
3404 }
3405 if (op == 15 &&
3406 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14) ||
3407 ((rn & 0x1e) == 0x4))) {
3408 /* VCVT from int or half precision is always from S reg
3409 * regardless of dp bit. VCVT with immediate frac_bits
3410 * has same format as SREG_M.
3411 */
3412 rm = VFP_SREG_M(insn);
3413 } else {
3414 VFP_DREG_M(rm, insn);
3415 }
3416 } else {
3417 rn = VFP_SREG_N(insn);
3418 if (op == 15 && rn == 15) {
3419 /* Double precision destination. */
3420 VFP_DREG_D(rd, insn);
3421 } else {
3422 rd = VFP_SREG_D(insn);
3423 }
3424 /* NB that we implicitly rely on the encoding for the frac_bits
3425 * in VCVT of fixed to float being the same as that of an SREG_M
3426 */
3427 rm = VFP_SREG_M(insn);
3428 }
3429
3430 veclen = s->vec_len;
3431 if (op == 15 && rn > 3)
3432 veclen = 0;
3433
3434 /* Shut up compiler warnings. */
3435 delta_m = 0;
3436 delta_d = 0;
3437 bank_mask = 0;
3438
3439 if (veclen > 0) {
3440 if (dp)
3441 bank_mask = 0xc;
3442 else
3443 bank_mask = 0x18;
3444
3445 /* Figure out what type of vector operation this is. */
3446 if ((rd & bank_mask) == 0) {
3447 /* scalar */
3448 veclen = 0;
3449 } else {
3450 if (dp)
3451 delta_d = (s->vec_stride >> 1) + 1;
3452 else
3453 delta_d = s->vec_stride + 1;
3454
3455 if ((rm & bank_mask) == 0) {
3456 /* mixed scalar/vector */
3457 delta_m = 0;
3458 } else {
3459 /* vector */
3460 delta_m = delta_d;
3461 }
3462 }
3463 }
3464
3465 /* Load the initial operands. */
3466 if (op == 15) {
3467 switch (rn) {
3468 case 16:
3469 case 17:
3470 /* Integer source */
3471 gen_mov_F0_vreg(0, rm);
3472 break;
3473 case 8:
3474 case 9:
3475 /* Compare */
3476 gen_mov_F0_vreg(dp, rd);
3477 gen_mov_F1_vreg(dp, rm);
3478 break;
3479 case 10:
3480 case 11:
3481 /* Compare with zero */
3482 gen_mov_F0_vreg(dp, rd);
3483 gen_vfp_F1_ld0(dp);
3484 break;
3485 case 20:
3486 case 21:
3487 case 22:
3488 case 23:
3489 case 28:
3490 case 29:
3491 case 30:
3492 case 31:
3493 /* Source and destination the same. */
3494 gen_mov_F0_vreg(dp, rd);
3495 break;
3496 case 4:
3497 case 5:
3498 case 6:
3499 case 7:
3500 /* VCVTB, VCVTT: only present with the halfprec extension
3501 * UNPREDICTABLE if bit 8 is set prior to ARMv8
3502 * (we choose to UNDEF)
3503 */
3504 if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
3505 !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
3506 return 1;
3507 }
3508 if (!extract32(rn, 1, 1)) {
3509 /* Half precision source. */
3510 gen_mov_F0_vreg(0, rm);
3511 break;
3512 }
3513 /* Otherwise fall through */
3514 default:
3515 /* One source operand. */
3516 gen_mov_F0_vreg(dp, rm);
3517 break;
3518 }
3519 } else {
3520 /* Two source operands. */
3521 gen_mov_F0_vreg(dp, rn);
3522 gen_mov_F1_vreg(dp, rm);
3523 }
3524
3525 for (;;) {
3526 /* Perform the calculation. */
3527 switch (op) {
3528 case 0: /* VMLA: fd + (fn * fm) */
3529 /* Note that order of inputs to the add matters for NaNs */
3530 gen_vfp_F1_mul(dp);
3531 gen_mov_F0_vreg(dp, rd);
3532 gen_vfp_add(dp);
3533 break;
3534 case 1: /* VMLS: fd + -(fn * fm) */
3535 gen_vfp_mul(dp);
3536 gen_vfp_F1_neg(dp);
3537 gen_mov_F0_vreg(dp, rd);
3538 gen_vfp_add(dp);
3539 break;
3540 case 2: /* VNMLS: -fd + (fn * fm) */
3541 /* Note that it isn't valid to replace (-A + B) with (B - A)
3542 * or similar plausible looking simplifications
3543 * because this will give wrong results for NaNs.
3544 */
3545 gen_vfp_F1_mul(dp);
3546 gen_mov_F0_vreg(dp, rd);
3547 gen_vfp_neg(dp);
3548 gen_vfp_add(dp);
3549 break;
3550 case 3: /* VNMLA: -fd + -(fn * fm) */
3551 gen_vfp_mul(dp);
3552 gen_vfp_F1_neg(dp);
3553 gen_mov_F0_vreg(dp, rd);
3554 gen_vfp_neg(dp);
3555 gen_vfp_add(dp);
3556 break;
3557 case 4: /* mul: fn * fm */
3558 gen_vfp_mul(dp);
3559 break;
3560 case 5: /* nmul: -(fn * fm) */
3561 gen_vfp_mul(dp);
3562 gen_vfp_neg(dp);
3563 break;
3564 case 6: /* add: fn + fm */
3565 gen_vfp_add(dp);
3566 break;
3567 case 7: /* sub: fn - fm */
3568 gen_vfp_sub(dp);
3569 break;
3570 case 8: /* div: fn / fm */
3571 gen_vfp_div(dp);
3572 break;
3573 case 10: /* VFNMA : fd = muladd(-fd, fn, fm) */
3574 case 11: /* VFNMS : fd = muladd(-fd, -fn, fm) */
3575 case 12: /* VFMA : fd = muladd( fd, fn, fm) */
3576 case 13: /* VFMS : fd = muladd( fd, -fn, fm) */
3577 /* These are fused multiply-add, and must be done as one
3578 * floating point operation with no rounding between the
3579 * multiplication and addition steps.
3580 * NB that doing the negations here as separate steps is
3581 * correct : an input NaN should come out with its sign bit
3582 * flipped if it is a negated-input.
3583 */
3584 if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
3585 return 1;
3586 }
3587 if (dp) {
3588 TCGv_ptr fpst;
3589 TCGv_i64 frd;
3590 if (op & 1) {
3591 /* VFNMS, VFMS */
3592 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
3593 }
3594 frd = tcg_temp_new_i64();
3595 tcg_gen_ld_f64(frd, cpu_env, vfp_reg_offset(dp, rd));
3596 if (op & 2) {
3597 /* VFNMA, VFNMS */
3598 gen_helper_vfp_negd(frd, frd);
3599 }
3600 fpst = get_fpstatus_ptr(0);
3601 gen_helper_vfp_muladdd(cpu_F0d, cpu_F0d,
3602 cpu_F1d, frd, fpst);
3603 tcg_temp_free_ptr(fpst);
3604 tcg_temp_free_i64(frd);
3605 } else {
3606 TCGv_ptr fpst;
3607 TCGv_i32 frd;
3608 if (op & 1) {
3609 /* VFNMS, VFMS */
3610 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
3611 }
3612 frd = tcg_temp_new_i32();
3613 tcg_gen_ld_f32(frd, cpu_env, vfp_reg_offset(dp, rd));
3614 if (op & 2) {
3615 gen_helper_vfp_negs(frd, frd);
3616 }
3617 fpst = get_fpstatus_ptr(0);
3618 gen_helper_vfp_muladds(cpu_F0s, cpu_F0s,
3619 cpu_F1s, frd, fpst);
3620 tcg_temp_free_ptr(fpst);
3621 tcg_temp_free_i32(frd);
3622 }
3623 break;
3624 case 14: /* fconst */
3625 if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3626 return 1;
3627 }
3628
3629 n = (insn << 12) & 0x80000000;
3630 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3631 if (dp) {
3632 if (i & 0x40)
3633 i |= 0x3f80;
3634 else
3635 i |= 0x4000;
3636 n |= i << 16;
3637 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
3638 } else {
3639 if (i & 0x40)
3640 i |= 0x780;
3641 else
3642 i |= 0x800;
3643 n |= i << 19;
3644 tcg_gen_movi_i32(cpu_F0s, n);
3645 }
3646 break;
3647 case 15: /* extension space */
3648 switch (rn) {
3649 case 0: /* cpy */
3650 /* no-op */
3651 break;
3652 case 1: /* abs */
3653 gen_vfp_abs(dp);
3654 break;
3655 case 2: /* neg */
3656 gen_vfp_neg(dp);
3657 break;
3658 case 3: /* sqrt */
3659 gen_vfp_sqrt(dp);
3660 break;
3661 case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */
3662 tmp = gen_vfp_mrs();
3663 tcg_gen_ext16u_i32(tmp, tmp);
3664 if (dp) {
3665 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp,
3666 cpu_env);
3667 } else {
3668 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp,
3669 cpu_env);
3670 }
3671 tcg_temp_free_i32(tmp);
3672 break;
3673 case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */
3674 tmp = gen_vfp_mrs();
3675 tcg_gen_shri_i32(tmp, tmp, 16);
3676 if (dp) {
3677 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp,
3678 cpu_env);
3679 } else {
3680 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp,
3681 cpu_env);
3682 }
3683 tcg_temp_free_i32(tmp);
3684 break;
3685 case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */
3686 tmp = tcg_temp_new_i32();
3687 if (dp) {
3688 gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d,
3689 cpu_env);
3690 } else {
3691 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s,
3692 cpu_env);
3693 }
3694 gen_mov_F0_vreg(0, rd);
3695 tmp2 = gen_vfp_mrs();
3696 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3697 tcg_gen_or_i32(tmp, tmp, tmp2);
3698 tcg_temp_free_i32(tmp2);
3699 gen_vfp_msr(tmp);
3700 break;
3701 case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */
3702 tmp = tcg_temp_new_i32();
3703 if (dp) {
3704 gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d,
3705 cpu_env);
3706 } else {
3707 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s,
3708 cpu_env);
3709 }
3710 tcg_gen_shli_i32(tmp, tmp, 16);
3711 gen_mov_F0_vreg(0, rd);
3712 tmp2 = gen_vfp_mrs();
3713 tcg_gen_ext16u_i32(tmp2, tmp2);
3714 tcg_gen_or_i32(tmp, tmp, tmp2);
3715 tcg_temp_free_i32(tmp2);
3716 gen_vfp_msr(tmp);
3717 break;
3718 case 8: /* cmp */
3719 gen_vfp_cmp(dp);
3720 break;
3721 case 9: /* cmpe */
3722 gen_vfp_cmpe(dp);
3723 break;
3724 case 10: /* cmpz */
3725 gen_vfp_cmp(dp);
3726 break;
3727 case 11: /* cmpez */
3728 gen_vfp_F1_ld0(dp);
3729 gen_vfp_cmpe(dp);
3730 break;
3731 case 12: /* vrintr */
3732 {
3733 TCGv_ptr fpst = get_fpstatus_ptr(0);
3734 if (dp) {
3735 gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
3736 } else {
3737 gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
3738 }
3739 tcg_temp_free_ptr(fpst);
3740 break;
3741 }
3742 case 13: /* vrintz */
3743 {
3744 TCGv_ptr fpst = get_fpstatus_ptr(0);
3745 TCGv_i32 tcg_rmode;
3746 tcg_rmode = tcg_const_i32(float_round_to_zero);
3747 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
3748 if (dp) {
3749 gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
3750 } else {
3751 gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
3752 }
3753 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
3754 tcg_temp_free_i32(tcg_rmode);
3755 tcg_temp_free_ptr(fpst);
3756 break;
3757 }
3758 case 14: /* vrintx */
3759 {
3760 TCGv_ptr fpst = get_fpstatus_ptr(0);
3761 if (dp) {
3762 gen_helper_rintd_exact(cpu_F0d, cpu_F0d, fpst);
3763 } else {
3764 gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpst);
3765 }
3766 tcg_temp_free_ptr(fpst);
3767 break;
3768 }
3769 case 15: /* single<->double conversion */
3770 if (dp)
3771 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3772 else
3773 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3774 break;
3775 case 16: /* fuito */
3776 gen_vfp_uito(dp, 0);
3777 break;
3778 case 17: /* fsito */
3779 gen_vfp_sito(dp, 0);
3780 break;
3781 case 20: /* fshto */
3782 if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3783 return 1;
3784 }
3785 gen_vfp_shto(dp, 16 - rm, 0);
3786 break;
3787 case 21: /* fslto */
3788 if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3789 return 1;
3790 }
3791 gen_vfp_slto(dp, 32 - rm, 0);
3792 break;
3793 case 22: /* fuhto */
3794 if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3795 return 1;
3796 }
3797 gen_vfp_uhto(dp, 16 - rm, 0);
3798 break;
3799 case 23: /* fulto */
3800 if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3801 return 1;
3802 }
3803 gen_vfp_ulto(dp, 32 - rm, 0);
3804 break;
3805 case 24: /* ftoui */
3806 gen_vfp_toui(dp, 0);
3807 break;
3808 case 25: /* ftouiz */
3809 gen_vfp_touiz(dp, 0);
3810 break;
3811 case 26: /* ftosi */
3812 gen_vfp_tosi(dp, 0);
3813 break;
3814 case 27: /* ftosiz */
3815 gen_vfp_tosiz(dp, 0);
3816 break;
3817 case 28: /* ftosh */
3818 if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3819 return 1;
3820 }
3821 gen_vfp_tosh(dp, 16 - rm, 0);
3822 break;
3823 case 29: /* ftosl */
3824 if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3825 return 1;
3826 }
3827 gen_vfp_tosl(dp, 32 - rm, 0);
3828 break;
3829 case 30: /* ftouh */
3830 if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3831 return 1;
3832 }
3833 gen_vfp_touh(dp, 16 - rm, 0);
3834 break;
3835 case 31: /* ftoul */
3836 if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
3837 return 1;
3838 }
3839 gen_vfp_toul(dp, 32 - rm, 0);
3840 break;
3841 default: /* undefined */
3842 return 1;
3843 }
3844 break;
3845 default: /* undefined */
3846 return 1;
3847 }
3848
3849 /* Write back the result. */
3850 if (op == 15 && (rn >= 8 && rn <= 11)) {
3851 /* Comparison, do nothing. */
3852 } else if (op == 15 && dp && ((rn & 0x1c) == 0x18 ||
3853 (rn & 0x1e) == 0x6)) {
3854 /* VCVT double to int: always integer result.
3855 * VCVT double to half precision is always a single
3856 * precision result.
3857 */
3858 gen_mov_vreg_F0(0, rd);
3859 } else if (op == 15 && rn == 15) {
3860 /* conversion */
3861 gen_mov_vreg_F0(!dp, rd);
3862 } else {
3863 gen_mov_vreg_F0(dp, rd);
3864 }
3865
3866 /* break out of the loop if we have finished */
3867 if (veclen == 0)
3868 break;
3869
3870 if (op == 15 && delta_m == 0) {
3871 /* single source one-many */
3872 while (veclen--) {
3873 rd = ((rd + delta_d) & (bank_mask - 1))
3874 | (rd & bank_mask);
3875 gen_mov_vreg_F0(dp, rd);
3876 }
3877 break;
3878 }
3879 /* Setup the next operands. */
3880 veclen--;
3881 rd = ((rd + delta_d) & (bank_mask - 1))
3882 | (rd & bank_mask);
3883
3884 if (op == 15) {
3885 /* One source operand. */
3886 rm = ((rm + delta_m) & (bank_mask - 1))
3887 | (rm & bank_mask);
3888 gen_mov_F0_vreg(dp, rm);
3889 } else {
3890 /* Two source operands. */
3891 rn = ((rn + delta_d) & (bank_mask - 1))
3892 | (rn & bank_mask);
3893 gen_mov_F0_vreg(dp, rn);
3894 if (delta_m) {
3895 rm = ((rm + delta_m) & (bank_mask - 1))
3896 | (rm & bank_mask);
3897 gen_mov_F1_vreg(dp, rm);
3898 }
3899 }
3900 }
3901 }
3902 break;
3903 case 0xc:
3904 case 0xd:
3905 if ((insn & 0x03e00000) == 0x00400000) {
3906 /* two-register transfer */
3907 rn = (insn >> 16) & 0xf;
3908 rd = (insn >> 12) & 0xf;
3909 if (dp) {
3910 VFP_DREG_M(rm, insn);
3911 } else {
3912 rm = VFP_SREG_M(insn);
3913 }
3914
3915 if (insn & ARM_CP_RW_BIT) {
3916 /* vfp->arm */
3917 if (dp) {
3918 gen_mov_F0_vreg(0, rm * 2);
3919 tmp = gen_vfp_mrs();
3920 store_reg(s, rd, tmp);
3921 gen_mov_F0_vreg(0, rm * 2 + 1);
3922 tmp = gen_vfp_mrs();
3923 store_reg(s, rn, tmp);
3924 } else {
3925 gen_mov_F0_vreg(0, rm);
3926 tmp = gen_vfp_mrs();
3927 store_reg(s, rd, tmp);
3928 gen_mov_F0_vreg(0, rm + 1);
3929 tmp = gen_vfp_mrs();
3930 store_reg(s, rn, tmp);
3931 }
3932 } else {
3933 /* arm->vfp */
3934 if (dp) {
3935 tmp = load_reg(s, rd);
3936 gen_vfp_msr(tmp);
3937 gen_mov_vreg_F0(0, rm * 2);
3938 tmp = load_reg(s, rn);
3939 gen_vfp_msr(tmp);
3940 gen_mov_vreg_F0(0, rm * 2 + 1);
3941 } else {
3942 tmp = load_reg(s, rd);
3943 gen_vfp_msr(tmp);
3944 gen_mov_vreg_F0(0, rm);
3945 tmp = load_reg(s, rn);
3946 gen_vfp_msr(tmp);
3947 gen_mov_vreg_F0(0, rm + 1);
3948 }
3949 }
3950 } else {
3951 /* Load/store */
3952 rn = (insn >> 16) & 0xf;
3953 if (dp)
3954 VFP_DREG_D(rd, insn);
3955 else
3956 rd = VFP_SREG_D(insn);
3957 if ((insn & 0x01200000) == 0x01000000) {
3958 /* Single load/store */
3959 offset = (insn & 0xff) << 2;
3960 if ((insn & (1 << 23)) == 0)
3961 offset = -offset;
3962 if (s->thumb && rn == 15) {
3963 /* This is actually UNPREDICTABLE */
3964 addr = tcg_temp_new_i32();
3965 tcg_gen_movi_i32(addr, s->pc & ~2);
3966 } else {
3967 addr = load_reg(s, rn);
3968 }
3969 tcg_gen_addi_i32(addr, addr, offset);
3970 if (insn & (1 << 20)) {
3971 gen_vfp_ld(s, dp, addr);
3972 gen_mov_vreg_F0(dp, rd);
3973 } else {
3974 gen_mov_F0_vreg(dp, rd);
3975 gen_vfp_st(s, dp, addr);
3976 }
3977 tcg_temp_free_i32(addr);
3978 } else {
3979 /* load/store multiple */
3980 int w = insn & (1 << 21);
3981 if (dp)
3982 n = (insn >> 1) & 0x7f;
3983 else
3984 n = insn & 0xff;
3985
3986 if (w && !(((insn >> 23) ^ (insn >> 24)) & 1)) {
3987 /* P == U , W == 1 => UNDEF */
3988 return 1;
3989 }
3990 if (n == 0 || (rd + n) > 32 || (dp && n > 16)) {
3991 /* UNPREDICTABLE cases for bad immediates: we choose to
3992 * UNDEF to avoid generating huge numbers of TCG ops
3993 */
3994 return 1;
3995 }
3996 if (rn == 15 && w) {
3997 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
3998 return 1;
3999 }
4000
4001 if (s->thumb && rn == 15) {
4002 /* This is actually UNPREDICTABLE */
4003 addr = tcg_temp_new_i32();
4004 tcg_gen_movi_i32(addr, s->pc & ~2);
4005 } else {
4006 addr = load_reg(s, rn);
4007 }
4008 if (insn & (1 << 24)) /* pre-decrement */
4009 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
4010
4011 if (dp)
4012 offset = 8;
4013 else
4014 offset = 4;
4015 for (i = 0; i < n; i++) {
4016 if (insn & ARM_CP_RW_BIT) {
4017 /* load */
4018 gen_vfp_ld(s, dp, addr);
4019 gen_mov_vreg_F0(dp, rd + i);
4020 } else {
4021 /* store */
4022 gen_mov_F0_vreg(dp, rd + i);
4023 gen_vfp_st(s, dp, addr);
4024 }
4025 tcg_gen_addi_i32(addr, addr, offset);
4026 }
4027 if (w) {
4028 /* writeback */
4029 if (insn & (1 << 24))
4030 offset = -offset * n;
4031 else if (dp && (insn & 1))
4032 offset = 4;
4033 else
4034 offset = 0;
4035
4036 if (offset != 0)
4037 tcg_gen_addi_i32(addr, addr, offset);
4038 store_reg(s, rn, addr);
4039 } else {
4040 tcg_temp_free_i32(addr);
4041 }
4042 }
4043 }
4044 break;
4045 default:
4046 /* Should never happen. */
4047 return 1;
4048 }
4049 return 0;
4050 }
4051
4052 static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
4053 {
4054 TranslationBlock *tb;
4055
4056 tb = s->tb;
4057 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
4058 tcg_gen_goto_tb(n);
4059 gen_set_pc_im(s, dest);
4060 tcg_gen_exit_tb((uintptr_t)tb + n);
4061 } else {
4062 gen_set_pc_im(s, dest);
4063 tcg_gen_exit_tb(0);
4064 }
4065 }
4066
4067 static inline void gen_jmp (DisasContext *s, uint32_t dest)
4068 {
4069 if (unlikely(s->singlestep_enabled || s->ss_active)) {
4070 /* An indirect jump so that we still trigger the debug exception. */
4071 if (s->thumb)
4072 dest |= 1;
4073 gen_bx_im(s, dest);
4074 } else {
4075 gen_goto_tb(s, 0, dest);
4076 s->is_jmp = DISAS_TB_JUMP;
4077 }
4078 }
4079
4080 static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
4081 {
4082 if (x)
4083 tcg_gen_sari_i32(t0, t0, 16);
4084 else
4085 gen_sxth(t0);
4086 if (y)
4087 tcg_gen_sari_i32(t1, t1, 16);
4088 else
4089 gen_sxth(t1);
4090 tcg_gen_mul_i32(t0, t0, t1);
4091 }
4092
4093 /* Return the mask of PSR bits set by a MSR instruction. */
4094 static uint32_t msr_mask(DisasContext *s, int flags, int spsr)
4095 {
4096 uint32_t mask;
4097
4098 mask = 0;
4099 if (flags & (1 << 0))
4100 mask |= 0xff;
4101 if (flags & (1 << 1))
4102 mask |= 0xff00;
4103 if (flags & (1 << 2))
4104 mask |= 0xff0000;
4105 if (flags & (1 << 3))
4106 mask |= 0xff000000;
4107
4108 /* Mask out undefined bits. */
4109 mask &= ~CPSR_RESERVED;
4110 if (!arm_dc_feature(s, ARM_FEATURE_V4T)) {
4111 mask &= ~CPSR_T;
4112 }
4113 if (!arm_dc_feature(s, ARM_FEATURE_V5)) {
4114 mask &= ~CPSR_Q; /* V5TE in reality*/
4115 }
4116 if (!arm_dc_feature(s, ARM_FEATURE_V6)) {
4117 mask &= ~(CPSR_E | CPSR_GE);
4118 }
4119 if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
4120 mask &= ~CPSR_IT;
4121 }
4122 /* Mask out execution state and reserved bits. */
4123 if (!spsr) {
4124 mask &= ~(CPSR_EXEC | CPSR_RESERVED);
4125 }
4126 /* Mask out privileged bits. */
4127 if (IS_USER(s))
4128 mask &= CPSR_USER;
4129 return mask;
4130 }
4131
4132 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
4133 static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv_i32 t0)
4134 {
4135 TCGv_i32 tmp;
4136 if (spsr) {
4137 /* ??? This is also undefined in system mode. */
4138 if (IS_USER(s))
4139 return 1;
4140
4141 tmp = load_cpu_field(spsr);
4142 tcg_gen_andi_i32(tmp, tmp, ~mask);
4143 tcg_gen_andi_i32(t0, t0, mask);
4144 tcg_gen_or_i32(tmp, tmp, t0);
4145 store_cpu_field(tmp, spsr);
4146 } else {
4147 gen_set_cpsr(t0, mask);
4148 }
4149 tcg_temp_free_i32(t0);
4150 gen_lookup_tb(s);
4151 return 0;
4152 }
4153
4154 /* Returns nonzero if access to the PSR is not permitted. */
4155 static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
4156 {
4157 TCGv_i32 tmp;
4158 tmp = tcg_temp_new_i32();
4159 tcg_gen_movi_i32(tmp, val);
4160 return gen_set_psr(s, mask, spsr, tmp);
4161 }
4162
4163 /* Generate an old-style exception return. Marks pc as dead. */
4164 static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
4165 {
4166 TCGv_i32 tmp;
4167 store_reg(s, 15, pc);
4168 tmp = load_cpu_field(spsr);
4169 gen_helper_cpsr_write_eret(cpu_env, tmp);
4170 tcg_temp_free_i32(tmp);
4171 s->is_jmp = DISAS_JUMP;
4172 }
4173
4174 /* Generate a v6 exception return. Marks both values as dead. */
4175 static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)
4176 {
4177 gen_helper_cpsr_write_eret(cpu_env, cpsr);
4178 tcg_temp_free_i32(cpsr);
4179 store_reg(s, 15, pc);
4180 s->is_jmp = DISAS_JUMP;
4181 }
4182
4183 static void gen_nop_hint(DisasContext *s, int val)
4184 {
4185 switch (val) {
4186 case 1: /* yield */
4187 gen_set_pc_im(s, s->pc);
4188 s->is_jmp = DISAS_YIELD;
4189 break;
4190 case 3: /* wfi */
4191 gen_set_pc_im(s, s->pc);
4192 s->is_jmp = DISAS_WFI;
4193 break;
4194 case 2: /* wfe */
4195 gen_set_pc_im(s, s->pc);
4196 s->is_jmp = DISAS_WFE;
4197 break;
4198 case 4: /* sev */
4199 case 5: /* sevl */
4200 /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */
4201 default: /* nop */
4202 break;
4203 }
4204 }
4205
4206 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
4207
4208 static inline void gen_neon_add(int size, TCGv_i32 t0, TCGv_i32 t1)
4209 {
4210 switch (size) {
4211 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
4212 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
4213 case 2: tcg_gen_add_i32(t0, t0, t1); break;
4214 default: abort();
4215 }
4216 }
4217
4218 static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
4219 {
4220 switch (size) {
4221 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
4222 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
4223 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
4224 default: return;
4225 }
4226 }
4227
4228 /* 32-bit pairwise ops end up the same as the elementwise versions. */
4229 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
4230 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
4231 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
4232 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
4233
4234 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
4235 switch ((size << 1) | u) { \
4236 case 0: \
4237 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
4238 break; \
4239 case 1: \
4240 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
4241 break; \
4242 case 2: \
4243 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
4244 break; \
4245 case 3: \
4246 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
4247 break; \
4248 case 4: \
4249 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
4250 break; \
4251 case 5: \
4252 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
4253 break; \
4254 default: return 1; \
4255 }} while (0)
4256
4257 #define GEN_NEON_INTEGER_OP(name) do { \
4258 switch ((size << 1) | u) { \
4259 case 0: \
4260 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
4261 break; \
4262 case 1: \
4263 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
4264 break; \
4265 case 2: \
4266 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
4267 break; \
4268 case 3: \
4269 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
4270 break; \
4271 case 4: \
4272 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
4273 break; \
4274 case 5: \
4275 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
4276 break; \
4277 default: return 1; \
4278 }} while (0)
4279
4280 static TCGv_i32 neon_load_scratch(int scratch)
4281 {
4282 TCGv_i32 tmp = tcg_temp_new_i32();
4283 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
4284 return tmp;
4285 }
4286
4287 static void neon_store_scratch(int scratch, TCGv_i32 var)
4288 {
4289 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
4290 tcg_temp_free_i32(var);
4291 }
4292
4293 static inline TCGv_i32 neon_get_scalar(int size, int reg)
4294 {
4295 TCGv_i32 tmp;
4296 if (size == 1) {
4297 tmp = neon_load_reg(reg & 7, reg >> 4);
4298 if (reg & 8) {
4299 gen_neon_dup_high16(tmp);
4300 } else {
4301 gen_neon_dup_low16(tmp);
4302 }
4303 } else {
4304 tmp = neon_load_reg(reg & 15, reg >> 4);
4305 }
4306 return tmp;
4307 }
4308
4309 static int gen_neon_unzip(int rd, int rm, int size, int q)
4310 {
4311 TCGv_i32 tmp, tmp2;
4312 if (!q && size == 2) {
4313 return 1;
4314 }
4315 tmp = tcg_const_i32(rd);
4316 tmp2 = tcg_const_i32(rm);
4317 if (q) {
4318 switch (size) {
4319 case 0:
4320 gen_helper_neon_qunzip8(cpu_env, tmp, tmp2);
4321 break;
4322 case 1:
4323 gen_helper_neon_qunzip16(cpu_env, tmp, tmp2);
4324 break;
4325 case 2:
4326 gen_helper_neon_qunzip32(cpu_env, tmp, tmp2);
4327 break;
4328 default:
4329 abort();
4330 }
4331 } else {
4332 switch (size) {
4333 case 0:
4334 gen_helper_neon_unzip8(cpu_env, tmp, tmp2);
4335 break;
4336 case 1:
4337 gen_helper_neon_unzip16(cpu_env, tmp, tmp2);
4338 break;
4339 default:
4340 abort();
4341 }
4342 }
4343 tcg_temp_free_i32(tmp);
4344 tcg_temp_free_i32(tmp2);
4345 return 0;
4346 }
4347
4348 static int gen_neon_zip(int rd, int rm, int size, int q)
4349 {
4350 TCGv_i32 tmp, tmp2;
4351 if (!q && size == 2) {
4352 return 1;
4353 }
4354 tmp = tcg_const_i32(rd);
4355 tmp2 = tcg_const_i32(rm);
4356 if (q) {
4357 switch (size) {
4358 case 0:
4359 gen_helper_neon_qzip8(cpu_env, tmp, tmp2);
4360 break;
4361 case 1:
4362 gen_helper_neon_qzip16(cpu_env, tmp, tmp2);
4363 break;
4364 case 2:
4365 gen_helper_neon_qzip32(cpu_env, tmp, tmp2);
4366 break;
4367 default:
4368 abort();
4369 }
4370 } else {
4371 switch (size) {
4372 case 0:
4373 gen_helper_neon_zip8(cpu_env, tmp, tmp2);
4374 break;
4375 case 1:
4376 gen_helper_neon_zip16(cpu_env, tmp, tmp2);
4377 break;
4378 default:
4379 abort();
4380 }
4381 }
4382 tcg_temp_free_i32(tmp);
4383 tcg_temp_free_i32(tmp2);
4384 return 0;
4385 }
4386
4387 static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
4388 {
4389 TCGv_i32 rd, tmp;
4390
4391 rd = tcg_temp_new_i32();
4392 tmp = tcg_temp_new_i32();
4393
4394 tcg_gen_shli_i32(rd, t0, 8);
4395 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
4396 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
4397 tcg_gen_or_i32(rd, rd, tmp);
4398
4399 tcg_gen_shri_i32(t1, t1, 8);
4400 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
4401 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
4402 tcg_gen_or_i32(t1, t1, tmp);
4403 tcg_gen_mov_i32(t0, rd);
4404
4405 tcg_temp_free_i32(tmp);
4406 tcg_temp_free_i32(rd);
4407 }
4408
4409 static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
4410 {
4411 TCGv_i32 rd, tmp;
4412
4413 rd = tcg_temp_new_i32();
4414 tmp = tcg_temp_new_i32();
4415
4416 tcg_gen_shli_i32(rd, t0, 16);
4417 tcg_gen_andi_i32(tmp, t1, 0xffff);
4418 tcg_gen_or_i32(rd, rd, tmp);
4419 tcg_gen_shri_i32(t1, t1, 16);
4420 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
4421 tcg_gen_or_i32(t1, t1, tmp);
4422 tcg_gen_mov_i32(t0, rd);
4423
4424 tcg_temp_free_i32(tmp);
4425 tcg_temp_free_i32(rd);
4426 }
4427
4428
4429 static struct {
4430 int nregs;
4431 int interleave;
4432 int spacing;
4433 } neon_ls_element_type[11] = {
4434 {4, 4, 1},
4435 {4, 4, 2},
4436 {4, 1, 1},
4437 {4, 2, 1},
4438 {3, 3, 1},
4439 {3, 3, 2},
4440 {3, 1, 1},
4441 {1, 1, 1},
4442 {2, 2, 1},
4443 {2, 2, 2},
4444 {2, 1, 1}
4445 };
4446
4447 /* Translate a NEON load/store element instruction. Return nonzero if the
4448 instruction is invalid. */
4449 static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
4450 {
4451 int rd, rn, rm;
4452 int op;
4453 int nregs;
4454 int interleave;
4455 int spacing;
4456 int stride;
4457 int size;
4458 int reg;
4459 int pass;
4460 int load;
4461 int shift;
4462 int n;
4463 TCGv_i32 addr;
4464 TCGv_i32 tmp;
4465 TCGv_i32 tmp2;
4466 TCGv_i64 tmp64;
4467
4468 /* FIXME: this access check should not take precedence over UNDEF
4469 * for invalid encodings; we will generate incorrect syndrome information
4470 * for attempts to execute invalid vfp/neon encodings with FP disabled.
4471 */
4472 if (s->fp_excp_el) {
4473 gen_exception_insn(s, 4, EXCP_UDEF,
4474 syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
4475 return 0;
4476 }
4477
4478 if (!s->vfp_enabled)
4479 return 1;
4480 VFP_DREG_D(rd, insn);
4481 rn = (insn >> 16) & 0xf;
4482 rm = insn & 0xf;
4483 load = (insn & (1 << 21)) != 0;
4484 if ((insn & (1 << 23)) == 0) {
4485 /* Load store all elements. */
4486 op = (insn >> 8) & 0xf;
4487 size = (insn >> 6) & 3;
4488 if (op > 10)
4489 return 1;
4490 /* Catch UNDEF cases for bad values of align field */
4491 switch (op & 0xc) {
4492 case 4:
4493 if (((insn >> 5) & 1) == 1) {
4494 return 1;
4495 }
4496 break;
4497 case 8:
4498 if (((insn >> 4) & 3) == 3) {
4499 return 1;
4500 }
4501 break;
4502 default:
4503 break;
4504 }
4505 nregs = neon_ls_element_type[op].nregs;
4506 interleave = neon_ls_element_type[op].interleave;
4507 spacing = neon_ls_element_type[op].spacing;
4508 if (size == 3 && (interleave | spacing) != 1)
4509 return 1;
4510 addr = tcg_temp_new_i32();
4511 load_reg_var(s, addr, rn);
4512 stride = (1 << size) * interleave;
4513 for (reg = 0; reg < nregs; reg++) {
4514 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
4515 load_reg_var(s, addr, rn);
4516 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
4517 } else if (interleave == 2 && nregs == 4 && reg == 2) {
4518 load_reg_var(s, addr, rn);
4519 tcg_gen_addi_i32(addr, addr, 1 << size);
4520 }
4521 if (size == 3) {
4522 tmp64 = tcg_temp_new_i64();
4523 if (load) {
4524 gen_aa32_ld64(s, tmp64, addr, get_mem_index(s));
4525 neon_store_reg64(tmp64, rd);
4526 } else {
4527 neon_load_reg64(tmp64, rd);
4528 gen_aa32_st64(s, tmp64, addr, get_mem_index(s));
4529 }
4530 tcg_temp_free_i64(tmp64);
4531 tcg_gen_addi_i32(addr, addr, stride);
4532 } else {
4533 for (pass = 0; pass < 2; pass++) {
4534 if (size == 2) {
4535 if (load) {
4536 tmp = tcg_temp_new_i32();
4537 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
4538 neon_store_reg(rd, pass, tmp);
4539 } else {
4540 tmp = neon_load_reg(rd, pass);
4541 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
4542 tcg_temp_free_i32(tmp);
4543 }
4544 tcg_gen_addi_i32(addr, addr, stride);
4545 } else if (size == 1) {
4546 if (load) {
4547 tmp = tcg_temp_new_i32();
4548 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
4549 tcg_gen_addi_i32(addr, addr, stride);
4550 tmp2 = tcg_temp_new_i32();
4551 gen_aa32_ld16u(s, tmp2, addr, get_mem_index(s));
4552 tcg_gen_addi_i32(addr, addr, stride);
4553 tcg_gen_shli_i32(tmp2, tmp2, 16);
4554 tcg_gen_or_i32(tmp, tmp, tmp2);
4555 tcg_temp_free_i32(tmp2);
4556 neon_store_reg(rd, pass, tmp);
4557 } else {
4558 tmp = neon_load_reg(rd, pass);
4559 tmp2 = tcg_temp_new_i32();
4560 tcg_gen_shri_i32(tmp2, tmp, 16);
4561 gen_aa32_st16(s, tmp, addr, get_mem_index(s));
4562 tcg_temp_free_i32(tmp);
4563 tcg_gen_addi_i32(addr, addr, stride);
4564 gen_aa32_st16(s, tmp2, addr, get_mem_index(s));
4565 tcg_temp_free_i32(tmp2);
4566 tcg_gen_addi_i32(addr, addr, stride);
4567 }
4568 } else /* size == 0 */ {
4569 if (load) {
4570 TCGV_UNUSED_I32(tmp2);
4571 for (n = 0; n < 4; n++) {
4572 tmp = tcg_temp_new_i32();
4573 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
4574 tcg_gen_addi_i32(addr, addr, stride);
4575 if (n == 0) {
4576 tmp2 = tmp;
4577 } else {
4578 tcg_gen_shli_i32(tmp, tmp, n * 8);
4579 tcg_gen_or_i32(tmp2, tmp2, tmp);
4580 tcg_temp_free_i32(tmp);
4581 }
4582 }
4583 neon_store_reg(rd, pass, tmp2);
4584 } else {
4585 tmp2 = neon_load_reg(rd, pass);
4586 for (n = 0; n < 4; n++) {
4587 tmp = tcg_temp_new_i32();
4588 if (n == 0) {
4589 tcg_gen_mov_i32(tmp, tmp2);
4590 } else {
4591 tcg_gen_shri_i32(tmp, tmp2, n * 8);
4592 }
4593 gen_aa32_st8(s, tmp, addr, get_mem_index(s));
4594 tcg_temp_free_i32(tmp);
4595 tcg_gen_addi_i32(addr, addr, stride);
4596 }
4597 tcg_temp_free_i32(tmp2);
4598 }
4599 }
4600 }
4601 }
4602 rd += spacing;
4603 }
4604 tcg_temp_free_i32(addr);
4605 stride = nregs * 8;
4606 } else {
4607 size = (insn >> 10) & 3;
4608 if (size == 3) {
4609 /* Load single element to all lanes. */
4610 int a = (insn >> 4) & 1;
4611 if (!load) {
4612 return 1;
4613 }
4614 size = (insn >> 6) & 3;
4615 nregs = ((insn >> 8) & 3) + 1;
4616
4617 if (size == 3) {
4618 if (nregs != 4 || a == 0) {
4619 return 1;
4620 }
4621 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
4622 size = 2;
4623 }
4624 if (nregs == 1 && a == 1 && size == 0) {
4625 return 1;
4626 }
4627 if (nregs == 3 && a == 1) {
4628 return 1;
4629 }
4630 addr = tcg_temp_new_i32();
4631 load_reg_var(s, addr, rn);
4632 if (nregs == 1) {
4633 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
4634 tmp = gen_load_and_replicate(s, addr, size);
4635 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
4636 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
4637 if (insn & (1 << 5)) {
4638 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0));
4639 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1));
4640 }
4641 tcg_temp_free_i32(tmp);
4642 } else {
4643 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
4644 stride = (insn & (1 << 5)) ? 2 : 1;
4645 for (reg = 0; reg < nregs; reg++) {
4646 tmp = gen_load_and_replicate(s, addr, size);
4647 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
4648 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
4649 tcg_temp_free_i32(tmp);
4650 tcg_gen_addi_i32(addr, addr, 1 << size);
4651 rd += stride;
4652 }
4653 }
4654 tcg_temp_free_i32(addr);
4655 stride = (1 << size) * nregs;
4656 } else {
4657 /* Single element. */
4658 int idx = (insn >> 4) & 0xf;
4659 pass = (insn >> 7) & 1;
4660 switch (size) {
4661 case 0:
4662 shift = ((insn >> 5) & 3) * 8;
4663 stride = 1;
4664 break;
4665 case 1:
4666 shift = ((insn >> 6) & 1) * 16;
4667 stride = (insn & (1 << 5)) ? 2 : 1;
4668 break;
4669 case 2:
4670 shift = 0;
4671 stride = (insn & (1 << 6)) ? 2 : 1;
4672 break;
4673 default:
4674 abort();
4675 }
4676 nregs = ((insn >> 8) & 3) + 1;
4677 /* Catch the UNDEF cases. This is unavoidably a bit messy. */
4678 switch (nregs) {
4679 case 1:
4680 if (((idx & (1 << size)) != 0) ||
4681 (size == 2 && ((idx & 3) == 1 || (idx & 3) == 2))) {
4682 return 1;
4683 }
4684 break;
4685 case 3:
4686 if ((idx & 1) != 0) {
4687 return 1;
4688 }
4689 /* fall through */
4690 case 2:
4691 if (size == 2 && (idx & 2) != 0) {
4692 return 1;
4693 }
4694 break;
4695 case 4:
4696 if ((size == 2) && ((idx & 3) == 3)) {
4697 return 1;
4698 }
4699 break;
4700 default:
4701 abort();
4702 }
4703 if ((rd + stride * (nregs - 1)) > 31) {
4704 /* Attempts to write off the end of the register file
4705 * are UNPREDICTABLE; we choose to UNDEF because otherwise
4706 * the neon_load_reg() would write off the end of the array.
4707 */
4708 return 1;
4709 }
4710 addr = tcg_temp_new_i32();
4711 load_reg_var(s, addr, rn);
4712 for (reg = 0; reg < nregs; reg++) {
4713 if (load) {
4714 tmp = tcg_temp_new_i32();
4715 switch (size) {
4716 case 0:
4717 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
4718 break;
4719 case 1:
4720 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
4721 break;
4722 case 2:
4723 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
4724 break;
4725 default: /* Avoid compiler warnings. */
4726 abort();
4727 }
4728 if (size != 2) {
4729 tmp2 = neon_load_reg(rd, pass);
4730 tcg_gen_deposit_i32(tmp, tmp2, tmp,
4731 shift, size ? 16 : 8);
4732 tcg_temp_free_i32(tmp2);
4733 }
4734 neon_store_reg(rd, pass, tmp);
4735 } else { /* Store */
4736 tmp = neon_load_reg(rd, pass);
4737 if (shift)
4738 tcg_gen_shri_i32(tmp, tmp, shift);
4739 switch (size) {
4740 case 0:
4741 gen_aa32_st8(s, tmp, addr, get_mem_index(s));
4742 break;
4743 case 1:
4744 gen_aa32_st16(s, tmp, addr, get_mem_index(s));
4745 break;
4746 case 2:
4747 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
4748 break;
4749 }
4750 tcg_temp_free_i32(tmp);
4751 }
4752 rd += stride;
4753 tcg_gen_addi_i32(addr, addr, 1 << size);
4754 }
4755 tcg_temp_free_i32(addr);
4756 stride = nregs * (1 << size);
4757 }
4758 }
4759 if (rm != 15) {
4760 TCGv_i32 base;
4761
4762 base = load_reg(s, rn);
4763 if (rm == 13) {
4764 tcg_gen_addi_i32(base, base, stride);
4765 } else {
4766 TCGv_i32 index;
4767 index = load_reg(s, rm);
4768 tcg_gen_add_i32(base, base, index);
4769 tcg_temp_free_i32(index);
4770 }
4771 store_reg(s, rn, base);
4772 }
4773 return 0;
4774 }
4775
4776 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4777 static void gen_neon_bsl(TCGv_i32 dest, TCGv_i32 t, TCGv_i32 f, TCGv_i32 c)
4778 {
4779 tcg_gen_and_i32(t, t, c);
4780 tcg_gen_andc_i32(f, f, c);
4781 tcg_gen_or_i32(dest, t, f);
4782 }
4783
4784 static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
4785 {
4786 switch (size) {
4787 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4788 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4789 case 2: tcg_gen_extrl_i64_i32(dest, src); break;
4790 default: abort();
4791 }
4792 }
4793
4794 static inline void gen_neon_narrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
4795 {
4796 switch (size) {
4797 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4798 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4799 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4800 default: abort();
4801 }
4802 }
4803
4804 static inline void gen_neon_narrow_satu(int size, TCGv_i32 dest, TCGv_i64 src)
4805 {
4806 switch (size) {
4807 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4808 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4809 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4810 default: abort();
4811 }
4812 }
4813
4814 static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
4815 {
4816 switch (size) {
4817 case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break;
4818 case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break;
4819 case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break;
4820 default: abort();
4821 }
4822 }
4823
4824 static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
4825 int q, int u)
4826 {
4827 if (q) {
4828 if (u) {
4829 switch (size) {
4830 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4831 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4832 default: abort();
4833 }
4834 } else {
4835 switch (size) {
4836 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4837 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4838 default: abort();
4839 }
4840 }
4841 } else {
4842 if (u) {
4843 switch (size) {
4844 case 1: gen_helper_neon_shl_u16(var, var, shift); break;
4845 case 2: gen_helper_neon_shl_u32(var, var, shift); break;
4846 default: abort();
4847 }
4848 } else {
4849 switch (size) {
4850 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4851 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4852 default: abort();
4853 }
4854 }
4855 }
4856 }
4857
4858 static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
4859 {
4860 if (u) {
4861 switch (size) {
4862 case 0: gen_helper_neon_widen_u8(dest, src); break;
4863 case 1: gen_helper_neon_widen_u16(dest, src); break;
4864 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4865 default: abort();
4866 }
4867 } else {
4868 switch (size) {
4869 case 0: gen_helper_neon_widen_s8(dest, src); break;
4870 case 1: gen_helper_neon_widen_s16(dest, src); break;
4871 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4872 default: abort();
4873 }
4874 }
4875 tcg_temp_free_i32(src);
4876 }
4877
4878 static inline void gen_neon_addl(int size)
4879 {
4880 switch (size) {
4881 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4882 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4883 case 2: tcg_gen_add_i64(CPU_V001); break;
4884 default: abort();
4885 }
4886 }
4887
4888 static inline void gen_neon_subl(int size)
4889 {
4890 switch (size) {
4891 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4892 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4893 case 2: tcg_gen_sub_i64(CPU_V001); break;
4894 default: abort();
4895 }
4896 }
4897
4898 static inline void gen_neon_negl(TCGv_i64 var, int size)
4899 {
4900 switch (size) {
4901 case 0: gen_helper_neon_negl_u16(var, var); break;
4902 case 1: gen_helper_neon_negl_u32(var, var); break;
4903 case 2:
4904 tcg_gen_neg_i64(var, var);
4905 break;
4906 default: abort();
4907 }
4908 }
4909
4910 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4911 {
4912 switch (size) {
4913 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4914 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4915 default: abort();
4916 }
4917 }
4918
4919 static inline void gen_neon_mull(TCGv_i64 dest, TCGv_i32 a, TCGv_i32 b,
4920 int size, int u)
4921 {
4922 TCGv_i64 tmp;
4923
4924 switch ((size << 1) | u) {
4925 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4926 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4927 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4928 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4929 case 4:
4930 tmp = gen_muls_i64_i32(a, b);
4931 tcg_gen_mov_i64(dest, tmp);
4932 tcg_temp_free_i64(tmp);
4933 break;
4934 case 5:
4935 tmp = gen_mulu_i64_i32(a, b);
4936 tcg_gen_mov_i64(dest, tmp);
4937 tcg_temp_free_i64(tmp);
4938 break;
4939 default: abort();
4940 }
4941
4942 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4943 Don't forget to clean them now. */
4944 if (size < 2) {
4945 tcg_temp_free_i32(a);
4946 tcg_temp_free_i32(b);
4947 }
4948 }
4949
4950 static void gen_neon_narrow_op(int op, int u, int size,
4951 TCGv_i32 dest, TCGv_i64 src)
4952 {
4953 if (op) {
4954 if (u) {
4955 gen_neon_unarrow_sats(size, dest, src);
4956 } else {
4957 gen_neon_narrow(size, dest, src);
4958 }
4959 } else {
4960 if (u) {
4961 gen_neon_narrow_satu(size, dest, src);
4962 } else {
4963 gen_neon_narrow_sats(size, dest, src);
4964 }
4965 }
4966 }
4967
4968 /* Symbolic constants for op fields for Neon 3-register same-length.
4969 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
4970 * table A7-9.
4971 */
4972 #define NEON_3R_VHADD 0
4973 #define NEON_3R_VQADD 1
4974 #define NEON_3R_VRHADD 2
4975 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
4976 #define NEON_3R_VHSUB 4
4977 #define NEON_3R_VQSUB 5
4978 #define NEON_3R_VCGT 6
4979 #define NEON_3R_VCGE 7
4980 #define NEON_3R_VSHL 8
4981 #define NEON_3R_VQSHL 9
4982 #define NEON_3R_VRSHL 10
4983 #define NEON_3R_VQRSHL 11
4984 #define NEON_3R_VMAX 12
4985 #define NEON_3R_VMIN 13
4986 #define NEON_3R_VABD 14
4987 #define NEON_3R_VABA 15
4988 #define NEON_3R_VADD_VSUB 16
4989 #define NEON_3R_VTST_VCEQ 17
4990 #define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
4991 #define NEON_3R_VMUL 19
4992 #define NEON_3R_VPMAX 20
4993 #define NEON_3R_VPMIN 21
4994 #define NEON_3R_VQDMULH_VQRDMULH 22
4995 #define NEON_3R_VPADD 23
4996 #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */
4997 #define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */
4998 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
4999 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
5000 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
5001 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
5002 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
5003 #define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
5004
5005 static const uint8_t neon_3r_sizes[] = {
5006 [NEON_3R_VHADD] = 0x7,
5007 [NEON_3R_VQADD] = 0xf,
5008 [NEON_3R_VRHADD] = 0x7,
5009 [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
5010 [NEON_3R_VHSUB] = 0x7,
5011 [NEON_3R_VQSUB] = 0xf,
5012 [NEON_3R_VCGT] = 0x7,
5013 [NEON_3R_VCGE] = 0x7,
5014 [NEON_3R_VSHL] = 0xf,
5015 [NEON_3R_VQSHL] = 0xf,
5016 [NEON_3R_VRSHL] = 0xf,
5017 [NEON_3R_VQRSHL] = 0xf,
5018 [NEON_3R_VMAX] = 0x7,
5019 [NEON_3R_VMIN] = 0x7,
5020 [NEON_3R_VABD] = 0x7,
5021 [NEON_3R_VABA] = 0x7,
5022 [NEON_3R_VADD_VSUB] = 0xf,
5023 [NEON_3R_VTST_VCEQ] = 0x7,
5024 [NEON_3R_VML] = 0x7,
5025 [NEON_3R_VMUL] = 0x7,
5026 [NEON_3R_VPMAX] = 0x7,
5027 [NEON_3R_VPMIN] = 0x7,
5028 [NEON_3R_VQDMULH_VQRDMULH] = 0x6,
5029 [NEON_3R_VPADD] = 0x7,
5030 [NEON_3R_SHA] = 0xf, /* size field encodes op type */
5031 [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */
5032 [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
5033 [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
5034 [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
5035 [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
5036 [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
5037 [NEON_3R_FLOAT_MISC] = 0x5, /* size bit 1 encodes op */
5038 };
5039
5040 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
5041 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
5042 * table A7-13.
5043 */
5044 #define NEON_2RM_VREV64 0
5045 #define NEON_2RM_VREV32 1
5046 #define NEON_2RM_VREV16 2
5047 #define NEON_2RM_VPADDL 4
5048 #define NEON_2RM_VPADDL_U 5
5049 #define NEON_2RM_AESE 6 /* Includes AESD */
5050 #define NEON_2RM_AESMC 7 /* Includes AESIMC */
5051 #define NEON_2RM_VCLS 8
5052 #define NEON_2RM_VCLZ 9
5053 #define NEON_2RM_VCNT 10
5054 #define NEON_2RM_VMVN 11
5055 #define NEON_2RM_VPADAL 12
5056 #define NEON_2RM_VPADAL_U 13
5057 #define NEON_2RM_VQABS 14
5058 #define NEON_2RM_VQNEG 15
5059 #define NEON_2RM_VCGT0 16
5060 #define NEON_2RM_VCGE0 17
5061 #define NEON_2RM_VCEQ0 18
5062 #define NEON_2RM_VCLE0 19
5063 #define NEON_2RM_VCLT0 20
5064 #define NEON_2RM_SHA1H 21
5065 #define NEON_2RM_VABS 22
5066 #define NEON_2RM_VNEG 23
5067 #define NEON_2RM_VCGT0_F 24
5068 #define NEON_2RM_VCGE0_F 25
5069 #define NEON_2RM_VCEQ0_F 26
5070 #define NEON_2RM_VCLE0_F 27
5071 #define NEON_2RM_VCLT0_F 28
5072 #define NEON_2RM_VABS_F 30
5073 #define NEON_2RM_VNEG_F 31
5074 #define NEON_2RM_VSWP 32
5075 #define NEON_2RM_VTRN 33
5076 #define NEON_2RM_VUZP 34
5077 #define NEON_2RM_VZIP 35
5078 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
5079 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
5080 #define NEON_2RM_VSHLL 38
5081 #define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
5082 #define NEON_2RM_VRINTN 40
5083 #define NEON_2RM_VRINTX 41
5084 #define NEON_2RM_VRINTA 42
5085 #define NEON_2RM_VRINTZ 43
5086 #define NEON_2RM_VCVT_F16_F32 44
5087 #define NEON_2RM_VRINTM 45
5088 #define NEON_2RM_VCVT_F32_F16 46
5089 #define NEON_2RM_VRINTP 47
5090 #define NEON_2RM_VCVTAU 48
5091 #define NEON_2RM_VCVTAS 49
5092 #define NEON_2RM_VCVTNU 50
5093 #define NEON_2RM_VCVTNS 51
5094 #define NEON_2RM_VCVTPU 52
5095 #define NEON_2RM_VCVTPS 53
5096 #define NEON_2RM_VCVTMU 54
5097 #define NEON_2RM_VCVTMS 55
5098 #define NEON_2RM_VRECPE 56
5099 #define NEON_2RM_VRSQRTE 57
5100 #define NEON_2RM_VRECPE_F 58
5101 #define NEON_2RM_VRSQRTE_F 59
5102 #define NEON_2RM_VCVT_FS 60
5103 #define NEON_2RM_VCVT_FU 61
5104 #define NEON_2RM_VCVT_SF 62
5105 #define NEON_2RM_VCVT_UF 63
5106
5107 static int neon_2rm_is_float_op(int op)
5108 {
5109 /* Return true if this neon 2reg-misc op is float-to-float */
5110 return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
5111 (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
5112 op == NEON_2RM_VRINTM ||
5113 (op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) ||
5114 op >= NEON_2RM_VRECPE_F);
5115 }
5116
5117 /* Each entry in this array has bit n set if the insn allows
5118 * size value n (otherwise it will UNDEF). Since unallocated
5119 * op values will have no bits set they always UNDEF.
5120 */
5121 static const uint8_t neon_2rm_sizes[] = {
5122 [NEON_2RM_VREV64] = 0x7,
5123 [NEON_2RM_VREV32] = 0x3,
5124 [NEON_2RM_VREV16] = 0x1,
5125 [NEON_2RM_VPADDL] = 0x7,
5126 [NEON_2RM_VPADDL_U] = 0x7,
5127 [NEON_2RM_AESE] = 0x1,
5128 [NEON_2RM_AESMC] = 0x1,
5129 [NEON_2RM_VCLS] = 0x7,
5130 [NEON_2RM_VCLZ] = 0x7,
5131 [NEON_2RM_VCNT] = 0x1,
5132 [NEON_2RM_VMVN] = 0x1,
5133 [NEON_2RM_VPADAL] = 0x7,
5134 [NEON_2RM_VPADAL_U] = 0x7,
5135 [NEON_2RM_VQABS] = 0x7,
5136 [NEON_2RM_VQNEG] = 0x7,
5137 [NEON_2RM_VCGT0] = 0x7,
5138 [NEON_2RM_VCGE0] = 0x7,
5139 [NEON_2RM_VCEQ0] = 0x7,
5140 [NEON_2RM_VCLE0] = 0x7,
5141 [NEON_2RM_VCLT0] = 0x7,
5142 [NEON_2RM_SHA1H] = 0x4,
5143 [NEON_2RM_VABS] = 0x7,
5144 [NEON_2RM_VNEG] = 0x7,
5145 [NEON_2RM_VCGT0_F] = 0x4,
5146 [NEON_2RM_VCGE0_F] = 0x4,
5147 [NEON_2RM_VCEQ0_F] = 0x4,
5148 [NEON_2RM_VCLE0_F] = 0x4,
5149 [NEON_2RM_VCLT0_F] = 0x4,
5150 [NEON_2RM_VABS_F] = 0x4,
5151 [NEON_2RM_VNEG_F] = 0x4,
5152 [NEON_2RM_VSWP] = 0x1,
5153 [NEON_2RM_VTRN] = 0x7,
5154 [NEON_2RM_VUZP] = 0x7,
5155 [NEON_2RM_VZIP] = 0x7,
5156 [NEON_2RM_VMOVN] = 0x7,
5157 [NEON_2RM_VQMOVN] = 0x7,
5158 [NEON_2RM_VSHLL] = 0x7,
5159 [NEON_2RM_SHA1SU1] = 0x4,
5160 [NEON_2RM_VRINTN] = 0x4,
5161 [NEON_2RM_VRINTX] = 0x4,
5162 [NEON_2RM_VRINTA] = 0x4,
5163 [NEON_2RM_VRINTZ] = 0x4,
5164 [NEON_2RM_VCVT_F16_F32] = 0x2,
5165 [NEON_2RM_VRINTM] = 0x4,
5166 [NEON_2RM_VCVT_F32_F16] = 0x2,
5167 [NEON_2RM_VRINTP] = 0x4,
5168 [NEON_2RM_VCVTAU] = 0x4,
5169 [NEON_2RM_VCVTAS] = 0x4,
5170 [NEON_2RM_VCVTNU] = 0x4,
5171 [NEON_2RM_VCVTNS] = 0x4,
5172 [NEON_2RM_VCVTPU] = 0x4,
5173 [NEON_2RM_VCVTPS] = 0x4,
5174 [NEON_2RM_VCVTMU] = 0x4,
5175 [NEON_2RM_VCVTMS] = 0x4,
5176 [NEON_2RM_VRECPE] = 0x4,
5177 [NEON_2RM_VRSQRTE] = 0x4,
5178 [NEON_2RM_VRECPE_F] = 0x4,
5179 [NEON_2RM_VRSQRTE_F] = 0x4,
5180 [NEON_2RM_VCVT_FS] = 0x4,
5181 [NEON_2RM_VCVT_FU] = 0x4,
5182 [NEON_2RM_VCVT_SF] = 0x4,
5183 [NEON_2RM_VCVT_UF] = 0x4,
5184 };
5185
5186 /* Translate a NEON data processing instruction. Return nonzero if the
5187 instruction is invalid.
5188 We process data in a mixture of 32-bit and 64-bit chunks.
5189 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
5190
5191 static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
5192 {
5193 int op;
5194 int q;
5195 int rd, rn, rm;
5196 int size;
5197 int shift;
5198 int pass;
5199 int count;
5200 int pairwise;
5201 int u;
5202 uint32_t imm, mask;
5203 TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
5204 TCGv_i64 tmp64;
5205
5206 /* FIXME: this access check should not take precedence over UNDEF
5207 * for invalid encodings; we will generate incorrect syndrome information
5208 * for attempts to execute invalid vfp/neon encodings with FP disabled.
5209 */
5210 if (s->fp_excp_el) {
5211 gen_exception_insn(s, 4, EXCP_UDEF,
5212 syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
5213 return 0;
5214 }
5215
5216 if (!s->vfp_enabled)
5217 return 1;
5218 q = (insn & (1 << 6)) != 0;
5219 u = (insn >> 24) & 1;
5220 VFP_DREG_D(rd, insn);
5221 VFP_DREG_N(rn, insn);
5222 VFP_DREG_M(rm, insn);
5223 size = (insn >> 20) & 3;
5224 if ((insn & (1 << 23)) == 0) {
5225 /* Three register same length. */
5226 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
5227 /* Catch invalid op and bad size combinations: UNDEF */
5228 if ((neon_3r_sizes[op] & (1 << size)) == 0) {
5229 return 1;
5230 }
5231 /* All insns of this form UNDEF for either this condition or the
5232 * superset of cases "Q==1"; we catch the latter later.
5233 */
5234 if (q && ((rd | rn | rm) & 1)) {
5235 return 1;
5236 }
5237 /*
5238 * The SHA-1/SHA-256 3-register instructions require special treatment
5239 * here, as their size field is overloaded as an op type selector, and
5240 * they all consume their input in a single pass.
5241 */
5242 if (op == NEON_3R_SHA) {
5243 if (!q) {
5244 return 1;
5245 }
5246 if (!u) { /* SHA-1 */
5247 if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) {
5248 return 1;
5249 }
5250 tmp = tcg_const_i32(rd);
5251 tmp2 = tcg_const_i32(rn);
5252 tmp3 = tcg_const_i32(rm);
5253 tmp4 = tcg_const_i32(size);
5254 gen_helper_crypto_sha1_3reg(cpu_env, tmp, tmp2, tmp3, tmp4);
5255 tcg_temp_free_i32(tmp4);
5256 } else { /* SHA-256 */
5257 if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256) || size == 3) {
5258 return 1;
5259 }
5260 tmp = tcg_const_i32(rd);
5261 tmp2 = tcg_const_i32(rn);
5262 tmp3 = tcg_const_i32(rm);
5263 switch (size) {
5264 case 0:
5265 gen_helper_crypto_sha256h(cpu_env, tmp, tmp2, tmp3);
5266 break;
5267 case 1:
5268 gen_helper_crypto_sha256h2(cpu_env, tmp, tmp2, tmp3);
5269 break;
5270 case 2:
5271 gen_helper_crypto_sha256su1(cpu_env, tmp, tmp2, tmp3);
5272 break;
5273 }
5274 }
5275 tcg_temp_free_i32(tmp);
5276 tcg_temp_free_i32(tmp2);
5277 tcg_temp_free_i32(tmp3);
5278 return 0;
5279 }
5280 if (size == 3 && op != NEON_3R_LOGIC) {
5281 /* 64-bit element instructions. */
5282 for (pass = 0; pass < (q ? 2 : 1); pass++) {
5283 neon_load_reg64(cpu_V0, rn + pass);
5284 neon_load_reg64(cpu_V1, rm + pass);
5285 switch (op) {
5286 case NEON_3R_VQADD:
5287 if (u) {
5288 gen_helper_neon_qadd_u64(cpu_V0, cpu_env,
5289 cpu_V0, cpu_V1);
5290 } else {
5291 gen_helper_neon_qadd_s64(cpu_V0, cpu_env,
5292 cpu_V0, cpu_V1);
5293 }
5294 break;
5295 case NEON_3R_VQSUB:
5296 if (u) {
5297 gen_helper_neon_qsub_u64(cpu_V0, cpu_env,
5298 cpu_V0, cpu_V1);
5299 } else {
5300 gen_helper_neon_qsub_s64(cpu_V0, cpu_env,
5301 cpu_V0, cpu_V1);
5302 }
5303 break;
5304 case NEON_3R_VSHL:
5305 if (u) {
5306 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
5307 } else {
5308 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
5309 }
5310 break;
5311 case NEON_3R_VQSHL:
5312 if (u) {
5313 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
5314 cpu_V1, cpu_V0);
5315 } else {
5316 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
5317 cpu_V1, cpu_V0);
5318 }
5319 break;
5320 case NEON_3R_VRSHL:
5321 if (u) {
5322 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
5323 } else {
5324 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
5325 }
5326 break;
5327 case NEON_3R_VQRSHL:
5328 if (u) {
5329 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
5330 cpu_V1, cpu_V0);
5331 } else {
5332 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
5333 cpu_V1, cpu_V0);
5334 }
5335 break;
5336 case NEON_3R_VADD_VSUB:
5337 if (u) {
5338 tcg_gen_sub_i64(CPU_V001);
5339 } else {
5340 tcg_gen_add_i64(CPU_V001);
5341 }
5342 break;
5343 default:
5344 abort();
5345 }
5346 neon_store_reg64(cpu_V0, rd + pass);
5347 }
5348 return 0;
5349 }
5350 pairwise = 0;
5351 switch (op) {
5352 case NEON_3R_VSHL:
5353 case NEON_3R_VQSHL:
5354 case NEON_3R_VRSHL:
5355 case NEON_3R_VQRSHL:
5356 {
5357 int rtmp;
5358 /* Shift instruction operands are reversed. */
5359 rtmp = rn;
5360 rn = rm;
5361 rm = rtmp;
5362 }
5363 break;
5364 case NEON_3R_VPADD:
5365 if (u) {
5366 return 1;
5367 }
5368 /* Fall through */
5369 case NEON_3R_VPMAX:
5370 case NEON_3R_VPMIN:
5371 pairwise = 1;
5372 break;
5373 case NEON_3R_FLOAT_ARITH:
5374 pairwise = (u && size < 2); /* if VPADD (float) */
5375 break;
5376 case NEON_3R_FLOAT_MINMAX:
5377 pairwise = u; /* if VPMIN/VPMAX (float) */
5378 break;
5379 case NEON_3R_FLOAT_CMP:
5380 if (!u && size) {
5381 /* no encoding for U=0 C=1x */
5382 return 1;
5383 }
5384 break;
5385 case NEON_3R_FLOAT_ACMP:
5386 if (!u) {
5387 return 1;
5388 }
5389 break;
5390 case NEON_3R_FLOAT_MISC:
5391 /* VMAXNM/VMINNM in ARMv8 */
5392 if (u && !arm_dc_feature(s, ARM_FEATURE_V8)) {
5393 return 1;
5394 }
5395 break;
5396 case NEON_3R_VMUL:
5397 if (u && (size != 0)) {
5398 /* UNDEF on invalid size for polynomial subcase */
5399 return 1;
5400 }
5401 break;
5402 case NEON_3R_VFM:
5403 if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) {
5404 return 1;
5405 }
5406 break;
5407 default:
5408 break;
5409 }
5410
5411 if (pairwise && q) {
5412 /* All the pairwise insns UNDEF if Q is set */
5413 return 1;
5414 }
5415
5416 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5417
5418 if (pairwise) {
5419 /* Pairwise. */
5420 if (pass < 1) {
5421 tmp = neon_load_reg(rn, 0);
5422 tmp2 = neon_load_reg(rn, 1);
5423 } else {
5424 tmp = neon_load_reg(rm, 0);
5425 tmp2 = neon_load_reg(rm, 1);
5426 }
5427 } else {
5428 /* Elementwise. */
5429 tmp = neon_load_reg(rn, pass);
5430 tmp2 = neon_load_reg(rm, pass);
5431 }
5432 switch (op) {
5433 case NEON_3R_VHADD:
5434 GEN_NEON_INTEGER_OP(hadd);
5435 break;
5436 case NEON_3R_VQADD:
5437 GEN_NEON_INTEGER_OP_ENV(qadd);
5438 break;
5439 case NEON_3R_VRHADD:
5440 GEN_NEON_INTEGER_OP(rhadd);
5441 break;
5442 case NEON_3R_LOGIC: /* Logic ops. */
5443 switch ((u << 2) | size) {
5444 case 0: /* VAND */
5445 tcg_gen_and_i32(tmp, tmp, tmp2);
5446 break;
5447 case 1: /* BIC */
5448 tcg_gen_andc_i32(tmp, tmp, tmp2);
5449 break;
5450 case 2: /* VORR */
5451 tcg_gen_or_i32(tmp, tmp, tmp2);
5452 break;
5453 case 3: /* VORN */
5454 tcg_gen_orc_i32(tmp, tmp, tmp2);
5455 break;
5456 case 4: /* VEOR */
5457 tcg_gen_xor_i32(tmp, tmp, tmp2);
5458 break;
5459 case 5: /* VBSL */
5460 tmp3 = neon_load_reg(rd, pass);
5461 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
5462 tcg_temp_free_i32(tmp3);
5463 break;
5464 case 6: /* VBIT */
5465 tmp3 = neon_load_reg(rd, pass);
5466 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
5467 tcg_temp_free_i32(tmp3);
5468 break;
5469 case 7: /* VBIF */
5470 tmp3 = neon_load_reg(rd, pass);
5471 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
5472 tcg_temp_free_i32(tmp3);
5473 break;
5474 }
5475 break;
5476 case NEON_3R_VHSUB:
5477 GEN_NEON_INTEGER_OP(hsub);
5478 break;
5479 case NEON_3R_VQSUB:
5480 GEN_NEON_INTEGER_OP_ENV(qsub);
5481 break;
5482 case NEON_3R_VCGT:
5483 GEN_NEON_INTEGER_OP(cgt);
5484 break;
5485 case NEON_3R_VCGE:
5486 GEN_NEON_INTEGER_OP(cge);
5487 break;
5488 case NEON_3R_VSHL:
5489 GEN_NEON_INTEGER_OP(shl);
5490 break;
5491 case NEON_3R_VQSHL:
5492 GEN_NEON_INTEGER_OP_ENV(qshl);
5493 break;
5494 case NEON_3R_VRSHL:
5495 GEN_NEON_INTEGER_OP(rshl);
5496 break;
5497 case NEON_3R_VQRSHL:
5498 GEN_NEON_INTEGER_OP_ENV(qrshl);
5499 break;
5500 case NEON_3R_VMAX:
5501 GEN_NEON_INTEGER_OP(max);
5502 break;
5503 case NEON_3R_VMIN:
5504 GEN_NEON_INTEGER_OP(min);
5505 break;
5506 case NEON_3R_VABD:
5507 GEN_NEON_INTEGER_OP(abd);
5508 break;
5509 case NEON_3R_VABA:
5510 GEN_NEON_INTEGER_OP(abd);
5511 tcg_temp_free_i32(tmp2);
5512 tmp2 = neon_load_reg(rd, pass);
5513 gen_neon_add(size, tmp, tmp2);
5514 break;
5515 case NEON_3R_VADD_VSUB:
5516 if (!u) { /* VADD */
5517 gen_neon_add(size, tmp, tmp2);
5518 } else { /* VSUB */
5519 switch (size) {
5520 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
5521 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
5522 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
5523 default: abort();
5524 }
5525 }
5526 break;
5527 case NEON_3R_VTST_VCEQ:
5528 if (!u) { /* VTST */
5529 switch (size) {
5530 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
5531 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
5532 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
5533 default: abort();
5534 }
5535 } else { /* VCEQ */
5536 switch (size) {
5537 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5538 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5539 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
5540 default: abort();
5541 }
5542 }
5543 break;
5544 case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */
5545 switch (size) {
5546 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5547 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5548 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5549 default: abort();
5550 }
5551 tcg_temp_free_i32(tmp2);
5552 tmp2 = neon_load_reg(rd, pass);
5553 if (u) { /* VMLS */
5554 gen_neon_rsb(size, tmp, tmp2);
5555 } else { /* VMLA */
5556 gen_neon_add(size, tmp, tmp2);
5557 }
5558 break;
5559 case NEON_3R_VMUL:
5560 if (u) { /* polynomial */
5561 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
5562 } else { /* Integer */
5563 switch (size) {
5564 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5565 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5566 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5567 default: abort();
5568 }
5569 }
5570 break;
5571 case NEON_3R_VPMAX:
5572 GEN_NEON_INTEGER_OP(pmax);
5573 break;
5574 case NEON_3R_VPMIN:
5575 GEN_NEON_INTEGER_OP(pmin);
5576 break;
5577 case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */
5578 if (!u) { /* VQDMULH */
5579 switch (size) {
5580 case 1:
5581 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
5582 break;
5583 case 2:
5584 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
5585 break;
5586 default: abort();
5587 }
5588 } else { /* VQRDMULH */
5589 switch (size) {
5590 case 1:
5591 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
5592 break;
5593 case 2:
5594 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
5595 break;
5596 default: abort();
5597 }
5598 }
5599 break;
5600 case NEON_3R_VPADD:
5601 switch (size) {
5602 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
5603 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
5604 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
5605 default: abort();
5606 }
5607 break;
5608 case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */
5609 {
5610 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5611 switch ((u << 2) | size) {
5612 case 0: /* VADD */
5613 case 4: /* VPADD */
5614 gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
5615 break;
5616 case 2: /* VSUB */
5617 gen_helper_vfp_subs(tmp, tmp, tmp2, fpstatus);
5618 break;
5619 case 6: /* VABD */
5620 gen_helper_neon_abd_f32(tmp, tmp, tmp2, fpstatus);
5621 break;
5622 default:
5623 abort();
5624 }
5625 tcg_temp_free_ptr(fpstatus);
5626 break;
5627 }
5628 case NEON_3R_FLOAT_MULTIPLY:
5629 {
5630 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5631 gen_helper_vfp_muls(tmp, tmp, tmp2, fpstatus);
5632 if (!u) {
5633 tcg_temp_free_i32(tmp2);
5634 tmp2 = neon_load_reg(rd, pass);
5635 if (size == 0) {
5636 gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
5637 } else {
5638 gen_helper_vfp_subs(tmp, tmp2, tmp, fpstatus);
5639 }
5640 }
5641 tcg_temp_free_ptr(fpstatus);
5642 break;
5643 }
5644 case NEON_3R_FLOAT_CMP:
5645 {
5646 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5647 if (!u) {
5648 gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus);
5649 } else {
5650 if (size == 0) {
5651 gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus);
5652 } else {
5653 gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus);
5654 }
5655 }
5656 tcg_temp_free_ptr(fpstatus);
5657 break;
5658 }
5659 case NEON_3R_FLOAT_ACMP:
5660 {
5661 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5662 if (size == 0) {
5663 gen_helper_neon_acge_f32(tmp, tmp, tmp2, fpstatus);
5664 } else {
5665 gen_helper_neon_acgt_f32(tmp, tmp, tmp2, fpstatus);
5666 }
5667 tcg_temp_free_ptr(fpstatus);
5668 break;
5669 }
5670 case NEON_3R_FLOAT_MINMAX:
5671 {
5672 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5673 if (size == 0) {
5674 gen_helper_vfp_maxs(tmp, tmp, tmp2, fpstatus);
5675 } else {
5676 gen_helper_vfp_mins(tmp, tmp, tmp2, fpstatus);
5677 }
5678 tcg_temp_free_ptr(fpstatus);
5679 break;
5680 }
5681 case NEON_3R_FLOAT_MISC:
5682 if (u) {
5683 /* VMAXNM/VMINNM */
5684 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5685 if (size == 0) {
5686 gen_helper_vfp_maxnums(tmp, tmp, tmp2, fpstatus);
5687 } else {
5688 gen_helper_vfp_minnums(tmp, tmp, tmp2, fpstatus);
5689 }
5690 tcg_temp_free_ptr(fpstatus);
5691 } else {
5692 if (size == 0) {
5693 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
5694 } else {
5695 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
5696 }
5697 }
5698 break;
5699 case NEON_3R_VFM:
5700 {
5701 /* VFMA, VFMS: fused multiply-add */
5702 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5703 TCGv_i32 tmp3 = neon_load_reg(rd, pass);
5704 if (size) {
5705 /* VFMS */
5706 gen_helper_vfp_negs(tmp, tmp);
5707 }
5708 gen_helper_vfp_muladds(tmp, tmp, tmp2, tmp3, fpstatus);
5709 tcg_temp_free_i32(tmp3);
5710 tcg_temp_free_ptr(fpstatus);
5711 break;
5712 }
5713 default:
5714 abort();
5715 }
5716 tcg_temp_free_i32(tmp2);
5717
5718 /* Save the result. For elementwise operations we can put it
5719 straight into the destination register. For pairwise operations
5720 we have to be careful to avoid clobbering the source operands. */
5721 if (pairwise && rd == rm) {
5722 neon_store_scratch(pass, tmp);
5723 } else {
5724 neon_store_reg(rd, pass, tmp);
5725 }
5726
5727 } /* for pass */
5728 if (pairwise && rd == rm) {
5729 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5730 tmp = neon_load_scratch(pass);
5731 neon_store_reg(rd, pass, tmp);
5732 }
5733 }
5734 /* End of 3 register same size operations. */
5735 } else if (insn & (1 << 4)) {
5736 if ((insn & 0x00380080) != 0) {
5737 /* Two registers and shift. */
5738 op = (insn >> 8) & 0xf;
5739 if (insn & (1 << 7)) {
5740 /* 64-bit shift. */
5741 if (op > 7) {
5742 return 1;
5743 }
5744 size = 3;
5745 } else {
5746 size = 2;
5747 while ((insn & (1 << (size + 19))) == 0)
5748 size--;
5749 }
5750 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
5751 /* To avoid excessive duplication of ops we implement shift
5752 by immediate using the variable shift operations. */
5753 if (op < 8) {
5754 /* Shift by immediate:
5755 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
5756 if (q && ((rd | rm) & 1)) {
5757 return 1;
5758 }
5759 if (!u && (op == 4 || op == 6)) {
5760 return 1;
5761 }
5762 /* Right shifts are encoded as N - shift, where N is the
5763 element size in bits. */
5764 if (op <= 4)
5765 shift = shift - (1 << (size + 3));
5766 if (size == 3) {
5767 count = q + 1;
5768 } else {
5769 count = q ? 4: 2;
5770 }
5771 switch (size) {
5772 case 0:
5773 imm = (uint8_t) shift;
5774 imm |= imm << 8;
5775 imm |= imm << 16;
5776 break;
5777 case 1:
5778 imm = (uint16_t) shift;
5779 imm |= imm << 16;
5780 break;
5781 case 2:
5782 case 3:
5783 imm = shift;
5784 break;
5785 default:
5786 abort();
5787 }
5788
5789 for (pass = 0; pass < count; pass++) {
5790 if (size == 3) {
5791 neon_load_reg64(cpu_V0, rm + pass);
5792 tcg_gen_movi_i64(cpu_V1, imm);
5793 switch (op) {
5794 case 0: /* VSHR */
5795 case 1: /* VSRA */
5796 if (u)
5797 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
5798 else
5799 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
5800 break;
5801 case 2: /* VRSHR */
5802 case 3: /* VRSRA */
5803 if (u)
5804 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
5805 else
5806 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
5807 break;
5808 case 4: /* VSRI */
5809 case 5: /* VSHL, VSLI */
5810 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
5811 break;
5812 case 6: /* VQSHLU */
5813 gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
5814 cpu_V0, cpu_V1);
5815 break;
5816 case 7: /* VQSHL */
5817 if (u) {
5818 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
5819 cpu_V0, cpu_V1);
5820 } else {
5821 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
5822 cpu_V0, cpu_V1);
5823 }
5824 break;
5825 }
5826 if (op == 1 || op == 3) {
5827 /* Accumulate. */
5828 neon_load_reg64(cpu_V1, rd + pass);
5829 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
5830 } else if (op == 4 || (op == 5 && u)) {
5831 /* Insert */
5832 neon_load_reg64(cpu_V1, rd + pass);
5833 uint64_t mask;
5834 if (shift < -63 || shift > 63) {
5835 mask = 0;
5836 } else {
5837 if (op == 4) {
5838 mask = 0xffffffffffffffffull >> -shift;
5839 } else {
5840 mask = 0xffffffffffffffffull << shift;
5841 }
5842 }
5843 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
5844 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5845 }
5846 neon_store_reg64(cpu_V0, rd + pass);
5847 } else { /* size < 3 */
5848 /* Operands in T0 and T1. */
5849 tmp = neon_load_reg(rm, pass);
5850 tmp2 = tcg_temp_new_i32();
5851 tcg_gen_movi_i32(tmp2, imm);
5852 switch (op) {
5853 case 0: /* VSHR */
5854 case 1: /* VSRA */
5855 GEN_NEON_INTEGER_OP(shl);
5856 break;
5857 case 2: /* VRSHR */
5858 case 3: /* VRSRA */
5859 GEN_NEON_INTEGER_OP(rshl);
5860 break;
5861 case 4: /* VSRI */
5862 case 5: /* VSHL, VSLI */
5863 switch (size) {
5864 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
5865 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
5866 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
5867 default: abort();
5868 }
5869 break;
5870 case 6: /* VQSHLU */
5871 switch (size) {
5872 case 0:
5873 gen_helper_neon_qshlu_s8(tmp, cpu_env,
5874 tmp, tmp2);
5875 break;
5876 case 1:
5877 gen_helper_neon_qshlu_s16(tmp, cpu_env,
5878 tmp, tmp2);
5879 break;
5880 case 2:
5881 gen_helper_neon_qshlu_s32(tmp, cpu_env,
5882 tmp, tmp2);
5883 break;
5884 default:
5885 abort();
5886 }
5887 break;
5888 case 7: /* VQSHL */
5889 GEN_NEON_INTEGER_OP_ENV(qshl);
5890 break;
5891 }
5892 tcg_temp_free_i32(tmp2);
5893
5894 if (op == 1 || op == 3) {
5895 /* Accumulate. */
5896 tmp2 = neon_load_reg(rd, pass);
5897 gen_neon_add(size, tmp, tmp2);
5898 tcg_temp_free_i32(tmp2);
5899 } else if (op == 4 || (op == 5 && u)) {
5900 /* Insert */
5901 switch (size) {
5902 case 0:
5903 if (op == 4)
5904 mask = 0xff >> -shift;
5905 else
5906 mask = (uint8_t)(0xff << shift);
5907 mask |= mask << 8;
5908 mask |= mask << 16;
5909 break;
5910 case 1:
5911 if (op == 4)
5912 mask = 0xffff >> -shift;
5913 else
5914 mask = (uint16_t)(0xffff << shift);
5915 mask |= mask << 16;
5916 break;
5917 case 2:
5918 if (shift < -31 || shift > 31) {
5919 mask = 0;
5920 } else {
5921 if (op == 4)
5922 mask = 0xffffffffu >> -shift;
5923 else
5924 mask = 0xffffffffu << shift;
5925 }
5926 break;
5927 default:
5928 abort();
5929 }
5930 tmp2 = neon_load_reg(rd, pass);
5931 tcg_gen_andi_i32(tmp, tmp, mask);
5932 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
5933 tcg_gen_or_i32(tmp, tmp, tmp2);
5934 tcg_temp_free_i32(tmp2);
5935 }
5936 neon_store_reg(rd, pass, tmp);
5937 }
5938 } /* for pass */
5939 } else if (op < 10) {
5940 /* Shift by immediate and narrow:
5941 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
5942 int input_unsigned = (op == 8) ? !u : u;
5943 if (rm & 1) {
5944 return 1;
5945 }
5946 shift = shift - (1 << (size + 3));
5947 size++;
5948 if (size == 3) {
5949 tmp64 = tcg_const_i64(shift);
5950 neon_load_reg64(cpu_V0, rm);
5951 neon_load_reg64(cpu_V1, rm + 1);
5952 for (pass = 0; pass < 2; pass++) {
5953 TCGv_i64 in;
5954 if (pass == 0) {
5955 in = cpu_V0;
5956 } else {
5957 in = cpu_V1;
5958 }
5959 if (q) {
5960 if (input_unsigned) {
5961 gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
5962 } else {
5963 gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
5964 }
5965 } else {
5966 if (input_unsigned) {
5967 gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
5968 } else {
5969 gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
5970 }
5971 }
5972 tmp = tcg_temp_new_i32();
5973 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
5974 neon_store_reg(rd, pass, tmp);
5975 } /* for pass */
5976 tcg_temp_free_i64(tmp64);
5977 } else {
5978 if (size == 1) {
5979 imm = (uint16_t)shift;
5980 imm |= imm << 16;
5981 } else {
5982 /* size == 2 */
5983 imm = (uint32_t)shift;
5984 }
5985 tmp2 = tcg_const_i32(imm);
5986 tmp4 = neon_load_reg(rm + 1, 0);
5987 tmp5 = neon_load_reg(rm + 1, 1);
5988 for (pass = 0; pass < 2; pass++) {
5989 if (pass == 0) {
5990 tmp = neon_load_reg(rm, 0);
5991 } else {
5992 tmp = tmp4;
5993 }
5994 gen_neon_shift_narrow(size, tmp, tmp2, q,
5995 input_unsigned);
5996 if (pass == 0) {
5997 tmp3 = neon_load_reg(rm, 1);
5998 } else {
5999 tmp3 = tmp5;
6000 }
6001 gen_neon_shift_narrow(size, tmp3, tmp2, q,
6002 input_unsigned);
6003 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
6004 tcg_temp_free_i32(tmp);
6005 tcg_temp_free_i32(tmp3);
6006 tmp = tcg_temp_new_i32();
6007 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
6008 neon_store_reg(rd, pass, tmp);
6009 } /* for pass */
6010 tcg_temp_free_i32(tmp2);
6011 }
6012 } else if (op == 10) {
6013 /* VSHLL, VMOVL */
6014 if (q || (rd & 1)) {
6015 return 1;
6016 }
6017 tmp = neon_load_reg(rm, 0);
6018 tmp2 = neon_load_reg(rm, 1);
6019 for (pass = 0; pass < 2; pass++) {
6020 if (pass == 1)
6021 tmp = tmp2;
6022
6023 gen_neon_widen(cpu_V0, tmp, size, u);
6024
6025 if (shift != 0) {
6026 /* The shift is less than the width of the source
6027 type, so we can just shift the whole register. */
6028 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
6029 /* Widen the result of shift: we need to clear
6030 * the potential overflow bits resulting from
6031 * left bits of the narrow input appearing as
6032 * right bits of left the neighbour narrow
6033 * input. */
6034 if (size < 2 || !u) {
6035 uint64_t imm64;
6036 if (size == 0) {
6037 imm = (0xffu >> (8 - shift));
6038 imm |= imm << 16;
6039 } else if (size == 1) {
6040 imm = 0xffff >> (16 - shift);
6041 } else {
6042 /* size == 2 */
6043 imm = 0xffffffff >> (32 - shift);
6044 }
6045 if (size < 2) {
6046 imm64 = imm | (((uint64_t)imm) << 32);
6047 } else {
6048 imm64 = imm;
6049 }
6050 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
6051 }
6052 }
6053 neon_store_reg64(cpu_V0, rd + pass);
6054 }
6055 } else if (op >= 14) {
6056 /* VCVT fixed-point. */
6057 if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
6058 return 1;
6059 }
6060 /* We have already masked out the must-be-1 top bit of imm6,
6061 * hence this 32-shift where the ARM ARM has 64-imm6.
6062 */
6063 shift = 32 - shift;
6064 for (pass = 0; pass < (q ? 4 : 2); pass++) {
6065 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
6066 if (!(op & 1)) {
6067 if (u)
6068 gen_vfp_ulto(0, shift, 1);
6069 else
6070 gen_vfp_slto(0, shift, 1);
6071 } else {
6072 if (u)
6073 gen_vfp_toul(0, shift, 1);
6074 else
6075 gen_vfp_tosl(0, shift, 1);
6076 }
6077 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
6078 }
6079 } else {
6080 return 1;
6081 }
6082 } else { /* (insn & 0x00380080) == 0 */
6083 int invert;
6084 if (q && (rd & 1)) {
6085 return 1;
6086 }
6087
6088 op = (insn >> 8) & 0xf;
6089 /* One register and immediate. */
6090 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
6091 invert = (insn & (1 << 5)) != 0;
6092 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
6093 * We choose to not special-case this and will behave as if a
6094 * valid constant encoding of 0 had been given.
6095 */
6096 switch (op) {
6097 case 0: case 1:
6098 /* no-op */
6099 break;
6100 case 2: case 3:
6101 imm <<= 8;
6102 break;
6103 case 4: case 5:
6104 imm <<= 16;
6105 break;
6106 case 6: case 7:
6107 imm <<= 24;
6108 break;
6109 case 8: case 9:
6110 imm |= imm << 16;
6111 break;
6112 case 10: case 11:
6113 imm = (imm << 8) | (imm << 24);
6114 break;
6115 case 12:
6116 imm = (imm << 8) | 0xff;
6117 break;
6118 case 13:
6119 imm = (imm << 16) | 0xffff;
6120 break;
6121 case 14:
6122 imm |= (imm << 8) | (imm << 16) | (imm << 24);
6123 if (invert)
6124 imm = ~imm;
6125 break;
6126 case 15:
6127 if (invert) {
6128 return 1;
6129 }
6130 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
6131 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
6132 break;
6133 }
6134 if (invert)
6135 imm = ~imm;
6136
6137 for (pass = 0; pass < (q ? 4 : 2); pass++) {
6138 if (op & 1 && op < 12) {
6139 tmp = neon_load_reg(rd, pass);
6140 if (invert) {
6141 /* The immediate value has already been inverted, so
6142 BIC becomes AND. */
6143 tcg_gen_andi_i32(tmp, tmp, imm);
6144 } else {
6145 tcg_gen_ori_i32(tmp, tmp, imm);
6146 }
6147 } else {
6148 /* VMOV, VMVN. */
6149 tmp = tcg_temp_new_i32();
6150 if (op == 14 && invert) {
6151 int n;
6152 uint32_t val;
6153 val = 0;
6154 for (n = 0; n < 4; n++) {
6155 if (imm & (1 << (n + (pass & 1) * 4)))
6156 val |= 0xff << (n * 8);
6157 }
6158 tcg_gen_movi_i32(tmp, val);
6159 } else {
6160 tcg_gen_movi_i32(tmp, imm);
6161 }
6162 }
6163 neon_store_reg(rd, pass, tmp);
6164 }
6165 }
6166 } else { /* (insn & 0x00800010 == 0x00800000) */
6167 if (size != 3) {
6168 op = (insn >> 8) & 0xf;
6169 if ((insn & (1 << 6)) == 0) {
6170 /* Three registers of different lengths. */
6171 int src1_wide;
6172 int src2_wide;
6173 int prewiden;
6174 /* undefreq: bit 0 : UNDEF if size == 0
6175 * bit 1 : UNDEF if size == 1
6176 * bit 2 : UNDEF if size == 2
6177 * bit 3 : UNDEF if U == 1
6178 * Note that [2:0] set implies 'always UNDEF'
6179 */
6180 int undefreq;
6181 /* prewiden, src1_wide, src2_wide, undefreq */
6182 static const int neon_3reg_wide[16][4] = {
6183 {1, 0, 0, 0}, /* VADDL */
6184 {1, 1, 0, 0}, /* VADDW */
6185 {1, 0, 0, 0}, /* VSUBL */
6186 {1, 1, 0, 0}, /* VSUBW */
6187 {0, 1, 1, 0}, /* VADDHN */
6188 {0, 0, 0, 0}, /* VABAL */
6189 {0, 1, 1, 0}, /* VSUBHN */
6190 {0, 0, 0, 0}, /* VABDL */
6191 {0, 0, 0, 0}, /* VMLAL */
6192 {0, 0, 0, 9}, /* VQDMLAL */
6193 {0, 0, 0, 0}, /* VMLSL */
6194 {0, 0, 0, 9}, /* VQDMLSL */
6195 {0, 0, 0, 0}, /* Integer VMULL */
6196 {0, 0, 0, 1}, /* VQDMULL */
6197 {0, 0, 0, 0xa}, /* Polynomial VMULL */
6198 {0, 0, 0, 7}, /* Reserved: always UNDEF */
6199 };
6200
6201 prewiden = neon_3reg_wide[op][0];
6202 src1_wide = neon_3reg_wide[op][1];
6203 src2_wide = neon_3reg_wide[op][2];
6204 undefreq = neon_3reg_wide[op][3];
6205
6206 if ((undefreq & (1 << size)) ||
6207 ((undefreq & 8) && u)) {
6208 return 1;
6209 }
6210 if ((src1_wide && (rn & 1)) ||
6211 (src2_wide && (rm & 1)) ||
6212 (!src2_wide && (rd & 1))) {
6213 return 1;
6214 }
6215
6216 /* Handle VMULL.P64 (Polynomial 64x64 to 128 bit multiply)
6217 * outside the loop below as it only performs a single pass.
6218 */
6219 if (op == 14 && size == 2) {
6220 TCGv_i64 tcg_rn, tcg_rm, tcg_rd;
6221
6222 if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) {
6223 return 1;
6224 }
6225 tcg_rn = tcg_temp_new_i64();
6226 tcg_rm = tcg_temp_new_i64();
6227 tcg_rd = tcg_temp_new_i64();
6228 neon_load_reg64(tcg_rn, rn);
6229 neon_load_reg64(tcg_rm, rm);
6230 gen_helper_neon_pmull_64_lo(tcg_rd, tcg_rn, tcg_rm);
6231 neon_store_reg64(tcg_rd, rd);
6232 gen_helper_neon_pmull_64_hi(tcg_rd, tcg_rn, tcg_rm);
6233 neon_store_reg64(tcg_rd, rd + 1);
6234 tcg_temp_free_i64(tcg_rn);
6235 tcg_temp_free_i64(tcg_rm);
6236 tcg_temp_free_i64(tcg_rd);
6237 return 0;
6238 }
6239
6240 /* Avoid overlapping operands. Wide source operands are
6241 always aligned so will never overlap with wide
6242 destinations in problematic ways. */
6243 if (rd == rm && !src2_wide) {
6244 tmp = neon_load_reg(rm, 1);
6245 neon_store_scratch(2, tmp);
6246 } else if (rd == rn && !src1_wide) {
6247 tmp = neon_load_reg(rn, 1);
6248 neon_store_scratch(2, tmp);
6249 }
6250 TCGV_UNUSED_I32(tmp3);
6251 for (pass = 0; pass < 2; pass++) {
6252 if (src1_wide) {
6253 neon_load_reg64(cpu_V0, rn + pass);
6254 TCGV_UNUSED_I32(tmp);
6255 } else {
6256 if (pass == 1 && rd == rn) {
6257 tmp = neon_load_scratch(2);
6258 } else {
6259 tmp = neon_load_reg(rn, pass);
6260 }
6261 if (prewiden) {
6262 gen_neon_widen(cpu_V0, tmp, size, u);
6263 }
6264 }
6265 if (src2_wide) {
6266 neon_load_reg64(cpu_V1, rm + pass);
6267 TCGV_UNUSED_I32(tmp2);
6268 } else {
6269 if (pass == 1 && rd == rm) {
6270 tmp2 = neon_load_scratch(2);
6271 } else {
6272 tmp2 = neon_load_reg(rm, pass);
6273 }
6274 if (prewiden) {
6275 gen_neon_widen(cpu_V1, tmp2, size, u);
6276 }
6277 }
6278 switch (op) {
6279 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
6280 gen_neon_addl(size);
6281 break;
6282 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
6283 gen_neon_subl(size);
6284 break;
6285 case 5: case 7: /* VABAL, VABDL */
6286 switch ((size << 1) | u) {
6287 case 0:
6288 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
6289 break;
6290 case 1:
6291 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
6292 break;
6293 case 2:
6294 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
6295 break;
6296 case 3:
6297 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
6298 break;
6299 case 4:
6300 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
6301 break;
6302 case 5:
6303 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
6304 break;
6305 default: abort();
6306 }
6307 tcg_temp_free_i32(tmp2);
6308 tcg_temp_free_i32(tmp);
6309 break;
6310 case 8: case 9: case 10: case 11: case 12: case 13:
6311 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
6312 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
6313 break;
6314 case 14: /* Polynomial VMULL */
6315 gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
6316 tcg_temp_free_i32(tmp2);
6317 tcg_temp_free_i32(tmp);
6318 break;
6319 default: /* 15 is RESERVED: caught earlier */
6320 abort();
6321 }
6322 if (op == 13) {
6323 /* VQDMULL */
6324 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
6325 neon_store_reg64(cpu_V0, rd + pass);
6326 } else if (op == 5 || (op >= 8 && op <= 11)) {
6327 /* Accumulate. */
6328 neon_load_reg64(cpu_V1, rd + pass);
6329 switch (op) {
6330 case 10: /* VMLSL */
6331 gen_neon_negl(cpu_V0, size);
6332 /* Fall through */
6333 case 5: case 8: /* VABAL, VMLAL */
6334 gen_neon_addl(size);
6335 break;
6336 case 9: case 11: /* VQDMLAL, VQDMLSL */
6337 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
6338 if (op == 11) {
6339 gen_neon_negl(cpu_V0, size);
6340 }
6341 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
6342 break;
6343 default:
6344 abort();
6345 }
6346 neon_store_reg64(cpu_V0, rd + pass);
6347 } else if (op == 4 || op == 6) {
6348 /* Narrowing operation. */
6349 tmp = tcg_temp_new_i32();
6350 if (!u) {
6351 switch (size) {
6352 case 0:
6353 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
6354 break;
6355 case 1:
6356 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
6357 break;
6358 case 2:
6359 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
6360 tcg_gen_extrl_i64_i32(tmp, cpu_V0);
6361 break;
6362 default: abort();
6363 }
6364 } else {
6365 switch (size) {
6366 case 0:
6367 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
6368 break;
6369 case 1:
6370 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
6371 break;
6372 case 2:
6373 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
6374 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
6375 tcg_gen_extrl_i64_i32(tmp, cpu_V0);
6376 break;
6377 default: abort();
6378 }
6379 }
6380 if (pass == 0) {
6381 tmp3 = tmp;
6382 } else {
6383 neon_store_reg(rd, 0, tmp3);
6384 neon_store_reg(rd, 1, tmp);
6385 }
6386 } else {
6387 /* Write back the result. */
6388 neon_store_reg64(cpu_V0, rd + pass);
6389 }
6390 }
6391 } else {
6392 /* Two registers and a scalar. NB that for ops of this form
6393 * the ARM ARM labels bit 24 as Q, but it is in our variable
6394 * 'u', not 'q'.
6395 */
6396 if (size == 0) {
6397 return 1;
6398 }
6399 switch (op) {
6400 case 1: /* Float VMLA scalar */
6401 case 5: /* Floating point VMLS scalar */
6402 case 9: /* Floating point VMUL scalar */
6403 if (size == 1) {
6404 return 1;
6405 }
6406 /* fall through */
6407 case 0: /* Integer VMLA scalar */
6408 case 4: /* Integer VMLS scalar */
6409 case 8: /* Integer VMUL scalar */
6410 case 12: /* VQDMULH scalar */
6411 case 13: /* VQRDMULH scalar */
6412 if (u && ((rd | rn) & 1)) {
6413 return 1;
6414 }
6415 tmp = neon_get_scalar(size, rm);
6416 neon_store_scratch(0, tmp);
6417 for (pass = 0; pass < (u ? 4 : 2); pass++) {
6418 tmp = neon_load_scratch(0);
6419 tmp2 = neon_load_reg(rn, pass);
6420 if (op == 12) {
6421 if (size == 1) {
6422 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
6423 } else {
6424 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
6425 }
6426 } else if (op == 13) {
6427 if (size == 1) {
6428 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
6429 } else {
6430 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
6431 }
6432 } else if (op & 1) {
6433 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6434 gen_helper_vfp_muls(tmp, tmp, tmp2, fpstatus);
6435 tcg_temp_free_ptr(fpstatus);
6436 } else {
6437 switch (size) {
6438 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
6439 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
6440 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
6441 default: abort();
6442 }
6443 }
6444 tcg_temp_free_i32(tmp2);
6445 if (op < 8) {
6446 /* Accumulate. */
6447 tmp2 = neon_load_reg(rd, pass);
6448 switch (op) {
6449 case 0:
6450 gen_neon_add(size, tmp, tmp2);
6451 break;
6452 case 1:
6453 {
6454 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6455 gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
6456 tcg_temp_free_ptr(fpstatus);
6457 break;
6458 }
6459 case 4:
6460 gen_neon_rsb(size, tmp, tmp2);
6461 break;
6462 case 5:
6463 {
6464 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6465 gen_helper_vfp_subs(tmp, tmp2, tmp, fpstatus);
6466 tcg_temp_free_ptr(fpstatus);
6467 break;
6468 }
6469 default:
6470 abort();
6471 }
6472 tcg_temp_free_i32(tmp2);
6473 }
6474 neon_store_reg(rd, pass, tmp);
6475 }
6476 break;
6477 case 3: /* VQDMLAL scalar */
6478 case 7: /* VQDMLSL scalar */
6479 case 11: /* VQDMULL scalar */
6480 if (u == 1) {
6481 return 1;
6482 }
6483 /* fall through */
6484 case 2: /* VMLAL sclar */
6485 case 6: /* VMLSL scalar */
6486 case 10: /* VMULL scalar */
6487 if (rd & 1) {
6488 return 1;
6489 }
6490 tmp2 = neon_get_scalar(size, rm);
6491 /* We need a copy of tmp2 because gen_neon_mull
6492 * deletes it during pass 0. */
6493 tmp4 = tcg_temp_new_i32();
6494 tcg_gen_mov_i32(tmp4, tmp2);
6495 tmp3 = neon_load_reg(rn, 1);
6496
6497 for (pass = 0; pass < 2; pass++) {
6498 if (pass == 0) {
6499 tmp = neon_load_reg(rn, 0);
6500 } else {
6501 tmp = tmp3;
6502 tmp2 = tmp4;
6503 }
6504 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
6505 if (op != 11) {
6506 neon_load_reg64(cpu_V1, rd + pass);
6507 }
6508 switch (op) {
6509 case 6:
6510 gen_neon_negl(cpu_V0, size);
6511 /* Fall through */
6512 case 2:
6513 gen_neon_addl(size);
6514 break;
6515 case 3: case 7:
6516 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
6517 if (op == 7) {
6518 gen_neon_negl(cpu_V0, size);
6519 }
6520 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
6521 break;
6522 case 10:
6523 /* no-op */
6524 break;
6525 case 11:
6526 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
6527 break;
6528 default:
6529 abort();
6530 }
6531 neon_store_reg64(cpu_V0, rd + pass);
6532 }
6533
6534
6535 break;
6536 default: /* 14 and 15 are RESERVED */
6537 return 1;
6538 }
6539 }
6540 } else { /* size == 3 */
6541 if (!u) {
6542 /* Extract. */
6543 imm = (insn >> 8) & 0xf;
6544
6545 if (imm > 7 && !q)
6546 return 1;
6547
6548 if (q && ((rd | rn | rm) & 1)) {
6549 return 1;
6550 }
6551
6552 if (imm == 0) {
6553 neon_load_reg64(cpu_V0, rn);
6554 if (q) {
6555 neon_load_reg64(cpu_V1, rn + 1);
6556 }
6557 } else if (imm == 8) {
6558 neon_load_reg64(cpu_V0, rn + 1);
6559 if (q) {
6560 neon_load_reg64(cpu_V1, rm);
6561 }
6562 } else if (q) {
6563 tmp64 = tcg_temp_new_i64();
6564 if (imm < 8) {
6565 neon_load_reg64(cpu_V0, rn);
6566 neon_load_reg64(tmp64, rn + 1);
6567 } else {
6568 neon_load_reg64(cpu_V0, rn + 1);
6569 neon_load_reg64(tmp64, rm);
6570 }
6571 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
6572 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
6573 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
6574 if (imm < 8) {
6575 neon_load_reg64(cpu_V1, rm);
6576 } else {
6577 neon_load_reg64(cpu_V1, rm + 1);
6578 imm -= 8;
6579 }
6580 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
6581 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
6582 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
6583 tcg_temp_free_i64(tmp64);
6584 } else {
6585 /* BUGFIX */
6586 neon_load_reg64(cpu_V0, rn);
6587 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
6588 neon_load_reg64(cpu_V1, rm);
6589 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
6590 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
6591 }
6592 neon_store_reg64(cpu_V0, rd);
6593 if (q) {
6594 neon_store_reg64(cpu_V1, rd + 1);
6595 }
6596 } else if ((insn & (1 << 11)) == 0) {
6597 /* Two register misc. */
6598 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
6599 size = (insn >> 18) & 3;
6600 /* UNDEF for unknown op values and bad op-size combinations */
6601 if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
6602 return 1;
6603 }
6604 if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
6605 q && ((rm | rd) & 1)) {
6606 return 1;
6607 }
6608 switch (op) {
6609 case NEON_2RM_VREV64:
6610 for (pass = 0; pass < (q ? 2 : 1); pass++) {
6611 tmp = neon_load_reg(rm, pass * 2);
6612 tmp2 = neon_load_reg(rm, pass * 2 + 1);
6613 switch (size) {
6614 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
6615 case 1: gen_swap_half(tmp); break;
6616 case 2: /* no-op */ break;
6617 default: abort();
6618 }
6619 neon_store_reg(rd, pass * 2 + 1, tmp);
6620 if (size == 2) {
6621 neon_store_reg(rd, pass * 2, tmp2);
6622 } else {
6623 switch (size) {
6624 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
6625 case 1: gen_swap_half(tmp2); break;
6626 default: abort();
6627 }
6628 neon_store_reg(rd, pass * 2, tmp2);
6629 }
6630 }
6631 break;
6632 case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
6633 case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
6634 for (pass = 0; pass < q + 1; pass++) {
6635 tmp = neon_load_reg(rm, pass * 2);
6636 gen_neon_widen(cpu_V0, tmp, size, op & 1);
6637 tmp = neon_load_reg(rm, pass * 2 + 1);
6638 gen_neon_widen(cpu_V1, tmp, size, op & 1);
6639 switch (size) {
6640 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
6641 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
6642 case 2: tcg_gen_add_i64(CPU_V001); break;
6643 default: abort();
6644 }
6645 if (op >= NEON_2RM_VPADAL) {
6646 /* Accumulate. */
6647 neon_load_reg64(cpu_V1, rd + pass);
6648 gen_neon_addl(size);
6649 }
6650 neon_store_reg64(cpu_V0, rd + pass);
6651 }
6652 break;
6653 case NEON_2RM_VTRN:
6654 if (size == 2) {
6655 int n;
6656 for (n = 0; n < (q ? 4 : 2); n += 2) {
6657 tmp = neon_load_reg(rm, n);
6658 tmp2 = neon_load_reg(rd, n + 1);
6659 neon_store_reg(rm, n, tmp2);
6660 neon_store_reg(rd, n + 1, tmp);
6661 }
6662 } else {
6663 goto elementwise;
6664 }
6665 break;
6666 case NEON_2RM_VUZP:
6667 if (gen_neon_unzip(rd, rm, size, q)) {
6668 return 1;
6669 }
6670 break;
6671 case NEON_2RM_VZIP:
6672 if (gen_neon_zip(rd, rm, size, q)) {
6673 return 1;
6674 }
6675 break;
6676 case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
6677 /* also VQMOVUN; op field and mnemonics don't line up */
6678 if (rm & 1) {
6679 return 1;
6680 }
6681 TCGV_UNUSED_I32(tmp2);
6682 for (pass = 0; pass < 2; pass++) {
6683 neon_load_reg64(cpu_V0, rm + pass);
6684 tmp = tcg_temp_new_i32();
6685 gen_neon_narrow_op(op == NEON_2RM_VMOVN, q, size,
6686 tmp, cpu_V0);
6687 if (pass == 0) {
6688 tmp2 = tmp;
6689 } else {
6690 neon_store_reg(rd, 0, tmp2);
6691 neon_store_reg(rd, 1, tmp);
6692 }
6693 }
6694 break;
6695 case NEON_2RM_VSHLL:
6696 if (q || (rd & 1)) {
6697 return 1;
6698 }
6699 tmp = neon_load_reg(rm, 0);
6700 tmp2 = neon_load_reg(rm, 1);
6701 for (pass = 0; pass < 2; pass++) {
6702 if (pass == 1)
6703 tmp = tmp2;
6704 gen_neon_widen(cpu_V0, tmp, size, 1);
6705 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
6706 neon_store_reg64(cpu_V0, rd + pass);
6707 }
6708 break;
6709 case NEON_2RM_VCVT_F16_F32:
6710 if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
6711 q || (rm & 1)) {
6712 return 1;
6713 }
6714 tmp = tcg_temp_new_i32();
6715 tmp2 = tcg_temp_new_i32();
6716 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
6717 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
6718 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
6719 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
6720 tcg_gen_shli_i32(tmp2, tmp2, 16);
6721 tcg_gen_or_i32(tmp2, tmp2, tmp);
6722 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
6723 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
6724 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
6725 neon_store_reg(rd, 0, tmp2);
6726 tmp2 = tcg_temp_new_i32();
6727 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
6728 tcg_gen_shli_i32(tmp2, tmp2, 16);
6729 tcg_gen_or_i32(tmp2, tmp2, tmp);
6730 neon_store_reg(rd, 1, tmp2);
6731 tcg_temp_free_i32(tmp);
6732 break;
6733 case NEON_2RM_VCVT_F32_F16:
6734 if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
6735 q || (rd & 1)) {
6736 return 1;
6737 }
6738 tmp3 = tcg_temp_new_i32();
6739 tmp = neon_load_reg(rm, 0);
6740 tmp2 = neon_load_reg(rm, 1);
6741 tcg_gen_ext16u_i32(tmp3, tmp);
6742 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
6743 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
6744 tcg_gen_shri_i32(tmp3, tmp, 16);
6745 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
6746 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
6747 tcg_temp_free_i32(tmp);
6748 tcg_gen_ext16u_i32(tmp3, tmp2);
6749 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
6750 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
6751 tcg_gen_shri_i32(tmp3, tmp2, 16);
6752 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
6753 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
6754 tcg_temp_free_i32(tmp2);
6755 tcg_temp_free_i32(tmp3);
6756 break;
6757 case NEON_2RM_AESE: case NEON_2RM_AESMC:
6758 if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)
6759 || ((rm | rd) & 1)) {
6760 return 1;
6761 }
6762 tmp = tcg_const_i32(rd);
6763 tmp2 = tcg_const_i32(rm);
6764
6765 /* Bit 6 is the lowest opcode bit; it distinguishes between
6766 * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
6767 */
6768 tmp3 = tcg_const_i32(extract32(insn, 6, 1));
6769
6770 if (op == NEON_2RM_AESE) {
6771 gen_helper_crypto_aese(cpu_env, tmp, tmp2, tmp3);
6772 } else {
6773 gen_helper_crypto_aesmc(cpu_env, tmp, tmp2, tmp3);
6774 }
6775 tcg_temp_free_i32(tmp);
6776 tcg_temp_free_i32(tmp2);
6777 tcg_temp_free_i32(tmp3);
6778 break;
6779 case NEON_2RM_SHA1H:
6780 if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)
6781 || ((rm | rd) & 1)) {
6782 return 1;
6783 }
6784 tmp = tcg_const_i32(rd);
6785 tmp2 = tcg_const_i32(rm);
6786
6787 gen_helper_crypto_sha1h(cpu_env, tmp, tmp2);
6788
6789 tcg_temp_free_i32(tmp);
6790 tcg_temp_free_i32(tmp2);
6791 break;
6792 case NEON_2RM_SHA1SU1:
6793 if ((rm | rd) & 1) {
6794 return 1;
6795 }
6796 /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
6797 if (q) {
6798 if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256)) {
6799 return 1;
6800 }
6801 } else if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) {
6802 return 1;
6803 }
6804 tmp = tcg_const_i32(rd);
6805 tmp2 = tcg_const_i32(rm);
6806 if (q) {
6807 gen_helper_crypto_sha256su0(cpu_env, tmp, tmp2);
6808 } else {
6809 gen_helper_crypto_sha1su1(cpu_env, tmp, tmp2);
6810 }
6811 tcg_temp_free_i32(tmp);
6812 tcg_temp_free_i32(tmp2);
6813 break;
6814 default:
6815 elementwise:
6816 for (pass = 0; pass < (q ? 4 : 2); pass++) {
6817 if (neon_2rm_is_float_op(op)) {
6818 tcg_gen_ld_f32(cpu_F0s, cpu_env,
6819 neon_reg_offset(rm, pass));
6820 TCGV_UNUSED_I32(tmp);
6821 } else {
6822 tmp = neon_load_reg(rm, pass);
6823 }
6824 switch (op) {
6825 case NEON_2RM_VREV32:
6826 switch (size) {
6827 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
6828 case 1: gen_swap_half(tmp); break;
6829 default: abort();
6830 }
6831 break;
6832 case NEON_2RM_VREV16:
6833 gen_rev16(tmp);
6834 break;
6835 case NEON_2RM_VCLS:
6836 switch (size) {
6837 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
6838 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
6839 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
6840 default: abort();
6841 }
6842 break;
6843 case NEON_2RM_VCLZ:
6844 switch (size) {
6845 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
6846 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
6847 case 2: gen_helper_clz(tmp, tmp); break;
6848 default: abort();
6849 }
6850 break;
6851 case NEON_2RM_VCNT:
6852 gen_helper_neon_cnt_u8(tmp, tmp);
6853 break;
6854 case NEON_2RM_VMVN:
6855 tcg_gen_not_i32(tmp, tmp);
6856 break;
6857 case NEON_2RM_VQABS:
6858 switch (size) {
6859 case 0:
6860 gen_helper_neon_qabs_s8(tmp, cpu_env, tmp);
6861 break;
6862 case 1:
6863 gen_helper_neon_qabs_s16(tmp, cpu_env, tmp);
6864 break;
6865 case 2:
6866 gen_helper_neon_qabs_s32(tmp, cpu_env, tmp);
6867 break;
6868 default: abort();
6869 }
6870 break;
6871 case NEON_2RM_VQNEG:
6872 switch (size) {
6873 case 0:
6874 gen_helper_neon_qneg_s8(tmp, cpu_env, tmp);
6875 break;
6876 case 1:
6877 gen_helper_neon_qneg_s16(tmp, cpu_env, tmp);
6878 break;
6879 case 2:
6880 gen_helper_neon_qneg_s32(tmp, cpu_env, tmp);
6881 break;
6882 default: abort();
6883 }
6884 break;
6885 case NEON_2RM_VCGT0: case NEON_2RM_VCLE0:
6886 tmp2 = tcg_const_i32(0);
6887 switch(size) {
6888 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
6889 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
6890 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
6891 default: abort();
6892 }
6893 tcg_temp_free_i32(tmp2);
6894 if (op == NEON_2RM_VCLE0) {
6895 tcg_gen_not_i32(tmp, tmp);
6896 }
6897 break;
6898 case NEON_2RM_VCGE0: case NEON_2RM_VCLT0:
6899 tmp2 = tcg_const_i32(0);
6900 switch(size) {
6901 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
6902 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
6903 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
6904 default: abort();
6905 }
6906 tcg_temp_free_i32(tmp2);
6907 if (op == NEON_2RM_VCLT0) {
6908 tcg_gen_not_i32(tmp, tmp);
6909 }
6910 break;
6911 case NEON_2RM_VCEQ0:
6912 tmp2 = tcg_const_i32(0);
6913 switch(size) {
6914 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
6915 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
6916 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
6917 default: abort();
6918 }
6919 tcg_temp_free_i32(tmp2);
6920 break;
6921 case NEON_2RM_VABS:
6922 switch(size) {
6923 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
6924 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
6925 case 2: tcg_gen_abs_i32(tmp, tmp); break;
6926 default: abort();
6927 }
6928 break;
6929 case NEON_2RM_VNEG:
6930 tmp2 = tcg_const_i32(0);
6931 gen_neon_rsb(size, tmp, tmp2);
6932 tcg_temp_free_i32(tmp2);
6933 break;
6934 case NEON_2RM_VCGT0_F:
6935 {
6936 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6937 tmp2 = tcg_const_i32(0);
6938 gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus);
6939 tcg_temp_free_i32(tmp2);
6940 tcg_temp_free_ptr(fpstatus);
6941 break;
6942 }
6943 case NEON_2RM_VCGE0_F:
6944 {
6945 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6946 tmp2 = tcg_const_i32(0);
6947 gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus);
6948 tcg_temp_free_i32(tmp2);
6949 tcg_temp_free_ptr(fpstatus);
6950 break;
6951 }
6952 case NEON_2RM_VCEQ0_F:
6953 {
6954 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6955 tmp2 = tcg_const_i32(0);
6956 gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus);
6957 tcg_temp_free_i32(tmp2);
6958 tcg_temp_free_ptr(fpstatus);
6959 break;
6960 }
6961 case NEON_2RM_VCLE0_F:
6962 {
6963 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6964 tmp2 = tcg_const_i32(0);
6965 gen_helper_neon_cge_f32(tmp, tmp2, tmp, fpstatus);
6966 tcg_temp_free_i32(tmp2);
6967 tcg_temp_free_ptr(fpstatus);
6968 break;
6969 }
6970 case NEON_2RM_VCLT0_F:
6971 {
6972 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6973 tmp2 = tcg_const_i32(0);
6974 gen_helper_neon_cgt_f32(tmp, tmp2, tmp, fpstatus);
6975 tcg_temp_free_i32(tmp2);
6976 tcg_temp_free_ptr(fpstatus);
6977 break;
6978 }
6979 case NEON_2RM_VABS_F:
6980 gen_vfp_abs(0);
6981 break;
6982 case NEON_2RM_VNEG_F:
6983 gen_vfp_neg(0);
6984 break;
6985 case NEON_2RM_VSWP:
6986 tmp2 = neon_load_reg(rd, pass);
6987 neon_store_reg(rm, pass, tmp2);
6988 break;
6989 case NEON_2RM_VTRN:
6990 tmp2 = neon_load_reg(rd, pass);
6991 switch (size) {
6992 case 0: gen_neon_trn_u8(tmp, tmp2); break;
6993 case 1: gen_neon_trn_u16(tmp, tmp2); break;
6994 default: abort();
6995 }
6996 neon_store_reg(rm, pass, tmp2);
6997 break;
6998 case NEON_2RM_VRINTN:
6999 case NEON_2RM_VRINTA:
7000 case NEON_2RM_VRINTM:
7001 case NEON_2RM_VRINTP:
7002 case NEON_2RM_VRINTZ:
7003 {
7004 TCGv_i32 tcg_rmode;
7005 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
7006 int rmode;
7007
7008 if (op == NEON_2RM_VRINTZ) {
7009 rmode = FPROUNDING_ZERO;
7010 } else {
7011 rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1];
7012 }
7013
7014 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
7015 gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
7016 cpu_env);
7017 gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
7018 gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
7019 cpu_env);
7020 tcg_temp_free_ptr(fpstatus);
7021 tcg_temp_free_i32(tcg_rmode);
7022 break;
7023 }
7024 case NEON_2RM_VRINTX:
7025 {
7026 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
7027 gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus);
7028 tcg_temp_free_ptr(fpstatus);
7029 break;
7030 }
7031 case NEON_2RM_VCVTAU:
7032 case NEON_2RM_VCVTAS:
7033 case NEON_2RM_VCVTNU:
7034 case NEON_2RM_VCVTNS:
7035 case NEON_2RM_VCVTPU:
7036 case NEON_2RM_VCVTPS:
7037 case NEON_2RM_VCVTMU:
7038 case NEON_2RM_VCVTMS:
7039 {
7040 bool is_signed = !extract32(insn, 7, 1);
7041 TCGv_ptr fpst = get_fpstatus_ptr(1);
7042 TCGv_i32 tcg_rmode, tcg_shift;
7043 int rmode = fp_decode_rm[extract32(insn, 8, 2)];
7044
7045 tcg_shift = tcg_const_i32(0);
7046 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
7047 gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
7048 cpu_env);
7049
7050 if (is_signed) {
7051 gen_helper_vfp_tosls(cpu_F0s, cpu_F0s,
7052 tcg_shift, fpst);
7053 } else {
7054 gen_helper_vfp_touls(cpu_F0s, cpu_F0s,
7055 tcg_shift, fpst);
7056 }
7057
7058 gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
7059 cpu_env);
7060 tcg_temp_free_i32(tcg_rmode);
7061 tcg_temp_free_i32(tcg_shift);
7062 tcg_temp_free_ptr(fpst);
7063 break;
7064 }
7065 case NEON_2RM_VRECPE:
7066 {
7067 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
7068 gen_helper_recpe_u32(tmp, tmp, fpstatus);
7069 tcg_temp_free_ptr(fpstatus);
7070 break;
7071 }
7072 case NEON_2RM_VRSQRTE:
7073 {
7074 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
7075 gen_helper_rsqrte_u32(tmp, tmp, fpstatus);
7076 tcg_temp_free_ptr(fpstatus);
7077 break;
7078 }
7079 case NEON_2RM_VRECPE_F:
7080 {
7081 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
7082 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, fpstatus);
7083 tcg_temp_free_ptr(fpstatus);
7084 break;
7085 }
7086 case NEON_2RM_VRSQRTE_F:
7087 {
7088 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
7089 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, fpstatus);
7090 tcg_temp_free_ptr(fpstatus);
7091 break;
7092 }
7093 case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */
7094 gen_vfp_sito(0, 1);
7095 break;
7096 case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */
7097 gen_vfp_uito(0, 1);
7098 break;
7099 case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */
7100 gen_vfp_tosiz(0, 1);
7101 break;
7102 case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */
7103 gen_vfp_touiz(0, 1);
7104 break;
7105 default:
7106 /* Reserved op values were caught by the
7107 * neon_2rm_sizes[] check earlier.
7108 */
7109 abort();
7110 }
7111 if (neon_2rm_is_float_op(op)) {
7112 tcg_gen_st_f32(cpu_F0s, cpu_env,
7113 neon_reg_offset(rd, pass));
7114 } else {
7115 neon_store_reg(rd, pass, tmp);
7116 }
7117 }
7118 break;
7119 }
7120 } else if ((insn & (1 << 10)) == 0) {
7121 /* VTBL, VTBX. */
7122 int n = ((insn >> 8) & 3) + 1;
7123 if ((rn + n) > 32) {
7124 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
7125 * helper function running off the end of the register file.
7126 */
7127 return 1;
7128 }
7129 n <<= 3;
7130 if (insn & (1 << 6)) {
7131 tmp = neon_load_reg(rd, 0);
7132 } else {
7133 tmp = tcg_temp_new_i32();
7134 tcg_gen_movi_i32(tmp, 0);
7135 }
7136 tmp2 = neon_load_reg(rm, 0);
7137 tmp4 = tcg_const_i32(rn);
7138 tmp5 = tcg_const_i32(n);
7139 gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5);
7140 tcg_temp_free_i32(tmp);
7141 if (insn & (1 << 6)) {
7142 tmp = neon_load_reg(rd, 1);
7143 } else {
7144 tmp = tcg_temp_new_i32();
7145 tcg_gen_movi_i32(tmp, 0);
7146 }
7147 tmp3 = neon_load_reg(rm, 1);
7148 gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5);
7149 tcg_temp_free_i32(tmp5);
7150 tcg_temp_free_i32(tmp4);
7151 neon_store_reg(rd, 0, tmp2);
7152 neon_store_reg(rd, 1, tmp3);
7153 tcg_temp_free_i32(tmp);
7154 } else if ((insn & 0x380) == 0) {
7155 /* VDUP */
7156 if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) {
7157 return 1;
7158 }
7159 if (insn & (1 << 19)) {
7160 tmp = neon_load_reg(rm, 1);
7161 } else {
7162 tmp = neon_load_reg(rm, 0);
7163 }
7164 if (insn & (1 << 16)) {
7165 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
7166 } else if (insn & (1 << 17)) {
7167 if ((insn >> 18) & 1)
7168 gen_neon_dup_high16(tmp);
7169 else
7170 gen_neon_dup_low16(tmp);
7171 }
7172 for (pass = 0; pass < (q ? 4 : 2); pass++) {
7173 tmp2 = tcg_temp_new_i32();
7174 tcg_gen_mov_i32(tmp2, tmp);
7175 neon_store_reg(rd, pass, tmp2);
7176 }
7177 tcg_temp_free_i32(tmp);
7178 } else {
7179 return 1;
7180 }
7181 }
7182 }
7183 return 0;
7184 }
7185
7186 static int disas_coproc_insn(DisasContext *s, uint32_t insn)
7187 {
7188 int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
7189 const ARMCPRegInfo *ri;
7190
7191 cpnum = (insn >> 8) & 0xf;
7192
7193 /* First check for coprocessor space used for XScale/iwMMXt insns */
7194 if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cpnum < 2)) {
7195 if (extract32(s->c15_cpar, cpnum, 1) == 0) {
7196 return 1;
7197 }
7198 if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
7199 return disas_iwmmxt_insn(s, insn);
7200 } else if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) {
7201 return disas_dsp_insn(s, insn);
7202 }
7203 return 1;
7204 }
7205
7206 /* Otherwise treat as a generic register access */
7207 is64 = (insn & (1 << 25)) == 0;
7208 if (!is64 && ((insn & (1 << 4)) == 0)) {
7209 /* cdp */
7210 return 1;
7211 }
7212
7213 crm = insn & 0xf;
7214 if (is64) {
7215 crn = 0;
7216 opc1 = (insn >> 4) & 0xf;
7217 opc2 = 0;
7218 rt2 = (insn >> 16) & 0xf;
7219 } else {
7220 crn = (insn >> 16) & 0xf;
7221 opc1 = (insn >> 21) & 7;
7222 opc2 = (insn >> 5) & 7;
7223 rt2 = 0;
7224 }
7225 isread = (insn >> 20) & 1;
7226 rt = (insn >> 12) & 0xf;
7227
7228 ri = get_arm_cp_reginfo(s->cp_regs,
7229 ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2));
7230 if (ri) {
7231 /* Check access permissions */
7232 if (!cp_access_ok(s->current_el, ri, isread)) {
7233 return 1;
7234 }
7235
7236 if (ri->accessfn ||
7237 (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
7238 /* Emit code to perform further access permissions checks at
7239 * runtime; this may result in an exception.
7240 * Note that on XScale all cp0..c13 registers do an access check
7241 * call in order to handle c15_cpar.
7242 */
7243 TCGv_ptr tmpptr;
7244 TCGv_i32 tcg_syn, tcg_isread;
7245 uint32_t syndrome;
7246
7247 /* Note that since we are an implementation which takes an
7248 * exception on a trapped conditional instruction only if the
7249 * instruction passes its condition code check, we can take
7250 * advantage of the clause in the ARM ARM that allows us to set
7251 * the COND field in the instruction to 0xE in all cases.
7252 * We could fish the actual condition out of the insn (ARM)
7253 * or the condexec bits (Thumb) but it isn't necessary.
7254 */
7255 switch (cpnum) {
7256 case 14:
7257 if (is64) {
7258 syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
7259 isread, false);
7260 } else {
7261 syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
7262 rt, isread, false);
7263 }
7264 break;
7265 case 15:
7266 if (is64) {
7267 syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
7268 isread, false);
7269 } else {
7270 syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
7271 rt, isread, false);
7272 }
7273 break;
7274 default:
7275 /* ARMv8 defines that only coprocessors 14 and 15 exist,
7276 * so this can only happen if this is an ARMv7 or earlier CPU,
7277 * in which case the syndrome information won't actually be
7278 * guest visible.
7279 */
7280 assert(!arm_dc_feature(s, ARM_FEATURE_V8));
7281 syndrome = syn_uncategorized();
7282 break;
7283 }
7284
7285 gen_set_condexec(s);
7286 gen_set_pc_im(s, s->pc - 4);
7287 tmpptr = tcg_const_ptr(ri);
7288 tcg_syn = tcg_const_i32(syndrome);
7289 tcg_isread = tcg_const_i32(isread);
7290 gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn,
7291 tcg_isread);
7292 tcg_temp_free_ptr(tmpptr);
7293 tcg_temp_free_i32(tcg_syn);
7294 tcg_temp_free_i32(tcg_isread);
7295 }
7296
7297 /* Handle special cases first */
7298 switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
7299 case ARM_CP_NOP:
7300 return 0;
7301 case ARM_CP_WFI:
7302 if (isread) {
7303 return 1;
7304 }
7305 gen_set_pc_im(s, s->pc);
7306 s->is_jmp = DISAS_WFI;
7307 return 0;
7308 default:
7309 break;
7310 }
7311
7312 if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
7313 gen_io_start();
7314 }
7315
7316 if (isread) {
7317 /* Read */
7318 if (is64) {
7319 TCGv_i64 tmp64;
7320 TCGv_i32 tmp;
7321 if (ri->type & ARM_CP_CONST) {
7322 tmp64 = tcg_const_i64(ri->resetvalue);
7323 } else if (ri->readfn) {
7324 TCGv_ptr tmpptr;
7325 tmp64 = tcg_temp_new_i64();
7326 tmpptr = tcg_const_ptr(ri);
7327 gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
7328 tcg_temp_free_ptr(tmpptr);
7329 } else {
7330 tmp64 = tcg_temp_new_i64();
7331 tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
7332 }
7333 tmp = tcg_temp_new_i32();
7334 tcg_gen_extrl_i64_i32(tmp, tmp64);
7335 store_reg(s, rt, tmp);
7336 tcg_gen_shri_i64(tmp64, tmp64, 32);
7337 tmp = tcg_temp_new_i32();
7338 tcg_gen_extrl_i64_i32(tmp, tmp64);
7339 tcg_temp_free_i64(tmp64);
7340 store_reg(s, rt2, tmp);
7341 } else {
7342 TCGv_i32 tmp;
7343 if (ri->type & ARM_CP_CONST) {
7344 tmp = tcg_const_i32(ri->resetvalue);
7345 } else if (ri->readfn) {
7346 TCGv_ptr tmpptr;
7347 tmp = tcg_temp_new_i32();
7348 tmpptr = tcg_const_ptr(ri);
7349 gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
7350 tcg_temp_free_ptr(tmpptr);
7351 } else {
7352 tmp = load_cpu_offset(ri->fieldoffset);
7353 }
7354 if (rt == 15) {
7355 /* Destination register of r15 for 32 bit loads sets
7356 * the condition codes from the high 4 bits of the value
7357 */
7358 gen_set_nzcv(tmp);
7359 tcg_temp_free_i32(tmp);
7360 } else {
7361 store_reg(s, rt, tmp);
7362 }
7363 }
7364 } else {
7365 /* Write */
7366 if (ri->type & ARM_CP_CONST) {
7367 /* If not forbidden by access permissions, treat as WI */
7368 return 0;
7369 }
7370
7371 if (is64) {
7372 TCGv_i32 tmplo, tmphi;
7373 TCGv_i64 tmp64 = tcg_temp_new_i64();
7374 tmplo = load_reg(s, rt);
7375 tmphi = load_reg(s, rt2);
7376 tcg_gen_concat_i32_i64(tmp64, tmplo, tmphi);
7377 tcg_temp_free_i32(tmplo);
7378 tcg_temp_free_i32(tmphi);
7379 if (ri->writefn) {
7380 TCGv_ptr tmpptr = tcg_const_ptr(ri);
7381 gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
7382 tcg_temp_free_ptr(tmpptr);
7383 } else {
7384 tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
7385 }
7386 tcg_temp_free_i64(tmp64);
7387 } else {
7388 if (ri->writefn) {
7389 TCGv_i32 tmp;
7390 TCGv_ptr tmpptr;
7391 tmp = load_reg(s, rt);
7392 tmpptr = tcg_const_ptr(ri);
7393 gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
7394 tcg_temp_free_ptr(tmpptr);
7395 tcg_temp_free_i32(tmp);
7396 } else {
7397 TCGv_i32 tmp = load_reg(s, rt);
7398 store_cpu_offset(tmp, ri->fieldoffset);
7399 }
7400 }
7401 }
7402
7403 if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
7404 /* I/O operations must end the TB here (whether read or write) */
7405 gen_io_end();
7406 gen_lookup_tb(s);
7407 } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
7408 /* We default to ending the TB on a coprocessor register write,
7409 * but allow this to be suppressed by the register definition
7410 * (usually only necessary to work around guest bugs).
7411 */
7412 gen_lookup_tb(s);
7413 }
7414
7415 return 0;
7416 }
7417
7418 /* Unknown register; this might be a guest error or a QEMU
7419 * unimplemented feature.
7420 */
7421 if (is64) {
7422 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
7423 "64 bit system register cp:%d opc1: %d crm:%d "
7424 "(%s)\n",
7425 isread ? "read" : "write", cpnum, opc1, crm,
7426 s->ns ? "non-secure" : "secure");
7427 } else {
7428 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
7429 "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
7430 "(%s)\n",
7431 isread ? "read" : "write", cpnum, opc1, crn, crm, opc2,
7432 s->ns ? "non-secure" : "secure");
7433 }
7434
7435 return 1;
7436 }
7437
7438
7439 /* Store a 64-bit value to a register pair. Clobbers val. */
7440 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
7441 {
7442 TCGv_i32 tmp;
7443 tmp = tcg_temp_new_i32();
7444 tcg_gen_extrl_i64_i32(tmp, val);
7445 store_reg(s, rlow, tmp);
7446 tmp = tcg_temp_new_i32();
7447 tcg_gen_shri_i64(val, val, 32);
7448 tcg_gen_extrl_i64_i32(tmp, val);
7449 store_reg(s, rhigh, tmp);
7450 }
7451
7452 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
7453 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
7454 {
7455 TCGv_i64 tmp;
7456 TCGv_i32 tmp2;
7457
7458 /* Load value and extend to 64 bits. */
7459 tmp = tcg_temp_new_i64();
7460 tmp2 = load_reg(s, rlow);
7461 tcg_gen_extu_i32_i64(tmp, tmp2);
7462 tcg_temp_free_i32(tmp2);
7463 tcg_gen_add_i64(val, val, tmp);
7464 tcg_temp_free_i64(tmp);
7465 }
7466
7467 /* load and add a 64-bit value from a register pair. */
7468 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
7469 {
7470 TCGv_i64 tmp;
7471 TCGv_i32 tmpl;
7472 TCGv_i32 tmph;
7473
7474 /* Load 64-bit value rd:rn. */
7475 tmpl = load_reg(s, rlow);
7476 tmph = load_reg(s, rhigh);
7477 tmp = tcg_temp_new_i64();
7478 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
7479 tcg_temp_free_i32(tmpl);
7480 tcg_temp_free_i32(tmph);
7481 tcg_gen_add_i64(val, val, tmp);
7482 tcg_temp_free_i64(tmp);
7483 }
7484
7485 /* Set N and Z flags from hi|lo. */
7486 static void gen_logicq_cc(TCGv_i32 lo, TCGv_i32 hi)
7487 {
7488 tcg_gen_mov_i32(cpu_NF, hi);
7489 tcg_gen_or_i32(cpu_ZF, lo, hi);
7490 }
7491
7492 /* Load/Store exclusive instructions are implemented by remembering
7493 the value/address loaded, and seeing if these are the same
7494 when the store is performed. This should be sufficient to implement
7495 the architecturally mandated semantics, and avoids having to monitor
7496 regular stores.
7497
7498 In system emulation mode only one CPU will be running at once, so
7499 this sequence is effectively atomic. In user emulation mode we
7500 throw an exception and handle the atomic operation elsewhere. */
7501 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
7502 TCGv_i32 addr, int size)
7503 {
7504 TCGv_i32 tmp = tcg_temp_new_i32();
7505
7506 s->is_ldex = true;
7507
7508 switch (size) {
7509 case 0:
7510 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
7511 break;
7512 case 1:
7513 gen_aa32_ld16ua(s, tmp, addr, get_mem_index(s));
7514 break;
7515 case 2:
7516 case 3:
7517 gen_aa32_ld32ua(s, tmp, addr, get_mem_index(s));
7518 break;
7519 default:
7520 abort();
7521 }
7522
7523 if (size == 3) {
7524 TCGv_i32 tmp2 = tcg_temp_new_i32();
7525 TCGv_i32 tmp3 = tcg_temp_new_i32();
7526
7527 tcg_gen_addi_i32(tmp2, addr, 4);
7528 gen_aa32_ld32u(s, tmp3, tmp2, get_mem_index(s));
7529 tcg_temp_free_i32(tmp2);
7530 tcg_gen_concat_i32_i64(cpu_exclusive_val, tmp, tmp3);
7531 store_reg(s, rt2, tmp3);
7532 } else {
7533 tcg_gen_extu_i32_i64(cpu_exclusive_val, tmp);
7534 }
7535
7536 store_reg(s, rt, tmp);
7537 tcg_gen_extu_i32_i64(cpu_exclusive_addr, addr);
7538 }
7539
7540 static void gen_clrex(DisasContext *s)
7541 {
7542 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
7543 }
7544
7545 #ifdef CONFIG_USER_ONLY
7546 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
7547 TCGv_i32 addr, int size)
7548 {
7549 tcg_gen_extu_i32_i64(cpu_exclusive_test, addr);
7550 tcg_gen_movi_i32(cpu_exclusive_info,
7551 size | (rd << 4) | (rt << 8) | (rt2 << 12));
7552 gen_exception_internal_insn(s, 4, EXCP_STREX);
7553 }
7554 #else
7555 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
7556 TCGv_i32 addr, int size)
7557 {
7558 TCGv_i32 tmp;
7559 TCGv_i64 val64, extaddr;
7560 TCGLabel *done_label;
7561 TCGLabel *fail_label;
7562
7563 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
7564 [addr] = {Rt};
7565 {Rd} = 0;
7566 } else {
7567 {Rd} = 1;
7568 } */
7569 fail_label = gen_new_label();
7570 done_label = gen_new_label();
7571 extaddr = tcg_temp_new_i64();
7572 tcg_gen_extu_i32_i64(extaddr, addr);
7573 tcg_gen_brcond_i64(TCG_COND_NE, extaddr, cpu_exclusive_addr, fail_label);
7574 tcg_temp_free_i64(extaddr);
7575
7576 tmp = tcg_temp_new_i32();
7577 switch (size) {
7578 case 0:
7579 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
7580 break;
7581 case 1:
7582 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
7583 break;
7584 case 2:
7585 case 3:
7586 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
7587 break;
7588 default:
7589 abort();
7590 }
7591
7592 val64 = tcg_temp_new_i64();
7593 if (size == 3) {
7594 TCGv_i32 tmp2 = tcg_temp_new_i32();
7595 TCGv_i32 tmp3 = tcg_temp_new_i32();
7596 tcg_gen_addi_i32(tmp2, addr, 4);
7597 gen_aa32_ld32u(s, tmp3, tmp2, get_mem_index(s));
7598 tcg_temp_free_i32(tmp2);
7599 tcg_gen_concat_i32_i64(val64, tmp, tmp3);
7600 tcg_temp_free_i32(tmp3);
7601 } else {
7602 tcg_gen_extu_i32_i64(val64, tmp);
7603 }
7604 tcg_temp_free_i32(tmp);
7605
7606 tcg_gen_brcond_i64(TCG_COND_NE, val64, cpu_exclusive_val, fail_label);
7607 tcg_temp_free_i64(val64);
7608
7609 tmp = load_reg(s, rt);
7610 switch (size) {
7611 case 0:
7612 gen_aa32_st8(s, tmp, addr, get_mem_index(s));
7613 break;
7614 case 1:
7615 gen_aa32_st16(s, tmp, addr, get_mem_index(s));
7616 break;
7617 case 2:
7618 case 3:
7619 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
7620 break;
7621 default:
7622 abort();
7623 }
7624 tcg_temp_free_i32(tmp);
7625 if (size == 3) {
7626 tcg_gen_addi_i32(addr, addr, 4);
7627 tmp = load_reg(s, rt2);
7628 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
7629 tcg_temp_free_i32(tmp);
7630 }
7631 tcg_gen_movi_i32(cpu_R[rd], 0);
7632 tcg_gen_br(done_label);
7633 gen_set_label(fail_label);
7634 tcg_gen_movi_i32(cpu_R[rd], 1);
7635 gen_set_label(done_label);
7636 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
7637 }
7638 #endif
7639
7640 /* gen_srs:
7641 * @env: CPUARMState
7642 * @s: DisasContext
7643 * @mode: mode field from insn (which stack to store to)
7644 * @amode: addressing mode (DA/IA/DB/IB), encoded as per P,U bits in ARM insn
7645 * @writeback: true if writeback bit set
7646 *
7647 * Generate code for the SRS (Store Return State) insn.
7648 */
7649 static void gen_srs(DisasContext *s,
7650 uint32_t mode, uint32_t amode, bool writeback)
7651 {
7652 int32_t offset;
7653 TCGv_i32 addr, tmp;
7654 bool undef = false;
7655
7656 /* SRS is:
7657 * - trapped to EL3 if EL3 is AArch64 and we are at Secure EL1
7658 * - UNDEFINED in Hyp mode
7659 * - UNPREDICTABLE in User or System mode
7660 * - UNPREDICTABLE if the specified mode is:
7661 * -- not implemented
7662 * -- not a valid mode number
7663 * -- a mode that's at a higher exception level
7664 * -- Monitor, if we are Non-secure
7665 * For the UNPREDICTABLE cases we choose to UNDEF.
7666 */
7667 if (s->current_el == 1 && !s->ns) {
7668 gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3);
7669 return;
7670 }
7671
7672 if (s->current_el == 0 || s->current_el == 2) {
7673 undef = true;
7674 }
7675
7676 switch (mode) {
7677 case ARM_CPU_MODE_USR:
7678 case ARM_CPU_MODE_FIQ:
7679 case ARM_CPU_MODE_IRQ:
7680 case ARM_CPU_MODE_SVC:
7681 case ARM_CPU_MODE_ABT:
7682 case ARM_CPU_MODE_UND:
7683 case ARM_CPU_MODE_SYS:
7684 break;
7685 case ARM_CPU_MODE_HYP:
7686 if (s->current_el == 1 || !arm_dc_feature(s, ARM_FEATURE_EL2)) {
7687 undef = true;
7688 }
7689 break;
7690 case ARM_CPU_MODE_MON:
7691 /* No need to check specifically for "are we non-secure" because
7692 * we've already made EL0 UNDEF and handled the trap for S-EL1;
7693 * so if this isn't EL3 then we must be non-secure.
7694 */
7695 if (s->current_el != 3) {
7696 undef = true;
7697 }
7698 break;
7699 default:
7700 undef = true;
7701 }
7702
7703 if (undef) {
7704 gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
7705 default_exception_el(s));
7706 return;
7707 }
7708
7709 addr = tcg_temp_new_i32();
7710 tmp = tcg_const_i32(mode);
7711 /* get_r13_banked() will raise an exception if called from System mode */
7712 gen_set_condexec(s);
7713 gen_set_pc_im(s, s->pc - 4);
7714 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7715 tcg_temp_free_i32(tmp);
7716 switch (amode) {
7717 case 0: /* DA */
7718 offset = -4;
7719 break;
7720 case 1: /* IA */
7721 offset = 0;
7722 break;
7723 case 2: /* DB */
7724 offset = -8;
7725 break;
7726 case 3: /* IB */
7727 offset = 4;
7728 break;
7729 default:
7730 abort();
7731 }
7732 tcg_gen_addi_i32(addr, addr, offset);
7733 tmp = load_reg(s, 14);
7734 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
7735 tcg_temp_free_i32(tmp);
7736 tmp = load_cpu_field(spsr);
7737 tcg_gen_addi_i32(addr, addr, 4);
7738 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
7739 tcg_temp_free_i32(tmp);
7740 if (writeback) {
7741 switch (amode) {
7742 case 0:
7743 offset = -8;
7744 break;
7745 case 1:
7746 offset = 4;
7747 break;
7748 case 2:
7749 offset = -4;
7750 break;
7751 case 3:
7752 offset = 0;
7753 break;
7754 default:
7755 abort();
7756 }
7757 tcg_gen_addi_i32(addr, addr, offset);
7758 tmp = tcg_const_i32(mode);
7759 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7760 tcg_temp_free_i32(tmp);
7761 }
7762 tcg_temp_free_i32(addr);
7763 s->is_jmp = DISAS_UPDATE;
7764 }
7765
7766 static void disas_arm_insn(DisasContext *s, unsigned int insn)
7767 {
7768 unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
7769 TCGv_i32 tmp;
7770 TCGv_i32 tmp2;
7771 TCGv_i32 tmp3;
7772 TCGv_i32 addr;
7773 TCGv_i64 tmp64;
7774
7775 /* M variants do not implement ARM mode. */
7776 if (arm_dc_feature(s, ARM_FEATURE_M)) {
7777 goto illegal_op;
7778 }
7779 cond = insn >> 28;
7780 if (cond == 0xf){
7781 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
7782 * choose to UNDEF. In ARMv5 and above the space is used
7783 * for miscellaneous unconditional instructions.
7784 */
7785 ARCH(5);
7786
7787 /* Unconditional instructions. */
7788 if (((insn >> 25) & 7) == 1) {
7789 /* NEON Data processing. */
7790 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
7791 goto illegal_op;
7792 }
7793
7794 if (disas_neon_data_insn(s, insn)) {
7795 goto illegal_op;
7796 }
7797 return;
7798 }
7799 if ((insn & 0x0f100000) == 0x04000000) {
7800 /* NEON load/store. */
7801 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
7802 goto illegal_op;
7803 }
7804
7805 if (disas_neon_ls_insn(s, insn)) {
7806 goto illegal_op;
7807 }
7808 return;
7809 }
7810 if ((insn & 0x0f000e10) == 0x0e000a00) {
7811 /* VFP. */
7812 if (disas_vfp_insn(s, insn)) {
7813 goto illegal_op;
7814 }
7815 return;
7816 }
7817 if (((insn & 0x0f30f000) == 0x0510f000) ||
7818 ((insn & 0x0f30f010) == 0x0710f000)) {
7819 if ((insn & (1 << 22)) == 0) {
7820 /* PLDW; v7MP */
7821 if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
7822 goto illegal_op;
7823 }
7824 }
7825 /* Otherwise PLD; v5TE+ */
7826 ARCH(5TE);
7827 return;
7828 }
7829 if (((insn & 0x0f70f000) == 0x0450f000) ||
7830 ((insn & 0x0f70f010) == 0x0650f000)) {
7831 ARCH(7);
7832 return; /* PLI; V7 */
7833 }
7834 if (((insn & 0x0f700000) == 0x04100000) ||
7835 ((insn & 0x0f700010) == 0x06100000)) {
7836 if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
7837 goto illegal_op;
7838 }
7839 return; /* v7MP: Unallocated memory hint: must NOP */
7840 }
7841
7842 if ((insn & 0x0ffffdff) == 0x01010000) {
7843 ARCH(6);
7844 /* setend */
7845 if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) {
7846 gen_helper_setend(cpu_env);
7847 s->is_jmp = DISAS_UPDATE;
7848 }
7849 return;
7850 } else if ((insn & 0x0fffff00) == 0x057ff000) {
7851 switch ((insn >> 4) & 0xf) {
7852 case 1: /* clrex */
7853 ARCH(6K);
7854 gen_clrex(s);
7855 return;
7856 case 4: /* dsb */
7857 case 5: /* dmb */
7858 ARCH(7);
7859 /* We don't emulate caches so these are a no-op. */
7860 return;
7861 case 6: /* isb */
7862 /* We need to break the TB after this insn to execute
7863 * self-modifying code correctly and also to take
7864 * any pending interrupts immediately.
7865 */
7866 gen_lookup_tb(s);
7867 return;
7868 default:
7869 goto illegal_op;
7870 }
7871 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
7872 /* srs */
7873 ARCH(6);
7874 gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21));
7875 return;
7876 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
7877 /* rfe */
7878 int32_t offset;
7879 if (IS_USER(s))
7880 goto illegal_op;
7881 ARCH(6);
7882 rn = (insn >> 16) & 0xf;
7883 addr = load_reg(s, rn);
7884 i = (insn >> 23) & 3;
7885 switch (i) {
7886 case 0: offset = -4; break; /* DA */
7887 case 1: offset = 0; break; /* IA */
7888 case 2: offset = -8; break; /* DB */
7889 case 3: offset = 4; break; /* IB */
7890 default: abort();
7891 }
7892 if (offset)
7893 tcg_gen_addi_i32(addr, addr, offset);
7894 /* Load PC into tmp and CPSR into tmp2. */
7895 tmp = tcg_temp_new_i32();
7896 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
7897 tcg_gen_addi_i32(addr, addr, 4);
7898 tmp2 = tcg_temp_new_i32();
7899 gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s));
7900 if (insn & (1 << 21)) {
7901 /* Base writeback. */
7902 switch (i) {
7903 case 0: offset = -8; break;
7904 case 1: offset = 4; break;
7905 case 2: offset = -4; break;
7906 case 3: offset = 0; break;
7907 default: abort();
7908 }
7909 if (offset)
7910 tcg_gen_addi_i32(addr, addr, offset);
7911 store_reg(s, rn, addr);
7912 } else {
7913 tcg_temp_free_i32(addr);
7914 }
7915 gen_rfe(s, tmp, tmp2);
7916 return;
7917 } else if ((insn & 0x0e000000) == 0x0a000000) {
7918 /* branch link and change to thumb (blx <offset>) */
7919 int32_t offset;
7920
7921 val = (uint32_t)s->pc;
7922 tmp = tcg_temp_new_i32();
7923 tcg_gen_movi_i32(tmp, val);
7924 store_reg(s, 14, tmp);
7925 /* Sign-extend the 24-bit offset */
7926 offset = (((int32_t)insn) << 8) >> 8;
7927 /* offset * 4 + bit24 * 2 + (thumb bit) */
7928 val += (offset << 2) | ((insn >> 23) & 2) | 1;
7929 /* pipeline offset */
7930 val += 4;
7931 /* protected by ARCH(5); above, near the start of uncond block */
7932 gen_bx_im(s, val);
7933 return;
7934 } else if ((insn & 0x0e000f00) == 0x0c000100) {
7935 if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
7936 /* iWMMXt register transfer. */
7937 if (extract32(s->c15_cpar, 1, 1)) {
7938 if (!disas_iwmmxt_insn(s, insn)) {
7939 return;
7940 }
7941 }
7942 }
7943 } else if ((insn & 0x0fe00000) == 0x0c400000) {
7944 /* Coprocessor double register transfer. */
7945 ARCH(5TE);
7946 } else if ((insn & 0x0f000010) == 0x0e000010) {
7947 /* Additional coprocessor register transfer. */
7948 } else if ((insn & 0x0ff10020) == 0x01000000) {
7949 uint32_t mask;
7950 uint32_t val;
7951 /* cps (privileged) */
7952 if (IS_USER(s))
7953 return;
7954 mask = val = 0;
7955 if (insn & (1 << 19)) {
7956 if (insn & (1 << 8))
7957 mask |= CPSR_A;
7958 if (insn & (1 << 7))
7959 mask |= CPSR_I;
7960 if (insn & (1 << 6))
7961 mask |= CPSR_F;
7962 if (insn & (1 << 18))
7963 val |= mask;
7964 }
7965 if (insn & (1 << 17)) {
7966 mask |= CPSR_M;
7967 val |= (insn & 0x1f);
7968 }
7969 if (mask) {
7970 gen_set_psr_im(s, mask, 0, val);
7971 }
7972 return;
7973 }
7974 goto illegal_op;
7975 }
7976 if (cond != 0xe) {
7977 /* if not always execute, we generate a conditional jump to
7978 next instruction */
7979 s->condlabel = gen_new_label();
7980 arm_gen_test_cc(cond ^ 1, s->condlabel);
7981 s->condjmp = 1;
7982 }
7983 if ((insn & 0x0f900000) == 0x03000000) {
7984 if ((insn & (1 << 21)) == 0) {
7985 ARCH(6T2);
7986 rd = (insn >> 12) & 0xf;
7987 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
7988 if ((insn & (1 << 22)) == 0) {
7989 /* MOVW */
7990 tmp = tcg_temp_new_i32();
7991 tcg_gen_movi_i32(tmp, val);
7992 } else {
7993 /* MOVT */
7994 tmp = load_reg(s, rd);
7995 tcg_gen_ext16u_i32(tmp, tmp);
7996 tcg_gen_ori_i32(tmp, tmp, val << 16);
7997 }
7998 store_reg(s, rd, tmp);
7999 } else {
8000 if (((insn >> 12) & 0xf) != 0xf)
8001 goto illegal_op;
8002 if (((insn >> 16) & 0xf) == 0) {
8003 gen_nop_hint(s, insn & 0xff);
8004 } else {
8005 /* CPSR = immediate */
8006 val = insn & 0xff;
8007 shift = ((insn >> 8) & 0xf) * 2;
8008 if (shift)
8009 val = (val >> shift) | (val << (32 - shift));
8010 i = ((insn & (1 << 22)) != 0);
8011 if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i),
8012 i, val)) {
8013 goto illegal_op;
8014 }
8015 }
8016 }
8017 } else if ((insn & 0x0f900000) == 0x01000000
8018 && (insn & 0x00000090) != 0x00000090) {
8019 /* miscellaneous instructions */
8020 op1 = (insn >> 21) & 3;
8021 sh = (insn >> 4) & 0xf;
8022 rm = insn & 0xf;
8023 switch (sh) {
8024 case 0x0: /* move program status register */
8025 if (op1 & 1) {
8026 /* PSR = reg */
8027 tmp = load_reg(s, rm);
8028 i = ((op1 & 2) != 0);
8029 if (gen_set_psr(s, msr_mask(s, (insn >> 16) & 0xf, i), i, tmp))
8030 goto illegal_op;
8031 } else {
8032 /* reg = PSR */
8033 rd = (insn >> 12) & 0xf;
8034 if (op1 & 2) {
8035 if (IS_USER(s))
8036 goto illegal_op;
8037 tmp = load_cpu_field(spsr);
8038 } else {
8039 tmp = tcg_temp_new_i32();
8040 gen_helper_cpsr_read(tmp, cpu_env);
8041 }
8042 store_reg(s, rd, tmp);
8043 }
8044 break;
8045 case 0x1:
8046 if (op1 == 1) {
8047 /* branch/exchange thumb (bx). */
8048 ARCH(4T);
8049 tmp = load_reg(s, rm);
8050 gen_bx(s, tmp);
8051 } else if (op1 == 3) {
8052 /* clz */
8053 ARCH(5);
8054 rd = (insn >> 12) & 0xf;
8055 tmp = load_reg(s, rm);
8056 gen_helper_clz(tmp, tmp);
8057 store_reg(s, rd, tmp);
8058 } else {
8059 goto illegal_op;
8060 }
8061 break;
8062 case 0x2:
8063 if (op1 == 1) {
8064 ARCH(5J); /* bxj */
8065 /* Trivial implementation equivalent to bx. */
8066 tmp = load_reg(s, rm);
8067 gen_bx(s, tmp);
8068 } else {
8069 goto illegal_op;
8070 }
8071 break;
8072 case 0x3:
8073 if (op1 != 1)
8074 goto illegal_op;
8075
8076 ARCH(5);
8077 /* branch link/exchange thumb (blx) */
8078 tmp = load_reg(s, rm);
8079 tmp2 = tcg_temp_new_i32();
8080 tcg_gen_movi_i32(tmp2, s->pc);
8081 store_reg(s, 14, tmp2);
8082 gen_bx(s, tmp);
8083 break;
8084 case 0x4:
8085 {
8086 /* crc32/crc32c */
8087 uint32_t c = extract32(insn, 8, 4);
8088
8089 /* Check this CPU supports ARMv8 CRC instructions.
8090 * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
8091 * Bits 8, 10 and 11 should be zero.
8092 */
8093 if (!arm_dc_feature(s, ARM_FEATURE_CRC) || op1 == 0x3 ||
8094 (c & 0xd) != 0) {
8095 goto illegal_op;
8096 }
8097
8098 rn = extract32(insn, 16, 4);
8099 rd = extract32(insn, 12, 4);
8100
8101 tmp = load_reg(s, rn);
8102 tmp2 = load_reg(s, rm);
8103 if (op1 == 0) {
8104 tcg_gen_andi_i32(tmp2, tmp2, 0xff);
8105 } else if (op1 == 1) {
8106 tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
8107 }
8108 tmp3 = tcg_const_i32(1 << op1);
8109 if (c & 0x2) {
8110 gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
8111 } else {
8112 gen_helper_crc32(tmp, tmp, tmp2, tmp3);
8113 }
8114 tcg_temp_free_i32(tmp2);
8115 tcg_temp_free_i32(tmp3);
8116 store_reg(s, rd, tmp);
8117 break;
8118 }
8119 case 0x5: /* saturating add/subtract */
8120 ARCH(5TE);
8121 rd = (insn >> 12) & 0xf;
8122 rn = (insn >> 16) & 0xf;
8123 tmp = load_reg(s, rm);
8124 tmp2 = load_reg(s, rn);
8125 if (op1 & 2)
8126 gen_helper_double_saturate(tmp2, cpu_env, tmp2);
8127 if (op1 & 1)
8128 gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
8129 else
8130 gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
8131 tcg_temp_free_i32(tmp2);
8132 store_reg(s, rd, tmp);
8133 break;
8134 case 7:
8135 {
8136 int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4);
8137 switch (op1) {
8138 case 1:
8139 /* bkpt */
8140 ARCH(5);
8141 gen_exception_insn(s, 4, EXCP_BKPT,
8142 syn_aa32_bkpt(imm16, false),
8143 default_exception_el(s));
8144 break;
8145 case 2:
8146 /* Hypervisor call (v7) */
8147 ARCH(7);
8148 if (IS_USER(s)) {
8149 goto illegal_op;
8150 }
8151 gen_hvc(s, imm16);
8152 break;
8153 case 3:
8154 /* Secure monitor call (v6+) */
8155 ARCH(6K);
8156 if (IS_USER(s)) {
8157 goto illegal_op;
8158 }
8159 gen_smc(s);
8160 break;
8161 default:
8162 goto illegal_op;
8163 }
8164 break;
8165 }
8166 case 0x8: /* signed multiply */
8167 case 0xa:
8168 case 0xc:
8169 case 0xe:
8170 ARCH(5TE);
8171 rs = (insn >> 8) & 0xf;
8172 rn = (insn >> 12) & 0xf;
8173 rd = (insn >> 16) & 0xf;
8174 if (op1 == 1) {
8175 /* (32 * 16) >> 16 */
8176 tmp = load_reg(s, rm);
8177 tmp2 = load_reg(s, rs);
8178 if (sh & 4)
8179 tcg_gen_sari_i32(tmp2, tmp2, 16);
8180 else
8181 gen_sxth(tmp2);
8182 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8183 tcg_gen_shri_i64(tmp64, tmp64, 16);
8184 tmp = tcg_temp_new_i32();
8185 tcg_gen_extrl_i64_i32(tmp, tmp64);
8186 tcg_temp_free_i64(tmp64);
8187 if ((sh & 2) == 0) {
8188 tmp2 = load_reg(s, rn);
8189 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
8190 tcg_temp_free_i32(tmp2);
8191 }
8192 store_reg(s, rd, tmp);
8193 } else {
8194 /* 16 * 16 */
8195 tmp = load_reg(s, rm);
8196 tmp2 = load_reg(s, rs);
8197 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
8198 tcg_temp_free_i32(tmp2);
8199 if (op1 == 2) {
8200 tmp64 = tcg_temp_new_i64();
8201 tcg_gen_ext_i32_i64(tmp64, tmp);
8202 tcg_temp_free_i32(tmp);
8203 gen_addq(s, tmp64, rn, rd);
8204 gen_storeq_reg(s, rn, rd, tmp64);
8205 tcg_temp_free_i64(tmp64);
8206 } else {
8207 if (op1 == 0) {
8208 tmp2 = load_reg(s, rn);
8209 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
8210 tcg_temp_free_i32(tmp2);
8211 }
8212 store_reg(s, rd, tmp);
8213 }
8214 }
8215 break;
8216 default:
8217 goto illegal_op;
8218 }
8219 } else if (((insn & 0x0e000000) == 0 &&
8220 (insn & 0x00000090) != 0x90) ||
8221 ((insn & 0x0e000000) == (1 << 25))) {
8222 int set_cc, logic_cc, shiftop;
8223
8224 op1 = (insn >> 21) & 0xf;
8225 set_cc = (insn >> 20) & 1;
8226 logic_cc = table_logic_cc[op1] & set_cc;
8227
8228 /* data processing instruction */
8229 if (insn & (1 << 25)) {
8230 /* immediate operand */
8231 val = insn & 0xff;
8232 shift = ((insn >> 8) & 0xf) * 2;
8233 if (shift) {
8234 val = (val >> shift) | (val << (32 - shift));
8235 }
8236 tmp2 = tcg_temp_new_i32();
8237 tcg_gen_movi_i32(tmp2, val);
8238 if (logic_cc && shift) {
8239 gen_set_CF_bit31(tmp2);
8240 }
8241 } else {
8242 /* register */
8243 rm = (insn) & 0xf;
8244 tmp2 = load_reg(s, rm);
8245 shiftop = (insn >> 5) & 3;
8246 if (!(insn & (1 << 4))) {
8247 shift = (insn >> 7) & 0x1f;
8248 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
8249 } else {
8250 rs = (insn >> 8) & 0xf;
8251 tmp = load_reg(s, rs);
8252 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
8253 }
8254 }
8255 if (op1 != 0x0f && op1 != 0x0d) {
8256 rn = (insn >> 16) & 0xf;
8257 tmp = load_reg(s, rn);
8258 } else {
8259 TCGV_UNUSED_I32(tmp);
8260 }
8261 rd = (insn >> 12) & 0xf;
8262 switch(op1) {
8263 case 0x00:
8264 tcg_gen_and_i32(tmp, tmp, tmp2);
8265 if (logic_cc) {
8266 gen_logic_CC(tmp);
8267 }
8268 store_reg_bx(s, rd, tmp);
8269 break;
8270 case 0x01:
8271 tcg_gen_xor_i32(tmp, tmp, tmp2);
8272 if (logic_cc) {
8273 gen_logic_CC(tmp);
8274 }
8275 store_reg_bx(s, rd, tmp);
8276 break;
8277 case 0x02:
8278 if (set_cc && rd == 15) {
8279 /* SUBS r15, ... is used for exception return. */
8280 if (IS_USER(s)) {
8281 goto illegal_op;
8282 }
8283 gen_sub_CC(tmp, tmp, tmp2);
8284 gen_exception_return(s, tmp);
8285 } else {
8286 if (set_cc) {
8287 gen_sub_CC(tmp, tmp, tmp2);
8288 } else {
8289 tcg_gen_sub_i32(tmp, tmp, tmp2);
8290 }
8291 store_reg_bx(s, rd, tmp);
8292 }
8293 break;
8294 case 0x03:
8295 if (set_cc) {
8296 gen_sub_CC(tmp, tmp2, tmp);
8297 } else {
8298 tcg_gen_sub_i32(tmp, tmp2, tmp);
8299 }
8300 store_reg_bx(s, rd, tmp);
8301 break;
8302 case 0x04:
8303 if (set_cc) {
8304 gen_add_CC(tmp, tmp, tmp2);
8305 } else {
8306 tcg_gen_add_i32(tmp, tmp, tmp2);
8307 }
8308 store_reg_bx(s, rd, tmp);
8309 break;
8310 case 0x05:
8311 if (set_cc) {
8312 gen_adc_CC(tmp, tmp, tmp2);
8313 } else {
8314 gen_add_carry(tmp, tmp, tmp2);
8315 }
8316 store_reg_bx(s, rd, tmp);
8317 break;
8318 case 0x06:
8319 if (set_cc) {
8320 gen_sbc_CC(tmp, tmp, tmp2);
8321 } else {
8322 gen_sub_carry(tmp, tmp, tmp2);
8323 }
8324 store_reg_bx(s, rd, tmp);
8325 break;
8326 case 0x07:
8327 if (set_cc) {
8328 gen_sbc_CC(tmp, tmp2, tmp);
8329 } else {
8330 gen_sub_carry(tmp, tmp2, tmp);
8331 }
8332 store_reg_bx(s, rd, tmp);
8333 break;
8334 case 0x08:
8335 if (set_cc) {
8336 tcg_gen_and_i32(tmp, tmp, tmp2);
8337 gen_logic_CC(tmp);
8338 }
8339 tcg_temp_free_i32(tmp);
8340 break;
8341 case 0x09:
8342 if (set_cc) {
8343 tcg_gen_xor_i32(tmp, tmp, tmp2);
8344 gen_logic_CC(tmp);
8345 }
8346 tcg_temp_free_i32(tmp);
8347 break;
8348 case 0x0a:
8349 if (set_cc) {
8350 gen_sub_CC(tmp, tmp, tmp2);
8351 }
8352 tcg_temp_free_i32(tmp);
8353 break;
8354 case 0x0b:
8355 if (set_cc) {
8356 gen_add_CC(tmp, tmp, tmp2);
8357 }
8358 tcg_temp_free_i32(tmp);
8359 break;
8360 case 0x0c:
8361 tcg_gen_or_i32(tmp, tmp, tmp2);
8362 if (logic_cc) {
8363 gen_logic_CC(tmp);
8364 }
8365 store_reg_bx(s, rd, tmp);
8366 break;
8367 case 0x0d:
8368 if (logic_cc && rd == 15) {
8369 /* MOVS r15, ... is used for exception return. */
8370 if (IS_USER(s)) {
8371 goto illegal_op;
8372 }
8373 gen_exception_return(s, tmp2);
8374 } else {
8375 if (logic_cc) {
8376 gen_logic_CC(tmp2);
8377 }
8378 store_reg_bx(s, rd, tmp2);
8379 }
8380 break;
8381 case 0x0e:
8382 tcg_gen_andc_i32(tmp, tmp, tmp2);
8383 if (logic_cc) {
8384 gen_logic_CC(tmp);
8385 }
8386 store_reg_bx(s, rd, tmp);
8387 break;
8388 default:
8389 case 0x0f:
8390 tcg_gen_not_i32(tmp2, tmp2);
8391 if (logic_cc) {
8392 gen_logic_CC(tmp2);
8393 }
8394 store_reg_bx(s, rd, tmp2);
8395 break;
8396 }
8397 if (op1 != 0x0f && op1 != 0x0d) {
8398 tcg_temp_free_i32(tmp2);
8399 }
8400 } else {
8401 /* other instructions */
8402 op1 = (insn >> 24) & 0xf;
8403 switch(op1) {
8404 case 0x0:
8405 case 0x1:
8406 /* multiplies, extra load/stores */
8407 sh = (insn >> 5) & 3;
8408 if (sh == 0) {
8409 if (op1 == 0x0) {
8410 rd = (insn >> 16) & 0xf;
8411 rn = (insn >> 12) & 0xf;
8412 rs = (insn >> 8) & 0xf;
8413 rm = (insn) & 0xf;
8414 op1 = (insn >> 20) & 0xf;
8415 switch (op1) {
8416 case 0: case 1: case 2: case 3: case 6:
8417 /* 32 bit mul */
8418 tmp = load_reg(s, rs);
8419 tmp2 = load_reg(s, rm);
8420 tcg_gen_mul_i32(tmp, tmp, tmp2);
8421 tcg_temp_free_i32(tmp2);
8422 if (insn & (1 << 22)) {
8423 /* Subtract (mls) */
8424 ARCH(6T2);
8425 tmp2 = load_reg(s, rn);
8426 tcg_gen_sub_i32(tmp, tmp2, tmp);
8427 tcg_temp_free_i32(tmp2);
8428 } else if (insn & (1 << 21)) {
8429 /* Add */
8430 tmp2 = load_reg(s, rn);
8431 tcg_gen_add_i32(tmp, tmp, tmp2);
8432 tcg_temp_free_i32(tmp2);
8433 }
8434 if (insn & (1 << 20))
8435 gen_logic_CC(tmp);
8436 store_reg(s, rd, tmp);
8437 break;
8438 case 4:
8439 /* 64 bit mul double accumulate (UMAAL) */
8440 ARCH(6);
8441 tmp = load_reg(s, rs);
8442 tmp2 = load_reg(s, rm);
8443 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
8444 gen_addq_lo(s, tmp64, rn);
8445 gen_addq_lo(s, tmp64, rd);
8446 gen_storeq_reg(s, rn, rd, tmp64);
8447 tcg_temp_free_i64(tmp64);
8448 break;
8449 case 8: case 9: case 10: case 11:
8450 case 12: case 13: case 14: case 15:
8451 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
8452 tmp = load_reg(s, rs);
8453 tmp2 = load_reg(s, rm);
8454 if (insn & (1 << 22)) {
8455 tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2);
8456 } else {
8457 tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2);
8458 }
8459 if (insn & (1 << 21)) { /* mult accumulate */
8460 TCGv_i32 al = load_reg(s, rn);
8461 TCGv_i32 ah = load_reg(s, rd);
8462 tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah);
8463 tcg_temp_free_i32(al);
8464 tcg_temp_free_i32(ah);
8465 }
8466 if (insn & (1 << 20)) {
8467 gen_logicq_cc(tmp, tmp2);
8468 }
8469 store_reg(s, rn, tmp);
8470 store_reg(s, rd, tmp2);
8471 break;
8472 default:
8473 goto illegal_op;
8474 }
8475 } else {
8476 rn = (insn >> 16) & 0xf;
8477 rd = (insn >> 12) & 0xf;
8478 if (insn & (1 << 23)) {
8479 /* load/store exclusive */
8480 int op2 = (insn >> 8) & 3;
8481 op1 = (insn >> 21) & 0x3;
8482
8483 switch (op2) {
8484 case 0: /* lda/stl */
8485 if (op1 == 1) {
8486 goto illegal_op;
8487 }
8488 ARCH(8);
8489 break;
8490 case 1: /* reserved */
8491 goto illegal_op;
8492 case 2: /* ldaex/stlex */
8493 ARCH(8);
8494 break;
8495 case 3: /* ldrex/strex */
8496 if (op1) {
8497 ARCH(6K);
8498 } else {
8499 ARCH(6);
8500 }
8501 break;
8502 }
8503
8504 addr = tcg_temp_local_new_i32();
8505 load_reg_var(s, addr, rn);
8506
8507 /* Since the emulation does not have barriers,
8508 the acquire/release semantics need no special
8509 handling */
8510 if (op2 == 0) {
8511 if (insn & (1 << 20)) {
8512 tmp = tcg_temp_new_i32();
8513 switch (op1) {
8514 case 0: /* lda */
8515 gen_aa32_ld32u(s, tmp, addr,
8516 get_mem_index(s));
8517 break;
8518 case 2: /* ldab */
8519 gen_aa32_ld8u(s, tmp, addr,
8520 get_mem_index(s));
8521 break;
8522 case 3: /* ldah */
8523 gen_aa32_ld16u(s, tmp, addr,
8524 get_mem_index(s));
8525 break;
8526 default:
8527 abort();
8528 }
8529 store_reg(s, rd, tmp);
8530 } else {
8531 rm = insn & 0xf;
8532 tmp = load_reg(s, rm);
8533 switch (op1) {
8534 case 0: /* stl */
8535 gen_aa32_st32(s, tmp, addr,
8536 get_mem_index(s));
8537 break;
8538 case 2: /* stlb */
8539 gen_aa32_st8(s, tmp, addr,
8540 get_mem_index(s));
8541 break;
8542 case 3: /* stlh */
8543 gen_aa32_st16(s, tmp, addr,
8544 get_mem_index(s));
8545 break;
8546 default:
8547 abort();
8548 }
8549 tcg_temp_free_i32(tmp);
8550 }
8551 } else if (insn & (1 << 20)) {
8552 switch (op1) {
8553 case 0: /* ldrex */
8554 gen_load_exclusive(s, rd, 15, addr, 2);
8555 break;
8556 case 1: /* ldrexd */
8557 gen_load_exclusive(s, rd, rd + 1, addr, 3);
8558 break;
8559 case 2: /* ldrexb */
8560 gen_load_exclusive(s, rd, 15, addr, 0);
8561 break;
8562 case 3: /* ldrexh */
8563 gen_load_exclusive(s, rd, 15, addr, 1);
8564 break;
8565 default:
8566 abort();
8567 }
8568 } else {
8569 rm = insn & 0xf;
8570 switch (op1) {
8571 case 0: /* strex */
8572 gen_store_exclusive(s, rd, rm, 15, addr, 2);
8573 break;
8574 case 1: /* strexd */
8575 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
8576 break;
8577 case 2: /* strexb */
8578 gen_store_exclusive(s, rd, rm, 15, addr, 0);
8579 break;
8580 case 3: /* strexh */
8581 gen_store_exclusive(s, rd, rm, 15, addr, 1);
8582 break;
8583 default:
8584 abort();
8585 }
8586 }
8587 tcg_temp_free_i32(addr);
8588 } else {
8589 /* SWP instruction */
8590 rm = (insn) & 0xf;
8591
8592 /* ??? This is not really atomic. However we know
8593 we never have multiple CPUs running in parallel,
8594 so it is good enough. */
8595 addr = load_reg(s, rn);
8596 tmp = load_reg(s, rm);
8597 tmp2 = tcg_temp_new_i32();
8598 if (insn & (1 << 22)) {
8599 gen_aa32_ld8u(s, tmp2, addr, get_mem_index(s));
8600 gen_aa32_st8(s, tmp, addr, get_mem_index(s));
8601 } else {
8602 gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s));
8603 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
8604 }
8605 tcg_temp_free_i32(tmp);
8606 tcg_temp_free_i32(addr);
8607 store_reg(s, rd, tmp2);
8608 }
8609 }
8610 } else {
8611 int address_offset;
8612 bool load = insn & (1 << 20);
8613 bool doubleword = false;
8614 /* Misc load/store */
8615 rn = (insn >> 16) & 0xf;
8616 rd = (insn >> 12) & 0xf;
8617
8618 if (!load && (sh & 2)) {
8619 /* doubleword */
8620 ARCH(5TE);
8621 if (rd & 1) {
8622 /* UNPREDICTABLE; we choose to UNDEF */
8623 goto illegal_op;
8624 }
8625 load = (sh & 1) == 0;
8626 doubleword = true;
8627 }
8628
8629 addr = load_reg(s, rn);
8630 if (insn & (1 << 24))
8631 gen_add_datah_offset(s, insn, 0, addr);
8632 address_offset = 0;
8633
8634 if (doubleword) {
8635 if (!load) {
8636 /* store */
8637 tmp = load_reg(s, rd);
8638 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
8639 tcg_temp_free_i32(tmp);
8640 tcg_gen_addi_i32(addr, addr, 4);
8641 tmp = load_reg(s, rd + 1);
8642 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
8643 tcg_temp_free_i32(tmp);
8644 } else {
8645 /* load */
8646 tmp = tcg_temp_new_i32();
8647 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
8648 store_reg(s, rd, tmp);
8649 tcg_gen_addi_i32(addr, addr, 4);
8650 tmp = tcg_temp_new_i32();
8651 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
8652 rd++;
8653 }
8654 address_offset = -4;
8655 } else if (load) {
8656 /* load */
8657 tmp = tcg_temp_new_i32();
8658 switch (sh) {
8659 case 1:
8660 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
8661 break;
8662 case 2:
8663 gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
8664 break;
8665 default:
8666 case 3:
8667 gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
8668 break;
8669 }
8670 } else {
8671 /* store */
8672 tmp = load_reg(s, rd);
8673 gen_aa32_st16(s, tmp, addr, get_mem_index(s));
8674 tcg_temp_free_i32(tmp);
8675 }
8676 /* Perform base writeback before the loaded value to
8677 ensure correct behavior with overlapping index registers.
8678 ldrd with base writeback is undefined if the
8679 destination and index registers overlap. */
8680 if (!(insn & (1 << 24))) {
8681 gen_add_datah_offset(s, insn, address_offset, addr);
8682 store_reg(s, rn, addr);
8683 } else if (insn & (1 << 21)) {
8684 if (address_offset)
8685 tcg_gen_addi_i32(addr, addr, address_offset);
8686 store_reg(s, rn, addr);
8687 } else {
8688 tcg_temp_free_i32(addr);
8689 }
8690 if (load) {
8691 /* Complete the load. */
8692 store_reg(s, rd, tmp);
8693 }
8694 }
8695 break;
8696 case 0x4:
8697 case 0x5:
8698 goto do_ldst;
8699 case 0x6:
8700 case 0x7:
8701 if (insn & (1 << 4)) {
8702 ARCH(6);
8703 /* Armv6 Media instructions. */
8704 rm = insn & 0xf;
8705 rn = (insn >> 16) & 0xf;
8706 rd = (insn >> 12) & 0xf;
8707 rs = (insn >> 8) & 0xf;
8708 switch ((insn >> 23) & 3) {
8709 case 0: /* Parallel add/subtract. */
8710 op1 = (insn >> 20) & 7;
8711 tmp = load_reg(s, rn);
8712 tmp2 = load_reg(s, rm);
8713 sh = (insn >> 5) & 7;
8714 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
8715 goto illegal_op;
8716 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
8717 tcg_temp_free_i32(tmp2);
8718 store_reg(s, rd, tmp);
8719 break;
8720 case 1:
8721 if ((insn & 0x00700020) == 0) {
8722 /* Halfword pack. */
8723 tmp = load_reg(s, rn);
8724 tmp2 = load_reg(s, rm);
8725 shift = (insn >> 7) & 0x1f;
8726 if (insn & (1 << 6)) {
8727 /* pkhtb */
8728 if (shift == 0)
8729 shift = 31;
8730 tcg_gen_sari_i32(tmp2, tmp2, shift);
8731 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
8732 tcg_gen_ext16u_i32(tmp2, tmp2);
8733 } else {
8734 /* pkhbt */
8735 if (shift)
8736 tcg_gen_shli_i32(tmp2, tmp2, shift);
8737 tcg_gen_ext16u_i32(tmp, tmp);
8738 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
8739 }
8740 tcg_gen_or_i32(tmp, tmp, tmp2);
8741 tcg_temp_free_i32(tmp2);
8742 store_reg(s, rd, tmp);
8743 } else if ((insn & 0x00200020) == 0x00200000) {
8744 /* [us]sat */
8745 tmp = load_reg(s, rm);
8746 shift = (insn >> 7) & 0x1f;
8747 if (insn & (1 << 6)) {
8748 if (shift == 0)
8749 shift = 31;
8750 tcg_gen_sari_i32(tmp, tmp, shift);
8751 } else {
8752 tcg_gen_shli_i32(tmp, tmp, shift);
8753 }
8754 sh = (insn >> 16) & 0x1f;
8755 tmp2 = tcg_const_i32(sh);
8756 if (insn & (1 << 22))
8757 gen_helper_usat(tmp, cpu_env, tmp, tmp2);
8758 else
8759 gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
8760 tcg_temp_free_i32(tmp2);
8761 store_reg(s, rd, tmp);
8762 } else if ((insn & 0x00300fe0) == 0x00200f20) {
8763 /* [us]sat16 */
8764 tmp = load_reg(s, rm);
8765 sh = (insn >> 16) & 0x1f;
8766 tmp2 = tcg_const_i32(sh);
8767 if (insn & (1 << 22))
8768 gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
8769 else
8770 gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
8771 tcg_temp_free_i32(tmp2);
8772 store_reg(s, rd, tmp);
8773 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
8774 /* Select bytes. */
8775 tmp = load_reg(s, rn);
8776 tmp2 = load_reg(s, rm);
8777 tmp3 = tcg_temp_new_i32();
8778 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
8779 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
8780 tcg_temp_free_i32(tmp3);
8781 tcg_temp_free_i32(tmp2);
8782 store_reg(s, rd, tmp);
8783 } else if ((insn & 0x000003e0) == 0x00000060) {
8784 tmp = load_reg(s, rm);
8785 shift = (insn >> 10) & 3;
8786 /* ??? In many cases it's not necessary to do a
8787 rotate, a shift is sufficient. */
8788 if (shift != 0)
8789 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
8790 op1 = (insn >> 20) & 7;
8791 switch (op1) {
8792 case 0: gen_sxtb16(tmp); break;
8793 case 2: gen_sxtb(tmp); break;
8794 case 3: gen_sxth(tmp); break;
8795 case 4: gen_uxtb16(tmp); break;
8796 case 6: gen_uxtb(tmp); break;
8797 case 7: gen_uxth(tmp); break;
8798 default: goto illegal_op;
8799 }
8800 if (rn != 15) {
8801 tmp2 = load_reg(s, rn);
8802 if ((op1 & 3) == 0) {
8803 gen_add16(tmp, tmp2);
8804 } else {
8805 tcg_gen_add_i32(tmp, tmp, tmp2);
8806 tcg_temp_free_i32(tmp2);
8807 }
8808 }
8809 store_reg(s, rd, tmp);
8810 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
8811 /* rev */
8812 tmp = load_reg(s, rm);
8813 if (insn & (1 << 22)) {
8814 if (insn & (1 << 7)) {
8815 gen_revsh(tmp);
8816 } else {
8817 ARCH(6T2);
8818 gen_helper_rbit(tmp, tmp);
8819 }
8820 } else {
8821 if (insn & (1 << 7))
8822 gen_rev16(tmp);
8823 else
8824 tcg_gen_bswap32_i32(tmp, tmp);
8825 }
8826 store_reg(s, rd, tmp);
8827 } else {
8828 goto illegal_op;
8829 }
8830 break;
8831 case 2: /* Multiplies (Type 3). */
8832 switch ((insn >> 20) & 0x7) {
8833 case 5:
8834 if (((insn >> 6) ^ (insn >> 7)) & 1) {
8835 /* op2 not 00x or 11x : UNDEF */
8836 goto illegal_op;
8837 }
8838 /* Signed multiply most significant [accumulate].
8839 (SMMUL, SMMLA, SMMLS) */
8840 tmp = load_reg(s, rm);
8841 tmp2 = load_reg(s, rs);
8842 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8843
8844 if (rd != 15) {
8845 tmp = load_reg(s, rd);
8846 if (insn & (1 << 6)) {
8847 tmp64 = gen_subq_msw(tmp64, tmp);
8848 } else {
8849 tmp64 = gen_addq_msw(tmp64, tmp);
8850 }
8851 }
8852 if (insn & (1 << 5)) {
8853 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
8854 }
8855 tcg_gen_shri_i64(tmp64, tmp64, 32);
8856 tmp = tcg_temp_new_i32();
8857 tcg_gen_extrl_i64_i32(tmp, tmp64);
8858 tcg_temp_free_i64(tmp64);
8859 store_reg(s, rn, tmp);
8860 break;
8861 case 0:
8862 case 4:
8863 /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */
8864 if (insn & (1 << 7)) {
8865 goto illegal_op;
8866 }
8867 tmp = load_reg(s, rm);
8868 tmp2 = load_reg(s, rs);
8869 if (insn & (1 << 5))
8870 gen_swap_half(tmp2);
8871 gen_smul_dual(tmp, tmp2);
8872 if (insn & (1 << 22)) {
8873 /* smlald, smlsld */
8874 TCGv_i64 tmp64_2;
8875
8876 tmp64 = tcg_temp_new_i64();
8877 tmp64_2 = tcg_temp_new_i64();
8878 tcg_gen_ext_i32_i64(tmp64, tmp);
8879 tcg_gen_ext_i32_i64(tmp64_2, tmp2);
8880 tcg_temp_free_i32(tmp);
8881 tcg_temp_free_i32(tmp2);
8882 if (insn & (1 << 6)) {
8883 tcg_gen_sub_i64(tmp64, tmp64, tmp64_2);
8884 } else {
8885 tcg_gen_add_i64(tmp64, tmp64, tmp64_2);
8886 }
8887 tcg_temp_free_i64(tmp64_2);
8888 gen_addq(s, tmp64, rd, rn);
8889 gen_storeq_reg(s, rd, rn, tmp64);
8890 tcg_temp_free_i64(tmp64);
8891 } else {
8892 /* smuad, smusd, smlad, smlsd */
8893 if (insn & (1 << 6)) {
8894 /* This subtraction cannot overflow. */
8895 tcg_gen_sub_i32(tmp, tmp, tmp2);
8896 } else {
8897 /* This addition cannot overflow 32 bits;
8898 * however it may overflow considered as a
8899 * signed operation, in which case we must set
8900 * the Q flag.
8901 */
8902 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
8903 }
8904 tcg_temp_free_i32(tmp2);
8905 if (rd != 15)
8906 {
8907 tmp2 = load_reg(s, rd);
8908 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
8909 tcg_temp_free_i32(tmp2);
8910 }
8911 store_reg(s, rn, tmp);
8912 }
8913 break;
8914 case 1:
8915 case 3:
8916 /* SDIV, UDIV */
8917 if (!arm_dc_feature(s, ARM_FEATURE_ARM_DIV)) {
8918 goto illegal_op;
8919 }
8920 if (((insn >> 5) & 7) || (rd != 15)) {
8921 goto illegal_op;
8922 }
8923 tmp = load_reg(s, rm);
8924 tmp2 = load_reg(s, rs);
8925 if (insn & (1 << 21)) {
8926 gen_helper_udiv(tmp, tmp, tmp2);
8927 } else {
8928 gen_helper_sdiv(tmp, tmp, tmp2);
8929 }
8930 tcg_temp_free_i32(tmp2);
8931 store_reg(s, rn, tmp);
8932 break;
8933 default:
8934 goto illegal_op;
8935 }
8936 break;
8937 case 3:
8938 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
8939 switch (op1) {
8940 case 0: /* Unsigned sum of absolute differences. */
8941 ARCH(6);
8942 tmp = load_reg(s, rm);
8943 tmp2 = load_reg(s, rs);
8944 gen_helper_usad8(tmp, tmp, tmp2);
8945 tcg_temp_free_i32(tmp2);
8946 if (rd != 15) {
8947 tmp2 = load_reg(s, rd);
8948 tcg_gen_add_i32(tmp, tmp, tmp2);
8949 tcg_temp_free_i32(tmp2);
8950 }
8951 store_reg(s, rn, tmp);
8952 break;
8953 case 0x20: case 0x24: case 0x28: case 0x2c:
8954 /* Bitfield insert/clear. */
8955 ARCH(6T2);
8956 shift = (insn >> 7) & 0x1f;
8957 i = (insn >> 16) & 0x1f;
8958 if (i < shift) {
8959 /* UNPREDICTABLE; we choose to UNDEF */
8960 goto illegal_op;
8961 }
8962 i = i + 1 - shift;
8963 if (rm == 15) {
8964 tmp = tcg_temp_new_i32();
8965 tcg_gen_movi_i32(tmp, 0);
8966 } else {
8967 tmp = load_reg(s, rm);
8968 }
8969 if (i != 32) {
8970 tmp2 = load_reg(s, rd);
8971 tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, i);
8972 tcg_temp_free_i32(tmp2);
8973 }
8974 store_reg(s, rd, tmp);
8975 break;
8976 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
8977 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
8978 ARCH(6T2);
8979 tmp = load_reg(s, rm);
8980 shift = (insn >> 7) & 0x1f;
8981 i = ((insn >> 16) & 0x1f) + 1;
8982 if (shift + i > 32)
8983 goto illegal_op;
8984 if (i < 32) {
8985 if (op1 & 0x20) {
8986 gen_ubfx(tmp, shift, (1u << i) - 1);
8987 } else {
8988 gen_sbfx(tmp, shift, i);
8989 }
8990 }
8991 store_reg(s, rd, tmp);
8992 break;
8993 default:
8994 goto illegal_op;
8995 }
8996 break;
8997 }
8998 break;
8999 }
9000 do_ldst:
9001 /* Check for undefined extension instructions
9002 * per the ARM Bible IE:
9003 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
9004 */
9005 sh = (0xf << 20) | (0xf << 4);
9006 if (op1 == 0x7 && ((insn & sh) == sh))
9007 {
9008 goto illegal_op;
9009 }
9010 /* load/store byte/word */
9011 rn = (insn >> 16) & 0xf;
9012 rd = (insn >> 12) & 0xf;
9013 tmp2 = load_reg(s, rn);
9014 if ((insn & 0x01200000) == 0x00200000) {
9015 /* ldrt/strt */
9016 i = get_a32_user_mem_index(s);
9017 } else {
9018 i = get_mem_index(s);
9019 }
9020 if (insn & (1 << 24))
9021 gen_add_data_offset(s, insn, tmp2);
9022 if (insn & (1 << 20)) {
9023 /* load */
9024 tmp = tcg_temp_new_i32();
9025 if (insn & (1 << 22)) {
9026 gen_aa32_ld8u(s, tmp, tmp2, i);
9027 } else {
9028 gen_aa32_ld32u(s, tmp, tmp2, i);
9029 }
9030 } else {
9031 /* store */
9032 tmp = load_reg(s, rd);
9033 if (insn & (1 << 22)) {
9034 gen_aa32_st8(s, tmp, tmp2, i);
9035 } else {
9036 gen_aa32_st32(s, tmp, tmp2, i);
9037 }
9038 tcg_temp_free_i32(tmp);
9039 }
9040 if (!(insn & (1 << 24))) {
9041 gen_add_data_offset(s, insn, tmp2);
9042 store_reg(s, rn, tmp2);
9043 } else if (insn & (1 << 21)) {
9044 store_reg(s, rn, tmp2);
9045 } else {
9046 tcg_temp_free_i32(tmp2);
9047 }
9048 if (insn & (1 << 20)) {
9049 /* Complete the load. */
9050 store_reg_from_load(s, rd, tmp);
9051 }
9052 break;
9053 case 0x08:
9054 case 0x09:
9055 {
9056 int j, n, loaded_base;
9057 bool exc_return = false;
9058 bool is_load = extract32(insn, 20, 1);
9059 bool user = false;
9060 TCGv_i32 loaded_var;
9061 /* load/store multiple words */
9062 /* XXX: store correct base if write back */
9063 if (insn & (1 << 22)) {
9064 /* LDM (user), LDM (exception return) and STM (user) */
9065 if (IS_USER(s))
9066 goto illegal_op; /* only usable in supervisor mode */
9067
9068 if (is_load && extract32(insn, 15, 1)) {
9069 exc_return = true;
9070 } else {
9071 user = true;
9072 }
9073 }
9074 rn = (insn >> 16) & 0xf;
9075 addr = load_reg(s, rn);
9076
9077 /* compute total size */
9078 loaded_base = 0;
9079 TCGV_UNUSED_I32(loaded_var);
9080 n = 0;
9081 for(i=0;i<16;i++) {
9082 if (insn & (1 << i))
9083 n++;
9084 }
9085 /* XXX: test invalid n == 0 case ? */
9086 if (insn & (1 << 23)) {
9087 if (insn & (1 << 24)) {
9088 /* pre increment */
9089 tcg_gen_addi_i32(addr, addr, 4);
9090 } else {
9091 /* post increment */
9092 }
9093 } else {
9094 if (insn & (1 << 24)) {
9095 /* pre decrement */
9096 tcg_gen_addi_i32(addr, addr, -(n * 4));
9097 } else {
9098 /* post decrement */
9099 if (n != 1)
9100 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9101 }
9102 }
9103 j = 0;
9104 for(i=0;i<16;i++) {
9105 if (insn & (1 << i)) {
9106 if (is_load) {
9107 /* load */
9108 tmp = tcg_temp_new_i32();
9109 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
9110 if (user) {
9111 tmp2 = tcg_const_i32(i);
9112 gen_helper_set_user_reg(cpu_env, tmp2, tmp);
9113 tcg_temp_free_i32(tmp2);
9114 tcg_temp_free_i32(tmp);
9115 } else if (i == rn) {
9116 loaded_var = tmp;
9117 loaded_base = 1;
9118 } else {
9119 store_reg_from_load(s, i, tmp);
9120 }
9121 } else {
9122 /* store */
9123 if (i == 15) {
9124 /* special case: r15 = PC + 8 */
9125 val = (long)s->pc + 4;
9126 tmp = tcg_temp_new_i32();
9127 tcg_gen_movi_i32(tmp, val);
9128 } else if (user) {
9129 tmp = tcg_temp_new_i32();
9130 tmp2 = tcg_const_i32(i);
9131 gen_helper_get_user_reg(tmp, cpu_env, tmp2);
9132 tcg_temp_free_i32(tmp2);
9133 } else {
9134 tmp = load_reg(s, i);
9135 }
9136 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
9137 tcg_temp_free_i32(tmp);
9138 }
9139 j++;
9140 /* no need to add after the last transfer */
9141 if (j != n)
9142 tcg_gen_addi_i32(addr, addr, 4);
9143 }
9144 }
9145 if (insn & (1 << 21)) {
9146 /* write back */
9147 if (insn & (1 << 23)) {
9148 if (insn & (1 << 24)) {
9149 /* pre increment */
9150 } else {
9151 /* post increment */
9152 tcg_gen_addi_i32(addr, addr, 4);
9153 }
9154 } else {
9155 if (insn & (1 << 24)) {
9156 /* pre decrement */
9157 if (n != 1)
9158 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9159 } else {
9160 /* post decrement */
9161 tcg_gen_addi_i32(addr, addr, -(n * 4));
9162 }
9163 }
9164 store_reg(s, rn, addr);
9165 } else {
9166 tcg_temp_free_i32(addr);
9167 }
9168 if (loaded_base) {
9169 store_reg(s, rn, loaded_var);
9170 }
9171 if (exc_return) {
9172 /* Restore CPSR from SPSR. */
9173 tmp = load_cpu_field(spsr);
9174 gen_helper_cpsr_write_eret(cpu_env, tmp);
9175 tcg_temp_free_i32(tmp);
9176 s->is_jmp = DISAS_JUMP;
9177 }
9178 }
9179 break;
9180 case 0xa:
9181 case 0xb:
9182 {
9183 int32_t offset;
9184
9185 /* branch (and link) */
9186 val = (int32_t)s->pc;
9187 if (insn & (1 << 24)) {
9188 tmp = tcg_temp_new_i32();
9189 tcg_gen_movi_i32(tmp, val);
9190 store_reg(s, 14, tmp);
9191 }
9192 offset = sextract32(insn << 2, 0, 26);
9193 val += offset + 4;
9194 gen_jmp(s, val);
9195 }
9196 break;
9197 case 0xc:
9198 case 0xd:
9199 case 0xe:
9200 if (((insn >> 8) & 0xe) == 10) {
9201 /* VFP. */
9202 if (disas_vfp_insn(s, insn)) {
9203 goto illegal_op;
9204 }
9205 } else if (disas_coproc_insn(s, insn)) {
9206 /* Coprocessor. */
9207 goto illegal_op;
9208 }
9209 break;
9210 case 0xf:
9211 /* swi */
9212 gen_set_pc_im(s, s->pc);
9213 s->svc_imm = extract32(insn, 0, 24);
9214 s->is_jmp = DISAS_SWI;
9215 break;
9216 default:
9217 illegal_op:
9218 gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
9219 default_exception_el(s));
9220 break;
9221 }
9222 }
9223 }
9224
9225 /* Return true if this is a Thumb-2 logical op. */
9226 static int
9227 thumb2_logic_op(int op)
9228 {
9229 return (op < 8);
9230 }
9231
9232 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
9233 then set condition code flags based on the result of the operation.
9234 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
9235 to the high bit of T1.
9236 Returns zero if the opcode is valid. */
9237
9238 static int
9239 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
9240 TCGv_i32 t0, TCGv_i32 t1)
9241 {
9242 int logic_cc;
9243
9244 logic_cc = 0;
9245 switch (op) {
9246 case 0: /* and */
9247 tcg_gen_and_i32(t0, t0, t1);
9248 logic_cc = conds;
9249 break;
9250 case 1: /* bic */
9251 tcg_gen_andc_i32(t0, t0, t1);
9252 logic_cc = conds;
9253 break;
9254 case 2: /* orr */
9255 tcg_gen_or_i32(t0, t0, t1);
9256 logic_cc = conds;
9257 break;
9258 case 3: /* orn */
9259 tcg_gen_orc_i32(t0, t0, t1);
9260 logic_cc = conds;
9261 break;
9262 case 4: /* eor */
9263 tcg_gen_xor_i32(t0, t0, t1);
9264 logic_cc = conds;
9265 break;
9266 case 8: /* add */
9267 if (conds)
9268 gen_add_CC(t0, t0, t1);
9269 else
9270 tcg_gen_add_i32(t0, t0, t1);
9271 break;
9272 case 10: /* adc */
9273 if (conds)
9274 gen_adc_CC(t0, t0, t1);
9275 else
9276 gen_adc(t0, t1);
9277 break;
9278 case 11: /* sbc */
9279 if (conds) {
9280 gen_sbc_CC(t0, t0, t1);
9281 } else {
9282 gen_sub_carry(t0, t0, t1);
9283 }
9284 break;
9285 case 13: /* sub */
9286 if (conds)
9287 gen_sub_CC(t0, t0, t1);
9288 else
9289 tcg_gen_sub_i32(t0, t0, t1);
9290 break;
9291 case 14: /* rsb */
9292 if (conds)
9293 gen_sub_CC(t0, t1, t0);
9294 else
9295 tcg_gen_sub_i32(t0, t1, t0);
9296 break;
9297 default: /* 5, 6, 7, 9, 12, 15. */
9298 return 1;
9299 }
9300 if (logic_cc) {
9301 gen_logic_CC(t0);
9302 if (shifter_out)
9303 gen_set_CF_bit31(t1);
9304 }
9305 return 0;
9306 }
9307
9308 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
9309 is not legal. */
9310 static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)
9311 {
9312 uint32_t insn, imm, shift, offset;
9313 uint32_t rd, rn, rm, rs;
9314 TCGv_i32 tmp;
9315 TCGv_i32 tmp2;
9316 TCGv_i32 tmp3;
9317 TCGv_i32 addr;
9318 TCGv_i64 tmp64;
9319 int op;
9320 int shiftop;
9321 int conds;
9322 int logic_cc;
9323
9324 if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
9325 || arm_dc_feature(s, ARM_FEATURE_M))) {
9326 /* Thumb-1 cores may need to treat bl and blx as a pair of
9327 16-bit instructions to get correct prefetch abort behavior. */
9328 insn = insn_hw1;
9329 if ((insn & (1 << 12)) == 0) {
9330 ARCH(5);
9331 /* Second half of blx. */
9332 offset = ((insn & 0x7ff) << 1);
9333 tmp = load_reg(s, 14);
9334 tcg_gen_addi_i32(tmp, tmp, offset);
9335 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9336
9337 tmp2 = tcg_temp_new_i32();
9338 tcg_gen_movi_i32(tmp2, s->pc | 1);
9339 store_reg(s, 14, tmp2);
9340 gen_bx(s, tmp);
9341 return 0;
9342 }
9343 if (insn & (1 << 11)) {
9344 /* Second half of bl. */
9345 offset = ((insn & 0x7ff) << 1) | 1;
9346 tmp = load_reg(s, 14);
9347 tcg_gen_addi_i32(tmp, tmp, offset);
9348
9349 tmp2 = tcg_temp_new_i32();
9350 tcg_gen_movi_i32(tmp2, s->pc | 1);
9351 store_reg(s, 14, tmp2);
9352 gen_bx(s, tmp);
9353 return 0;
9354 }
9355 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
9356 /* Instruction spans a page boundary. Implement it as two
9357 16-bit instructions in case the second half causes an
9358 prefetch abort. */
9359 offset = ((int32_t)insn << 21) >> 9;
9360 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
9361 return 0;
9362 }
9363 /* Fall through to 32-bit decode. */
9364 }
9365
9366 insn = arm_lduw_code(env, s->pc, s->sctlr_b);
9367 s->pc += 2;
9368 insn |= (uint32_t)insn_hw1 << 16;
9369
9370 if ((insn & 0xf800e800) != 0xf000e800) {
9371 ARCH(6T2);
9372 }
9373
9374 rn = (insn >> 16) & 0xf;
9375 rs = (insn >> 12) & 0xf;
9376 rd = (insn >> 8) & 0xf;
9377 rm = insn & 0xf;
9378 switch ((insn >> 25) & 0xf) {
9379 case 0: case 1: case 2: case 3:
9380 /* 16-bit instructions. Should never happen. */
9381 abort();
9382 case 4:
9383 if (insn & (1 << 22)) {
9384 /* Other load/store, table branch. */
9385 if (insn & 0x01200000) {
9386 /* Load/store doubleword. */
9387 if (rn == 15) {
9388 addr = tcg_temp_new_i32();
9389 tcg_gen_movi_i32(addr, s->pc & ~3);
9390 } else {
9391 addr = load_reg(s, rn);
9392 }
9393 offset = (insn & 0xff) * 4;
9394 if ((insn & (1 << 23)) == 0)
9395 offset = -offset;
9396 if (insn & (1 << 24)) {
9397 tcg_gen_addi_i32(addr, addr, offset);
9398 offset = 0;
9399 }
9400 if (insn & (1 << 20)) {
9401 /* ldrd */
9402 tmp = tcg_temp_new_i32();
9403 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
9404 store_reg(s, rs, tmp);
9405 tcg_gen_addi_i32(addr, addr, 4);
9406 tmp = tcg_temp_new_i32();
9407 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
9408 store_reg(s, rd, tmp);
9409 } else {
9410 /* strd */
9411 tmp = load_reg(s, rs);
9412 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
9413 tcg_temp_free_i32(tmp);
9414 tcg_gen_addi_i32(addr, addr, 4);
9415 tmp = load_reg(s, rd);
9416 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
9417 tcg_temp_free_i32(tmp);
9418 }
9419 if (insn & (1 << 21)) {
9420 /* Base writeback. */
9421 if (rn == 15)
9422 goto illegal_op;
9423 tcg_gen_addi_i32(addr, addr, offset - 4);
9424 store_reg(s, rn, addr);
9425 } else {
9426 tcg_temp_free_i32(addr);
9427 }
9428 } else if ((insn & (1 << 23)) == 0) {
9429 /* Load/store exclusive word. */
9430 addr = tcg_temp_local_new_i32();
9431 load_reg_var(s, addr, rn);
9432 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
9433 if (insn & (1 << 20)) {
9434 gen_load_exclusive(s, rs, 15, addr, 2);
9435 } else {
9436 gen_store_exclusive(s, rd, rs, 15, addr, 2);
9437 }
9438 tcg_temp_free_i32(addr);
9439 } else if ((insn & (7 << 5)) == 0) {
9440 /* Table Branch. */
9441 if (rn == 15) {
9442 addr = tcg_temp_new_i32();
9443 tcg_gen_movi_i32(addr, s->pc);
9444 } else {
9445 addr = load_reg(s, rn);
9446 }
9447 tmp = load_reg(s, rm);
9448 tcg_gen_add_i32(addr, addr, tmp);
9449 if (insn & (1 << 4)) {
9450 /* tbh */
9451 tcg_gen_add_i32(addr, addr, tmp);
9452 tcg_temp_free_i32(tmp);
9453 tmp = tcg_temp_new_i32();
9454 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
9455 } else { /* tbb */
9456 tcg_temp_free_i32(tmp);
9457 tmp = tcg_temp_new_i32();
9458 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
9459 }
9460 tcg_temp_free_i32(addr);
9461 tcg_gen_shli_i32(tmp, tmp, 1);
9462 tcg_gen_addi_i32(tmp, tmp, s->pc);
9463 store_reg(s, 15, tmp);
9464 } else {
9465 int op2 = (insn >> 6) & 0x3;
9466 op = (insn >> 4) & 0x3;
9467 switch (op2) {
9468 case 0:
9469 goto illegal_op;
9470 case 1:
9471 /* Load/store exclusive byte/halfword/doubleword */
9472 if (op == 2) {
9473 goto illegal_op;
9474 }
9475 ARCH(7);
9476 break;
9477 case 2:
9478 /* Load-acquire/store-release */
9479 if (op == 3) {
9480 goto illegal_op;
9481 }
9482 /* Fall through */
9483 case 3:
9484 /* Load-acquire/store-release exclusive */
9485 ARCH(8);
9486 break;
9487 }
9488 addr = tcg_temp_local_new_i32();
9489 load_reg_var(s, addr, rn);
9490 if (!(op2 & 1)) {
9491 if (insn & (1 << 20)) {
9492 tmp = tcg_temp_new_i32();
9493 switch (op) {
9494 case 0: /* ldab */
9495 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
9496 break;
9497 case 1: /* ldah */
9498 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
9499 break;
9500 case 2: /* lda */
9501 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
9502 break;
9503 default:
9504 abort();
9505 }
9506 store_reg(s, rs, tmp);
9507 } else {
9508 tmp = load_reg(s, rs);
9509 switch (op) {
9510 case 0: /* stlb */
9511 gen_aa32_st8(s, tmp, addr, get_mem_index(s));
9512 break;
9513 case 1: /* stlh */
9514 gen_aa32_st16(s, tmp, addr, get_mem_index(s));
9515 break;
9516 case 2: /* stl */
9517 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
9518 break;
9519 default:
9520 abort();
9521 }
9522 tcg_temp_free_i32(tmp);
9523 }
9524 } else if (insn & (1 << 20)) {
9525 gen_load_exclusive(s, rs, rd, addr, op);
9526 } else {
9527 gen_store_exclusive(s, rm, rs, rd, addr, op);
9528 }
9529 tcg_temp_free_i32(addr);
9530 }
9531 } else {
9532 /* Load/store multiple, RFE, SRS. */
9533 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
9534 /* RFE, SRS: not available in user mode or on M profile */
9535 if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
9536 goto illegal_op;
9537 }
9538 if (insn & (1 << 20)) {
9539 /* rfe */
9540 addr = load_reg(s, rn);
9541 if ((insn & (1 << 24)) == 0)
9542 tcg_gen_addi_i32(addr, addr, -8);
9543 /* Load PC into tmp and CPSR into tmp2. */
9544 tmp = tcg_temp_new_i32();
9545 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
9546 tcg_gen_addi_i32(addr, addr, 4);
9547 tmp2 = tcg_temp_new_i32();
9548 gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s));
9549 if (insn & (1 << 21)) {
9550 /* Base writeback. */
9551 if (insn & (1 << 24)) {
9552 tcg_gen_addi_i32(addr, addr, 4);
9553 } else {
9554 tcg_gen_addi_i32(addr, addr, -4);
9555 }
9556 store_reg(s, rn, addr);
9557 } else {
9558 tcg_temp_free_i32(addr);
9559 }
9560 gen_rfe(s, tmp, tmp2);
9561 } else {
9562 /* srs */
9563 gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2,
9564 insn & (1 << 21));
9565 }
9566 } else {
9567 int i, loaded_base = 0;
9568 TCGv_i32 loaded_var;
9569 /* Load/store multiple. */
9570 addr = load_reg(s, rn);
9571 offset = 0;
9572 for (i = 0; i < 16; i++) {
9573 if (insn & (1 << i))
9574 offset += 4;
9575 }
9576 if (insn & (1 << 24)) {
9577 tcg_gen_addi_i32(addr, addr, -offset);
9578 }
9579
9580 TCGV_UNUSED_I32(loaded_var);
9581 for (i = 0; i < 16; i++) {
9582 if ((insn & (1 << i)) == 0)
9583 continue;
9584 if (insn & (1 << 20)) {
9585 /* Load. */
9586 tmp = tcg_temp_new_i32();
9587 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
9588 if (i == 15) {
9589 gen_bx(s, tmp);
9590 } else if (i == rn) {
9591 loaded_var = tmp;
9592 loaded_base = 1;
9593 } else {
9594 store_reg(s, i, tmp);
9595 }
9596 } else {
9597 /* Store. */
9598 tmp = load_reg(s, i);
9599 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
9600 tcg_temp_free_i32(tmp);
9601 }
9602 tcg_gen_addi_i32(addr, addr, 4);
9603 }
9604 if (loaded_base) {
9605 store_reg(s, rn, loaded_var);
9606 }
9607 if (insn & (1 << 21)) {
9608 /* Base register writeback. */
9609 if (insn & (1 << 24)) {
9610 tcg_gen_addi_i32(addr, addr, -offset);
9611 }
9612 /* Fault if writeback register is in register list. */
9613 if (insn & (1 << rn))
9614 goto illegal_op;
9615 store_reg(s, rn, addr);
9616 } else {
9617 tcg_temp_free_i32(addr);
9618 }
9619 }
9620 }
9621 break;
9622 case 5:
9623
9624 op = (insn >> 21) & 0xf;
9625 if (op == 6) {
9626 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
9627 goto illegal_op;
9628 }
9629 /* Halfword pack. */
9630 tmp = load_reg(s, rn);
9631 tmp2 = load_reg(s, rm);
9632 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
9633 if (insn & (1 << 5)) {
9634 /* pkhtb */
9635 if (shift == 0)
9636 shift = 31;
9637 tcg_gen_sari_i32(tmp2, tmp2, shift);
9638 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
9639 tcg_gen_ext16u_i32(tmp2, tmp2);
9640 } else {
9641 /* pkhbt */
9642 if (shift)
9643 tcg_gen_shli_i32(tmp2, tmp2, shift);
9644 tcg_gen_ext16u_i32(tmp, tmp);
9645 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
9646 }
9647 tcg_gen_or_i32(tmp, tmp, tmp2);
9648 tcg_temp_free_i32(tmp2);
9649 store_reg(s, rd, tmp);
9650 } else {
9651 /* Data processing register constant shift. */
9652 if (rn == 15) {
9653 tmp = tcg_temp_new_i32();
9654 tcg_gen_movi_i32(tmp, 0);
9655 } else {
9656 tmp = load_reg(s, rn);
9657 }
9658 tmp2 = load_reg(s, rm);
9659
9660 shiftop = (insn >> 4) & 3;
9661 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
9662 conds = (insn & (1 << 20)) != 0;
9663 logic_cc = (conds && thumb2_logic_op(op));
9664 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9665 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
9666 goto illegal_op;
9667 tcg_temp_free_i32(tmp2);
9668 if (rd != 15) {
9669 store_reg(s, rd, tmp);
9670 } else {
9671 tcg_temp_free_i32(tmp);
9672 }
9673 }
9674 break;
9675 case 13: /* Misc data processing. */
9676 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
9677 if (op < 4 && (insn & 0xf000) != 0xf000)
9678 goto illegal_op;
9679 switch (op) {
9680 case 0: /* Register controlled shift. */
9681 tmp = load_reg(s, rn);
9682 tmp2 = load_reg(s, rm);
9683 if ((insn & 0x70) != 0)
9684 goto illegal_op;
9685 op = (insn >> 21) & 3;
9686 logic_cc = (insn & (1 << 20)) != 0;
9687 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
9688 if (logic_cc)
9689 gen_logic_CC(tmp);
9690 store_reg_bx(s, rd, tmp);
9691 break;
9692 case 1: /* Sign/zero extend. */
9693 op = (insn >> 20) & 7;
9694 switch (op) {
9695 case 0: /* SXTAH, SXTH */
9696 case 1: /* UXTAH, UXTH */
9697 case 4: /* SXTAB, SXTB */
9698 case 5: /* UXTAB, UXTB */
9699 break;
9700 case 2: /* SXTAB16, SXTB16 */
9701 case 3: /* UXTAB16, UXTB16 */
9702 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
9703 goto illegal_op;
9704 }
9705 break;
9706 default:
9707 goto illegal_op;
9708 }
9709 if (rn != 15) {
9710 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
9711 goto illegal_op;
9712 }
9713 }
9714 tmp = load_reg(s, rm);
9715 shift = (insn >> 4) & 3;
9716 /* ??? In many cases it's not necessary to do a
9717 rotate, a shift is sufficient. */
9718 if (shift != 0)
9719 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9720 op = (insn >> 20) & 7;
9721 switch (op) {
9722 case 0: gen_sxth(tmp); break;
9723 case 1: gen_uxth(tmp); break;
9724 case 2: gen_sxtb16(tmp); break;
9725 case 3: gen_uxtb16(tmp); break;
9726 case 4: gen_sxtb(tmp); break;
9727 case 5: gen_uxtb(tmp); break;
9728 default:
9729 g_assert_not_reached();
9730 }
9731 if (rn != 15) {
9732 tmp2 = load_reg(s, rn);
9733 if ((op >> 1) == 1) {
9734 gen_add16(tmp, tmp2);
9735 } else {
9736 tcg_gen_add_i32(tmp, tmp, tmp2);
9737 tcg_temp_free_i32(tmp2);
9738 }
9739 }
9740 store_reg(s, rd, tmp);
9741 break;
9742 case 2: /* SIMD add/subtract. */
9743 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
9744 goto illegal_op;
9745 }
9746 op = (insn >> 20) & 7;
9747 shift = (insn >> 4) & 7;
9748 if ((op & 3) == 3 || (shift & 3) == 3)
9749 goto illegal_op;
9750 tmp = load_reg(s, rn);
9751 tmp2 = load_reg(s, rm);
9752 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
9753 tcg_temp_free_i32(tmp2);
9754 store_reg(s, rd, tmp);
9755 break;
9756 case 3: /* Other data processing. */
9757 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
9758 if (op < 4) {
9759 /* Saturating add/subtract. */
9760 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
9761 goto illegal_op;
9762 }
9763 tmp = load_reg(s, rn);
9764 tmp2 = load_reg(s, rm);
9765 if (op & 1)
9766 gen_helper_double_saturate(tmp, cpu_env, tmp);
9767 if (op & 2)
9768 gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
9769 else
9770 gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
9771 tcg_temp_free_i32(tmp2);
9772 } else {
9773 switch (op) {
9774 case 0x0a: /* rbit */
9775 case 0x08: /* rev */
9776 case 0x09: /* rev16 */
9777 case 0x0b: /* revsh */
9778 case 0x18: /* clz */
9779 break;
9780 case 0x10: /* sel */
9781 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
9782 goto illegal_op;
9783 }
9784 break;
9785 case 0x20: /* crc32/crc32c */
9786 case 0x21:
9787 case 0x22:
9788 case 0x28:
9789 case 0x29:
9790 case 0x2a:
9791 if (!arm_dc_feature(s, ARM_FEATURE_CRC)) {
9792 goto illegal_op;
9793 }
9794 break;
9795 default:
9796 goto illegal_op;
9797 }
9798 tmp = load_reg(s, rn);
9799 switch (op) {
9800 case 0x0a: /* rbit */
9801 gen_helper_rbit(tmp, tmp);
9802 break;
9803 case 0x08: /* rev */
9804 tcg_gen_bswap32_i32(tmp, tmp);
9805 break;
9806 case 0x09: /* rev16 */
9807 gen_rev16(tmp);
9808 break;
9809 case 0x0b: /* revsh */
9810 gen_revsh(tmp);
9811 break;
9812 case 0x10: /* sel */
9813 tmp2 = load_reg(s, rm);
9814 tmp3 = tcg_temp_new_i32();
9815 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
9816 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
9817 tcg_temp_free_i32(tmp3);
9818 tcg_temp_free_i32(tmp2);
9819 break;
9820 case 0x18: /* clz */
9821 gen_helper_clz(tmp, tmp);
9822 break;
9823 case 0x20:
9824 case 0x21:
9825 case 0x22:
9826 case 0x28:
9827 case 0x29:
9828 case 0x2a:
9829 {
9830 /* crc32/crc32c */
9831 uint32_t sz = op & 0x3;
9832 uint32_t c = op & 0x8;
9833
9834 tmp2 = load_reg(s, rm);
9835 if (sz == 0) {
9836 tcg_gen_andi_i32(tmp2, tmp2, 0xff);
9837 } else if (sz == 1) {
9838 tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
9839 }
9840 tmp3 = tcg_const_i32(1 << sz);
9841 if (c) {
9842 gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
9843 } else {
9844 gen_helper_crc32(tmp, tmp, tmp2, tmp3);
9845 }
9846 tcg_temp_free_i32(tmp2);
9847 tcg_temp_free_i32(tmp3);
9848 break;
9849 }
9850 default:
9851 g_assert_not_reached();
9852 }
9853 }
9854 store_reg(s, rd, tmp);
9855 break;
9856 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
9857 switch ((insn >> 20) & 7) {
9858 case 0: /* 32 x 32 -> 32 */
9859 case 7: /* Unsigned sum of absolute differences. */
9860 break;
9861 case 1: /* 16 x 16 -> 32 */
9862 case 2: /* Dual multiply add. */
9863 case 3: /* 32 * 16 -> 32msb */
9864 case 4: /* Dual multiply subtract. */
9865 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
9866 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
9867 goto illegal_op;
9868 }
9869 break;
9870 }
9871 op = (insn >> 4) & 0xf;
9872 tmp = load_reg(s, rn);
9873 tmp2 = load_reg(s, rm);
9874 switch ((insn >> 20) & 7) {
9875 case 0: /* 32 x 32 -> 32 */
9876 tcg_gen_mul_i32(tmp, tmp, tmp2);
9877 tcg_temp_free_i32(tmp2);
9878 if (rs != 15) {
9879 tmp2 = load_reg(s, rs);
9880 if (op)
9881 tcg_gen_sub_i32(tmp, tmp2, tmp);
9882 else
9883 tcg_gen_add_i32(tmp, tmp, tmp2);
9884 tcg_temp_free_i32(tmp2);
9885 }
9886 break;
9887 case 1: /* 16 x 16 -> 32 */
9888 gen_mulxy(tmp, tmp2, op & 2, op & 1);
9889 tcg_temp_free_i32(tmp2);
9890 if (rs != 15) {
9891 tmp2 = load_reg(s, rs);
9892 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
9893 tcg_temp_free_i32(tmp2);
9894 }
9895 break;
9896 case 2: /* Dual multiply add. */
9897 case 4: /* Dual multiply subtract. */
9898 if (op)
9899 gen_swap_half(tmp2);
9900 gen_smul_dual(tmp, tmp2);
9901 if (insn & (1 << 22)) {
9902 /* This subtraction cannot overflow. */
9903 tcg_gen_sub_i32(tmp, tmp, tmp2);
9904 } else {
9905 /* This addition cannot overflow 32 bits;
9906 * however it may overflow considered as a signed
9907 * operation, in which case we must set the Q flag.
9908 */
9909 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
9910 }
9911 tcg_temp_free_i32(tmp2);
9912 if (rs != 15)
9913 {
9914 tmp2 = load_reg(s, rs);
9915 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
9916 tcg_temp_free_i32(tmp2);
9917 }
9918 break;
9919 case 3: /* 32 * 16 -> 32msb */
9920 if (op)
9921 tcg_gen_sari_i32(tmp2, tmp2, 16);
9922 else
9923 gen_sxth(tmp2);
9924 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9925 tcg_gen_shri_i64(tmp64, tmp64, 16);
9926 tmp = tcg_temp_new_i32();
9927 tcg_gen_extrl_i64_i32(tmp, tmp64);
9928 tcg_temp_free_i64(tmp64);
9929 if (rs != 15)
9930 {
9931 tmp2 = load_reg(s, rs);
9932 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
9933 tcg_temp_free_i32(tmp2);
9934 }
9935 break;
9936 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
9937 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9938 if (rs != 15) {
9939 tmp = load_reg(s, rs);
9940 if (insn & (1 << 20)) {
9941 tmp64 = gen_addq_msw(tmp64, tmp);
9942 } else {
9943 tmp64 = gen_subq_msw(tmp64, tmp);
9944 }
9945 }
9946 if (insn & (1 << 4)) {
9947 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
9948 }
9949 tcg_gen_shri_i64(tmp64, tmp64, 32);
9950 tmp = tcg_temp_new_i32();
9951 tcg_gen_extrl_i64_i32(tmp, tmp64);
9952 tcg_temp_free_i64(tmp64);
9953 break;
9954 case 7: /* Unsigned sum of absolute differences. */
9955 gen_helper_usad8(tmp, tmp, tmp2);
9956 tcg_temp_free_i32(tmp2);
9957 if (rs != 15) {
9958 tmp2 = load_reg(s, rs);
9959 tcg_gen_add_i32(tmp, tmp, tmp2);
9960 tcg_temp_free_i32(tmp2);
9961 }
9962 break;
9963 }
9964 store_reg(s, rd, tmp);
9965 break;
9966 case 6: case 7: /* 64-bit multiply, Divide. */
9967 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
9968 tmp = load_reg(s, rn);
9969 tmp2 = load_reg(s, rm);
9970 if ((op & 0x50) == 0x10) {
9971 /* sdiv, udiv */
9972 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DIV)) {
9973 goto illegal_op;
9974 }
9975 if (op & 0x20)
9976 gen_helper_udiv(tmp, tmp, tmp2);
9977 else
9978 gen_helper_sdiv(tmp, tmp, tmp2);
9979 tcg_temp_free_i32(tmp2);
9980 store_reg(s, rd, tmp);
9981 } else if ((op & 0xe) == 0xc) {
9982 /* Dual multiply accumulate long. */
9983 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
9984 tcg_temp_free_i32(tmp);
9985 tcg_temp_free_i32(tmp2);
9986 goto illegal_op;
9987 }
9988 if (op & 1)
9989 gen_swap_half(tmp2);
9990 gen_smul_dual(tmp, tmp2);
9991 if (op & 0x10) {
9992 tcg_gen_sub_i32(tmp, tmp, tmp2);
9993 } else {
9994 tcg_gen_add_i32(tmp, tmp, tmp2);
9995 }
9996 tcg_temp_free_i32(tmp2);
9997 /* BUGFIX */
9998 tmp64 = tcg_temp_new_i64();
9999 tcg_gen_ext_i32_i64(tmp64, tmp);
10000 tcg_temp_free_i32(tmp);
10001 gen_addq(s, tmp64, rs, rd);
10002 gen_storeq_reg(s, rs, rd, tmp64);
10003 tcg_temp_free_i64(tmp64);
10004 } else {
10005 if (op & 0x20) {
10006 /* Unsigned 64-bit multiply */
10007 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
10008 } else {
10009 if (op & 8) {
10010 /* smlalxy */
10011 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
10012 tcg_temp_free_i32(tmp2);
10013 tcg_temp_free_i32(tmp);
10014 goto illegal_op;
10015 }
10016 gen_mulxy(tmp, tmp2, op & 2, op & 1);
10017 tcg_temp_free_i32(tmp2);
10018 tmp64 = tcg_temp_new_i64();
10019 tcg_gen_ext_i32_i64(tmp64, tmp);
10020 tcg_temp_free_i32(tmp);
10021 } else {
10022 /* Signed 64-bit multiply */
10023 tmp64 = gen_muls_i64_i32(tmp, tmp2);
10024 }
10025 }
10026 if (op & 4) {
10027 /* umaal */
10028 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
10029 tcg_temp_free_i64(tmp64);
10030 goto illegal_op;
10031 }
10032 gen_addq_lo(s, tmp64, rs);
10033 gen_addq_lo(s, tmp64, rd);
10034 } else if (op & 0x40) {
10035 /* 64-bit accumulate. */
10036 gen_addq(s, tmp64, rs, rd);
10037 }
10038 gen_storeq_reg(s, rs, rd, tmp64);
10039 tcg_temp_free_i64(tmp64);
10040 }
10041 break;
10042 }
10043 break;
10044 case 6: case 7: case 14: case 15:
10045 /* Coprocessor. */
10046 if (((insn >> 24) & 3) == 3) {
10047 /* Translate into the equivalent ARM encoding. */
10048 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
10049 if (disas_neon_data_insn(s, insn)) {
10050 goto illegal_op;
10051 }
10052 } else if (((insn >> 8) & 0xe) == 10) {
10053 if (disas_vfp_insn(s, insn)) {
10054 goto illegal_op;
10055 }
10056 } else {
10057 if (insn & (1 << 28))
10058 goto illegal_op;
10059 if (disas_coproc_insn(s, insn)) {
10060 goto illegal_op;
10061 }
10062 }
10063 break;
10064 case 8: case 9: case 10: case 11:
10065 if (insn & (1 << 15)) {
10066 /* Branches, misc control. */
10067 if (insn & 0x5000) {
10068 /* Unconditional branch. */
10069 /* signextend(hw1[10:0]) -> offset[:12]. */
10070 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
10071 /* hw1[10:0] -> offset[11:1]. */
10072 offset |= (insn & 0x7ff) << 1;
10073 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
10074 offset[24:22] already have the same value because of the
10075 sign extension above. */
10076 offset ^= ((~insn) & (1 << 13)) << 10;
10077 offset ^= ((~insn) & (1 << 11)) << 11;
10078
10079 if (insn & (1 << 14)) {
10080 /* Branch and link. */
10081 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
10082 }
10083
10084 offset += s->pc;
10085 if (insn & (1 << 12)) {
10086 /* b/bl */
10087 gen_jmp(s, offset);
10088 } else {
10089 /* blx */
10090 offset &= ~(uint32_t)2;
10091 /* thumb2 bx, no need to check */
10092 gen_bx_im(s, offset);
10093 }
10094 } else if (((insn >> 23) & 7) == 7) {
10095 /* Misc control */
10096 if (insn & (1 << 13))
10097 goto illegal_op;
10098
10099 if (insn & (1 << 26)) {
10100 if (!(insn & (1 << 20))) {
10101 /* Hypervisor call (v7) */
10102 int imm16 = extract32(insn, 16, 4) << 12
10103 | extract32(insn, 0, 12);
10104 ARCH(7);
10105 if (IS_USER(s)) {
10106 goto illegal_op;
10107 }
10108 gen_hvc(s, imm16);
10109 } else {
10110 /* Secure monitor call (v6+) */
10111 ARCH(6K);
10112 if (IS_USER(s)) {
10113 goto illegal_op;
10114 }
10115 gen_smc(s);
10116 }
10117 } else {
10118 op = (insn >> 20) & 7;
10119 switch (op) {
10120 case 0: /* msr cpsr. */
10121 if (arm_dc_feature(s, ARM_FEATURE_M)) {
10122 tmp = load_reg(s, rn);
10123 addr = tcg_const_i32(insn & 0xff);
10124 gen_helper_v7m_msr(cpu_env, addr, tmp);
10125 tcg_temp_free_i32(addr);
10126 tcg_temp_free_i32(tmp);
10127 gen_lookup_tb(s);
10128 break;
10129 }
10130 /* fall through */
10131 case 1: /* msr spsr. */
10132 if (arm_dc_feature(s, ARM_FEATURE_M)) {
10133 goto illegal_op;
10134 }
10135 tmp = load_reg(s, rn);
10136 if (gen_set_psr(s,
10137 msr_mask(s, (insn >> 8) & 0xf, op == 1),
10138 op == 1, tmp))
10139 goto illegal_op;
10140 break;
10141 case 2: /* cps, nop-hint. */
10142 if (((insn >> 8) & 7) == 0) {
10143 gen_nop_hint(s, insn & 0xff);
10144 }
10145 /* Implemented as NOP in user mode. */
10146 if (IS_USER(s))
10147 break;
10148 offset = 0;
10149 imm = 0;
10150 if (insn & (1 << 10)) {
10151 if (insn & (1 << 7))
10152 offset |= CPSR_A;
10153 if (insn & (1 << 6))
10154 offset |= CPSR_I;
10155 if (insn & (1 << 5))
10156 offset |= CPSR_F;
10157 if (insn & (1 << 9))
10158 imm = CPSR_A | CPSR_I | CPSR_F;
10159 }
10160 if (insn & (1 << 8)) {
10161 offset |= 0x1f;
10162 imm |= (insn & 0x1f);
10163 }
10164 if (offset) {
10165 gen_set_psr_im(s, offset, 0, imm);
10166 }
10167 break;
10168 case 3: /* Special control operations. */
10169 ARCH(7);
10170 op = (insn >> 4) & 0xf;
10171 switch (op) {
10172 case 2: /* clrex */
10173 gen_clrex(s);
10174 break;
10175 case 4: /* dsb */
10176 case 5: /* dmb */
10177 /* These execute as NOPs. */
10178 break;
10179 case 6: /* isb */
10180 /* We need to break the TB after this insn
10181 * to execute self-modifying code correctly
10182 * and also to take any pending interrupts
10183 * immediately.
10184 */
10185 gen_lookup_tb(s);
10186 break;
10187 default:
10188 goto illegal_op;
10189 }
10190 break;
10191 case 4: /* bxj */
10192 /* Trivial implementation equivalent to bx. */
10193 tmp = load_reg(s, rn);
10194 gen_bx(s, tmp);
10195 break;
10196 case 5: /* Exception return. */
10197 if (IS_USER(s)) {
10198 goto illegal_op;
10199 }
10200 if (rn != 14 || rd != 15) {
10201 goto illegal_op;
10202 }
10203 tmp = load_reg(s, rn);
10204 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
10205 gen_exception_return(s, tmp);
10206 break;
10207 case 6: /* mrs cpsr. */
10208 tmp = tcg_temp_new_i32();
10209 if (arm_dc_feature(s, ARM_FEATURE_M)) {
10210 addr = tcg_const_i32(insn & 0xff);
10211 gen_helper_v7m_mrs(tmp, cpu_env, addr);
10212 tcg_temp_free_i32(addr);
10213 } else {
10214 gen_helper_cpsr_read(tmp, cpu_env);
10215 }
10216 store_reg(s, rd, tmp);
10217 break;
10218 case 7: /* mrs spsr. */
10219 /* Not accessible in user mode. */
10220 if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
10221 goto illegal_op;
10222 }
10223 tmp = load_cpu_field(spsr);
10224 store_reg(s, rd, tmp);
10225 break;
10226 }
10227 }
10228 } else {
10229 /* Conditional branch. */
10230 op = (insn >> 22) & 0xf;
10231 /* Generate a conditional jump to next instruction. */
10232 s->condlabel = gen_new_label();
10233 arm_gen_test_cc(op ^ 1, s->condlabel);
10234 s->condjmp = 1;
10235
10236 /* offset[11:1] = insn[10:0] */
10237 offset = (insn & 0x7ff) << 1;
10238 /* offset[17:12] = insn[21:16]. */
10239 offset |= (insn & 0x003f0000) >> 4;
10240 /* offset[31:20] = insn[26]. */
10241 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
10242 /* offset[18] = insn[13]. */
10243 offset |= (insn & (1 << 13)) << 5;
10244 /* offset[19] = insn[11]. */
10245 offset |= (insn & (1 << 11)) << 8;
10246
10247 /* jump to the offset */
10248 gen_jmp(s, s->pc + offset);
10249 }
10250 } else {
10251 /* Data processing immediate. */
10252 if (insn & (1 << 25)) {
10253 if (insn & (1 << 24)) {
10254 if (insn & (1 << 20))
10255 goto illegal_op;
10256 /* Bitfield/Saturate. */
10257 op = (insn >> 21) & 7;
10258 imm = insn & 0x1f;
10259 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
10260 if (rn == 15) {
10261 tmp = tcg_temp_new_i32();
10262 tcg_gen_movi_i32(tmp, 0);
10263 } else {
10264 tmp = load_reg(s, rn);
10265 }
10266 switch (op) {
10267 case 2: /* Signed bitfield extract. */
10268 imm++;
10269 if (shift + imm > 32)
10270 goto illegal_op;
10271 if (imm < 32)
10272 gen_sbfx(tmp, shift, imm);
10273 break;
10274 case 6: /* Unsigned bitfield extract. */
10275 imm++;
10276 if (shift + imm > 32)
10277 goto illegal_op;
10278 if (imm < 32)
10279 gen_ubfx(tmp, shift, (1u << imm) - 1);
10280 break;
10281 case 3: /* Bitfield insert/clear. */
10282 if (imm < shift)
10283 goto illegal_op;
10284 imm = imm + 1 - shift;
10285 if (imm != 32) {
10286 tmp2 = load_reg(s, rd);
10287 tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, imm);
10288 tcg_temp_free_i32(tmp2);
10289 }
10290 break;
10291 case 7:
10292 goto illegal_op;
10293 default: /* Saturate. */
10294 if (shift) {
10295 if (op & 1)
10296 tcg_gen_sari_i32(tmp, tmp, shift);
10297 else
10298 tcg_gen_shli_i32(tmp, tmp, shift);
10299 }
10300 tmp2 = tcg_const_i32(imm);
10301 if (op & 4) {
10302 /* Unsigned. */
10303 if ((op & 1) && shift == 0) {
10304 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
10305 tcg_temp_free_i32(tmp);
10306 tcg_temp_free_i32(tmp2);
10307 goto illegal_op;
10308 }
10309 gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
10310 } else {
10311 gen_helper_usat(tmp, cpu_env, tmp, tmp2);
10312 }
10313 } else {
10314 /* Signed. */
10315 if ((op & 1) && shift == 0) {
10316 if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
10317 tcg_temp_free_i32(tmp);
10318 tcg_temp_free_i32(tmp2);
10319 goto illegal_op;
10320 }
10321 gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
10322 } else {
10323 gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
10324 }
10325 }
10326 tcg_temp_free_i32(tmp2);
10327 break;
10328 }
10329 store_reg(s, rd, tmp);
10330 } else {
10331 imm = ((insn & 0x04000000) >> 15)
10332 | ((insn & 0x7000) >> 4) | (insn & 0xff);
10333 if (insn & (1 << 22)) {
10334 /* 16-bit immediate. */
10335 imm |= (insn >> 4) & 0xf000;
10336 if (insn & (1 << 23)) {
10337 /* movt */
10338 tmp = load_reg(s, rd);
10339 tcg_gen_ext16u_i32(tmp, tmp);
10340 tcg_gen_ori_i32(tmp, tmp, imm << 16);
10341 } else {
10342 /* movw */
10343 tmp = tcg_temp_new_i32();
10344 tcg_gen_movi_i32(tmp, imm);
10345 }
10346 } else {
10347 /* Add/sub 12-bit immediate. */
10348 if (rn == 15) {
10349 offset = s->pc & ~(uint32_t)3;
10350 if (insn & (1 << 23))
10351 offset -= imm;
10352 else
10353 offset += imm;
10354 tmp = tcg_temp_new_i32();
10355 tcg_gen_movi_i32(tmp, offset);
10356 } else {
10357 tmp = load_reg(s, rn);
10358 if (insn & (1 << 23))
10359 tcg_gen_subi_i32(tmp, tmp, imm);
10360 else
10361 tcg_gen_addi_i32(tmp, tmp, imm);
10362 }
10363 }
10364 store_reg(s, rd, tmp);
10365 }
10366 } else {
10367 int shifter_out = 0;
10368 /* modified 12-bit immediate. */
10369 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
10370 imm = (insn & 0xff);
10371 switch (shift) {
10372 case 0: /* XY */
10373 /* Nothing to do. */
10374 break;
10375 case 1: /* 00XY00XY */
10376 imm |= imm << 16;
10377 break;
10378 case 2: /* XY00XY00 */
10379 imm |= imm << 16;
10380 imm <<= 8;
10381 break;
10382 case 3: /* XYXYXYXY */
10383 imm |= imm << 16;
10384 imm |= imm << 8;
10385 break;
10386 default: /* Rotated constant. */
10387 shift = (shift << 1) | (imm >> 7);
10388 imm |= 0x80;
10389 imm = imm << (32 - shift);
10390 shifter_out = 1;
10391 break;
10392 }
10393 tmp2 = tcg_temp_new_i32();
10394 tcg_gen_movi_i32(tmp2, imm);
10395 rn = (insn >> 16) & 0xf;
10396 if (rn == 15) {
10397 tmp = tcg_temp_new_i32();
10398 tcg_gen_movi_i32(tmp, 0);
10399 } else {
10400 tmp = load_reg(s, rn);
10401 }
10402 op = (insn >> 21) & 0xf;
10403 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
10404 shifter_out, tmp, tmp2))
10405 goto illegal_op;
10406 tcg_temp_free_i32(tmp2);
10407 rd = (insn >> 8) & 0xf;
10408 if (rd != 15) {
10409 store_reg(s, rd, tmp);
10410 } else {
10411 tcg_temp_free_i32(tmp);
10412 }
10413 }
10414 }
10415 break;
10416 case 12: /* Load/store single data item. */
10417 {
10418 int postinc = 0;
10419 int writeback = 0;
10420 int memidx;
10421 if ((insn & 0x01100000) == 0x01000000) {
10422 if (disas_neon_ls_insn(s, insn)) {
10423 goto illegal_op;
10424 }
10425 break;
10426 }
10427 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
10428 if (rs == 15) {
10429 if (!(insn & (1 << 20))) {
10430 goto illegal_op;
10431 }
10432 if (op != 2) {
10433 /* Byte or halfword load space with dest == r15 : memory hints.
10434 * Catch them early so we don't emit pointless addressing code.
10435 * This space is a mix of:
10436 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
10437 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
10438 * cores)
10439 * unallocated hints, which must be treated as NOPs
10440 * UNPREDICTABLE space, which we NOP or UNDEF depending on
10441 * which is easiest for the decoding logic
10442 * Some space which must UNDEF
10443 */
10444 int op1 = (insn >> 23) & 3;
10445 int op2 = (insn >> 6) & 0x3f;
10446 if (op & 2) {
10447 goto illegal_op;
10448 }
10449 if (rn == 15) {
10450 /* UNPREDICTABLE, unallocated hint or
10451 * PLD/PLDW/PLI (literal)
10452 */
10453 return 0;
10454 }
10455 if (op1 & 1) {
10456 return 0; /* PLD/PLDW/PLI or unallocated hint */
10457 }
10458 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
10459 return 0; /* PLD/PLDW/PLI or unallocated hint */
10460 }
10461 /* UNDEF space, or an UNPREDICTABLE */
10462 return 1;
10463 }
10464 }
10465 memidx = get_mem_index(s);
10466 if (rn == 15) {
10467 addr = tcg_temp_new_i32();
10468 /* PC relative. */
10469 /* s->pc has already been incremented by 4. */
10470 imm = s->pc & 0xfffffffc;
10471 if (insn & (1 << 23))
10472 imm += insn & 0xfff;
10473 else
10474 imm -= insn & 0xfff;
10475 tcg_gen_movi_i32(addr, imm);
10476 } else {
10477 addr = load_reg(s, rn);
10478 if (insn & (1 << 23)) {
10479 /* Positive offset. */
10480 imm = insn & 0xfff;
10481 tcg_gen_addi_i32(addr, addr, imm);
10482 } else {
10483 imm = insn & 0xff;
10484 switch ((insn >> 8) & 0xf) {
10485 case 0x0: /* Shifted Register. */
10486 shift = (insn >> 4) & 0xf;
10487 if (shift > 3) {
10488 tcg_temp_free_i32(addr);
10489 goto illegal_op;
10490 }
10491 tmp = load_reg(s, rm);
10492 if (shift)
10493 tcg_gen_shli_i32(tmp, tmp, shift);
10494 tcg_gen_add_i32(addr, addr, tmp);
10495 tcg_temp_free_i32(tmp);
10496 break;
10497 case 0xc: /* Negative offset. */
10498 tcg_gen_addi_i32(addr, addr, -imm);
10499 break;
10500 case 0xe: /* User privilege. */
10501 tcg_gen_addi_i32(addr, addr, imm);
10502 memidx = get_a32_user_mem_index(s);
10503 break;
10504 case 0x9: /* Post-decrement. */
10505 imm = -imm;
10506 /* Fall through. */
10507 case 0xb: /* Post-increment. */
10508 postinc = 1;
10509 writeback = 1;
10510 break;
10511 case 0xd: /* Pre-decrement. */
10512 imm = -imm;
10513 /* Fall through. */
10514 case 0xf: /* Pre-increment. */
10515 tcg_gen_addi_i32(addr, addr, imm);
10516 writeback = 1;
10517 break;
10518 default:
10519 tcg_temp_free_i32(addr);
10520 goto illegal_op;
10521 }
10522 }
10523 }
10524 if (insn & (1 << 20)) {
10525 /* Load. */
10526 tmp = tcg_temp_new_i32();
10527 switch (op) {
10528 case 0:
10529 gen_aa32_ld8u(s, tmp, addr, memidx);
10530 break;
10531 case 4:
10532 gen_aa32_ld8s(s, tmp, addr, memidx);
10533 break;
10534 case 1:
10535 gen_aa32_ld16u(s, tmp, addr, memidx);
10536 break;
10537 case 5:
10538 gen_aa32_ld16s(s, tmp, addr, memidx);
10539 break;
10540 case 2:
10541 gen_aa32_ld32u(s, tmp, addr, memidx);
10542 break;
10543 default:
10544 tcg_temp_free_i32(tmp);
10545 tcg_temp_free_i32(addr);
10546 goto illegal_op;
10547 }
10548 if (rs == 15) {
10549 gen_bx(s, tmp);
10550 } else {
10551 store_reg(s, rs, tmp);
10552 }
10553 } else {
10554 /* Store. */
10555 tmp = load_reg(s, rs);
10556 switch (op) {
10557 case 0:
10558 gen_aa32_st8(s, tmp, addr, memidx);
10559 break;
10560 case 1:
10561 gen_aa32_st16(s, tmp, addr, memidx);
10562 break;
10563 case 2:
10564 gen_aa32_st32(s, tmp, addr, memidx);
10565 break;
10566 default:
10567 tcg_temp_free_i32(tmp);
10568 tcg_temp_free_i32(addr);
10569 goto illegal_op;
10570 }
10571 tcg_temp_free_i32(tmp);
10572 }
10573 if (postinc)
10574 tcg_gen_addi_i32(addr, addr, imm);
10575 if (writeback) {
10576 store_reg(s, rn, addr);
10577 } else {
10578 tcg_temp_free_i32(addr);
10579 }
10580 }
10581 break;
10582 default:
10583 goto illegal_op;
10584 }
10585 return 0;
10586 illegal_op:
10587 return 1;
10588 }
10589
10590 static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
10591 {
10592 uint32_t val, insn, op, rm, rn, rd, shift, cond;
10593 int32_t offset;
10594 int i;
10595 TCGv_i32 tmp;
10596 TCGv_i32 tmp2;
10597 TCGv_i32 addr;
10598
10599 if (s->condexec_mask) {
10600 cond = s->condexec_cond;
10601 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
10602 s->condlabel = gen_new_label();
10603 arm_gen_test_cc(cond ^ 1, s->condlabel);
10604 s->condjmp = 1;
10605 }
10606 }
10607
10608 insn = arm_lduw_code(env, s->pc, s->sctlr_b);
10609 s->pc += 2;
10610
10611 switch (insn >> 12) {
10612 case 0: case 1:
10613
10614 rd = insn & 7;
10615 op = (insn >> 11) & 3;
10616 if (op == 3) {
10617 /* add/subtract */
10618 rn = (insn >> 3) & 7;
10619 tmp = load_reg(s, rn);
10620 if (insn & (1 << 10)) {
10621 /* immediate */
10622 tmp2 = tcg_temp_new_i32();
10623 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
10624 } else {
10625 /* reg */
10626 rm = (insn >> 6) & 7;
10627 tmp2 = load_reg(s, rm);
10628 }
10629 if (insn & (1 << 9)) {
10630 if (s->condexec_mask)
10631 tcg_gen_sub_i32(tmp, tmp, tmp2);
10632 else
10633 gen_sub_CC(tmp, tmp, tmp2);
10634 } else {
10635 if (s->condexec_mask)
10636 tcg_gen_add_i32(tmp, tmp, tmp2);
10637 else
10638 gen_add_CC(tmp, tmp, tmp2);
10639 }
10640 tcg_temp_free_i32(tmp2);
10641 store_reg(s, rd, tmp);
10642 } else {
10643 /* shift immediate */
10644 rm = (insn >> 3) & 7;
10645 shift = (insn >> 6) & 0x1f;
10646 tmp = load_reg(s, rm);
10647 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
10648 if (!s->condexec_mask)
10649 gen_logic_CC(tmp);
10650 store_reg(s, rd, tmp);
10651 }
10652 break;
10653 case 2: case 3:
10654 /* arithmetic large immediate */
10655 op = (insn >> 11) & 3;
10656 rd = (insn >> 8) & 0x7;
10657 if (op == 0) { /* mov */
10658 tmp = tcg_temp_new_i32();
10659 tcg_gen_movi_i32(tmp, insn & 0xff);
10660 if (!s->condexec_mask)
10661 gen_logic_CC(tmp);
10662 store_reg(s, rd, tmp);
10663 } else {
10664 tmp = load_reg(s, rd);
10665 tmp2 = tcg_temp_new_i32();
10666 tcg_gen_movi_i32(tmp2, insn & 0xff);
10667 switch (op) {
10668 case 1: /* cmp */
10669 gen_sub_CC(tmp, tmp, tmp2);
10670 tcg_temp_free_i32(tmp);
10671 tcg_temp_free_i32(tmp2);
10672 break;
10673 case 2: /* add */
10674 if (s->condexec_mask)
10675 tcg_gen_add_i32(tmp, tmp, tmp2);
10676 else
10677 gen_add_CC(tmp, tmp, tmp2);
10678 tcg_temp_free_i32(tmp2);
10679 store_reg(s, rd, tmp);
10680 break;
10681 case 3: /* sub */
10682 if (s->condexec_mask)
10683 tcg_gen_sub_i32(tmp, tmp, tmp2);
10684 else
10685 gen_sub_CC(tmp, tmp, tmp2);
10686 tcg_temp_free_i32(tmp2);
10687 store_reg(s, rd, tmp);
10688 break;
10689 }
10690 }
10691 break;
10692 case 4:
10693 if (insn & (1 << 11)) {
10694 rd = (insn >> 8) & 7;
10695 /* load pc-relative. Bit 1 of PC is ignored. */
10696 val = s->pc + 2 + ((insn & 0xff) * 4);
10697 val &= ~(uint32_t)2;
10698 addr = tcg_temp_new_i32();
10699 tcg_gen_movi_i32(addr, val);
10700 tmp = tcg_temp_new_i32();
10701 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
10702 tcg_temp_free_i32(addr);
10703 store_reg(s, rd, tmp);
10704 break;
10705 }
10706 if (insn & (1 << 10)) {
10707 /* data processing extended or blx */
10708 rd = (insn & 7) | ((insn >> 4) & 8);
10709 rm = (insn >> 3) & 0xf;
10710 op = (insn >> 8) & 3;
10711 switch (op) {
10712 case 0: /* add */
10713 tmp = load_reg(s, rd);
10714 tmp2 = load_reg(s, rm);
10715 tcg_gen_add_i32(tmp, tmp, tmp2);
10716 tcg_temp_free_i32(tmp2);
10717 store_reg(s, rd, tmp);
10718 break;
10719 case 1: /* cmp */
10720 tmp = load_reg(s, rd);
10721 tmp2 = load_reg(s, rm);
10722 gen_sub_CC(tmp, tmp, tmp2);
10723 tcg_temp_free_i32(tmp2);
10724 tcg_temp_free_i32(tmp);
10725 break;
10726 case 2: /* mov/cpy */
10727 tmp = load_reg(s, rm);
10728 store_reg(s, rd, tmp);
10729 break;
10730 case 3:/* branch [and link] exchange thumb register */
10731 tmp = load_reg(s, rm);
10732 if (insn & (1 << 7)) {
10733 ARCH(5);
10734 val = (uint32_t)s->pc | 1;
10735 tmp2 = tcg_temp_new_i32();
10736 tcg_gen_movi_i32(tmp2, val);
10737 store_reg(s, 14, tmp2);
10738 }
10739 /* already thumb, no need to check */
10740 gen_bx(s, tmp);
10741 break;
10742 }
10743 break;
10744 }
10745
10746 /* data processing register */
10747 rd = insn & 7;
10748 rm = (insn >> 3) & 7;
10749 op = (insn >> 6) & 0xf;
10750 if (op == 2 || op == 3 || op == 4 || op == 7) {
10751 /* the shift/rotate ops want the operands backwards */
10752 val = rm;
10753 rm = rd;
10754 rd = val;
10755 val = 1;
10756 } else {
10757 val = 0;
10758 }
10759
10760 if (op == 9) { /* neg */
10761 tmp = tcg_temp_new_i32();
10762 tcg_gen_movi_i32(tmp, 0);
10763 } else if (op != 0xf) { /* mvn doesn't read its first operand */
10764 tmp = load_reg(s, rd);
10765 } else {
10766 TCGV_UNUSED_I32(tmp);
10767 }
10768
10769 tmp2 = load_reg(s, rm);
10770 switch (op) {
10771 case 0x0: /* and */
10772 tcg_gen_and_i32(tmp, tmp, tmp2);
10773 if (!s->condexec_mask)
10774 gen_logic_CC(tmp);
10775 break;
10776 case 0x1: /* eor */
10777 tcg_gen_xor_i32(tmp, tmp, tmp2);
10778 if (!s->condexec_mask)
10779 gen_logic_CC(tmp);
10780 break;
10781 case 0x2: /* lsl */
10782 if (s->condexec_mask) {
10783 gen_shl(tmp2, tmp2, tmp);
10784 } else {
10785 gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
10786 gen_logic_CC(tmp2);
10787 }
10788 break;
10789 case 0x3: /* lsr */
10790 if (s->condexec_mask) {
10791 gen_shr(tmp2, tmp2, tmp);
10792 } else {
10793 gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
10794 gen_logic_CC(tmp2);
10795 }
10796 break;
10797 case 0x4: /* asr */
10798 if (s->condexec_mask) {
10799 gen_sar(tmp2, tmp2, tmp);
10800 } else {
10801 gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
10802 gen_logic_CC(tmp2);
10803 }
10804 break;
10805 case 0x5: /* adc */
10806 if (s->condexec_mask) {
10807 gen_adc(tmp, tmp2);
10808 } else {
10809 gen_adc_CC(tmp, tmp, tmp2);
10810 }
10811 break;
10812 case 0x6: /* sbc */
10813 if (s->condexec_mask) {
10814 gen_sub_carry(tmp, tmp, tmp2);
10815 } else {
10816 gen_sbc_CC(tmp, tmp, tmp2);
10817 }
10818 break;
10819 case 0x7: /* ror */
10820 if (s->condexec_mask) {
10821 tcg_gen_andi_i32(tmp, tmp, 0x1f);
10822 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
10823 } else {
10824 gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
10825 gen_logic_CC(tmp2);
10826 }
10827 break;
10828 case 0x8: /* tst */
10829 tcg_gen_and_i32(tmp, tmp, tmp2);
10830 gen_logic_CC(tmp);
10831 rd = 16;
10832 break;
10833 case 0x9: /* neg */
10834 if (s->condexec_mask)
10835 tcg_gen_neg_i32(tmp, tmp2);
10836 else
10837 gen_sub_CC(tmp, tmp, tmp2);
10838 break;
10839 case 0xa: /* cmp */
10840 gen_sub_CC(tmp, tmp, tmp2);
10841 rd = 16;
10842 break;
10843 case 0xb: /* cmn */
10844 gen_add_CC(tmp, tmp, tmp2);
10845 rd = 16;
10846 break;
10847 case 0xc: /* orr */
10848 tcg_gen_or_i32(tmp, tmp, tmp2);
10849 if (!s->condexec_mask)
10850 gen_logic_CC(tmp);
10851 break;
10852 case 0xd: /* mul */
10853 tcg_gen_mul_i32(tmp, tmp, tmp2);
10854 if (!s->condexec_mask)
10855 gen_logic_CC(tmp);
10856 break;
10857 case 0xe: /* bic */
10858 tcg_gen_andc_i32(tmp, tmp, tmp2);
10859 if (!s->condexec_mask)
10860 gen_logic_CC(tmp);
10861 break;
10862 case 0xf: /* mvn */
10863 tcg_gen_not_i32(tmp2, tmp2);
10864 if (!s->condexec_mask)
10865 gen_logic_CC(tmp2);
10866 val = 1;
10867 rm = rd;
10868 break;
10869 }
10870 if (rd != 16) {
10871 if (val) {
10872 store_reg(s, rm, tmp2);
10873 if (op != 0xf)
10874 tcg_temp_free_i32(tmp);
10875 } else {
10876 store_reg(s, rd, tmp);
10877 tcg_temp_free_i32(tmp2);
10878 }
10879 } else {
10880 tcg_temp_free_i32(tmp);
10881 tcg_temp_free_i32(tmp2);
10882 }
10883 break;
10884
10885 case 5:
10886 /* load/store register offset. */
10887 rd = insn & 7;
10888 rn = (insn >> 3) & 7;
10889 rm = (insn >> 6) & 7;
10890 op = (insn >> 9) & 7;
10891 addr = load_reg(s, rn);
10892 tmp = load_reg(s, rm);
10893 tcg_gen_add_i32(addr, addr, tmp);
10894 tcg_temp_free_i32(tmp);
10895
10896 if (op < 3) { /* store */
10897 tmp = load_reg(s, rd);
10898 } else {
10899 tmp = tcg_temp_new_i32();
10900 }
10901
10902 switch (op) {
10903 case 0: /* str */
10904 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
10905 break;
10906 case 1: /* strh */
10907 gen_aa32_st16(s, tmp, addr, get_mem_index(s));
10908 break;
10909 case 2: /* strb */
10910 gen_aa32_st8(s, tmp, addr, get_mem_index(s));
10911 break;
10912 case 3: /* ldrsb */
10913 gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
10914 break;
10915 case 4: /* ldr */
10916 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
10917 break;
10918 case 5: /* ldrh */
10919 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
10920 break;
10921 case 6: /* ldrb */
10922 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
10923 break;
10924 case 7: /* ldrsh */
10925 gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
10926 break;
10927 }
10928 if (op >= 3) { /* load */
10929 store_reg(s, rd, tmp);
10930 } else {
10931 tcg_temp_free_i32(tmp);
10932 }
10933 tcg_temp_free_i32(addr);
10934 break;
10935
10936 case 6:
10937 /* load/store word immediate offset */
10938 rd = insn & 7;
10939 rn = (insn >> 3) & 7;
10940 addr = load_reg(s, rn);
10941 val = (insn >> 4) & 0x7c;
10942 tcg_gen_addi_i32(addr, addr, val);
10943
10944 if (insn & (1 << 11)) {
10945 /* load */
10946 tmp = tcg_temp_new_i32();
10947 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
10948 store_reg(s, rd, tmp);
10949 } else {
10950 /* store */
10951 tmp = load_reg(s, rd);
10952 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
10953 tcg_temp_free_i32(tmp);
10954 }
10955 tcg_temp_free_i32(addr);
10956 break;
10957
10958 case 7:
10959 /* load/store byte immediate offset */
10960 rd = insn & 7;
10961 rn = (insn >> 3) & 7;
10962 addr = load_reg(s, rn);
10963 val = (insn >> 6) & 0x1f;
10964 tcg_gen_addi_i32(addr, addr, val);
10965
10966 if (insn & (1 << 11)) {
10967 /* load */
10968 tmp = tcg_temp_new_i32();
10969 gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
10970 store_reg(s, rd, tmp);
10971 } else {
10972 /* store */
10973 tmp = load_reg(s, rd);
10974 gen_aa32_st8(s, tmp, addr, get_mem_index(s));
10975 tcg_temp_free_i32(tmp);
10976 }
10977 tcg_temp_free_i32(addr);
10978 break;
10979
10980 case 8:
10981 /* load/store halfword immediate offset */
10982 rd = insn & 7;
10983 rn = (insn >> 3) & 7;
10984 addr = load_reg(s, rn);
10985 val = (insn >> 5) & 0x3e;
10986 tcg_gen_addi_i32(addr, addr, val);
10987
10988 if (insn & (1 << 11)) {
10989 /* load */
10990 tmp = tcg_temp_new_i32();
10991 gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
10992 store_reg(s, rd, tmp);
10993 } else {
10994 /* store */
10995 tmp = load_reg(s, rd);
10996 gen_aa32_st16(s, tmp, addr, get_mem_index(s));
10997 tcg_temp_free_i32(tmp);
10998 }
10999 tcg_temp_free_i32(addr);
11000 break;
11001
11002 case 9:
11003 /* load/store from stack */
11004 rd = (insn >> 8) & 7;
11005 addr = load_reg(s, 13);
11006 val = (insn & 0xff) * 4;
11007 tcg_gen_addi_i32(addr, addr, val);
11008
11009 if (insn & (1 << 11)) {
11010 /* load */
11011 tmp = tcg_temp_new_i32();
11012 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
11013 store_reg(s, rd, tmp);
11014 } else {
11015 /* store */
11016 tmp = load_reg(s, rd);
11017 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
11018 tcg_temp_free_i32(tmp);
11019 }
11020 tcg_temp_free_i32(addr);
11021 break;
11022
11023 case 10:
11024 /* add to high reg */
11025 rd = (insn >> 8) & 7;
11026 if (insn & (1 << 11)) {
11027 /* SP */
11028 tmp = load_reg(s, 13);
11029 } else {
11030 /* PC. bit 1 is ignored. */
11031 tmp = tcg_temp_new_i32();
11032 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
11033 }
11034 val = (insn & 0xff) * 4;
11035 tcg_gen_addi_i32(tmp, tmp, val);
11036 store_reg(s, rd, tmp);
11037 break;
11038
11039 case 11:
11040 /* misc */
11041 op = (insn >> 8) & 0xf;
11042 switch (op) {
11043 case 0:
11044 /* adjust stack pointer */
11045 tmp = load_reg(s, 13);
11046 val = (insn & 0x7f) * 4;
11047 if (insn & (1 << 7))
11048 val = -(int32_t)val;
11049 tcg_gen_addi_i32(tmp, tmp, val);
11050 store_reg(s, 13, tmp);
11051 break;
11052
11053 case 2: /* sign/zero extend. */
11054 ARCH(6);
11055 rd = insn & 7;
11056 rm = (insn >> 3) & 7;
11057 tmp = load_reg(s, rm);
11058 switch ((insn >> 6) & 3) {
11059 case 0: gen_sxth(tmp); break;
11060 case 1: gen_sxtb(tmp); break;
11061 case 2: gen_uxth(tmp); break;
11062 case 3: gen_uxtb(tmp); break;
11063 }
11064 store_reg(s, rd, tmp);
11065 break;
11066 case 4: case 5: case 0xc: case 0xd:
11067 /* push/pop */
11068 addr = load_reg(s, 13);
11069 if (insn & (1 << 8))
11070 offset = 4;
11071 else
11072 offset = 0;
11073 for (i = 0; i < 8; i++) {
11074 if (insn & (1 << i))
11075 offset += 4;
11076 }
11077 if ((insn & (1 << 11)) == 0) {
11078 tcg_gen_addi_i32(addr, addr, -offset);
11079 }
11080 for (i = 0; i < 8; i++) {
11081 if (insn & (1 << i)) {
11082 if (insn & (1 << 11)) {
11083 /* pop */
11084 tmp = tcg_temp_new_i32();
11085 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
11086 store_reg(s, i, tmp);
11087 } else {
11088 /* push */
11089 tmp = load_reg(s, i);
11090 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
11091 tcg_temp_free_i32(tmp);
11092 }
11093 /* advance to the next address. */
11094 tcg_gen_addi_i32(addr, addr, 4);
11095 }
11096 }
11097 TCGV_UNUSED_I32(tmp);
11098 if (insn & (1 << 8)) {
11099 if (insn & (1 << 11)) {
11100 /* pop pc */
11101 tmp = tcg_temp_new_i32();
11102 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
11103 /* don't set the pc until the rest of the instruction
11104 has completed */
11105 } else {
11106 /* push lr */
11107 tmp = load_reg(s, 14);
11108 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
11109 tcg_temp_free_i32(tmp);
11110 }
11111 tcg_gen_addi_i32(addr, addr, 4);
11112 }
11113 if ((insn & (1 << 11)) == 0) {
11114 tcg_gen_addi_i32(addr, addr, -offset);
11115 }
11116 /* write back the new stack pointer */
11117 store_reg(s, 13, addr);
11118 /* set the new PC value */
11119 if ((insn & 0x0900) == 0x0900) {
11120 store_reg_from_load(s, 15, tmp);
11121 }
11122 break;
11123
11124 case 1: case 3: case 9: case 11: /* czb */
11125 rm = insn & 7;
11126 tmp = load_reg(s, rm);
11127 s->condlabel = gen_new_label();
11128 s->condjmp = 1;
11129 if (insn & (1 << 11))
11130 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
11131 else
11132 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
11133 tcg_temp_free_i32(tmp);
11134 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
11135 val = (uint32_t)s->pc + 2;
11136 val += offset;
11137 gen_jmp(s, val);
11138 break;
11139
11140 case 15: /* IT, nop-hint. */
11141 if ((insn & 0xf) == 0) {
11142 gen_nop_hint(s, (insn >> 4) & 0xf);
11143 break;
11144 }
11145 /* If Then. */
11146 s->condexec_cond = (insn >> 4) & 0xe;
11147 s->condexec_mask = insn & 0x1f;
11148 /* No actual code generated for this insn, just setup state. */
11149 break;
11150
11151 case 0xe: /* bkpt */
11152 {
11153 int imm8 = extract32(insn, 0, 8);
11154 ARCH(5);
11155 gen_exception_insn(s, 2, EXCP_BKPT, syn_aa32_bkpt(imm8, true),
11156 default_exception_el(s));
11157 break;
11158 }
11159
11160 case 0xa: /* rev */
11161 ARCH(6);
11162 rn = (insn >> 3) & 0x7;
11163 rd = insn & 0x7;
11164 tmp = load_reg(s, rn);
11165 switch ((insn >> 6) & 3) {
11166 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
11167 case 1: gen_rev16(tmp); break;
11168 case 3: gen_revsh(tmp); break;
11169 default: goto illegal_op;
11170 }
11171 store_reg(s, rd, tmp);
11172 break;
11173
11174 case 6:
11175 switch ((insn >> 5) & 7) {
11176 case 2:
11177 /* setend */
11178 ARCH(6);
11179 if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) {
11180 gen_helper_setend(cpu_env);
11181 s->is_jmp = DISAS_UPDATE;
11182 }
11183 break;
11184 case 3:
11185 /* cps */
11186 ARCH(6);
11187 if (IS_USER(s)) {
11188 break;
11189 }
11190 if (arm_dc_feature(s, ARM_FEATURE_M)) {
11191 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
11192 /* FAULTMASK */
11193 if (insn & 1) {
11194 addr = tcg_const_i32(19);
11195 gen_helper_v7m_msr(cpu_env, addr, tmp);
11196 tcg_temp_free_i32(addr);
11197 }
11198 /* PRIMASK */
11199 if (insn & 2) {
11200 addr = tcg_const_i32(16);
11201 gen_helper_v7m_msr(cpu_env, addr, tmp);
11202 tcg_temp_free_i32(addr);
11203 }
11204 tcg_temp_free_i32(tmp);
11205 gen_lookup_tb(s);
11206 } else {
11207 if (insn & (1 << 4)) {
11208 shift = CPSR_A | CPSR_I | CPSR_F;
11209 } else {
11210 shift = 0;
11211 }
11212 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
11213 }
11214 break;
11215 default:
11216 goto undef;
11217 }
11218 break;
11219
11220 default:
11221 goto undef;
11222 }
11223 break;
11224
11225 case 12:
11226 {
11227 /* load/store multiple */
11228 TCGv_i32 loaded_var;
11229 TCGV_UNUSED_I32(loaded_var);
11230 rn = (insn >> 8) & 0x7;
11231 addr = load_reg(s, rn);
11232 for (i = 0; i < 8; i++) {
11233 if (insn & (1 << i)) {
11234 if (insn & (1 << 11)) {
11235 /* load */
11236 tmp = tcg_temp_new_i32();
11237 gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
11238 if (i == rn) {
11239 loaded_var = tmp;
11240 } else {
11241 store_reg(s, i, tmp);
11242 }
11243 } else {
11244 /* store */
11245 tmp = load_reg(s, i);
11246 gen_aa32_st32(s, tmp, addr, get_mem_index(s));
11247 tcg_temp_free_i32(tmp);
11248 }
11249 /* advance to the next address */
11250 tcg_gen_addi_i32(addr, addr, 4);
11251 }
11252 }
11253 if ((insn & (1 << rn)) == 0) {
11254 /* base reg not in list: base register writeback */
11255 store_reg(s, rn, addr);
11256 } else {
11257 /* base reg in list: if load, complete it now */
11258 if (insn & (1 << 11)) {
11259 store_reg(s, rn, loaded_var);
11260 }
11261 tcg_temp_free_i32(addr);
11262 }
11263 break;
11264 }
11265 case 13:
11266 /* conditional branch or swi */
11267 cond = (insn >> 8) & 0xf;
11268 if (cond == 0xe)
11269 goto undef;
11270
11271 if (cond == 0xf) {
11272 /* swi */
11273 gen_set_pc_im(s, s->pc);
11274 s->svc_imm = extract32(insn, 0, 8);
11275 s->is_jmp = DISAS_SWI;
11276 break;
11277 }
11278 /* generate a conditional jump to next instruction */
11279 s->condlabel = gen_new_label();
11280 arm_gen_test_cc(cond ^ 1, s->condlabel);
11281 s->condjmp = 1;
11282
11283 /* jump to the offset */
11284 val = (uint32_t)s->pc + 2;
11285 offset = ((int32_t)insn << 24) >> 24;
11286 val += offset << 1;
11287 gen_jmp(s, val);
11288 break;
11289
11290 case 14:
11291 if (insn & (1 << 11)) {
11292 if (disas_thumb2_insn(env, s, insn))
11293 goto undef32;
11294 break;
11295 }
11296 /* unconditional branch */
11297 val = (uint32_t)s->pc;
11298 offset = ((int32_t)insn << 21) >> 21;
11299 val += (offset << 1) + 2;
11300 gen_jmp(s, val);
11301 break;
11302
11303 case 15:
11304 if (disas_thumb2_insn(env, s, insn))
11305 goto undef32;
11306 break;
11307 }
11308 return;
11309 undef32:
11310 gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
11311 default_exception_el(s));
11312 return;
11313 illegal_op:
11314 undef:
11315 gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
11316 default_exception_el(s));
11317 }
11318
11319 static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
11320 {
11321 /* Return true if the insn at dc->pc might cross a page boundary.
11322 * (False positives are OK, false negatives are not.)
11323 */
11324 uint16_t insn;
11325
11326 if ((s->pc & 3) == 0) {
11327 /* At a 4-aligned address we can't be crossing a page */
11328 return false;
11329 }
11330
11331 /* This must be a Thumb insn */
11332 insn = arm_lduw_code(env, s->pc, s->sctlr_b);
11333
11334 if ((insn >> 11) >= 0x1d) {
11335 /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
11336 * First half of a 32-bit Thumb insn. Thumb-1 cores might
11337 * end up actually treating this as two 16-bit insns (see the
11338 * code at the start of disas_thumb2_insn()) but we don't bother
11339 * to check for that as it is unlikely, and false positives here
11340 * are harmless.
11341 */
11342 return true;
11343 }
11344 /* Definitely a 16-bit insn, can't be crossing a page. */
11345 return false;
11346 }
11347
11348 /* generate intermediate code for basic block 'tb'. */
11349 void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
11350 {
11351 ARMCPU *cpu = arm_env_get_cpu(env);
11352 CPUState *cs = CPU(cpu);
11353 DisasContext dc1, *dc = &dc1;
11354 target_ulong pc_start;
11355 target_ulong next_page_start;
11356 int num_insns;
11357 int max_insns;
11358 bool end_of_page;
11359
11360 /* generate intermediate code */
11361
11362 /* The A64 decoder has its own top level loop, because it doesn't need
11363 * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
11364 */
11365 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
11366 gen_intermediate_code_a64(cpu, tb);
11367 return;
11368 }
11369
11370 pc_start = tb->pc;
11371
11372 dc->tb = tb;
11373
11374 dc->is_jmp = DISAS_NEXT;
11375 dc->pc = pc_start;
11376 dc->singlestep_enabled = cs->singlestep_enabled;
11377 dc->condjmp = 0;
11378
11379 dc->aarch64 = 0;
11380 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11381 * there is no secure EL1, so we route exceptions to EL3.
11382 */
11383 dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
11384 !arm_el_is_aa64(env, 3);
11385 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
11386 dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags);
11387 dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE;
11388 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
11389 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
11390 dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
11391 dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
11392 #if !defined(CONFIG_USER_ONLY)
11393 dc->user = (dc->current_el == 0);
11394 #endif
11395 dc->ns = ARM_TBFLAG_NS(tb->flags);
11396 dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags);
11397 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
11398 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
11399 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
11400 dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
11401 dc->cp_regs = cpu->cp_regs;
11402 dc->features = env->features;
11403
11404 /* Single step state. The code-generation logic here is:
11405 * SS_ACTIVE == 0:
11406 * generate code with no special handling for single-stepping (except
11407 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11408 * this happens anyway because those changes are all system register or
11409 * PSTATE writes).
11410 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11411 * emit code for one insn
11412 * emit code to clear PSTATE.SS
11413 * emit code to generate software step exception for completed step
11414 * end TB (as usual for having generated an exception)
11415 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11416 * emit code to generate a software step exception
11417 * end the TB
11418 */
11419 dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags);
11420 dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags);
11421 dc->is_ldex = false;
11422 dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */
11423
11424 cpu_F0s = tcg_temp_new_i32();
11425 cpu_F1s = tcg_temp_new_i32();
11426 cpu_F0d = tcg_temp_new_i64();
11427 cpu_F1d = tcg_temp_new_i64();
11428 cpu_V0 = cpu_F0d;
11429 cpu_V1 = cpu_F1d;
11430 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
11431 cpu_M0 = tcg_temp_new_i64();
11432 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
11433 num_insns = 0;
11434 max_insns = tb->cflags & CF_COUNT_MASK;
11435 if (max_insns == 0) {
11436 max_insns = CF_COUNT_MASK;
11437 }
11438 if (max_insns > TCG_MAX_INSNS) {
11439 max_insns = TCG_MAX_INSNS;
11440 }
11441
11442 gen_tb_start(tb);
11443
11444 tcg_clear_temp_count();
11445
11446 /* A note on handling of the condexec (IT) bits:
11447 *
11448 * We want to avoid the overhead of having to write the updated condexec
11449 * bits back to the CPUARMState for every instruction in an IT block. So:
11450 * (1) if the condexec bits are not already zero then we write
11451 * zero back into the CPUARMState now. This avoids complications trying
11452 * to do it at the end of the block. (For example if we don't do this
11453 * it's hard to identify whether we can safely skip writing condexec
11454 * at the end of the TB, which we definitely want to do for the case
11455 * where a TB doesn't do anything with the IT state at all.)
11456 * (2) if we are going to leave the TB then we call gen_set_condexec()
11457 * which will write the correct value into CPUARMState if zero is wrong.
11458 * This is done both for leaving the TB at the end, and for leaving
11459 * it because of an exception we know will happen, which is done in
11460 * gen_exception_insn(). The latter is necessary because we need to
11461 * leave the TB with the PC/IT state just prior to execution of the
11462 * instruction which caused the exception.
11463 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
11464 * then the CPUARMState will be wrong and we need to reset it.
11465 * This is handled in the same way as restoration of the
11466 * PC in these situations; we save the value of the condexec bits
11467 * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()
11468 * then uses this to restore them after an exception.
11469 *
11470 * Note that there are no instructions which can read the condexec
11471 * bits, and none which can write non-static values to them, so
11472 * we don't need to care about whether CPUARMState is correct in the
11473 * middle of a TB.
11474 */
11475
11476 /* Reset the conditional execution bits immediately. This avoids
11477 complications trying to do it at the end of the block. */
11478 if (dc->condexec_mask || dc->condexec_cond)
11479 {
11480 TCGv_i32 tmp = tcg_temp_new_i32();
11481 tcg_gen_movi_i32(tmp, 0);
11482 store_cpu_field(tmp, condexec_bits);
11483 }
11484 do {
11485 tcg_gen_insn_start(dc->pc,
11486 (dc->condexec_cond << 4) | (dc->condexec_mask >> 1));
11487 num_insns++;
11488
11489 #ifdef CONFIG_USER_ONLY
11490 /* Intercept jump to the magic kernel page. */
11491 if (dc->pc >= 0xffff0000) {
11492 /* We always get here via a jump, so know we are not in a
11493 conditional execution block. */
11494 gen_exception_internal(EXCP_KERNEL_TRAP);
11495 dc->is_jmp = DISAS_EXC;
11496 break;
11497 }
11498 #else
11499 if (dc->pc >= 0xfffffff0 && arm_dc_feature(dc, ARM_FEATURE_M)) {
11500 /* We always get here via a jump, so know we are not in a
11501 conditional execution block. */
11502 gen_exception_internal(EXCP_EXCEPTION_EXIT);
11503 dc->is_jmp = DISAS_EXC;
11504 break;
11505 }
11506 #endif
11507
11508 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11509 CPUBreakpoint *bp;
11510 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11511 if (bp->pc == dc->pc) {
11512 if (bp->flags & BP_CPU) {
11513 gen_set_condexec(dc);
11514 gen_set_pc_im(dc, dc->pc);
11515 gen_helper_check_breakpoints(cpu_env);
11516 /* End the TB early; it's likely not going to be executed */
11517 dc->is_jmp = DISAS_UPDATE;
11518 } else {
11519 gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
11520 /* The address covered by the breakpoint must be
11521 included in [tb->pc, tb->pc + tb->size) in order
11522 to for it to be properly cleared -- thus we
11523 increment the PC here so that the logic setting
11524 tb->size below does the right thing. */
11525 /* TODO: Advance PC by correct instruction length to
11526 * avoid disassembler error messages */
11527 dc->pc += 2;
11528 goto done_generating;
11529 }
11530 break;
11531 }
11532 }
11533 }
11534
11535 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
11536 gen_io_start();
11537 }
11538
11539 if (dc->ss_active && !dc->pstate_ss) {
11540 /* Singlestep state is Active-pending.
11541 * If we're in this state at the start of a TB then either
11542 * a) we just took an exception to an EL which is being debugged
11543 * and this is the first insn in the exception handler
11544 * b) debug exceptions were masked and we just unmasked them
11545 * without changing EL (eg by clearing PSTATE.D)
11546 * In either case we're going to take a swstep exception in the
11547 * "did not step an insn" case, and so the syndrome ISV and EX
11548 * bits should be zero.
11549 */
11550 assert(num_insns == 1);
11551 gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
11552 default_exception_el(dc));
11553 goto done_generating;
11554 }
11555
11556 if (dc->thumb) {
11557 disas_thumb_insn(env, dc);
11558 if (dc->condexec_mask) {
11559 dc->condexec_cond = (dc->condexec_cond & 0xe)
11560 | ((dc->condexec_mask >> 4) & 1);
11561 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
11562 if (dc->condexec_mask == 0) {
11563 dc->condexec_cond = 0;
11564 }
11565 }
11566 } else {
11567 unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
11568 dc->pc += 4;
11569 disas_arm_insn(dc, insn);
11570 }
11571
11572 if (dc->condjmp && !dc->is_jmp) {
11573 gen_set_label(dc->condlabel);
11574 dc->condjmp = 0;
11575 }
11576
11577 if (tcg_check_temp_count()) {
11578 fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
11579 dc->pc);
11580 }
11581
11582 /* Translation stops when a conditional branch is encountered.
11583 * Otherwise the subsequent code could get translated several times.
11584 * Also stop translation when a page boundary is reached. This
11585 * ensures prefetch aborts occur at the right place. */
11586
11587 /* We want to stop the TB if the next insn starts in a new page,
11588 * or if it spans between this page and the next. This means that
11589 * if we're looking at the last halfword in the page we need to
11590 * see if it's a 16-bit Thumb insn (which will fit in this TB)
11591 * or a 32-bit Thumb insn (which won't).
11592 * This is to avoid generating a silly TB with a single 16-bit insn
11593 * in it at the end of this page (which would execute correctly
11594 * but isn't very efficient).
11595 */
11596 end_of_page = (dc->pc >= next_page_start) ||
11597 ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));
11598
11599 } while (!dc->is_jmp && !tcg_op_buf_full() &&
11600 !cs->singlestep_enabled &&
11601 !singlestep &&
11602 !dc->ss_active &&
11603 !end_of_page &&
11604 num_insns < max_insns);
11605
11606 if (tb->cflags & CF_LAST_IO) {
11607 if (dc->condjmp) {
11608 /* FIXME: This can theoretically happen with self-modifying
11609 code. */
11610 cpu_abort(cs, "IO on conditional branch instruction");
11611 }
11612 gen_io_end();
11613 }
11614
11615 /* At this stage dc->condjmp will only be set when the skipped
11616 instruction was a conditional branch or trap, and the PC has
11617 already been written. */
11618 if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
11619 /* Unconditional and "condition passed" instruction codepath. */
11620 gen_set_condexec(dc);
11621 switch (dc->is_jmp) {
11622 case DISAS_SWI:
11623 gen_ss_advance(dc);
11624 gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
11625 default_exception_el(dc));
11626 break;
11627 case DISAS_HVC:
11628 gen_ss_advance(dc);
11629 gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
11630 break;
11631 case DISAS_SMC:
11632 gen_ss_advance(dc);
11633 gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
11634 break;
11635 case DISAS_NEXT:
11636 case DISAS_UPDATE:
11637 gen_set_pc_im(dc, dc->pc);
11638 /* fall through */
11639 default:
11640 if (dc->ss_active) {
11641 gen_step_complete_exception(dc);
11642 } else {
11643 /* FIXME: Single stepping a WFI insn will not halt
11644 the CPU. */
11645 gen_exception_internal(EXCP_DEBUG);
11646 }
11647 }
11648 if (dc->condjmp) {
11649 /* "Condition failed" instruction codepath. */
11650 gen_set_label(dc->condlabel);
11651 gen_set_condexec(dc);
11652 gen_set_pc_im(dc, dc->pc);
11653 if (dc->ss_active) {
11654 gen_step_complete_exception(dc);
11655 } else {
11656 gen_exception_internal(EXCP_DEBUG);
11657 }
11658 }
11659 } else {
11660 /* While branches must always occur at the end of an IT block,
11661 there are a few other things that can cause us to terminate
11662 the TB in the middle of an IT block:
11663 - Exception generating instructions (bkpt, swi, undefined).
11664 - Page boundaries.
11665 - Hardware watchpoints.
11666 Hardware breakpoints have already been handled and skip this code.
11667 */
11668 gen_set_condexec(dc);
11669 switch(dc->is_jmp) {
11670 case DISAS_NEXT:
11671 gen_goto_tb(dc, 1, dc->pc);
11672 break;
11673 case DISAS_UPDATE:
11674 gen_set_pc_im(dc, dc->pc);
11675 /* fall through */
11676 case DISAS_JUMP:
11677 default:
11678 /* indicate that the hash table must be used to find the next TB */
11679 tcg_gen_exit_tb(0);
11680 break;
11681 case DISAS_TB_JUMP:
11682 /* nothing more to generate */
11683 break;
11684 case DISAS_WFI:
11685 gen_helper_wfi(cpu_env);
11686 /* The helper doesn't necessarily throw an exception, but we
11687 * must go back to the main loop to check for interrupts anyway.
11688 */
11689 tcg_gen_exit_tb(0);
11690 break;
11691 case DISAS_WFE:
11692 gen_helper_wfe(cpu_env);
11693 break;
11694 case DISAS_YIELD:
11695 gen_helper_yield(cpu_env);
11696 break;
11697 case DISAS_SWI:
11698 gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
11699 default_exception_el(dc));
11700 break;
11701 case DISAS_HVC:
11702 gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
11703 break;
11704 case DISAS_SMC:
11705 gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
11706 break;
11707 }
11708 if (dc->condjmp) {
11709 gen_set_label(dc->condlabel);
11710 gen_set_condexec(dc);
11711 gen_goto_tb(dc, 1, dc->pc);
11712 dc->condjmp = 0;
11713 }
11714 }
11715
11716 done_generating:
11717 gen_tb_end(tb, num_insns);
11718
11719 #ifdef DEBUG_DISAS
11720 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11721 qemu_log("----------------\n");
11722 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11723 log_target_disas(cs, pc_start, dc->pc - pc_start,
11724 dc->thumb | (dc->sctlr_b << 1));
11725 qemu_log("\n");
11726 }
11727 #endif
11728 tb->size = dc->pc - pc_start;
11729 tb->icount = num_insns;
11730 }
11731
11732 static const char *cpu_mode_names[16] = {
11733 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
11734 "???", "???", "hyp", "und", "???", "???", "???", "sys"
11735 };
11736
11737 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11738 int flags)
11739 {
11740 ARMCPU *cpu = ARM_CPU(cs);
11741 CPUARMState *env = &cpu->env;
11742 int i;
11743 uint32_t psr;
11744 const char *ns_status;
11745
11746 if (is_a64(env)) {
11747 aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags);
11748 return;
11749 }
11750
11751 for(i=0;i<16;i++) {
11752 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
11753 if ((i % 4) == 3)
11754 cpu_fprintf(f, "\n");
11755 else
11756 cpu_fprintf(f, " ");
11757 }
11758 psr = cpsr_read(env);
11759
11760 if (arm_feature(env, ARM_FEATURE_EL3) &&
11761 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
11762 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
11763 } else {
11764 ns_status = "";
11765 }
11766
11767 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
11768 psr,
11769 psr & (1 << 31) ? 'N' : '-',
11770 psr & (1 << 30) ? 'Z' : '-',
11771 psr & (1 << 29) ? 'C' : '-',
11772 psr & (1 << 28) ? 'V' : '-',
11773 psr & CPSR_T ? 'T' : 'A',
11774 ns_status,
11775 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
11776
11777 if (flags & CPU_DUMP_FPU) {
11778 int numvfpregs = 0;
11779 if (arm_feature(env, ARM_FEATURE_VFP)) {
11780 numvfpregs += 16;
11781 }
11782 if (arm_feature(env, ARM_FEATURE_VFP3)) {
11783 numvfpregs += 16;
11784 }
11785 for (i = 0; i < numvfpregs; i++) {
11786 uint64_t v = float64_val(env->vfp.regs[i]);
11787 cpu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
11788 i * 2, (uint32_t)v,
11789 i * 2 + 1, (uint32_t)(v >> 32),
11790 i, v);
11791 }
11792 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
11793 }
11794 }
11795
11796 void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
11797 target_ulong *data)
11798 {
11799 if (is_a64(env)) {
11800 env->pc = data[0];
11801 env->condexec_bits = 0;
11802 } else {
11803 env->regs[15] = data[0];
11804 env->condexec_bits = data[1];
11805 }
11806 }
CRIS target port of Qemu