rdma: bug fixes
[qemu/cris-port.git] / target-arm / cpu.c
blob05e52e0e835eae03a9f1f4eaf98a969aa7fe5297
1 /*
2 * QEMU ARM CPU
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "cpu.h"
22 #include "internals.h"
23 #include "qemu-common.h"
24 #include "hw/qdev-properties.h"
25 #include "qapi/qmp/qerror.h"
26 #if !defined(CONFIG_USER_ONLY)
27 #include "hw/loader.h"
28 #endif
29 #include "hw/arm/arm.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_arm.h"
34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
36 ARMCPU *cpu = ARM_CPU(cs);
38 cpu->env.regs[15] = value;
41 static bool arm_cpu_has_work(CPUState *cs)
43 return cs->interrupt_request &
44 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
47 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
49 /* Reset a single ARMCPRegInfo register */
50 ARMCPRegInfo *ri = value;
51 ARMCPU *cpu = opaque;
53 if (ri->type & ARM_CP_SPECIAL) {
54 return;
57 if (ri->resetfn) {
58 ri->resetfn(&cpu->env, ri);
59 return;
62 /* A zero offset is never possible as it would be regs[0]
63 * so we use it to indicate that reset is being handled elsewhere.
64 * This is basically only used for fields in non-core coprocessors
65 * (like the pxa2xx ones).
67 if (!ri->fieldoffset) {
68 return;
71 if (cpreg_field_is_64bit(ri)) {
72 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
73 } else {
74 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
78 /* CPUClass::reset() */
79 static void arm_cpu_reset(CPUState *s)
81 ARMCPU *cpu = ARM_CPU(s);
82 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
83 CPUARMState *env = &cpu->env;
85 acc->parent_reset(s);
87 memset(env, 0, offsetof(CPUARMState, features));
88 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
89 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
90 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
91 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
92 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
94 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
95 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
98 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
99 /* 64 bit CPUs always start in 64 bit mode */
100 env->aarch64 = 1;
101 #if defined(CONFIG_USER_ONLY)
102 env->pstate = PSTATE_MODE_EL0t;
103 /* Userspace expects access to CTL_EL0 and the cache ops */
104 env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
105 /* and to the FP/Neon instructions */
106 env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
107 #else
108 env->pstate = PSTATE_MODE_EL1h;
109 env->pc = cpu->rvbar;
110 #endif
111 } else {
112 #if defined(CONFIG_USER_ONLY)
113 /* Userspace expects access to cp10 and cp11 for FP/Neon */
114 env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
115 #endif
118 #if defined(CONFIG_USER_ONLY)
119 env->uncached_cpsr = ARM_CPU_MODE_USR;
120 /* For user mode we must enable access to coprocessors */
121 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
122 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
123 env->cp15.c15_cpar = 3;
124 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
125 env->cp15.c15_cpar = 1;
127 #else
128 /* SVC mode with interrupts disabled. */
129 env->uncached_cpsr = ARM_CPU_MODE_SVC;
130 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
131 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
132 clear at reset. Initial SP and PC are loaded from ROM. */
133 if (IS_M(env)) {
134 uint32_t pc;
135 uint8_t *rom;
136 env->daif &= ~PSTATE_I;
137 rom = rom_ptr(0);
138 if (rom) {
139 /* We should really use ldl_phys here, in case the guest
140 modified flash and reset itself. However images
141 loaded via -kernel have not been copied yet, so load the
142 values directly from there. */
143 env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
144 pc = ldl_p(rom + 4);
145 env->thumb = pc & 1;
146 env->regs[15] = pc & ~1;
150 if (env->cp15.c1_sys & SCTLR_V) {
151 env->regs[15] = 0xFFFF0000;
154 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
155 #endif
156 set_flush_to_zero(1, &env->vfp.standard_fp_status);
157 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
158 set_default_nan_mode(1, &env->vfp.standard_fp_status);
159 set_float_detect_tininess(float_tininess_before_rounding,
160 &env->vfp.fp_status);
161 set_float_detect_tininess(float_tininess_before_rounding,
162 &env->vfp.standard_fp_status);
163 tlb_flush(s, 1);
164 /* Reset is a state change for some CPUARMState fields which we
165 * bake assumptions about into translated code, so we need to
166 * tb_flush().
168 tb_flush(env);
170 #ifndef CONFIG_USER_ONLY
171 if (kvm_enabled()) {
172 kvm_arm_reset_vcpu(cpu);
174 #endif
177 #ifndef CONFIG_USER_ONLY
178 static void arm_cpu_set_irq(void *opaque, int irq, int level)
180 ARMCPU *cpu = opaque;
181 CPUState *cs = CPU(cpu);
183 switch (irq) {
184 case ARM_CPU_IRQ:
185 if (level) {
186 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
187 } else {
188 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
190 break;
191 case ARM_CPU_FIQ:
192 if (level) {
193 cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
194 } else {
195 cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
197 break;
198 default:
199 hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
203 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
205 #ifdef CONFIG_KVM
206 ARMCPU *cpu = opaque;
207 CPUState *cs = CPU(cpu);
208 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
210 switch (irq) {
211 case ARM_CPU_IRQ:
212 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
213 break;
214 case ARM_CPU_FIQ:
215 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
216 break;
217 default:
218 hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
220 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
221 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
222 #endif
224 #endif
226 static inline void set_feature(CPUARMState *env, int feature)
228 env->features |= 1ULL << feature;
231 static void arm_cpu_initfn(Object *obj)
233 CPUState *cs = CPU(obj);
234 ARMCPU *cpu = ARM_CPU(obj);
235 static bool inited;
237 cs->env_ptr = &cpu->env;
238 cpu_exec_init(&cpu->env);
239 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
240 g_free, g_free);
242 #ifndef CONFIG_USER_ONLY
243 /* Our inbound IRQ and FIQ lines */
244 if (kvm_enabled()) {
245 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
246 } else {
247 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
250 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
251 arm_gt_ptimer_cb, cpu);
252 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
253 arm_gt_vtimer_cb, cpu);
254 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
255 ARRAY_SIZE(cpu->gt_timer_outputs));
256 #endif
258 /* DTB consumers generally don't in fact care what the 'compatible'
259 * string is, so always provide some string and trust that a hypothetical
260 * picky DTB consumer will also provide a helpful error message.
262 cpu->dtb_compatible = "qemu,unknown";
263 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
264 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
266 if (tcg_enabled() && !inited) {
267 inited = true;
268 arm_translate_init();
272 static Property arm_cpu_reset_cbar_property =
273 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
275 static Property arm_cpu_reset_hivecs_property =
276 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
278 static Property arm_cpu_rvbar_property =
279 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
281 static void arm_cpu_post_init(Object *obj)
283 ARMCPU *cpu = ARM_CPU(obj);
285 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
286 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
287 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
288 &error_abort);
291 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
292 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
293 &error_abort);
296 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
297 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
298 &error_abort);
302 static void arm_cpu_finalizefn(Object *obj)
304 ARMCPU *cpu = ARM_CPU(obj);
305 g_hash_table_destroy(cpu->cp_regs);
308 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
310 CPUState *cs = CPU(dev);
311 ARMCPU *cpu = ARM_CPU(dev);
312 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
313 CPUARMState *env = &cpu->env;
315 /* Some features automatically imply others: */
316 if (arm_feature(env, ARM_FEATURE_V8)) {
317 set_feature(env, ARM_FEATURE_V7);
318 set_feature(env, ARM_FEATURE_ARM_DIV);
319 set_feature(env, ARM_FEATURE_LPAE);
321 if (arm_feature(env, ARM_FEATURE_V7)) {
322 set_feature(env, ARM_FEATURE_VAPA);
323 set_feature(env, ARM_FEATURE_THUMB2);
324 set_feature(env, ARM_FEATURE_MPIDR);
325 if (!arm_feature(env, ARM_FEATURE_M)) {
326 set_feature(env, ARM_FEATURE_V6K);
327 } else {
328 set_feature(env, ARM_FEATURE_V6);
331 if (arm_feature(env, ARM_FEATURE_V6K)) {
332 set_feature(env, ARM_FEATURE_V6);
333 set_feature(env, ARM_FEATURE_MVFR);
335 if (arm_feature(env, ARM_FEATURE_V6)) {
336 set_feature(env, ARM_FEATURE_V5);
337 if (!arm_feature(env, ARM_FEATURE_M)) {
338 set_feature(env, ARM_FEATURE_AUXCR);
341 if (arm_feature(env, ARM_FEATURE_V5)) {
342 set_feature(env, ARM_FEATURE_V4T);
344 if (arm_feature(env, ARM_FEATURE_M)) {
345 set_feature(env, ARM_FEATURE_THUMB_DIV);
347 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
348 set_feature(env, ARM_FEATURE_THUMB_DIV);
350 if (arm_feature(env, ARM_FEATURE_VFP4)) {
351 set_feature(env, ARM_FEATURE_VFP3);
352 set_feature(env, ARM_FEATURE_VFP_FP16);
354 if (arm_feature(env, ARM_FEATURE_VFP3)) {
355 set_feature(env, ARM_FEATURE_VFP);
357 if (arm_feature(env, ARM_FEATURE_LPAE)) {
358 set_feature(env, ARM_FEATURE_V7MP);
359 set_feature(env, ARM_FEATURE_PXN);
361 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
362 set_feature(env, ARM_FEATURE_CBAR);
365 if (cpu->reset_hivecs) {
366 cpu->reset_sctlr |= (1 << 13);
369 register_cp_regs_for_features(cpu);
370 arm_cpu_register_gdb_regs_for_features(cpu);
372 init_cpreg_list(cpu);
374 qemu_init_vcpu(cs);
375 cpu_reset(cs);
377 acc->parent_realize(dev, errp);
380 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
382 ObjectClass *oc;
383 char *typename;
385 if (!cpu_model) {
386 return NULL;
389 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
390 oc = object_class_by_name(typename);
391 g_free(typename);
392 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
393 object_class_is_abstract(oc)) {
394 return NULL;
396 return oc;
399 /* CPU models. These are not needed for the AArch64 linux-user build. */
400 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
402 static void arm926_initfn(Object *obj)
404 ARMCPU *cpu = ARM_CPU(obj);
406 cpu->dtb_compatible = "arm,arm926";
407 set_feature(&cpu->env, ARM_FEATURE_V5);
408 set_feature(&cpu->env, ARM_FEATURE_VFP);
409 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
410 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
411 cpu->midr = 0x41069265;
412 cpu->reset_fpsid = 0x41011090;
413 cpu->ctr = 0x1dd20d2;
414 cpu->reset_sctlr = 0x00090078;
417 static void arm946_initfn(Object *obj)
419 ARMCPU *cpu = ARM_CPU(obj);
421 cpu->dtb_compatible = "arm,arm946";
422 set_feature(&cpu->env, ARM_FEATURE_V5);
423 set_feature(&cpu->env, ARM_FEATURE_MPU);
424 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
425 cpu->midr = 0x41059461;
426 cpu->ctr = 0x0f004006;
427 cpu->reset_sctlr = 0x00000078;
430 static void arm1026_initfn(Object *obj)
432 ARMCPU *cpu = ARM_CPU(obj);
434 cpu->dtb_compatible = "arm,arm1026";
435 set_feature(&cpu->env, ARM_FEATURE_V5);
436 set_feature(&cpu->env, ARM_FEATURE_VFP);
437 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
438 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
439 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
440 cpu->midr = 0x4106a262;
441 cpu->reset_fpsid = 0x410110a0;
442 cpu->ctr = 0x1dd20d2;
443 cpu->reset_sctlr = 0x00090078;
444 cpu->reset_auxcr = 1;
446 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
447 ARMCPRegInfo ifar = {
448 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
449 .access = PL1_RW,
450 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),
451 .resetvalue = 0
453 define_one_arm_cp_reg(cpu, &ifar);
457 static void arm1136_r2_initfn(Object *obj)
459 ARMCPU *cpu = ARM_CPU(obj);
460 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
461 * older core than plain "arm1136". In particular this does not
462 * have the v6K features.
463 * These ID register values are correct for 1136 but may be wrong
464 * for 1136_r2 (in particular r0p2 does not actually implement most
465 * of the ID registers).
468 cpu->dtb_compatible = "arm,arm1136";
469 set_feature(&cpu->env, ARM_FEATURE_V6);
470 set_feature(&cpu->env, ARM_FEATURE_VFP);
471 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
472 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
473 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
474 cpu->midr = 0x4107b362;
475 cpu->reset_fpsid = 0x410120b4;
476 cpu->mvfr0 = 0x11111111;
477 cpu->mvfr1 = 0x00000000;
478 cpu->ctr = 0x1dd20d2;
479 cpu->reset_sctlr = 0x00050078;
480 cpu->id_pfr0 = 0x111;
481 cpu->id_pfr1 = 0x1;
482 cpu->id_dfr0 = 0x2;
483 cpu->id_afr0 = 0x3;
484 cpu->id_mmfr0 = 0x01130003;
485 cpu->id_mmfr1 = 0x10030302;
486 cpu->id_mmfr2 = 0x01222110;
487 cpu->id_isar0 = 0x00140011;
488 cpu->id_isar1 = 0x12002111;
489 cpu->id_isar2 = 0x11231111;
490 cpu->id_isar3 = 0x01102131;
491 cpu->id_isar4 = 0x141;
492 cpu->reset_auxcr = 7;
495 static void arm1136_initfn(Object *obj)
497 ARMCPU *cpu = ARM_CPU(obj);
499 cpu->dtb_compatible = "arm,arm1136";
500 set_feature(&cpu->env, ARM_FEATURE_V6K);
501 set_feature(&cpu->env, ARM_FEATURE_V6);
502 set_feature(&cpu->env, ARM_FEATURE_VFP);
503 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
504 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
505 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
506 cpu->midr = 0x4117b363;
507 cpu->reset_fpsid = 0x410120b4;
508 cpu->mvfr0 = 0x11111111;
509 cpu->mvfr1 = 0x00000000;
510 cpu->ctr = 0x1dd20d2;
511 cpu->reset_sctlr = 0x00050078;
512 cpu->id_pfr0 = 0x111;
513 cpu->id_pfr1 = 0x1;
514 cpu->id_dfr0 = 0x2;
515 cpu->id_afr0 = 0x3;
516 cpu->id_mmfr0 = 0x01130003;
517 cpu->id_mmfr1 = 0x10030302;
518 cpu->id_mmfr2 = 0x01222110;
519 cpu->id_isar0 = 0x00140011;
520 cpu->id_isar1 = 0x12002111;
521 cpu->id_isar2 = 0x11231111;
522 cpu->id_isar3 = 0x01102131;
523 cpu->id_isar4 = 0x141;
524 cpu->reset_auxcr = 7;
527 static void arm1176_initfn(Object *obj)
529 ARMCPU *cpu = ARM_CPU(obj);
531 cpu->dtb_compatible = "arm,arm1176";
532 set_feature(&cpu->env, ARM_FEATURE_V6K);
533 set_feature(&cpu->env, ARM_FEATURE_VFP);
534 set_feature(&cpu->env, ARM_FEATURE_VAPA);
535 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
536 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
537 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
538 cpu->midr = 0x410fb767;
539 cpu->reset_fpsid = 0x410120b5;
540 cpu->mvfr0 = 0x11111111;
541 cpu->mvfr1 = 0x00000000;
542 cpu->ctr = 0x1dd20d2;
543 cpu->reset_sctlr = 0x00050078;
544 cpu->id_pfr0 = 0x111;
545 cpu->id_pfr1 = 0x11;
546 cpu->id_dfr0 = 0x33;
547 cpu->id_afr0 = 0;
548 cpu->id_mmfr0 = 0x01130003;
549 cpu->id_mmfr1 = 0x10030302;
550 cpu->id_mmfr2 = 0x01222100;
551 cpu->id_isar0 = 0x0140011;
552 cpu->id_isar1 = 0x12002111;
553 cpu->id_isar2 = 0x11231121;
554 cpu->id_isar3 = 0x01102131;
555 cpu->id_isar4 = 0x01141;
556 cpu->reset_auxcr = 7;
559 static void arm11mpcore_initfn(Object *obj)
561 ARMCPU *cpu = ARM_CPU(obj);
563 cpu->dtb_compatible = "arm,arm11mpcore";
564 set_feature(&cpu->env, ARM_FEATURE_V6K);
565 set_feature(&cpu->env, ARM_FEATURE_VFP);
566 set_feature(&cpu->env, ARM_FEATURE_VAPA);
567 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
568 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
569 cpu->midr = 0x410fb022;
570 cpu->reset_fpsid = 0x410120b4;
571 cpu->mvfr0 = 0x11111111;
572 cpu->mvfr1 = 0x00000000;
573 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
574 cpu->id_pfr0 = 0x111;
575 cpu->id_pfr1 = 0x1;
576 cpu->id_dfr0 = 0;
577 cpu->id_afr0 = 0x2;
578 cpu->id_mmfr0 = 0x01100103;
579 cpu->id_mmfr1 = 0x10020302;
580 cpu->id_mmfr2 = 0x01222000;
581 cpu->id_isar0 = 0x00100011;
582 cpu->id_isar1 = 0x12002111;
583 cpu->id_isar2 = 0x11221011;
584 cpu->id_isar3 = 0x01102131;
585 cpu->id_isar4 = 0x141;
586 cpu->reset_auxcr = 1;
589 static void cortex_m3_initfn(Object *obj)
591 ARMCPU *cpu = ARM_CPU(obj);
592 set_feature(&cpu->env, ARM_FEATURE_V7);
593 set_feature(&cpu->env, ARM_FEATURE_M);
594 cpu->midr = 0x410fc231;
597 static void arm_v7m_class_init(ObjectClass *oc, void *data)
599 #ifndef CONFIG_USER_ONLY
600 CPUClass *cc = CPU_CLASS(oc);
602 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
603 #endif
606 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
607 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
608 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
609 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
610 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
611 REGINFO_SENTINEL
614 static void cortex_a8_initfn(Object *obj)
616 ARMCPU *cpu = ARM_CPU(obj);
618 cpu->dtb_compatible = "arm,cortex-a8";
619 set_feature(&cpu->env, ARM_FEATURE_V7);
620 set_feature(&cpu->env, ARM_FEATURE_VFP3);
621 set_feature(&cpu->env, ARM_FEATURE_NEON);
622 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
623 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
624 cpu->midr = 0x410fc080;
625 cpu->reset_fpsid = 0x410330c0;
626 cpu->mvfr0 = 0x11110222;
627 cpu->mvfr1 = 0x00011100;
628 cpu->ctr = 0x82048004;
629 cpu->reset_sctlr = 0x00c50078;
630 cpu->id_pfr0 = 0x1031;
631 cpu->id_pfr1 = 0x11;
632 cpu->id_dfr0 = 0x400;
633 cpu->id_afr0 = 0;
634 cpu->id_mmfr0 = 0x31100003;
635 cpu->id_mmfr1 = 0x20000000;
636 cpu->id_mmfr2 = 0x01202000;
637 cpu->id_mmfr3 = 0x11;
638 cpu->id_isar0 = 0x00101111;
639 cpu->id_isar1 = 0x12112111;
640 cpu->id_isar2 = 0x21232031;
641 cpu->id_isar3 = 0x11112131;
642 cpu->id_isar4 = 0x00111142;
643 cpu->clidr = (1 << 27) | (2 << 24) | 3;
644 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
645 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
646 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
647 cpu->reset_auxcr = 2;
648 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
651 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
652 /* power_control should be set to maximum latency. Again,
653 * default to 0 and set by private hook
655 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
656 .access = PL1_RW, .resetvalue = 0,
657 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
658 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
659 .access = PL1_RW, .resetvalue = 0,
660 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
661 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
662 .access = PL1_RW, .resetvalue = 0,
663 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
664 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
665 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
666 /* TLB lockdown control */
667 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
668 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
669 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
670 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
671 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
672 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
673 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
674 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
675 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
676 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
677 REGINFO_SENTINEL
680 static void cortex_a9_initfn(Object *obj)
682 ARMCPU *cpu = ARM_CPU(obj);
684 cpu->dtb_compatible = "arm,cortex-a9";
685 set_feature(&cpu->env, ARM_FEATURE_V7);
686 set_feature(&cpu->env, ARM_FEATURE_VFP3);
687 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
688 set_feature(&cpu->env, ARM_FEATURE_NEON);
689 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
690 /* Note that A9 supports the MP extensions even for
691 * A9UP and single-core A9MP (which are both different
692 * and valid configurations; we don't model A9UP).
694 set_feature(&cpu->env, ARM_FEATURE_V7MP);
695 set_feature(&cpu->env, ARM_FEATURE_CBAR);
696 cpu->midr = 0x410fc090;
697 cpu->reset_fpsid = 0x41033090;
698 cpu->mvfr0 = 0x11110222;
699 cpu->mvfr1 = 0x01111111;
700 cpu->ctr = 0x80038003;
701 cpu->reset_sctlr = 0x00c50078;
702 cpu->id_pfr0 = 0x1031;
703 cpu->id_pfr1 = 0x11;
704 cpu->id_dfr0 = 0x000;
705 cpu->id_afr0 = 0;
706 cpu->id_mmfr0 = 0x00100103;
707 cpu->id_mmfr1 = 0x20000000;
708 cpu->id_mmfr2 = 0x01230000;
709 cpu->id_mmfr3 = 0x00002111;
710 cpu->id_isar0 = 0x00101111;
711 cpu->id_isar1 = 0x13112111;
712 cpu->id_isar2 = 0x21232041;
713 cpu->id_isar3 = 0x11112131;
714 cpu->id_isar4 = 0x00111142;
715 cpu->clidr = (1 << 27) | (1 << 24) | 3;
716 cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
717 cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
718 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
721 #ifndef CONFIG_USER_ONLY
722 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
724 /* Linux wants the number of processors from here.
725 * Might as well set the interrupt-controller bit too.
727 return ((smp_cpus - 1) << 24) | (1 << 23);
729 #endif
731 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
732 #ifndef CONFIG_USER_ONLY
733 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
734 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
735 .writefn = arm_cp_write_ignore, },
736 #endif
737 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
738 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
739 REGINFO_SENTINEL
742 static void cortex_a15_initfn(Object *obj)
744 ARMCPU *cpu = ARM_CPU(obj);
746 cpu->dtb_compatible = "arm,cortex-a15";
747 set_feature(&cpu->env, ARM_FEATURE_V7);
748 set_feature(&cpu->env, ARM_FEATURE_VFP4);
749 set_feature(&cpu->env, ARM_FEATURE_NEON);
750 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
751 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
752 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
753 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
754 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
755 set_feature(&cpu->env, ARM_FEATURE_LPAE);
756 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
757 cpu->midr = 0x412fc0f1;
758 cpu->reset_fpsid = 0x410430f0;
759 cpu->mvfr0 = 0x10110222;
760 cpu->mvfr1 = 0x11111111;
761 cpu->ctr = 0x8444c004;
762 cpu->reset_sctlr = 0x00c50078;
763 cpu->id_pfr0 = 0x00001131;
764 cpu->id_pfr1 = 0x00011011;
765 cpu->id_dfr0 = 0x02010555;
766 cpu->id_afr0 = 0x00000000;
767 cpu->id_mmfr0 = 0x10201105;
768 cpu->id_mmfr1 = 0x20000000;
769 cpu->id_mmfr2 = 0x01240000;
770 cpu->id_mmfr3 = 0x02102211;
771 cpu->id_isar0 = 0x02101110;
772 cpu->id_isar1 = 0x13112111;
773 cpu->id_isar2 = 0x21232041;
774 cpu->id_isar3 = 0x11112131;
775 cpu->id_isar4 = 0x10011142;
776 cpu->clidr = 0x0a200023;
777 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
778 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
779 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
780 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
783 static void ti925t_initfn(Object *obj)
785 ARMCPU *cpu = ARM_CPU(obj);
786 set_feature(&cpu->env, ARM_FEATURE_V4T);
787 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
788 cpu->midr = ARM_CPUID_TI925T;
789 cpu->ctr = 0x5109149;
790 cpu->reset_sctlr = 0x00000070;
793 static void sa1100_initfn(Object *obj)
795 ARMCPU *cpu = ARM_CPU(obj);
797 cpu->dtb_compatible = "intel,sa1100";
798 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
799 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
800 cpu->midr = 0x4401A11B;
801 cpu->reset_sctlr = 0x00000070;
804 static void sa1110_initfn(Object *obj)
806 ARMCPU *cpu = ARM_CPU(obj);
807 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
808 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
809 cpu->midr = 0x6901B119;
810 cpu->reset_sctlr = 0x00000070;
813 static void pxa250_initfn(Object *obj)
815 ARMCPU *cpu = ARM_CPU(obj);
817 cpu->dtb_compatible = "marvell,xscale";
818 set_feature(&cpu->env, ARM_FEATURE_V5);
819 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
820 cpu->midr = 0x69052100;
821 cpu->ctr = 0xd172172;
822 cpu->reset_sctlr = 0x00000078;
825 static void pxa255_initfn(Object *obj)
827 ARMCPU *cpu = ARM_CPU(obj);
829 cpu->dtb_compatible = "marvell,xscale";
830 set_feature(&cpu->env, ARM_FEATURE_V5);
831 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
832 cpu->midr = 0x69052d00;
833 cpu->ctr = 0xd172172;
834 cpu->reset_sctlr = 0x00000078;
837 static void pxa260_initfn(Object *obj)
839 ARMCPU *cpu = ARM_CPU(obj);
841 cpu->dtb_compatible = "marvell,xscale";
842 set_feature(&cpu->env, ARM_FEATURE_V5);
843 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
844 cpu->midr = 0x69052903;
845 cpu->ctr = 0xd172172;
846 cpu->reset_sctlr = 0x00000078;
849 static void pxa261_initfn(Object *obj)
851 ARMCPU *cpu = ARM_CPU(obj);
853 cpu->dtb_compatible = "marvell,xscale";
854 set_feature(&cpu->env, ARM_FEATURE_V5);
855 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
856 cpu->midr = 0x69052d05;
857 cpu->ctr = 0xd172172;
858 cpu->reset_sctlr = 0x00000078;
861 static void pxa262_initfn(Object *obj)
863 ARMCPU *cpu = ARM_CPU(obj);
865 cpu->dtb_compatible = "marvell,xscale";
866 set_feature(&cpu->env, ARM_FEATURE_V5);
867 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
868 cpu->midr = 0x69052d06;
869 cpu->ctr = 0xd172172;
870 cpu->reset_sctlr = 0x00000078;
873 static void pxa270a0_initfn(Object *obj)
875 ARMCPU *cpu = ARM_CPU(obj);
877 cpu->dtb_compatible = "marvell,xscale";
878 set_feature(&cpu->env, ARM_FEATURE_V5);
879 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
880 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
881 cpu->midr = 0x69054110;
882 cpu->ctr = 0xd172172;
883 cpu->reset_sctlr = 0x00000078;
886 static void pxa270a1_initfn(Object *obj)
888 ARMCPU *cpu = ARM_CPU(obj);
890 cpu->dtb_compatible = "marvell,xscale";
891 set_feature(&cpu->env, ARM_FEATURE_V5);
892 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
893 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
894 cpu->midr = 0x69054111;
895 cpu->ctr = 0xd172172;
896 cpu->reset_sctlr = 0x00000078;
899 static void pxa270b0_initfn(Object *obj)
901 ARMCPU *cpu = ARM_CPU(obj);
903 cpu->dtb_compatible = "marvell,xscale";
904 set_feature(&cpu->env, ARM_FEATURE_V5);
905 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
906 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
907 cpu->midr = 0x69054112;
908 cpu->ctr = 0xd172172;
909 cpu->reset_sctlr = 0x00000078;
912 static void pxa270b1_initfn(Object *obj)
914 ARMCPU *cpu = ARM_CPU(obj);
916 cpu->dtb_compatible = "marvell,xscale";
917 set_feature(&cpu->env, ARM_FEATURE_V5);
918 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
919 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
920 cpu->midr = 0x69054113;
921 cpu->ctr = 0xd172172;
922 cpu->reset_sctlr = 0x00000078;
925 static void pxa270c0_initfn(Object *obj)
927 ARMCPU *cpu = ARM_CPU(obj);
929 cpu->dtb_compatible = "marvell,xscale";
930 set_feature(&cpu->env, ARM_FEATURE_V5);
931 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
932 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
933 cpu->midr = 0x69054114;
934 cpu->ctr = 0xd172172;
935 cpu->reset_sctlr = 0x00000078;
938 static void pxa270c5_initfn(Object *obj)
940 ARMCPU *cpu = ARM_CPU(obj);
942 cpu->dtb_compatible = "marvell,xscale";
943 set_feature(&cpu->env, ARM_FEATURE_V5);
944 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
945 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
946 cpu->midr = 0x69054117;
947 cpu->ctr = 0xd172172;
948 cpu->reset_sctlr = 0x00000078;
951 #ifdef CONFIG_USER_ONLY
952 static void arm_any_initfn(Object *obj)
954 ARMCPU *cpu = ARM_CPU(obj);
955 set_feature(&cpu->env, ARM_FEATURE_V8);
956 set_feature(&cpu->env, ARM_FEATURE_VFP4);
957 set_feature(&cpu->env, ARM_FEATURE_NEON);
958 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
959 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
960 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
961 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
962 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
963 set_feature(&cpu->env, ARM_FEATURE_CRC);
964 cpu->midr = 0xffffffff;
966 #endif
968 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
970 typedef struct ARMCPUInfo {
971 const char *name;
972 void (*initfn)(Object *obj);
973 void (*class_init)(ObjectClass *oc, void *data);
974 } ARMCPUInfo;
976 static const ARMCPUInfo arm_cpus[] = {
977 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
978 { .name = "arm926", .initfn = arm926_initfn },
979 { .name = "arm946", .initfn = arm946_initfn },
980 { .name = "arm1026", .initfn = arm1026_initfn },
981 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
982 * older core than plain "arm1136". In particular this does not
983 * have the v6K features.
985 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
986 { .name = "arm1136", .initfn = arm1136_initfn },
987 { .name = "arm1176", .initfn = arm1176_initfn },
988 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
989 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
990 .class_init = arm_v7m_class_init },
991 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
992 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
993 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
994 { .name = "ti925t", .initfn = ti925t_initfn },
995 { .name = "sa1100", .initfn = sa1100_initfn },
996 { .name = "sa1110", .initfn = sa1110_initfn },
997 { .name = "pxa250", .initfn = pxa250_initfn },
998 { .name = "pxa255", .initfn = pxa255_initfn },
999 { .name = "pxa260", .initfn = pxa260_initfn },
1000 { .name = "pxa261", .initfn = pxa261_initfn },
1001 { .name = "pxa262", .initfn = pxa262_initfn },
1002 /* "pxa270" is an alias for "pxa270-a0" */
1003 { .name = "pxa270", .initfn = pxa270a0_initfn },
1004 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1005 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1006 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1007 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1008 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1009 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1010 #ifdef CONFIG_USER_ONLY
1011 { .name = "any", .initfn = arm_any_initfn },
1012 #endif
1013 #endif
1014 { .name = NULL }
1017 static Property arm_cpu_properties[] = {
1018 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1019 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1020 DEFINE_PROP_END_OF_LIST()
1023 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1025 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1026 CPUClass *cc = CPU_CLASS(acc);
1027 DeviceClass *dc = DEVICE_CLASS(oc);
1029 acc->parent_realize = dc->realize;
1030 dc->realize = arm_cpu_realizefn;
1031 dc->props = arm_cpu_properties;
1033 acc->parent_reset = cc->reset;
1034 cc->reset = arm_cpu_reset;
1036 cc->class_by_name = arm_cpu_class_by_name;
1037 cc->has_work = arm_cpu_has_work;
1038 cc->do_interrupt = arm_cpu_do_interrupt;
1039 cc->dump_state = arm_cpu_dump_state;
1040 cc->set_pc = arm_cpu_set_pc;
1041 cc->gdb_read_register = arm_cpu_gdb_read_register;
1042 cc->gdb_write_register = arm_cpu_gdb_write_register;
1043 #ifdef CONFIG_USER_ONLY
1044 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1045 #else
1046 cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1047 cc->vmsd = &vmstate_arm_cpu;
1048 #endif
1049 cc->gdb_num_core_regs = 26;
1050 cc->gdb_core_xml_file = "arm-core.xml";
1053 static void cpu_register(const ARMCPUInfo *info)
1055 TypeInfo type_info = {
1056 .parent = TYPE_ARM_CPU,
1057 .instance_size = sizeof(ARMCPU),
1058 .instance_init = info->initfn,
1059 .class_size = sizeof(ARMCPUClass),
1060 .class_init = info->class_init,
1063 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1064 type_register(&type_info);
1065 g_free((void *)type_info.name);
1068 static const TypeInfo arm_cpu_type_info = {
1069 .name = TYPE_ARM_CPU,
1070 .parent = TYPE_CPU,
1071 .instance_size = sizeof(ARMCPU),
1072 .instance_init = arm_cpu_initfn,
1073 .instance_post_init = arm_cpu_post_init,
1074 .instance_finalize = arm_cpu_finalizefn,
1075 .abstract = true,
1076 .class_size = sizeof(ARMCPUClass),
1077 .class_init = arm_cpu_class_init,
1080 static void arm_cpu_register_types(void)
1082 const ARMCPUInfo *info = arm_cpus;
1084 type_register_static(&arm_cpu_type_info);
1086 while (info->name) {
1087 cpu_register(info);
1088 info++;
1092 type_init(arm_cpu_register_types)