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virtio-serial: save/load: Ensure target has enough ports
[qemu/cris-port.git] / hw / ppc405_uc.c
blobd9bbd93789ca919d0acba8c009099e838536bc57
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31
32 #define DEBUG_OPBA
33 #define DEBUG_SDRAM
34 #define DEBUG_GPIO
35 #define DEBUG_SERIAL
36 #define DEBUG_OCM
37 //#define DEBUG_I2C
38 #define DEBUG_GPT
39 #define DEBUG_MAL
40 #define DEBUG_CLOCKS
41 //#define DEBUG_CLOCKS_LL
42
43 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
44 uint32_t flags)
45 {
46 ram_addr_t bdloc;
47 int i, n;
48
49 /* We put the bd structure at the top of memory */
50 if (bd->bi_memsize >= 0x01000000UL)
51 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
52 else
53 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
54 stl_phys(bdloc + 0x00, bd->bi_memstart);
55 stl_phys(bdloc + 0x04, bd->bi_memsize);
56 stl_phys(bdloc + 0x08, bd->bi_flashstart);
57 stl_phys(bdloc + 0x0C, bd->bi_flashsize);
58 stl_phys(bdloc + 0x10, bd->bi_flashoffset);
59 stl_phys(bdloc + 0x14, bd->bi_sramstart);
60 stl_phys(bdloc + 0x18, bd->bi_sramsize);
61 stl_phys(bdloc + 0x1C, bd->bi_bootflags);
62 stl_phys(bdloc + 0x20, bd->bi_ipaddr);
63 for (i = 0; i < 6; i++)
64 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
65 stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
66 stl_phys(bdloc + 0x2C, bd->bi_intfreq);
67 stl_phys(bdloc + 0x30, bd->bi_busfreq);
68 stl_phys(bdloc + 0x34, bd->bi_baudrate);
69 for (i = 0; i < 4; i++)
70 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
71 for (i = 0; i < 32; i++)
72 stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
73 stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
74 stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
75 for (i = 0; i < 6; i++)
76 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
77 n = 0x6A;
78 if (flags & 0x00000001) {
79 for (i = 0; i < 6; i++)
80 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
81 }
82 stl_phys(bdloc + n, bd->bi_opbfreq);
83 n += 4;
84 for (i = 0; i < 2; i++) {
85 stl_phys(bdloc + n, bd->bi_iic_fast[i]);
86 n += 4;
87 }
88
89 return bdloc;
90 }
91
92 /*****************************************************************************/
93 /* Shared peripherals */
94
95 /*****************************************************************************/
96 /* Peripheral local bus arbitrer */
97 enum {
98 PLB0_BESR = 0x084,
99 PLB0_BEAR = 0x086,
100 PLB0_ACR = 0x087,
101 };
102
103 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
104 struct ppc4xx_plb_t {
105 uint32_t acr;
106 uint32_t bear;
107 uint32_t besr;
108 };
109
110 static uint32_t dcr_read_plb (void *opaque, int dcrn)
111 {
112 ppc4xx_plb_t *plb;
113 uint32_t ret;
114
115 plb = opaque;
116 switch (dcrn) {
117 case PLB0_ACR:
118 ret = plb->acr;
119 break;
120 case PLB0_BEAR:
121 ret = plb->bear;
122 break;
123 case PLB0_BESR:
124 ret = plb->besr;
125 break;
126 default:
127 /* Avoid gcc warning */
128 ret = 0;
129 break;
130 }
131
132 return ret;
133 }
134
135 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
136 {
137 ppc4xx_plb_t *plb;
138
139 plb = opaque;
140 switch (dcrn) {
141 case PLB0_ACR:
142 /* We don't care about the actual parameters written as
143 * we don't manage any priorities on the bus
144 */
145 plb->acr = val & 0xF8000000;
146 break;
147 case PLB0_BEAR:
148 /* Read only */
149 break;
150 case PLB0_BESR:
151 /* Write-clear */
152 plb->besr &= ~val;
153 break;
154 }
155 }
156
157 static void ppc4xx_plb_reset (void *opaque)
158 {
159 ppc4xx_plb_t *plb;
160
161 plb = opaque;
162 plb->acr = 0x00000000;
163 plb->bear = 0x00000000;
164 plb->besr = 0x00000000;
165 }
166
167 static void ppc4xx_plb_init(CPUState *env)
168 {
169 ppc4xx_plb_t *plb;
170
171 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
172 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
173 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
174 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
175 qemu_register_reset(ppc4xx_plb_reset, plb);
176 }
177
178 /*****************************************************************************/
179 /* PLB to OPB bridge */
180 enum {
181 POB0_BESR0 = 0x0A0,
182 POB0_BESR1 = 0x0A2,
183 POB0_BEAR = 0x0A4,
184 };
185
186 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
187 struct ppc4xx_pob_t {
188 uint32_t bear;
189 uint32_t besr[2];
190 };
191
192 static uint32_t dcr_read_pob (void *opaque, int dcrn)
193 {
194 ppc4xx_pob_t *pob;
195 uint32_t ret;
196
197 pob = opaque;
198 switch (dcrn) {
199 case POB0_BEAR:
200 ret = pob->bear;
201 break;
202 case POB0_BESR0:
203 case POB0_BESR1:
204 ret = pob->besr[dcrn - POB0_BESR0];
205 break;
206 default:
207 /* Avoid gcc warning */
208 ret = 0;
209 break;
210 }
211
212 return ret;
213 }
214
215 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
216 {
217 ppc4xx_pob_t *pob;
218
219 pob = opaque;
220 switch (dcrn) {
221 case POB0_BEAR:
222 /* Read only */
223 break;
224 case POB0_BESR0:
225 case POB0_BESR1:
226 /* Write-clear */
227 pob->besr[dcrn - POB0_BESR0] &= ~val;
228 break;
229 }
230 }
231
232 static void ppc4xx_pob_reset (void *opaque)
233 {
234 ppc4xx_pob_t *pob;
235
236 pob = opaque;
237 /* No error */
238 pob->bear = 0x00000000;
239 pob->besr[0] = 0x0000000;
240 pob->besr[1] = 0x0000000;
241 }
242
243 static void ppc4xx_pob_init(CPUState *env)
244 {
245 ppc4xx_pob_t *pob;
246
247 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
248 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
249 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
250 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
251 qemu_register_reset(ppc4xx_pob_reset, pob);
252 }
253
254 /*****************************************************************************/
255 /* OPB arbitrer */
256 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
257 struct ppc4xx_opba_t {
258 uint8_t cr;
259 uint8_t pr;
260 };
261
262 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
263 {
264 ppc4xx_opba_t *opba;
265 uint32_t ret;
266
267 #ifdef DEBUG_OPBA
268 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
269 #endif
270 opba = opaque;
271 switch (addr) {
272 case 0x00:
273 ret = opba->cr;
274 break;
275 case 0x01:
276 ret = opba->pr;
277 break;
278 default:
279 ret = 0x00;
280 break;
281 }
282
283 return ret;
284 }
285
286 static void opba_writeb (void *opaque,
287 target_phys_addr_t addr, uint32_t value)
288 {
289 ppc4xx_opba_t *opba;
290
291 #ifdef DEBUG_OPBA
292 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
293 value);
294 #endif
295 opba = opaque;
296 switch (addr) {
297 case 0x00:
298 opba->cr = value & 0xF8;
299 break;
300 case 0x01:
301 opba->pr = value & 0xFF;
302 break;
303 default:
304 break;
305 }
306 }
307
308 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
309 {
310 uint32_t ret;
311
312 #ifdef DEBUG_OPBA
313 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
314 #endif
315 ret = opba_readb(opaque, addr) << 8;
316 ret |= opba_readb(opaque, addr + 1);
317
318 return ret;
319 }
320
321 static void opba_writew (void *opaque,
322 target_phys_addr_t addr, uint32_t value)
323 {
324 #ifdef DEBUG_OPBA
325 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
326 value);
327 #endif
328 opba_writeb(opaque, addr, value >> 8);
329 opba_writeb(opaque, addr + 1, value);
330 }
331
332 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
333 {
334 uint32_t ret;
335
336 #ifdef DEBUG_OPBA
337 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
338 #endif
339 ret = opba_readb(opaque, addr) << 24;
340 ret |= opba_readb(opaque, addr + 1) << 16;
341
342 return ret;
343 }
344
345 static void opba_writel (void *opaque,
346 target_phys_addr_t addr, uint32_t value)
347 {
348 #ifdef DEBUG_OPBA
349 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
350 value);
351 #endif
352 opba_writeb(opaque, addr, value >> 24);
353 opba_writeb(opaque, addr + 1, value >> 16);
354 }
355
356 static CPUReadMemoryFunc * const opba_read[] = {
357 &opba_readb,
358 &opba_readw,
359 &opba_readl,
360 };
361
362 static CPUWriteMemoryFunc * const opba_write[] = {
363 &opba_writeb,
364 &opba_writew,
365 &opba_writel,
366 };
367
368 static void ppc4xx_opba_reset (void *opaque)
369 {
370 ppc4xx_opba_t *opba;
371
372 opba = opaque;
373 opba->cr = 0x00; /* No dynamic priorities - park disabled */
374 opba->pr = 0x11;
375 }
376
377 static void ppc4xx_opba_init(target_phys_addr_t base)
378 {
379 ppc4xx_opba_t *opba;
380 int io;
381
382 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
383 #ifdef DEBUG_OPBA
384 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
385 #endif
386 io = cpu_register_io_memory(opba_read, opba_write, opba);
387 cpu_register_physical_memory(base, 0x002, io);
388 qemu_register_reset(ppc4xx_opba_reset, opba);
389 }
390
391 /*****************************************************************************/
392 /* Code decompression controller */
393 /* XXX: TODO */
394
395 /*****************************************************************************/
396 /* Peripheral controller */
397 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
398 struct ppc4xx_ebc_t {
399 uint32_t addr;
400 uint32_t bcr[8];
401 uint32_t bap[8];
402 uint32_t bear;
403 uint32_t besr0;
404 uint32_t besr1;
405 uint32_t cfg;
406 };
407
408 enum {
409 EBC0_CFGADDR = 0x012,
410 EBC0_CFGDATA = 0x013,
411 };
412
413 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
414 {
415 ppc4xx_ebc_t *ebc;
416 uint32_t ret;
417
418 ebc = opaque;
419 switch (dcrn) {
420 case EBC0_CFGADDR:
421 ret = ebc->addr;
422 break;
423 case EBC0_CFGDATA:
424 switch (ebc->addr) {
425 case 0x00: /* B0CR */
426 ret = ebc->bcr[0];
427 break;
428 case 0x01: /* B1CR */
429 ret = ebc->bcr[1];
430 break;
431 case 0x02: /* B2CR */
432 ret = ebc->bcr[2];
433 break;
434 case 0x03: /* B3CR */
435 ret = ebc->bcr[3];
436 break;
437 case 0x04: /* B4CR */
438 ret = ebc->bcr[4];
439 break;
440 case 0x05: /* B5CR */
441 ret = ebc->bcr[5];
442 break;
443 case 0x06: /* B6CR */
444 ret = ebc->bcr[6];
445 break;
446 case 0x07: /* B7CR */
447 ret = ebc->bcr[7];
448 break;
449 case 0x10: /* B0AP */
450 ret = ebc->bap[0];
451 break;
452 case 0x11: /* B1AP */
453 ret = ebc->bap[1];
454 break;
455 case 0x12: /* B2AP */
456 ret = ebc->bap[2];
457 break;
458 case 0x13: /* B3AP */
459 ret = ebc->bap[3];
460 break;
461 case 0x14: /* B4AP */
462 ret = ebc->bap[4];
463 break;
464 case 0x15: /* B5AP */
465 ret = ebc->bap[5];
466 break;
467 case 0x16: /* B6AP */
468 ret = ebc->bap[6];
469 break;
470 case 0x17: /* B7AP */
471 ret = ebc->bap[7];
472 break;
473 case 0x20: /* BEAR */
474 ret = ebc->bear;
475 break;
476 case 0x21: /* BESR0 */
477 ret = ebc->besr0;
478 break;
479 case 0x22: /* BESR1 */
480 ret = ebc->besr1;
481 break;
482 case 0x23: /* CFG */
483 ret = ebc->cfg;
484 break;
485 default:
486 ret = 0x00000000;
487 break;
488 }
489 break;
490 default:
491 ret = 0x00000000;
492 break;
493 }
494
495 return ret;
496 }
497
498 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
499 {
500 ppc4xx_ebc_t *ebc;
501
502 ebc = opaque;
503 switch (dcrn) {
504 case EBC0_CFGADDR:
505 ebc->addr = val;
506 break;
507 case EBC0_CFGDATA:
508 switch (ebc->addr) {
509 case 0x00: /* B0CR */
510 break;
511 case 0x01: /* B1CR */
512 break;
513 case 0x02: /* B2CR */
514 break;
515 case 0x03: /* B3CR */
516 break;
517 case 0x04: /* B4CR */
518 break;
519 case 0x05: /* B5CR */
520 break;
521 case 0x06: /* B6CR */
522 break;
523 case 0x07: /* B7CR */
524 break;
525 case 0x10: /* B0AP */
526 break;
527 case 0x11: /* B1AP */
528 break;
529 case 0x12: /* B2AP */
530 break;
531 case 0x13: /* B3AP */
532 break;
533 case 0x14: /* B4AP */
534 break;
535 case 0x15: /* B5AP */
536 break;
537 case 0x16: /* B6AP */
538 break;
539 case 0x17: /* B7AP */
540 break;
541 case 0x20: /* BEAR */
542 break;
543 case 0x21: /* BESR0 */
544 break;
545 case 0x22: /* BESR1 */
546 break;
547 case 0x23: /* CFG */
548 break;
549 default:
550 break;
551 }
552 break;
553 default:
554 break;
555 }
556 }
557
558 static void ebc_reset (void *opaque)
559 {
560 ppc4xx_ebc_t *ebc;
561 int i;
562
563 ebc = opaque;
564 ebc->addr = 0x00000000;
565 ebc->bap[0] = 0x7F8FFE80;
566 ebc->bcr[0] = 0xFFE28000;
567 for (i = 0; i < 8; i++) {
568 ebc->bap[i] = 0x00000000;
569 ebc->bcr[i] = 0x00000000;
570 }
571 ebc->besr0 = 0x00000000;
572 ebc->besr1 = 0x00000000;
573 ebc->cfg = 0x80400000;
574 }
575
576 static void ppc405_ebc_init(CPUState *env)
577 {
578 ppc4xx_ebc_t *ebc;
579
580 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
581 qemu_register_reset(&ebc_reset, ebc);
582 ppc_dcr_register(env, EBC0_CFGADDR,
583 ebc, &dcr_read_ebc, &dcr_write_ebc);
584 ppc_dcr_register(env, EBC0_CFGDATA,
585 ebc, &dcr_read_ebc, &dcr_write_ebc);
586 }
587
588 /*****************************************************************************/
589 /* DMA controller */
590 enum {
591 DMA0_CR0 = 0x100,
592 DMA0_CT0 = 0x101,
593 DMA0_DA0 = 0x102,
594 DMA0_SA0 = 0x103,
595 DMA0_SG0 = 0x104,
596 DMA0_CR1 = 0x108,
597 DMA0_CT1 = 0x109,
598 DMA0_DA1 = 0x10A,
599 DMA0_SA1 = 0x10B,
600 DMA0_SG1 = 0x10C,
601 DMA0_CR2 = 0x110,
602 DMA0_CT2 = 0x111,
603 DMA0_DA2 = 0x112,
604 DMA0_SA2 = 0x113,
605 DMA0_SG2 = 0x114,
606 DMA0_CR3 = 0x118,
607 DMA0_CT3 = 0x119,
608 DMA0_DA3 = 0x11A,
609 DMA0_SA3 = 0x11B,
610 DMA0_SG3 = 0x11C,
611 DMA0_SR = 0x120,
612 DMA0_SGC = 0x123,
613 DMA0_SLP = 0x125,
614 DMA0_POL = 0x126,
615 };
616
617 typedef struct ppc405_dma_t ppc405_dma_t;
618 struct ppc405_dma_t {
619 qemu_irq irqs[4];
620 uint32_t cr[4];
621 uint32_t ct[4];
622 uint32_t da[4];
623 uint32_t sa[4];
624 uint32_t sg[4];
625 uint32_t sr;
626 uint32_t sgc;
627 uint32_t slp;
628 uint32_t pol;
629 };
630
631 static uint32_t dcr_read_dma (void *opaque, int dcrn)
632 {
633 ppc405_dma_t *dma;
634
635 dma = opaque;
636
637 return 0;
638 }
639
640 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
641 {
642 ppc405_dma_t *dma;
643
644 dma = opaque;
645 }
646
647 static void ppc405_dma_reset (void *opaque)
648 {
649 ppc405_dma_t *dma;
650 int i;
651
652 dma = opaque;
653 for (i = 0; i < 4; i++) {
654 dma->cr[i] = 0x00000000;
655 dma->ct[i] = 0x00000000;
656 dma->da[i] = 0x00000000;
657 dma->sa[i] = 0x00000000;
658 dma->sg[i] = 0x00000000;
659 }
660 dma->sr = 0x00000000;
661 dma->sgc = 0x00000000;
662 dma->slp = 0x7C000000;
663 dma->pol = 0x00000000;
664 }
665
666 static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
667 {
668 ppc405_dma_t *dma;
669
670 dma = qemu_mallocz(sizeof(ppc405_dma_t));
671 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
672 qemu_register_reset(&ppc405_dma_reset, dma);
673 ppc_dcr_register(env, DMA0_CR0,
674 dma, &dcr_read_dma, &dcr_write_dma);
675 ppc_dcr_register(env, DMA0_CT0,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_DA0,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_SA0,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_SG0,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_CR1,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_CT1,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_DA1,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_SA1,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_SG1,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_CR2,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_CT2,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_DA2,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_SA2,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_SG2,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_CR3,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_CT3,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_DA3,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_SA3,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SG3,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_SR,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 ppc_dcr_register(env, DMA0_SGC,
716 dma, &dcr_read_dma, &dcr_write_dma);
717 ppc_dcr_register(env, DMA0_SLP,
718 dma, &dcr_read_dma, &dcr_write_dma);
719 ppc_dcr_register(env, DMA0_POL,
720 dma, &dcr_read_dma, &dcr_write_dma);
721 }
722
723 /*****************************************************************************/
724 /* GPIO */
725 typedef struct ppc405_gpio_t ppc405_gpio_t;
726 struct ppc405_gpio_t {
727 uint32_t or;
728 uint32_t tcr;
729 uint32_t osrh;
730 uint32_t osrl;
731 uint32_t tsrh;
732 uint32_t tsrl;
733 uint32_t odr;
734 uint32_t ir;
735 uint32_t rr1;
736 uint32_t isr1h;
737 uint32_t isr1l;
738 };
739
740 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
741 {
742 ppc405_gpio_t *gpio;
743
744 gpio = opaque;
745 #ifdef DEBUG_GPIO
746 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
747 #endif
748
749 return 0;
750 }
751
752 static void ppc405_gpio_writeb (void *opaque,
753 target_phys_addr_t addr, uint32_t value)
754 {
755 ppc405_gpio_t *gpio;
756
757 gpio = opaque;
758 #ifdef DEBUG_GPIO
759 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
760 value);
761 #endif
762 }
763
764 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
765 {
766 ppc405_gpio_t *gpio;
767
768 gpio = opaque;
769 #ifdef DEBUG_GPIO
770 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
771 #endif
772
773 return 0;
774 }
775
776 static void ppc405_gpio_writew (void *opaque,
777 target_phys_addr_t addr, uint32_t value)
778 {
779 ppc405_gpio_t *gpio;
780
781 gpio = opaque;
782 #ifdef DEBUG_GPIO
783 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
784 value);
785 #endif
786 }
787
788 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
789 {
790 ppc405_gpio_t *gpio;
791
792 gpio = opaque;
793 #ifdef DEBUG_GPIO
794 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
795 #endif
796
797 return 0;
798 }
799
800 static void ppc405_gpio_writel (void *opaque,
801 target_phys_addr_t addr, uint32_t value)
802 {
803 ppc405_gpio_t *gpio;
804
805 gpio = opaque;
806 #ifdef DEBUG_GPIO
807 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
808 value);
809 #endif
810 }
811
812 static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
813 &ppc405_gpio_readb,
814 &ppc405_gpio_readw,
815 &ppc405_gpio_readl,
816 };
817
818 static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
819 &ppc405_gpio_writeb,
820 &ppc405_gpio_writew,
821 &ppc405_gpio_writel,
822 };
823
824 static void ppc405_gpio_reset (void *opaque)
825 {
826 ppc405_gpio_t *gpio;
827
828 gpio = opaque;
829 }
830
831 static void ppc405_gpio_init(target_phys_addr_t base)
832 {
833 ppc405_gpio_t *gpio;
834 int io;
835
836 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
837 #ifdef DEBUG_GPIO
838 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
839 #endif
840 io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
841 cpu_register_physical_memory(base, 0x038, io);
842 qemu_register_reset(&ppc405_gpio_reset, gpio);
843 }
844
845 /*****************************************************************************/
846 /* On Chip Memory */
847 enum {
848 OCM0_ISARC = 0x018,
849 OCM0_ISACNTL = 0x019,
850 OCM0_DSARC = 0x01A,
851 OCM0_DSACNTL = 0x01B,
852 };
853
854 typedef struct ppc405_ocm_t ppc405_ocm_t;
855 struct ppc405_ocm_t {
856 target_ulong offset;
857 uint32_t isarc;
858 uint32_t isacntl;
859 uint32_t dsarc;
860 uint32_t dsacntl;
861 };
862
863 static void ocm_update_mappings (ppc405_ocm_t *ocm,
864 uint32_t isarc, uint32_t isacntl,
865 uint32_t dsarc, uint32_t dsacntl)
866 {
867 #ifdef DEBUG_OCM
868 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
869 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
870 " (%08" PRIx32 " %08" PRIx32 ")\n",
871 isarc, isacntl, dsarc, dsacntl,
872 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
873 #endif
874 if (ocm->isarc != isarc ||
875 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
876 if (ocm->isacntl & 0x80000000) {
877 /* Unmap previously assigned memory region */
878 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
879 cpu_register_physical_memory(ocm->isarc, 0x04000000,
880 IO_MEM_UNASSIGNED);
881 }
882 if (isacntl & 0x80000000) {
883 /* Map new instruction memory region */
884 #ifdef DEBUG_OCM
885 printf("OCM map ISA %08" PRIx32 "\n", isarc);
886 #endif
887 cpu_register_physical_memory(isarc, 0x04000000,
888 ocm->offset | IO_MEM_RAM);
889 }
890 }
891 if (ocm->dsarc != dsarc ||
892 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
893 if (ocm->dsacntl & 0x80000000) {
894 /* Beware not to unmap the region we just mapped */
895 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
896 /* Unmap previously assigned memory region */
897 #ifdef DEBUG_OCM
898 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
899 #endif
900 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
901 IO_MEM_UNASSIGNED);
902 }
903 }
904 if (dsacntl & 0x80000000) {
905 /* Beware not to remap the region we just mapped */
906 if (!(isacntl & 0x80000000) || dsarc != isarc) {
907 /* Map new data memory region */
908 #ifdef DEBUG_OCM
909 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
910 #endif
911 cpu_register_physical_memory(dsarc, 0x04000000,
912 ocm->offset | IO_MEM_RAM);
913 }
914 }
915 }
916 }
917
918 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
919 {
920 ppc405_ocm_t *ocm;
921 uint32_t ret;
922
923 ocm = opaque;
924 switch (dcrn) {
925 case OCM0_ISARC:
926 ret = ocm->isarc;
927 break;
928 case OCM0_ISACNTL:
929 ret = ocm->isacntl;
930 break;
931 case OCM0_DSARC:
932 ret = ocm->dsarc;
933 break;
934 case OCM0_DSACNTL:
935 ret = ocm->dsacntl;
936 break;
937 default:
938 ret = 0;
939 break;
940 }
941
942 return ret;
943 }
944
945 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
946 {
947 ppc405_ocm_t *ocm;
948 uint32_t isarc, dsarc, isacntl, dsacntl;
949
950 ocm = opaque;
951 isarc = ocm->isarc;
952 dsarc = ocm->dsarc;
953 isacntl = ocm->isacntl;
954 dsacntl = ocm->dsacntl;
955 switch (dcrn) {
956 case OCM0_ISARC:
957 isarc = val & 0xFC000000;
958 break;
959 case OCM0_ISACNTL:
960 isacntl = val & 0xC0000000;
961 break;
962 case OCM0_DSARC:
963 isarc = val & 0xFC000000;
964 break;
965 case OCM0_DSACNTL:
966 isacntl = val & 0xC0000000;
967 break;
968 }
969 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
970 ocm->isarc = isarc;
971 ocm->dsarc = dsarc;
972 ocm->isacntl = isacntl;
973 ocm->dsacntl = dsacntl;
974 }
975
976 static void ocm_reset (void *opaque)
977 {
978 ppc405_ocm_t *ocm;
979 uint32_t isarc, dsarc, isacntl, dsacntl;
980
981 ocm = opaque;
982 isarc = 0x00000000;
983 isacntl = 0x00000000;
984 dsarc = 0x00000000;
985 dsacntl = 0x00000000;
986 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
987 ocm->isarc = isarc;
988 ocm->dsarc = dsarc;
989 ocm->isacntl = isacntl;
990 ocm->dsacntl = dsacntl;
991 }
992
993 static void ppc405_ocm_init(CPUState *env)
994 {
995 ppc405_ocm_t *ocm;
996
997 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
998 ocm->offset = qemu_ram_alloc(4096);
999 qemu_register_reset(&ocm_reset, ocm);
1000 ppc_dcr_register(env, OCM0_ISARC,
1001 ocm, &dcr_read_ocm, &dcr_write_ocm);
1002 ppc_dcr_register(env, OCM0_ISACNTL,
1003 ocm, &dcr_read_ocm, &dcr_write_ocm);
1004 ppc_dcr_register(env, OCM0_DSARC,
1005 ocm, &dcr_read_ocm, &dcr_write_ocm);
1006 ppc_dcr_register(env, OCM0_DSACNTL,
1007 ocm, &dcr_read_ocm, &dcr_write_ocm);
1008 }
1009
1010 /*****************************************************************************/
1011 /* I2C controller */
1012 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
1013 struct ppc4xx_i2c_t {
1014 qemu_irq irq;
1015 uint8_t mdata;
1016 uint8_t lmadr;
1017 uint8_t hmadr;
1018 uint8_t cntl;
1019 uint8_t mdcntl;
1020 uint8_t sts;
1021 uint8_t extsts;
1022 uint8_t sdata;
1023 uint8_t lsadr;
1024 uint8_t hsadr;
1025 uint8_t clkdiv;
1026 uint8_t intrmsk;
1027 uint8_t xfrcnt;
1028 uint8_t xtcntlss;
1029 uint8_t directcntl;
1030 };
1031
1032 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1033 {
1034 ppc4xx_i2c_t *i2c;
1035 uint32_t ret;
1036
1037 #ifdef DEBUG_I2C
1038 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1039 #endif
1040 i2c = opaque;
1041 switch (addr) {
1042 case 0x00:
1043 // i2c_readbyte(&i2c->mdata);
1044 ret = i2c->mdata;
1045 break;
1046 case 0x02:
1047 ret = i2c->sdata;
1048 break;
1049 case 0x04:
1050 ret = i2c->lmadr;
1051 break;
1052 case 0x05:
1053 ret = i2c->hmadr;
1054 break;
1055 case 0x06:
1056 ret = i2c->cntl;
1057 break;
1058 case 0x07:
1059 ret = i2c->mdcntl;
1060 break;
1061 case 0x08:
1062 ret = i2c->sts;
1063 break;
1064 case 0x09:
1065 ret = i2c->extsts;
1066 break;
1067 case 0x0A:
1068 ret = i2c->lsadr;
1069 break;
1070 case 0x0B:
1071 ret = i2c->hsadr;
1072 break;
1073 case 0x0C:
1074 ret = i2c->clkdiv;
1075 break;
1076 case 0x0D:
1077 ret = i2c->intrmsk;
1078 break;
1079 case 0x0E:
1080 ret = i2c->xfrcnt;
1081 break;
1082 case 0x0F:
1083 ret = i2c->xtcntlss;
1084 break;
1085 case 0x10:
1086 ret = i2c->directcntl;
1087 break;
1088 default:
1089 ret = 0x00;
1090 break;
1091 }
1092 #ifdef DEBUG_I2C
1093 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1094 #endif
1095
1096 return ret;
1097 }
1098
1099 static void ppc4xx_i2c_writeb (void *opaque,
1100 target_phys_addr_t addr, uint32_t value)
1101 {
1102 ppc4xx_i2c_t *i2c;
1103
1104 #ifdef DEBUG_I2C
1105 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1106 value);
1107 #endif
1108 i2c = opaque;
1109 switch (addr) {
1110 case 0x00:
1111 i2c->mdata = value;
1112 // i2c_sendbyte(&i2c->mdata);
1113 break;
1114 case 0x02:
1115 i2c->sdata = value;
1116 break;
1117 case 0x04:
1118 i2c->lmadr = value;
1119 break;
1120 case 0x05:
1121 i2c->hmadr = value;
1122 break;
1123 case 0x06:
1124 i2c->cntl = value;
1125 break;
1126 case 0x07:
1127 i2c->mdcntl = value & 0xDF;
1128 break;
1129 case 0x08:
1130 i2c->sts &= ~(value & 0x0A);
1131 break;
1132 case 0x09:
1133 i2c->extsts &= ~(value & 0x8F);
1134 break;
1135 case 0x0A:
1136 i2c->lsadr = value;
1137 break;
1138 case 0x0B:
1139 i2c->hsadr = value;
1140 break;
1141 case 0x0C:
1142 i2c->clkdiv = value;
1143 break;
1144 case 0x0D:
1145 i2c->intrmsk = value;
1146 break;
1147 case 0x0E:
1148 i2c->xfrcnt = value & 0x77;
1149 break;
1150 case 0x0F:
1151 i2c->xtcntlss = value;
1152 break;
1153 case 0x10:
1154 i2c->directcntl = value & 0x7;
1155 break;
1156 }
1157 }
1158
1159 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1160 {
1161 uint32_t ret;
1162
1163 #ifdef DEBUG_I2C
1164 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1165 #endif
1166 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1167 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1168
1169 return ret;
1170 }
1171
1172 static void ppc4xx_i2c_writew (void *opaque,
1173 target_phys_addr_t addr, uint32_t value)
1174 {
1175 #ifdef DEBUG_I2C
1176 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1177 value);
1178 #endif
1179 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1180 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1181 }
1182
1183 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1184 {
1185 uint32_t ret;
1186
1187 #ifdef DEBUG_I2C
1188 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1189 #endif
1190 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1191 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1192 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1193 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1194
1195 return ret;
1196 }
1197
1198 static void ppc4xx_i2c_writel (void *opaque,
1199 target_phys_addr_t addr, uint32_t value)
1200 {
1201 #ifdef DEBUG_I2C
1202 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1203 value);
1204 #endif
1205 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1206 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1207 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1208 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1209 }
1210
1211 static CPUReadMemoryFunc * const i2c_read[] = {
1212 &ppc4xx_i2c_readb,
1213 &ppc4xx_i2c_readw,
1214 &ppc4xx_i2c_readl,
1215 };
1216
1217 static CPUWriteMemoryFunc * const i2c_write[] = {
1218 &ppc4xx_i2c_writeb,
1219 &ppc4xx_i2c_writew,
1220 &ppc4xx_i2c_writel,
1221 };
1222
1223 static void ppc4xx_i2c_reset (void *opaque)
1224 {
1225 ppc4xx_i2c_t *i2c;
1226
1227 i2c = opaque;
1228 i2c->mdata = 0x00;
1229 i2c->sdata = 0x00;
1230 i2c->cntl = 0x00;
1231 i2c->mdcntl = 0x00;
1232 i2c->sts = 0x00;
1233 i2c->extsts = 0x00;
1234 i2c->clkdiv = 0x00;
1235 i2c->xfrcnt = 0x00;
1236 i2c->directcntl = 0x0F;
1237 }
1238
1239 static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
1240 {
1241 ppc4xx_i2c_t *i2c;
1242 int io;
1243
1244 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
1245 i2c->irq = irq;
1246 #ifdef DEBUG_I2C
1247 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1248 #endif
1249 io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
1250 cpu_register_physical_memory(base, 0x011, io);
1251 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1252 }
1253
1254 /*****************************************************************************/
1255 /* General purpose timers */
1256 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1257 struct ppc4xx_gpt_t {
1258 int64_t tb_offset;
1259 uint32_t tb_freq;
1260 struct QEMUTimer *timer;
1261 qemu_irq irqs[5];
1262 uint32_t oe;
1263 uint32_t ol;
1264 uint32_t im;
1265 uint32_t is;
1266 uint32_t ie;
1267 uint32_t comp[5];
1268 uint32_t mask[5];
1269 };
1270
1271 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1272 {
1273 #ifdef DEBUG_GPT
1274 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1275 #endif
1276 /* XXX: generate a bus fault */
1277 return -1;
1278 }
1279
1280 static void ppc4xx_gpt_writeb (void *opaque,
1281 target_phys_addr_t addr, uint32_t value)
1282 {
1283 #ifdef DEBUG_I2C
1284 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1285 value);
1286 #endif
1287 /* XXX: generate a bus fault */
1288 }
1289
1290 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1291 {
1292 #ifdef DEBUG_GPT
1293 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1294 #endif
1295 /* XXX: generate a bus fault */
1296 return -1;
1297 }
1298
1299 static void ppc4xx_gpt_writew (void *opaque,
1300 target_phys_addr_t addr, uint32_t value)
1301 {
1302 #ifdef DEBUG_I2C
1303 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1304 value);
1305 #endif
1306 /* XXX: generate a bus fault */
1307 }
1308
1309 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1310 {
1311 /* XXX: TODO */
1312 return 0;
1313 }
1314
1315 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1316 {
1317 /* XXX: TODO */
1318 }
1319
1320 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1321 {
1322 uint32_t mask;
1323 int i;
1324
1325 mask = 0x80000000;
1326 for (i = 0; i < 5; i++) {
1327 if (gpt->oe & mask) {
1328 /* Output is enabled */
1329 if (ppc4xx_gpt_compare(gpt, i)) {
1330 /* Comparison is OK */
1331 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1332 } else {
1333 /* Comparison is KO */
1334 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1335 }
1336 }
1337 mask = mask >> 1;
1338 }
1339 }
1340
1341 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1342 {
1343 uint32_t mask;
1344 int i;
1345
1346 mask = 0x00008000;
1347 for (i = 0; i < 5; i++) {
1348 if (gpt->is & gpt->im & mask)
1349 qemu_irq_raise(gpt->irqs[i]);
1350 else
1351 qemu_irq_lower(gpt->irqs[i]);
1352 mask = mask >> 1;
1353 }
1354 }
1355
1356 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1357 {
1358 /* XXX: TODO */
1359 }
1360
1361 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1362 {
1363 ppc4xx_gpt_t *gpt;
1364 uint32_t ret;
1365 int idx;
1366
1367 #ifdef DEBUG_GPT
1368 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1369 #endif
1370 gpt = opaque;
1371 switch (addr) {
1372 case 0x00:
1373 /* Time base counter */
1374 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
1375 gpt->tb_freq, get_ticks_per_sec());
1376 break;
1377 case 0x10:
1378 /* Output enable */
1379 ret = gpt->oe;
1380 break;
1381 case 0x14:
1382 /* Output level */
1383 ret = gpt->ol;
1384 break;
1385 case 0x18:
1386 /* Interrupt mask */
1387 ret = gpt->im;
1388 break;
1389 case 0x1C:
1390 case 0x20:
1391 /* Interrupt status */
1392 ret = gpt->is;
1393 break;
1394 case 0x24:
1395 /* Interrupt enable */
1396 ret = gpt->ie;
1397 break;
1398 case 0x80 ... 0x90:
1399 /* Compare timer */
1400 idx = (addr - 0x80) >> 2;
1401 ret = gpt->comp[idx];
1402 break;
1403 case 0xC0 ... 0xD0:
1404 /* Compare mask */
1405 idx = (addr - 0xC0) >> 2;
1406 ret = gpt->mask[idx];
1407 break;
1408 default:
1409 ret = -1;
1410 break;
1411 }
1412
1413 return ret;
1414 }
1415
1416 static void ppc4xx_gpt_writel (void *opaque,
1417 target_phys_addr_t addr, uint32_t value)
1418 {
1419 ppc4xx_gpt_t *gpt;
1420 int idx;
1421
1422 #ifdef DEBUG_I2C
1423 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1424 value);
1425 #endif
1426 gpt = opaque;
1427 switch (addr) {
1428 case 0x00:
1429 /* Time base counter */
1430 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1431 - qemu_get_clock(vm_clock);
1432 ppc4xx_gpt_compute_timer(gpt);
1433 break;
1434 case 0x10:
1435 /* Output enable */
1436 gpt->oe = value & 0xF8000000;
1437 ppc4xx_gpt_set_outputs(gpt);
1438 break;
1439 case 0x14:
1440 /* Output level */
1441 gpt->ol = value & 0xF8000000;
1442 ppc4xx_gpt_set_outputs(gpt);
1443 break;
1444 case 0x18:
1445 /* Interrupt mask */
1446 gpt->im = value & 0x0000F800;
1447 break;
1448 case 0x1C:
1449 /* Interrupt status set */
1450 gpt->is |= value & 0x0000F800;
1451 ppc4xx_gpt_set_irqs(gpt);
1452 break;
1453 case 0x20:
1454 /* Interrupt status clear */
1455 gpt->is &= ~(value & 0x0000F800);
1456 ppc4xx_gpt_set_irqs(gpt);
1457 break;
1458 case 0x24:
1459 /* Interrupt enable */
1460 gpt->ie = value & 0x0000F800;
1461 ppc4xx_gpt_set_irqs(gpt);
1462 break;
1463 case 0x80 ... 0x90:
1464 /* Compare timer */
1465 idx = (addr - 0x80) >> 2;
1466 gpt->comp[idx] = value & 0xF8000000;
1467 ppc4xx_gpt_compute_timer(gpt);
1468 break;
1469 case 0xC0 ... 0xD0:
1470 /* Compare mask */
1471 idx = (addr - 0xC0) >> 2;
1472 gpt->mask[idx] = value & 0xF8000000;
1473 ppc4xx_gpt_compute_timer(gpt);
1474 break;
1475 }
1476 }
1477
1478 static CPUReadMemoryFunc * const gpt_read[] = {
1479 &ppc4xx_gpt_readb,
1480 &ppc4xx_gpt_readw,
1481 &ppc4xx_gpt_readl,
1482 };
1483
1484 static CPUWriteMemoryFunc * const gpt_write[] = {
1485 &ppc4xx_gpt_writeb,
1486 &ppc4xx_gpt_writew,
1487 &ppc4xx_gpt_writel,
1488 };
1489
1490 static void ppc4xx_gpt_cb (void *opaque)
1491 {
1492 ppc4xx_gpt_t *gpt;
1493
1494 gpt = opaque;
1495 ppc4xx_gpt_set_irqs(gpt);
1496 ppc4xx_gpt_set_outputs(gpt);
1497 ppc4xx_gpt_compute_timer(gpt);
1498 }
1499
1500 static void ppc4xx_gpt_reset (void *opaque)
1501 {
1502 ppc4xx_gpt_t *gpt;
1503 int i;
1504
1505 gpt = opaque;
1506 qemu_del_timer(gpt->timer);
1507 gpt->oe = 0x00000000;
1508 gpt->ol = 0x00000000;
1509 gpt->im = 0x00000000;
1510 gpt->is = 0x00000000;
1511 gpt->ie = 0x00000000;
1512 for (i = 0; i < 5; i++) {
1513 gpt->comp[i] = 0x00000000;
1514 gpt->mask[i] = 0x00000000;
1515 }
1516 }
1517
1518 static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
1519 {
1520 ppc4xx_gpt_t *gpt;
1521 int i;
1522 int io;
1523
1524 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
1525 for (i = 0; i < 5; i++) {
1526 gpt->irqs[i] = irqs[i];
1527 }
1528 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
1529 #ifdef DEBUG_GPT
1530 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1531 #endif
1532 io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
1533 cpu_register_physical_memory(base, 0x0d4, io);
1534 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1535 }
1536
1537 /*****************************************************************************/
1538 /* MAL */
1539 enum {
1540 MAL0_CFG = 0x180,
1541 MAL0_ESR = 0x181,
1542 MAL0_IER = 0x182,
1543 MAL0_TXCASR = 0x184,
1544 MAL0_TXCARR = 0x185,
1545 MAL0_TXEOBISR = 0x186,
1546 MAL0_TXDEIR = 0x187,
1547 MAL0_RXCASR = 0x190,
1548 MAL0_RXCARR = 0x191,
1549 MAL0_RXEOBISR = 0x192,
1550 MAL0_RXDEIR = 0x193,
1551 MAL0_TXCTP0R = 0x1A0,
1552 MAL0_TXCTP1R = 0x1A1,
1553 MAL0_TXCTP2R = 0x1A2,
1554 MAL0_TXCTP3R = 0x1A3,
1555 MAL0_RXCTP0R = 0x1C0,
1556 MAL0_RXCTP1R = 0x1C1,
1557 MAL0_RCBS0 = 0x1E0,
1558 MAL0_RCBS1 = 0x1E1,
1559 };
1560
1561 typedef struct ppc40x_mal_t ppc40x_mal_t;
1562 struct ppc40x_mal_t {
1563 qemu_irq irqs[4];
1564 uint32_t cfg;
1565 uint32_t esr;
1566 uint32_t ier;
1567 uint32_t txcasr;
1568 uint32_t txcarr;
1569 uint32_t txeobisr;
1570 uint32_t txdeir;
1571 uint32_t rxcasr;
1572 uint32_t rxcarr;
1573 uint32_t rxeobisr;
1574 uint32_t rxdeir;
1575 uint32_t txctpr[4];
1576 uint32_t rxctpr[2];
1577 uint32_t rcbs[2];
1578 };
1579
1580 static void ppc40x_mal_reset (void *opaque);
1581
1582 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1583 {
1584 ppc40x_mal_t *mal;
1585 uint32_t ret;
1586
1587 mal = opaque;
1588 switch (dcrn) {
1589 case MAL0_CFG:
1590 ret = mal->cfg;
1591 break;
1592 case MAL0_ESR:
1593 ret = mal->esr;
1594 break;
1595 case MAL0_IER:
1596 ret = mal->ier;
1597 break;
1598 case MAL0_TXCASR:
1599 ret = mal->txcasr;
1600 break;
1601 case MAL0_TXCARR:
1602 ret = mal->txcarr;
1603 break;
1604 case MAL0_TXEOBISR:
1605 ret = mal->txeobisr;
1606 break;
1607 case MAL0_TXDEIR:
1608 ret = mal->txdeir;
1609 break;
1610 case MAL0_RXCASR:
1611 ret = mal->rxcasr;
1612 break;
1613 case MAL0_RXCARR:
1614 ret = mal->rxcarr;
1615 break;
1616 case MAL0_RXEOBISR:
1617 ret = mal->rxeobisr;
1618 break;
1619 case MAL0_RXDEIR:
1620 ret = mal->rxdeir;
1621 break;
1622 case MAL0_TXCTP0R:
1623 ret = mal->txctpr[0];
1624 break;
1625 case MAL0_TXCTP1R:
1626 ret = mal->txctpr[1];
1627 break;
1628 case MAL0_TXCTP2R:
1629 ret = mal->txctpr[2];
1630 break;
1631 case MAL0_TXCTP3R:
1632 ret = mal->txctpr[3];
1633 break;
1634 case MAL0_RXCTP0R:
1635 ret = mal->rxctpr[0];
1636 break;
1637 case MAL0_RXCTP1R:
1638 ret = mal->rxctpr[1];
1639 break;
1640 case MAL0_RCBS0:
1641 ret = mal->rcbs[0];
1642 break;
1643 case MAL0_RCBS1:
1644 ret = mal->rcbs[1];
1645 break;
1646 default:
1647 ret = 0;
1648 break;
1649 }
1650
1651 return ret;
1652 }
1653
1654 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1655 {
1656 ppc40x_mal_t *mal;
1657 int idx;
1658
1659 mal = opaque;
1660 switch (dcrn) {
1661 case MAL0_CFG:
1662 if (val & 0x80000000)
1663 ppc40x_mal_reset(mal);
1664 mal->cfg = val & 0x00FFC087;
1665 break;
1666 case MAL0_ESR:
1667 /* Read/clear */
1668 mal->esr &= ~val;
1669 break;
1670 case MAL0_IER:
1671 mal->ier = val & 0x0000001F;
1672 break;
1673 case MAL0_TXCASR:
1674 mal->txcasr = val & 0xF0000000;
1675 break;
1676 case MAL0_TXCARR:
1677 mal->txcarr = val & 0xF0000000;
1678 break;
1679 case MAL0_TXEOBISR:
1680 /* Read/clear */
1681 mal->txeobisr &= ~val;
1682 break;
1683 case MAL0_TXDEIR:
1684 /* Read/clear */
1685 mal->txdeir &= ~val;
1686 break;
1687 case MAL0_RXCASR:
1688 mal->rxcasr = val & 0xC0000000;
1689 break;
1690 case MAL0_RXCARR:
1691 mal->rxcarr = val & 0xC0000000;
1692 break;
1693 case MAL0_RXEOBISR:
1694 /* Read/clear */
1695 mal->rxeobisr &= ~val;
1696 break;
1697 case MAL0_RXDEIR:
1698 /* Read/clear */
1699 mal->rxdeir &= ~val;
1700 break;
1701 case MAL0_TXCTP0R:
1702 idx = 0;
1703 goto update_tx_ptr;
1704 case MAL0_TXCTP1R:
1705 idx = 1;
1706 goto update_tx_ptr;
1707 case MAL0_TXCTP2R:
1708 idx = 2;
1709 goto update_tx_ptr;
1710 case MAL0_TXCTP3R:
1711 idx = 3;
1712 update_tx_ptr:
1713 mal->txctpr[idx] = val;
1714 break;
1715 case MAL0_RXCTP0R:
1716 idx = 0;
1717 goto update_rx_ptr;
1718 case MAL0_RXCTP1R:
1719 idx = 1;
1720 update_rx_ptr:
1721 mal->rxctpr[idx] = val;
1722 break;
1723 case MAL0_RCBS0:
1724 idx = 0;
1725 goto update_rx_size;
1726 case MAL0_RCBS1:
1727 idx = 1;
1728 update_rx_size:
1729 mal->rcbs[idx] = val & 0x000000FF;
1730 break;
1731 }
1732 }
1733
1734 static void ppc40x_mal_reset (void *opaque)
1735 {
1736 ppc40x_mal_t *mal;
1737
1738 mal = opaque;
1739 mal->cfg = 0x0007C000;
1740 mal->esr = 0x00000000;
1741 mal->ier = 0x00000000;
1742 mal->rxcasr = 0x00000000;
1743 mal->rxdeir = 0x00000000;
1744 mal->rxeobisr = 0x00000000;
1745 mal->txcasr = 0x00000000;
1746 mal->txdeir = 0x00000000;
1747 mal->txeobisr = 0x00000000;
1748 }
1749
1750 static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
1751 {
1752 ppc40x_mal_t *mal;
1753 int i;
1754
1755 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
1756 for (i = 0; i < 4; i++)
1757 mal->irqs[i] = irqs[i];
1758 qemu_register_reset(&ppc40x_mal_reset, mal);
1759 ppc_dcr_register(env, MAL0_CFG,
1760 mal, &dcr_read_mal, &dcr_write_mal);
1761 ppc_dcr_register(env, MAL0_ESR,
1762 mal, &dcr_read_mal, &dcr_write_mal);
1763 ppc_dcr_register(env, MAL0_IER,
1764 mal, &dcr_read_mal, &dcr_write_mal);
1765 ppc_dcr_register(env, MAL0_TXCASR,
1766 mal, &dcr_read_mal, &dcr_write_mal);
1767 ppc_dcr_register(env, MAL0_TXCARR,
1768 mal, &dcr_read_mal, &dcr_write_mal);
1769 ppc_dcr_register(env, MAL0_TXEOBISR,
1770 mal, &dcr_read_mal, &dcr_write_mal);
1771 ppc_dcr_register(env, MAL0_TXDEIR,
1772 mal, &dcr_read_mal, &dcr_write_mal);
1773 ppc_dcr_register(env, MAL0_RXCASR,
1774 mal, &dcr_read_mal, &dcr_write_mal);
1775 ppc_dcr_register(env, MAL0_RXCARR,
1776 mal, &dcr_read_mal, &dcr_write_mal);
1777 ppc_dcr_register(env, MAL0_RXEOBISR,
1778 mal, &dcr_read_mal, &dcr_write_mal);
1779 ppc_dcr_register(env, MAL0_RXDEIR,
1780 mal, &dcr_read_mal, &dcr_write_mal);
1781 ppc_dcr_register(env, MAL0_TXCTP0R,
1782 mal, &dcr_read_mal, &dcr_write_mal);
1783 ppc_dcr_register(env, MAL0_TXCTP1R,
1784 mal, &dcr_read_mal, &dcr_write_mal);
1785 ppc_dcr_register(env, MAL0_TXCTP2R,
1786 mal, &dcr_read_mal, &dcr_write_mal);
1787 ppc_dcr_register(env, MAL0_TXCTP3R,
1788 mal, &dcr_read_mal, &dcr_write_mal);
1789 ppc_dcr_register(env, MAL0_RXCTP0R,
1790 mal, &dcr_read_mal, &dcr_write_mal);
1791 ppc_dcr_register(env, MAL0_RXCTP1R,
1792 mal, &dcr_read_mal, &dcr_write_mal);
1793 ppc_dcr_register(env, MAL0_RCBS0,
1794 mal, &dcr_read_mal, &dcr_write_mal);
1795 ppc_dcr_register(env, MAL0_RCBS1,
1796 mal, &dcr_read_mal, &dcr_write_mal);
1797 }
1798
1799 /*****************************************************************************/
1800 /* SPR */
1801 void ppc40x_core_reset (CPUState *env)
1802 {
1803 target_ulong dbsr;
1804
1805 printf("Reset PowerPC core\n");
1806 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1807 /* XXX: TOFIX */
1808 #if 0
1809 cpu_reset(env);
1810 #else
1811 qemu_system_reset_request();
1812 #endif
1813 dbsr = env->spr[SPR_40x_DBSR];
1814 dbsr &= ~0x00000300;
1815 dbsr |= 0x00000100;
1816 env->spr[SPR_40x_DBSR] = dbsr;
1817 }
1818
1819 void ppc40x_chip_reset (CPUState *env)
1820 {
1821 target_ulong dbsr;
1822
1823 printf("Reset PowerPC chip\n");
1824 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1825 /* XXX: TOFIX */
1826 #if 0
1827 cpu_reset(env);
1828 #else
1829 qemu_system_reset_request();
1830 #endif
1831 /* XXX: TODO reset all internal peripherals */
1832 dbsr = env->spr[SPR_40x_DBSR];
1833 dbsr &= ~0x00000300;
1834 dbsr |= 0x00000200;
1835 env->spr[SPR_40x_DBSR] = dbsr;
1836 }
1837
1838 void ppc40x_system_reset (CPUState *env)
1839 {
1840 printf("Reset PowerPC system\n");
1841 qemu_system_reset_request();
1842 }
1843
1844 void store_40x_dbcr0 (CPUState *env, uint32_t val)
1845 {
1846 switch ((val >> 28) & 0x3) {
1847 case 0x0:
1848 /* No action */
1849 break;
1850 case 0x1:
1851 /* Core reset */
1852 ppc40x_core_reset(env);
1853 break;
1854 case 0x2:
1855 /* Chip reset */
1856 ppc40x_chip_reset(env);
1857 break;
1858 case 0x3:
1859 /* System reset */
1860 ppc40x_system_reset(env);
1861 break;
1862 }
1863 }
1864
1865 /*****************************************************************************/
1866 /* PowerPC 405CR */
1867 enum {
1868 PPC405CR_CPC0_PLLMR = 0x0B0,
1869 PPC405CR_CPC0_CR0 = 0x0B1,
1870 PPC405CR_CPC0_CR1 = 0x0B2,
1871 PPC405CR_CPC0_PSR = 0x0B4,
1872 PPC405CR_CPC0_JTAGID = 0x0B5,
1873 PPC405CR_CPC0_ER = 0x0B9,
1874 PPC405CR_CPC0_FR = 0x0BA,
1875 PPC405CR_CPC0_SR = 0x0BB,
1876 };
1877
1878 enum {
1879 PPC405CR_CPU_CLK = 0,
1880 PPC405CR_TMR_CLK = 1,
1881 PPC405CR_PLB_CLK = 2,
1882 PPC405CR_SDRAM_CLK = 3,
1883 PPC405CR_OPB_CLK = 4,
1884 PPC405CR_EXT_CLK = 5,
1885 PPC405CR_UART_CLK = 6,
1886 PPC405CR_CLK_NB = 7,
1887 };
1888
1889 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1890 struct ppc405cr_cpc_t {
1891 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1892 uint32_t sysclk;
1893 uint32_t psr;
1894 uint32_t cr0;
1895 uint32_t cr1;
1896 uint32_t jtagid;
1897 uint32_t pllmr;
1898 uint32_t er;
1899 uint32_t fr;
1900 };
1901
1902 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1903 {
1904 uint64_t VCO_out, PLL_out;
1905 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1906 int M, D0, D1, D2;
1907
1908 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1909 if (cpc->pllmr & 0x80000000) {
1910 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1911 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1912 M = D0 * D1 * D2;
1913 VCO_out = cpc->sysclk * M;
1914 if (VCO_out < 400000000 || VCO_out > 800000000) {
1915 /* PLL cannot lock */
1916 cpc->pllmr &= ~0x80000000;
1917 goto bypass_pll;
1918 }
1919 PLL_out = VCO_out / D2;
1920 } else {
1921 /* Bypass PLL */
1922 bypass_pll:
1923 M = D0;
1924 PLL_out = cpc->sysclk * M;
1925 }
1926 CPU_clk = PLL_out;
1927 if (cpc->cr1 & 0x00800000)
1928 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1929 else
1930 TMR_clk = CPU_clk;
1931 PLB_clk = CPU_clk / D0;
1932 SDRAM_clk = PLB_clk;
1933 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1934 OPB_clk = PLB_clk / D0;
1935 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1936 EXT_clk = PLB_clk / D0;
1937 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1938 UART_clk = CPU_clk / D0;
1939 /* Setup CPU clocks */
1940 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1941 /* Setup time-base clock */
1942 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1943 /* Setup PLB clock */
1944 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1945 /* Setup SDRAM clock */
1946 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1947 /* Setup OPB clock */
1948 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1949 /* Setup external clock */
1950 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1951 /* Setup UART clock */
1952 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1953 }
1954
1955 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1956 {
1957 ppc405cr_cpc_t *cpc;
1958 uint32_t ret;
1959
1960 cpc = opaque;
1961 switch (dcrn) {
1962 case PPC405CR_CPC0_PLLMR:
1963 ret = cpc->pllmr;
1964 break;
1965 case PPC405CR_CPC0_CR0:
1966 ret = cpc->cr0;
1967 break;
1968 case PPC405CR_CPC0_CR1:
1969 ret = cpc->cr1;
1970 break;
1971 case PPC405CR_CPC0_PSR:
1972 ret = cpc->psr;
1973 break;
1974 case PPC405CR_CPC0_JTAGID:
1975 ret = cpc->jtagid;
1976 break;
1977 case PPC405CR_CPC0_ER:
1978 ret = cpc->er;
1979 break;
1980 case PPC405CR_CPC0_FR:
1981 ret = cpc->fr;
1982 break;
1983 case PPC405CR_CPC0_SR:
1984 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1985 break;
1986 default:
1987 /* Avoid gcc warning */
1988 ret = 0;
1989 break;
1990 }
1991
1992 return ret;
1993 }
1994
1995 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1996 {
1997 ppc405cr_cpc_t *cpc;
1998
1999 cpc = opaque;
2000 switch (dcrn) {
2001 case PPC405CR_CPC0_PLLMR:
2002 cpc->pllmr = val & 0xFFF77C3F;
2003 break;
2004 case PPC405CR_CPC0_CR0:
2005 cpc->cr0 = val & 0x0FFFFFFE;
2006 break;
2007 case PPC405CR_CPC0_CR1:
2008 cpc->cr1 = val & 0x00800000;
2009 break;
2010 case PPC405CR_CPC0_PSR:
2011 /* Read-only */
2012 break;
2013 case PPC405CR_CPC0_JTAGID:
2014 /* Read-only */
2015 break;
2016 case PPC405CR_CPC0_ER:
2017 cpc->er = val & 0xBFFC0000;
2018 break;
2019 case PPC405CR_CPC0_FR:
2020 cpc->fr = val & 0xBFFC0000;
2021 break;
2022 case PPC405CR_CPC0_SR:
2023 /* Read-only */
2024 break;
2025 }
2026 }
2027
2028 static void ppc405cr_cpc_reset (void *opaque)
2029 {
2030 ppc405cr_cpc_t *cpc;
2031 int D;
2032
2033 cpc = opaque;
2034 /* Compute PLLMR value from PSR settings */
2035 cpc->pllmr = 0x80000000;
2036 /* PFWD */
2037 switch ((cpc->psr >> 30) & 3) {
2038 case 0:
2039 /* Bypass */
2040 cpc->pllmr &= ~0x80000000;
2041 break;
2042 case 1:
2043 /* Divide by 3 */
2044 cpc->pllmr |= 5 << 16;
2045 break;
2046 case 2:
2047 /* Divide by 4 */
2048 cpc->pllmr |= 4 << 16;
2049 break;
2050 case 3:
2051 /* Divide by 6 */
2052 cpc->pllmr |= 2 << 16;
2053 break;
2054 }
2055 /* PFBD */
2056 D = (cpc->psr >> 28) & 3;
2057 cpc->pllmr |= (D + 1) << 20;
2058 /* PT */
2059 D = (cpc->psr >> 25) & 7;
2060 switch (D) {
2061 case 0x2:
2062 cpc->pllmr |= 0x13;
2063 break;
2064 case 0x4:
2065 cpc->pllmr |= 0x15;
2066 break;
2067 case 0x5:
2068 cpc->pllmr |= 0x16;
2069 break;
2070 default:
2071 break;
2072 }
2073 /* PDC */
2074 D = (cpc->psr >> 23) & 3;
2075 cpc->pllmr |= D << 26;
2076 /* ODP */
2077 D = (cpc->psr >> 21) & 3;
2078 cpc->pllmr |= D << 10;
2079 /* EBPD */
2080 D = (cpc->psr >> 17) & 3;
2081 cpc->pllmr |= D << 24;
2082 cpc->cr0 = 0x0000003C;
2083 cpc->cr1 = 0x2B0D8800;
2084 cpc->er = 0x00000000;
2085 cpc->fr = 0x00000000;
2086 ppc405cr_clk_setup(cpc);
2087 }
2088
2089 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2090 {
2091 int D;
2092
2093 /* XXX: this should be read from IO pins */
2094 cpc->psr = 0x00000000; /* 8 bits ROM */
2095 /* PFWD */
2096 D = 0x2; /* Divide by 4 */
2097 cpc->psr |= D << 30;
2098 /* PFBD */
2099 D = 0x1; /* Divide by 2 */
2100 cpc->psr |= D << 28;
2101 /* PDC */
2102 D = 0x1; /* Divide by 2 */
2103 cpc->psr |= D << 23;
2104 /* PT */
2105 D = 0x5; /* M = 16 */
2106 cpc->psr |= D << 25;
2107 /* ODP */
2108 D = 0x1; /* Divide by 2 */
2109 cpc->psr |= D << 21;
2110 /* EBDP */
2111 D = 0x2; /* Divide by 4 */
2112 cpc->psr |= D << 17;
2113 }
2114
2115 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2116 uint32_t sysclk)
2117 {
2118 ppc405cr_cpc_t *cpc;
2119
2120 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2121 memcpy(cpc->clk_setup, clk_setup,
2122 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2123 cpc->sysclk = sysclk;
2124 cpc->jtagid = 0x42051049;
2125 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2126 &dcr_read_crcpc, &dcr_write_crcpc);
2127 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2128 &dcr_read_crcpc, &dcr_write_crcpc);
2129 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2130 &dcr_read_crcpc, &dcr_write_crcpc);
2131 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2132 &dcr_read_crcpc, &dcr_write_crcpc);
2133 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2134 &dcr_read_crcpc, &dcr_write_crcpc);
2135 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2136 &dcr_read_crcpc, &dcr_write_crcpc);
2137 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2138 &dcr_read_crcpc, &dcr_write_crcpc);
2139 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2140 &dcr_read_crcpc, &dcr_write_crcpc);
2141 ppc405cr_clk_init(cpc);
2142 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2143 }
2144
2145 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2146 target_phys_addr_t ram_sizes[4],
2147 uint32_t sysclk, qemu_irq **picp,
2148 int do_init)
2149 {
2150 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2151 qemu_irq dma_irqs[4];
2152 CPUState *env;
2153 qemu_irq *pic, *irqs;
2154
2155 memset(clk_setup, 0, sizeof(clk_setup));
2156 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2157 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2158 /* Memory mapped devices registers */
2159 /* PLB arbitrer */
2160 ppc4xx_plb_init(env);
2161 /* PLB to OPB bridge */
2162 ppc4xx_pob_init(env);
2163 /* OBP arbitrer */
2164 ppc4xx_opba_init(0xef600600);
2165 /* Universal interrupt controller */
2166 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2167 irqs[PPCUIC_OUTPUT_INT] =
2168 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2169 irqs[PPCUIC_OUTPUT_CINT] =
2170 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2171 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2172 *picp = pic;
2173 /* SDRAM controller */
2174 ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2175 /* External bus controller */
2176 ppc405_ebc_init(env);
2177 /* DMA controller */
2178 dma_irqs[0] = pic[26];
2179 dma_irqs[1] = pic[25];
2180 dma_irqs[2] = pic[24];
2181 dma_irqs[3] = pic[23];
2182 ppc405_dma_init(env, dma_irqs);
2183 /* Serial ports */
2184 if (serial_hds[0] != NULL) {
2185 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2186 serial_hds[0], 1, 1);
2187 }
2188 if (serial_hds[1] != NULL) {
2189 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2190 serial_hds[1], 1, 1);
2191 }
2192 /* IIC controller */
2193 ppc405_i2c_init(0xef600500, pic[2]);
2194 /* GPIO */
2195 ppc405_gpio_init(0xef600700);
2196 /* CPU control */
2197 ppc405cr_cpc_init(env, clk_setup, sysclk);
2198
2199 return env;
2200 }
2201
2202 /*****************************************************************************/
2203 /* PowerPC 405EP */
2204 /* CPU control */
2205 enum {
2206 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2207 PPC405EP_CPC0_BOOT = 0x0F1,
2208 PPC405EP_CPC0_EPCTL = 0x0F3,
2209 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2210 PPC405EP_CPC0_UCR = 0x0F5,
2211 PPC405EP_CPC0_SRR = 0x0F6,
2212 PPC405EP_CPC0_JTAGID = 0x0F7,
2213 PPC405EP_CPC0_PCI = 0x0F9,
2214 #if 0
2215 PPC405EP_CPC0_ER = xxx,
2216 PPC405EP_CPC0_FR = xxx,
2217 PPC405EP_CPC0_SR = xxx,
2218 #endif
2219 };
2220
2221 enum {
2222 PPC405EP_CPU_CLK = 0,
2223 PPC405EP_PLB_CLK = 1,
2224 PPC405EP_OPB_CLK = 2,
2225 PPC405EP_EBC_CLK = 3,
2226 PPC405EP_MAL_CLK = 4,
2227 PPC405EP_PCI_CLK = 5,
2228 PPC405EP_UART0_CLK = 6,
2229 PPC405EP_UART1_CLK = 7,
2230 PPC405EP_CLK_NB = 8,
2231 };
2232
2233 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2234 struct ppc405ep_cpc_t {
2235 uint32_t sysclk;
2236 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2237 uint32_t boot;
2238 uint32_t epctl;
2239 uint32_t pllmr[2];
2240 uint32_t ucr;
2241 uint32_t srr;
2242 uint32_t jtagid;
2243 uint32_t pci;
2244 /* Clock and power management */
2245 uint32_t er;
2246 uint32_t fr;
2247 uint32_t sr;
2248 };
2249
2250 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2251 {
2252 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2253 uint32_t UART0_clk, UART1_clk;
2254 uint64_t VCO_out, PLL_out;
2255 int M, D;
2256
2257 VCO_out = 0;
2258 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2259 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2260 #ifdef DEBUG_CLOCKS_LL
2261 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2262 #endif
2263 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2264 #ifdef DEBUG_CLOCKS_LL
2265 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2266 #endif
2267 VCO_out = cpc->sysclk * M * D;
2268 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2269 /* Error - unlock the PLL */
2270 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2271 #if 0
2272 cpc->pllmr[1] &= ~0x80000000;
2273 goto pll_bypass;
2274 #endif
2275 }
2276 PLL_out = VCO_out / D;
2277 /* Pretend the PLL is locked */
2278 cpc->boot |= 0x00000001;
2279 } else {
2280 #if 0
2281 pll_bypass:
2282 #endif
2283 PLL_out = cpc->sysclk;
2284 if (cpc->pllmr[1] & 0x40000000) {
2285 /* Pretend the PLL is not locked */
2286 cpc->boot &= ~0x00000001;
2287 }
2288 }
2289 /* Now, compute all other clocks */
2290 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2291 #ifdef DEBUG_CLOCKS_LL
2292 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2293 #endif
2294 CPU_clk = PLL_out / D;
2295 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2296 #ifdef DEBUG_CLOCKS_LL
2297 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2298 #endif
2299 PLB_clk = CPU_clk / D;
2300 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2301 #ifdef DEBUG_CLOCKS_LL
2302 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2303 #endif
2304 OPB_clk = PLB_clk / D;
2305 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2306 #ifdef DEBUG_CLOCKS_LL
2307 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2308 #endif
2309 EBC_clk = PLB_clk / D;
2310 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2311 #ifdef DEBUG_CLOCKS_LL
2312 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2313 #endif
2314 MAL_clk = PLB_clk / D;
2315 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2316 #ifdef DEBUG_CLOCKS_LL
2317 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2318 #endif
2319 PCI_clk = PLB_clk / D;
2320 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2321 #ifdef DEBUG_CLOCKS_LL
2322 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2323 #endif
2324 UART0_clk = PLL_out / D;
2325 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2326 #ifdef DEBUG_CLOCKS_LL
2327 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2328 #endif
2329 UART1_clk = PLL_out / D;
2330 #ifdef DEBUG_CLOCKS
2331 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2332 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2333 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2334 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2335 " UART1 %" PRIu32 "\n",
2336 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2337 UART0_clk, UART1_clk);
2338 #endif
2339 /* Setup CPU clocks */
2340 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2341 /* Setup PLB clock */
2342 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2343 /* Setup OPB clock */
2344 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2345 /* Setup external clock */
2346 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2347 /* Setup MAL clock */
2348 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2349 /* Setup PCI clock */
2350 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2351 /* Setup UART0 clock */
2352 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2353 /* Setup UART1 clock */
2354 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2355 }
2356
2357 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2358 {
2359 ppc405ep_cpc_t *cpc;
2360 uint32_t ret;
2361
2362 cpc = opaque;
2363 switch (dcrn) {
2364 case PPC405EP_CPC0_BOOT:
2365 ret = cpc->boot;
2366 break;
2367 case PPC405EP_CPC0_EPCTL:
2368 ret = cpc->epctl;
2369 break;
2370 case PPC405EP_CPC0_PLLMR0:
2371 ret = cpc->pllmr[0];
2372 break;
2373 case PPC405EP_CPC0_PLLMR1:
2374 ret = cpc->pllmr[1];
2375 break;
2376 case PPC405EP_CPC0_UCR:
2377 ret = cpc->ucr;
2378 break;
2379 case PPC405EP_CPC0_SRR:
2380 ret = cpc->srr;
2381 break;
2382 case PPC405EP_CPC0_JTAGID:
2383 ret = cpc->jtagid;
2384 break;
2385 case PPC405EP_CPC0_PCI:
2386 ret = cpc->pci;
2387 break;
2388 default:
2389 /* Avoid gcc warning */
2390 ret = 0;
2391 break;
2392 }
2393
2394 return ret;
2395 }
2396
2397 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2398 {
2399 ppc405ep_cpc_t *cpc;
2400
2401 cpc = opaque;
2402 switch (dcrn) {
2403 case PPC405EP_CPC0_BOOT:
2404 /* Read-only register */
2405 break;
2406 case PPC405EP_CPC0_EPCTL:
2407 /* Don't care for now */
2408 cpc->epctl = val & 0xC00000F3;
2409 break;
2410 case PPC405EP_CPC0_PLLMR0:
2411 cpc->pllmr[0] = val & 0x00633333;
2412 ppc405ep_compute_clocks(cpc);
2413 break;
2414 case PPC405EP_CPC0_PLLMR1:
2415 cpc->pllmr[1] = val & 0xC0F73FFF;
2416 ppc405ep_compute_clocks(cpc);
2417 break;
2418 case PPC405EP_CPC0_UCR:
2419 /* UART control - don't care for now */
2420 cpc->ucr = val & 0x003F7F7F;
2421 break;
2422 case PPC405EP_CPC0_SRR:
2423 cpc->srr = val;
2424 break;
2425 case PPC405EP_CPC0_JTAGID:
2426 /* Read-only */
2427 break;
2428 case PPC405EP_CPC0_PCI:
2429 cpc->pci = val;
2430 break;
2431 }
2432 }
2433
2434 static void ppc405ep_cpc_reset (void *opaque)
2435 {
2436 ppc405ep_cpc_t *cpc = opaque;
2437
2438 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2439 cpc->epctl = 0x00000000;
2440 cpc->pllmr[0] = 0x00011010;
2441 cpc->pllmr[1] = 0x40000000;
2442 cpc->ucr = 0x00000000;
2443 cpc->srr = 0x00040000;
2444 cpc->pci = 0x00000000;
2445 cpc->er = 0x00000000;
2446 cpc->fr = 0x00000000;
2447 cpc->sr = 0x00000000;
2448 ppc405ep_compute_clocks(cpc);
2449 }
2450
2451 /* XXX: sysclk should be between 25 and 100 MHz */
2452 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2453 uint32_t sysclk)
2454 {
2455 ppc405ep_cpc_t *cpc;
2456
2457 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2458 memcpy(cpc->clk_setup, clk_setup,
2459 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2460 cpc->jtagid = 0x20267049;
2461 cpc->sysclk = sysclk;
2462 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2463 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2464 &dcr_read_epcpc, &dcr_write_epcpc);
2465 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2466 &dcr_read_epcpc, &dcr_write_epcpc);
2467 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2468 &dcr_read_epcpc, &dcr_write_epcpc);
2469 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2470 &dcr_read_epcpc, &dcr_write_epcpc);
2471 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2472 &dcr_read_epcpc, &dcr_write_epcpc);
2473 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2474 &dcr_read_epcpc, &dcr_write_epcpc);
2475 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2476 &dcr_read_epcpc, &dcr_write_epcpc);
2477 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2478 &dcr_read_epcpc, &dcr_write_epcpc);
2479 #if 0
2480 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2481 &dcr_read_epcpc, &dcr_write_epcpc);
2482 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2483 &dcr_read_epcpc, &dcr_write_epcpc);
2484 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2485 &dcr_read_epcpc, &dcr_write_epcpc);
2486 #endif
2487 }
2488
2489 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2490 target_phys_addr_t ram_sizes[2],
2491 uint32_t sysclk, qemu_irq **picp,
2492 int do_init)
2493 {
2494 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2495 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2496 CPUState *env;
2497 qemu_irq *pic, *irqs;
2498
2499 memset(clk_setup, 0, sizeof(clk_setup));
2500 /* init CPUs */
2501 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2502 &tlb_clk_setup, sysclk);
2503 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2504 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2505 /* Internal devices init */
2506 /* Memory mapped devices registers */
2507 /* PLB arbitrer */
2508 ppc4xx_plb_init(env);
2509 /* PLB to OPB bridge */
2510 ppc4xx_pob_init(env);
2511 /* OBP arbitrer */
2512 ppc4xx_opba_init(0xef600600);
2513 /* Universal interrupt controller */
2514 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2515 irqs[PPCUIC_OUTPUT_INT] =
2516 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2517 irqs[PPCUIC_OUTPUT_CINT] =
2518 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2519 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2520 *picp = pic;
2521 /* SDRAM controller */
2522 /* XXX 405EP has no ECC interrupt */
2523 ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
2524 /* External bus controller */
2525 ppc405_ebc_init(env);
2526 /* DMA controller */
2527 dma_irqs[0] = pic[5];
2528 dma_irqs[1] = pic[6];
2529 dma_irqs[2] = pic[7];
2530 dma_irqs[3] = pic[8];
2531 ppc405_dma_init(env, dma_irqs);
2532 /* IIC controller */
2533 ppc405_i2c_init(0xef600500, pic[2]);
2534 /* GPIO */
2535 ppc405_gpio_init(0xef600700);
2536 /* Serial ports */
2537 if (serial_hds[0] != NULL) {
2538 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2539 serial_hds[0], 1, 1);
2540 }
2541 if (serial_hds[1] != NULL) {
2542 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2543 serial_hds[1], 1, 1);
2544 }
2545 /* OCM */
2546 ppc405_ocm_init(env);
2547 /* GPT */
2548 gpt_irqs[0] = pic[19];
2549 gpt_irqs[1] = pic[20];
2550 gpt_irqs[2] = pic[21];
2551 gpt_irqs[3] = pic[22];
2552 gpt_irqs[4] = pic[23];
2553 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2554 /* PCI */
2555 /* Uses pic[3], pic[16], pic[18] */
2556 /* MAL */
2557 mal_irqs[0] = pic[11];
2558 mal_irqs[1] = pic[12];
2559 mal_irqs[2] = pic[13];
2560 mal_irqs[3] = pic[14];
2561 ppc405_mal_init(env, mal_irqs);
2562 /* Ethernet */
2563 /* Uses pic[9], pic[15], pic[17] */
2564 /* CPU control */
2565 ppc405ep_cpc_init(env, clk_setup, sysclk);
2566
2567 return env;
2568 }
CRIS target port of Qemu