?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
migration_completion: Take current state
[qemu/cris-port.git] / target-mips / op_helper.c
blob056d53b9ef7b21cb40116f3cb9c5f582f667cabc
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
24 #include "sysemu/kvm.h"
25
26 #ifndef CONFIG_USER_ONLY
27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
28 #endif
29
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
32
33 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
34 int error_code)
35 {
36 do_raise_exception_err(env, exception, error_code, 0);
37 }
38
39 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
40 {
41 do_raise_exception(env, exception, GETPC());
42 }
43
44 void helper_raise_exception_debug(CPUMIPSState *env)
45 {
46 do_raise_exception(env, EXCP_DEBUG, 0);
47 }
48
49 static void raise_exception(CPUMIPSState *env, uint32_t exception)
50 {
51 do_raise_exception(env, exception, 0);
52 }
53
54 #if defined(CONFIG_USER_ONLY)
55 #define HELPER_LD(name, insn, type) \
56 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
57 int mem_idx, uintptr_t retaddr) \
58 { \
59 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
60 }
61 #else
62 #define HELPER_LD(name, insn, type) \
63 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
64 int mem_idx, uintptr_t retaddr) \
65 { \
66 switch (mem_idx) \
67 { \
68 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
69 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
70 default: \
71 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
72 } \
73 }
74 #endif
75 HELPER_LD(lw, ldl, int32_t)
76 #if defined(TARGET_MIPS64)
77 HELPER_LD(ld, ldq, int64_t)
78 #endif
79 #undef HELPER_LD
80
81 #if defined(CONFIG_USER_ONLY)
82 #define HELPER_ST(name, insn, type) \
83 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
84 type val, int mem_idx, uintptr_t retaddr) \
85 { \
86 cpu_##insn##_data_ra(env, addr, val, retaddr); \
87 }
88 #else
89 #define HELPER_ST(name, insn, type) \
90 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
91 type val, int mem_idx, uintptr_t retaddr) \
92 { \
93 switch (mem_idx) \
94 { \
95 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
96 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
97 default: \
98 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
99 } \
100 }
101 #endif
102 HELPER_ST(sb, stb, uint8_t)
103 HELPER_ST(sw, stl, uint32_t)
104 #if defined(TARGET_MIPS64)
105 HELPER_ST(sd, stq, uint64_t)
106 #endif
107 #undef HELPER_ST
108
109 target_ulong helper_clo (target_ulong arg1)
110 {
111 return clo32(arg1);
112 }
113
114 target_ulong helper_clz (target_ulong arg1)
115 {
116 return clz32(arg1);
117 }
118
119 #if defined(TARGET_MIPS64)
120 target_ulong helper_dclo (target_ulong arg1)
121 {
122 return clo64(arg1);
123 }
124
125 target_ulong helper_dclz (target_ulong arg1)
126 {
127 return clz64(arg1);
128 }
129 #endif /* TARGET_MIPS64 */
130
131 /* 64 bits arithmetic for 32 bits hosts */
132 static inline uint64_t get_HILO(CPUMIPSState *env)
133 {
134 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
135 }
136
137 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
138 {
139 target_ulong tmp;
140 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
141 tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
142 return tmp;
143 }
144
145 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
146 {
147 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
148 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
149 return tmp;
150 }
151
152 /* Multiplication variants of the vr54xx. */
153 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
154 target_ulong arg2)
155 {
156 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
157 (int64_t)(int32_t)arg2));
158 }
159
160 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
161 target_ulong arg2)
162 {
163 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
164 (uint64_t)(uint32_t)arg2);
165 }
166
167 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
168 target_ulong arg2)
169 {
170 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
171 (int64_t)(int32_t)arg2);
172 }
173
174 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
175 target_ulong arg2)
176 {
177 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
178 (int64_t)(int32_t)arg2);
179 }
180
181 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
182 target_ulong arg2)
183 {
184 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
185 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
186 }
187
188 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
189 target_ulong arg2)
190 {
191 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
192 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
193 }
194
195 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
196 target_ulong arg2)
197 {
198 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
199 (int64_t)(int32_t)arg2);
200 }
201
202 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
203 target_ulong arg2)
204 {
205 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
206 (int64_t)(int32_t)arg2);
207 }
208
209 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
210 target_ulong arg2)
211 {
212 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
213 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
214 }
215
216 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
217 target_ulong arg2)
218 {
219 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
220 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
221 }
222
223 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
224 target_ulong arg2)
225 {
226 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
227 }
228
229 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
230 target_ulong arg2)
231 {
232 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
233 (uint64_t)(uint32_t)arg2);
234 }
235
236 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
237 target_ulong arg2)
238 {
239 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
240 (int64_t)(int32_t)arg2);
241 }
242
243 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
244 target_ulong arg2)
245 {
246 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
247 (uint64_t)(uint32_t)arg2);
248 }
249
250 static inline target_ulong bitswap(target_ulong v)
251 {
252 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
253 ((v & (target_ulong)0x5555555555555555ULL) << 1);
254 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
255 ((v & (target_ulong)0x3333333333333333ULL) << 2);
256 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
257 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
258 return v;
259 }
260
261 #ifdef TARGET_MIPS64
262 target_ulong helper_dbitswap(target_ulong rt)
263 {
264 return bitswap(rt);
265 }
266 #endif
267
268 target_ulong helper_bitswap(target_ulong rt)
269 {
270 return (int32_t)bitswap(rt);
271 }
272
273 #ifndef CONFIG_USER_ONLY
274
275 static inline hwaddr do_translate_address(CPUMIPSState *env,
276 target_ulong address,
277 int rw, uintptr_t retaddr)
278 {
279 hwaddr lladdr;
280 CPUState *cs = CPU(mips_env_get_cpu(env));
281
282 lladdr = cpu_mips_translate_address(env, address, rw);
283
284 if (lladdr == -1LL) {
285 cpu_loop_exit_restore(cs, retaddr);
286 } else {
287 return lladdr;
288 }
289 }
290
291 #define HELPER_LD_ATOMIC(name, insn, almask) \
292 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
293 { \
294 if (arg & almask) { \
295 env->CP0_BadVAddr = arg; \
296 do_raise_exception(env, EXCP_AdEL, GETPC()); \
297 } \
298 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
299 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
300 return env->llval; \
301 }
302 HELPER_LD_ATOMIC(ll, lw, 0x3)
303 #ifdef TARGET_MIPS64
304 HELPER_LD_ATOMIC(lld, ld, 0x7)
305 #endif
306 #undef HELPER_LD_ATOMIC
307
308 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
310 target_ulong arg2, int mem_idx) \
311 { \
312 target_long tmp; \
313 \
314 if (arg2 & almask) { \
315 env->CP0_BadVAddr = arg2; \
316 do_raise_exception(env, EXCP_AdES, GETPC()); \
317 } \
318 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
319 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
320 if (tmp == env->llval) { \
321 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
322 return 1; \
323 } \
324 } \
325 return 0; \
326 }
327 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
328 #ifdef TARGET_MIPS64
329 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
330 #endif
331 #undef HELPER_ST_ATOMIC
332 #endif
333
334 #ifdef TARGET_WORDS_BIGENDIAN
335 #define GET_LMASK(v) ((v) & 3)
336 #define GET_OFFSET(addr, offset) (addr + (offset))
337 #else
338 #define GET_LMASK(v) (((v) & 3) ^ 3)
339 #define GET_OFFSET(addr, offset) (addr - (offset))
340 #endif
341
342 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
343 int mem_idx)
344 {
345 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
346
347 if (GET_LMASK(arg2) <= 2) {
348 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
349 GETPC());
350 }
351
352 if (GET_LMASK(arg2) <= 1) {
353 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
354 GETPC());
355 }
356
357 if (GET_LMASK(arg2) == 0) {
358 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
359 GETPC());
360 }
361 }
362
363 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
364 int mem_idx)
365 {
366 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
367
368 if (GET_LMASK(arg2) >= 1) {
369 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
370 GETPC());
371 }
372
373 if (GET_LMASK(arg2) >= 2) {
374 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
375 GETPC());
376 }
377
378 if (GET_LMASK(arg2) == 3) {
379 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
380 GETPC());
381 }
382 }
383
384 #if defined(TARGET_MIPS64)
385 /* "half" load and stores. We must do the memory access inline,
386 or fault handling won't work. */
387
388 #ifdef TARGET_WORDS_BIGENDIAN
389 #define GET_LMASK64(v) ((v) & 7)
390 #else
391 #define GET_LMASK64(v) (((v) & 7) ^ 7)
392 #endif
393
394 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
395 int mem_idx)
396 {
397 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
398
399 if (GET_LMASK64(arg2) <= 6) {
400 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
401 GETPC());
402 }
403
404 if (GET_LMASK64(arg2) <= 5) {
405 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
406 GETPC());
407 }
408
409 if (GET_LMASK64(arg2) <= 4) {
410 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
411 GETPC());
412 }
413
414 if (GET_LMASK64(arg2) <= 3) {
415 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
416 GETPC());
417 }
418
419 if (GET_LMASK64(arg2) <= 2) {
420 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
421 GETPC());
422 }
423
424 if (GET_LMASK64(arg2) <= 1) {
425 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
426 GETPC());
427 }
428
429 if (GET_LMASK64(arg2) <= 0) {
430 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
431 GETPC());
432 }
433 }
434
435 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
436 int mem_idx)
437 {
438 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
439
440 if (GET_LMASK64(arg2) >= 1) {
441 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
442 GETPC());
443 }
444
445 if (GET_LMASK64(arg2) >= 2) {
446 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
447 GETPC());
448 }
449
450 if (GET_LMASK64(arg2) >= 3) {
451 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
452 GETPC());
453 }
454
455 if (GET_LMASK64(arg2) >= 4) {
456 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
457 GETPC());
458 }
459
460 if (GET_LMASK64(arg2) >= 5) {
461 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
462 GETPC());
463 }
464
465 if (GET_LMASK64(arg2) >= 6) {
466 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
467 GETPC());
468 }
469
470 if (GET_LMASK64(arg2) == 7) {
471 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
472 GETPC());
473 }
474 }
475 #endif /* TARGET_MIPS64 */
476
477 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
478
479 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
480 uint32_t mem_idx)
481 {
482 target_ulong base_reglist = reglist & 0xf;
483 target_ulong do_r31 = reglist & 0x10;
484
485 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
486 target_ulong i;
487
488 for (i = 0; i < base_reglist; i++) {
489 env->active_tc.gpr[multiple_regs[i]] =
490 (target_long)do_lw(env, addr, mem_idx, GETPC());
491 addr += 4;
492 }
493 }
494
495 if (do_r31) {
496 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
497 GETPC());
498 }
499 }
500
501 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
502 uint32_t mem_idx)
503 {
504 target_ulong base_reglist = reglist & 0xf;
505 target_ulong do_r31 = reglist & 0x10;
506
507 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
508 target_ulong i;
509
510 for (i = 0; i < base_reglist; i++) {
511 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
512 GETPC());
513 addr += 4;
514 }
515 }
516
517 if (do_r31) {
518 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
519 }
520 }
521
522 #if defined(TARGET_MIPS64)
523 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
524 uint32_t mem_idx)
525 {
526 target_ulong base_reglist = reglist & 0xf;
527 target_ulong do_r31 = reglist & 0x10;
528
529 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
530 target_ulong i;
531
532 for (i = 0; i < base_reglist; i++) {
533 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
534 GETPC());
535 addr += 8;
536 }
537 }
538
539 if (do_r31) {
540 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
541 }
542 }
543
544 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
545 uint32_t mem_idx)
546 {
547 target_ulong base_reglist = reglist & 0xf;
548 target_ulong do_r31 = reglist & 0x10;
549
550 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
551 target_ulong i;
552
553 for (i = 0; i < base_reglist; i++) {
554 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
555 GETPC());
556 addr += 8;
557 }
558 }
559
560 if (do_r31) {
561 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
562 }
563 }
564 #endif
565
566 #ifndef CONFIG_USER_ONLY
567 /* SMP helpers. */
568 static bool mips_vpe_is_wfi(MIPSCPU *c)
569 {
570 CPUState *cpu = CPU(c);
571 CPUMIPSState *env = &c->env;
572
573 /* If the VPE is halted but otherwise active, it means it's waiting for
574 an interrupt. */
575 return cpu->halted && mips_vpe_active(env);
576 }
577
578 static inline void mips_vpe_wake(MIPSCPU *c)
579 {
580 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
581 because there might be other conditions that state that c should
582 be sleeping. */
583 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
584 }
585
586 static inline void mips_vpe_sleep(MIPSCPU *cpu)
587 {
588 CPUState *cs = CPU(cpu);
589
590 /* The VPE was shut off, really go to bed.
591 Reset any old _WAKE requests. */
592 cs->halted = 1;
593 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
594 }
595
596 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
597 {
598 CPUMIPSState *c = &cpu->env;
599
600 /* FIXME: TC reschedule. */
601 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
602 mips_vpe_wake(cpu);
603 }
604 }
605
606 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
607 {
608 CPUMIPSState *c = &cpu->env;
609
610 /* FIXME: TC reschedule. */
611 if (!mips_vpe_active(c)) {
612 mips_vpe_sleep(cpu);
613 }
614 }
615
616 /**
617 * mips_cpu_map_tc:
618 * @env: CPU from which mapping is performed.
619 * @tc: Should point to an int with the value of the global TC index.
620 *
621 * This function will transform @tc into a local index within the
622 * returned #CPUMIPSState.
623 */
624 /* FIXME: This code assumes that all VPEs have the same number of TCs,
625 which depends on runtime setup. Can probably be fixed by
626 walking the list of CPUMIPSStates. */
627 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
628 {
629 MIPSCPU *cpu;
630 CPUState *cs;
631 CPUState *other_cs;
632 int vpe_idx;
633 int tc_idx = *tc;
634
635 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
636 /* Not allowed to address other CPUs. */
637 *tc = env->current_tc;
638 return env;
639 }
640
641 cs = CPU(mips_env_get_cpu(env));
642 vpe_idx = tc_idx / cs->nr_threads;
643 *tc = tc_idx % cs->nr_threads;
644 other_cs = qemu_get_cpu(vpe_idx);
645 if (other_cs == NULL) {
646 return env;
647 }
648 cpu = MIPS_CPU(other_cs);
649 return &cpu->env;
650 }
651
652 /* The per VPE CP0_Status register shares some fields with the per TC
653 CP0_TCStatus registers. These fields are wired to the same registers,
654 so changes to either of them should be reflected on both registers.
655
656 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
657
658 These helper call synchronizes the regs for a given cpu. */
659
660 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
661 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
662 int tc); */
663
664 /* Called for updates to CP0_TCStatus. */
665 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
666 target_ulong v)
667 {
668 uint32_t status;
669 uint32_t tcu, tmx, tasid, tksu;
670 uint32_t mask = ((1U << CP0St_CU3)
671 | (1 << CP0St_CU2)
672 | (1 << CP0St_CU1)
673 | (1 << CP0St_CU0)
674 | (1 << CP0St_MX)
675 | (3 << CP0St_KSU));
676
677 tcu = (v >> CP0TCSt_TCU0) & 0xf;
678 tmx = (v >> CP0TCSt_TMX) & 0x1;
679 tasid = v & 0xff;
680 tksu = (v >> CP0TCSt_TKSU) & 0x3;
681
682 status = tcu << CP0St_CU0;
683 status |= tmx << CP0St_MX;
684 status |= tksu << CP0St_KSU;
685
686 cpu->CP0_Status &= ~mask;
687 cpu->CP0_Status |= status;
688
689 /* Sync the TASID with EntryHi. */
690 cpu->CP0_EntryHi &= ~0xff;
691 cpu->CP0_EntryHi |= tasid;
692
693 compute_hflags(cpu);
694 }
695
696 /* Called for updates to CP0_EntryHi. */
697 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
698 {
699 int32_t *tcst;
700 uint32_t asid, v = cpu->CP0_EntryHi;
701
702 asid = v & 0xff;
703
704 if (tc == cpu->current_tc) {
705 tcst = &cpu->active_tc.CP0_TCStatus;
706 } else {
707 tcst = &cpu->tcs[tc].CP0_TCStatus;
708 }
709
710 *tcst &= ~0xff;
711 *tcst |= asid;
712 }
713
714 /* CP0 helpers */
715 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
716 {
717 return env->mvp->CP0_MVPControl;
718 }
719
720 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
721 {
722 return env->mvp->CP0_MVPConf0;
723 }
724
725 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
726 {
727 return env->mvp->CP0_MVPConf1;
728 }
729
730 target_ulong helper_mfc0_random(CPUMIPSState *env)
731 {
732 return (int32_t)cpu_mips_get_random(env);
733 }
734
735 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
736 {
737 return env->active_tc.CP0_TCStatus;
738 }
739
740 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
741 {
742 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
743 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
744
745 if (other_tc == other->current_tc)
746 return other->active_tc.CP0_TCStatus;
747 else
748 return other->tcs[other_tc].CP0_TCStatus;
749 }
750
751 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
752 {
753 return env->active_tc.CP0_TCBind;
754 }
755
756 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
757 {
758 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
759 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
760
761 if (other_tc == other->current_tc)
762 return other->active_tc.CP0_TCBind;
763 else
764 return other->tcs[other_tc].CP0_TCBind;
765 }
766
767 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
768 {
769 return env->active_tc.PC;
770 }
771
772 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
773 {
774 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
775 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
776
777 if (other_tc == other->current_tc)
778 return other->active_tc.PC;
779 else
780 return other->tcs[other_tc].PC;
781 }
782
783 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
784 {
785 return env->active_tc.CP0_TCHalt;
786 }
787
788 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
789 {
790 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
791 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
792
793 if (other_tc == other->current_tc)
794 return other->active_tc.CP0_TCHalt;
795 else
796 return other->tcs[other_tc].CP0_TCHalt;
797 }
798
799 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
800 {
801 return env->active_tc.CP0_TCContext;
802 }
803
804 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
805 {
806 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
807 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
808
809 if (other_tc == other->current_tc)
810 return other->active_tc.CP0_TCContext;
811 else
812 return other->tcs[other_tc].CP0_TCContext;
813 }
814
815 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
816 {
817 return env->active_tc.CP0_TCSchedule;
818 }
819
820 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
821 {
822 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
823 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
824
825 if (other_tc == other->current_tc)
826 return other->active_tc.CP0_TCSchedule;
827 else
828 return other->tcs[other_tc].CP0_TCSchedule;
829 }
830
831 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
832 {
833 return env->active_tc.CP0_TCScheFBack;
834 }
835
836 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
837 {
838 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
839 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
840
841 if (other_tc == other->current_tc)
842 return other->active_tc.CP0_TCScheFBack;
843 else
844 return other->tcs[other_tc].CP0_TCScheFBack;
845 }
846
847 target_ulong helper_mfc0_count(CPUMIPSState *env)
848 {
849 return (int32_t)cpu_mips_get_count(env);
850 }
851
852 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
853 {
854 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
855 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
856
857 return other->CP0_EntryHi;
858 }
859
860 target_ulong helper_mftc0_cause(CPUMIPSState *env)
861 {
862 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
863 int32_t tccause;
864 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
865
866 if (other_tc == other->current_tc) {
867 tccause = other->CP0_Cause;
868 } else {
869 tccause = other->CP0_Cause;
870 }
871
872 return tccause;
873 }
874
875 target_ulong helper_mftc0_status(CPUMIPSState *env)
876 {
877 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
878 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
879
880 return other->CP0_Status;
881 }
882
883 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
884 {
885 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
886 }
887
888 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
889 {
890 return (int32_t)env->CP0_WatchLo[sel];
891 }
892
893 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
894 {
895 return env->CP0_WatchHi[sel];
896 }
897
898 target_ulong helper_mfc0_debug(CPUMIPSState *env)
899 {
900 target_ulong t0 = env->CP0_Debug;
901 if (env->hflags & MIPS_HFLAG_DM)
902 t0 |= 1 << CP0DB_DM;
903
904 return t0;
905 }
906
907 target_ulong helper_mftc0_debug(CPUMIPSState *env)
908 {
909 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
910 int32_t tcstatus;
911 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
912
913 if (other_tc == other->current_tc)
914 tcstatus = other->active_tc.CP0_Debug_tcstatus;
915 else
916 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
917
918 /* XXX: Might be wrong, check with EJTAG spec. */
919 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
920 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
921 }
922
923 #if defined(TARGET_MIPS64)
924 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
925 {
926 return env->active_tc.PC;
927 }
928
929 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
930 {
931 return env->active_tc.CP0_TCHalt;
932 }
933
934 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
935 {
936 return env->active_tc.CP0_TCContext;
937 }
938
939 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
940 {
941 return env->active_tc.CP0_TCSchedule;
942 }
943
944 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
945 {
946 return env->active_tc.CP0_TCScheFBack;
947 }
948
949 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
950 {
951 return env->lladdr >> env->CP0_LLAddr_shift;
952 }
953
954 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
955 {
956 return env->CP0_WatchLo[sel];
957 }
958 #endif /* TARGET_MIPS64 */
959
960 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
961 {
962 uint32_t index_p = env->CP0_Index & 0x80000000;
963 uint32_t tlb_index = arg1 & 0x7fffffff;
964 if (tlb_index < env->tlb->nb_tlb) {
965 if (env->insn_flags & ISA_MIPS32R6) {
966 index_p |= arg1 & 0x80000000;
967 }
968 env->CP0_Index = index_p | tlb_index;
969 }
970 }
971
972 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
973 {
974 uint32_t mask = 0;
975 uint32_t newval;
976
977 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
978 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
979 (1 << CP0MVPCo_EVP);
980 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
981 mask |= (1 << CP0MVPCo_STLB);
982 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
983
984 // TODO: Enable/disable shared TLB, enable/disable VPEs.
985
986 env->mvp->CP0_MVPControl = newval;
987 }
988
989 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
990 {
991 uint32_t mask;
992 uint32_t newval;
993
994 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
995 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
996 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
997
998 /* Yield scheduler intercept not implemented. */
999 /* Gating storage scheduler intercept not implemented. */
1000
1001 // TODO: Enable/disable TCs.
1002
1003 env->CP0_VPEControl = newval;
1004 }
1005
1006 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1007 {
1008 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1009 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1010 uint32_t mask;
1011 uint32_t newval;
1012
1013 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1014 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1015 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1016
1017 /* TODO: Enable/disable TCs. */
1018
1019 other->CP0_VPEControl = newval;
1020 }
1021
1022 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1023 {
1024 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1025 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1026 /* FIXME: Mask away return zero on read bits. */
1027 return other->CP0_VPEControl;
1028 }
1029
1030 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1031 {
1032 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1033 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1034
1035 return other->CP0_VPEConf0;
1036 }
1037
1038 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1039 {
1040 uint32_t mask = 0;
1041 uint32_t newval;
1042
1043 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1044 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1045 mask |= (0xff << CP0VPEC0_XTC);
1046 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1047 }
1048 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1049
1050 // TODO: TC exclusive handling due to ERL/EXL.
1051
1052 env->CP0_VPEConf0 = newval;
1053 }
1054
1055 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1056 {
1057 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1058 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1059 uint32_t mask = 0;
1060 uint32_t newval;
1061
1062 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1063 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1064
1065 /* TODO: TC exclusive handling due to ERL/EXL. */
1066 other->CP0_VPEConf0 = newval;
1067 }
1068
1069 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1070 {
1071 uint32_t mask = 0;
1072 uint32_t newval;
1073
1074 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1075 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1076 (0xff << CP0VPEC1_NCP1);
1077 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1078
1079 /* UDI not implemented. */
1080 /* CP2 not implemented. */
1081
1082 // TODO: Handle FPU (CP1) binding.
1083
1084 env->CP0_VPEConf1 = newval;
1085 }
1086
1087 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1088 {
1089 /* Yield qualifier inputs not implemented. */
1090 env->CP0_YQMask = 0x00000000;
1091 }
1092
1093 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1094 {
1095 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1096 }
1097
1098 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1099
1100 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1101 {
1102 /* 1k pages not implemented */
1103 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1104 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1105 | (rxi << (CP0EnLo_XI - 30));
1106 }
1107
1108 #if defined(TARGET_MIPS64)
1109 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1110
1111 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1112 {
1113 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1114 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1115 }
1116 #endif
1117
1118 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1119 {
1120 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1121 uint32_t newval;
1122
1123 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1124
1125 env->active_tc.CP0_TCStatus = newval;
1126 sync_c0_tcstatus(env, env->current_tc, newval);
1127 }
1128
1129 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1130 {
1131 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1132 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1133
1134 if (other_tc == other->current_tc)
1135 other->active_tc.CP0_TCStatus = arg1;
1136 else
1137 other->tcs[other_tc].CP0_TCStatus = arg1;
1138 sync_c0_tcstatus(other, other_tc, arg1);
1139 }
1140
1141 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1142 {
1143 uint32_t mask = (1 << CP0TCBd_TBE);
1144 uint32_t newval;
1145
1146 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1147 mask |= (1 << CP0TCBd_CurVPE);
1148 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1149 env->active_tc.CP0_TCBind = newval;
1150 }
1151
1152 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1153 {
1154 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1155 uint32_t mask = (1 << CP0TCBd_TBE);
1156 uint32_t newval;
1157 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1158
1159 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1160 mask |= (1 << CP0TCBd_CurVPE);
1161 if (other_tc == other->current_tc) {
1162 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1163 other->active_tc.CP0_TCBind = newval;
1164 } else {
1165 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1166 other->tcs[other_tc].CP0_TCBind = newval;
1167 }
1168 }
1169
1170 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1171 {
1172 env->active_tc.PC = arg1;
1173 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1174 env->lladdr = 0ULL;
1175 /* MIPS16 not implemented. */
1176 }
1177
1178 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1179 {
1180 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1182
1183 if (other_tc == other->current_tc) {
1184 other->active_tc.PC = arg1;
1185 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1186 other->lladdr = 0ULL;
1187 /* MIPS16 not implemented. */
1188 } else {
1189 other->tcs[other_tc].PC = arg1;
1190 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1191 other->lladdr = 0ULL;
1192 /* MIPS16 not implemented. */
1193 }
1194 }
1195
1196 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1197 {
1198 MIPSCPU *cpu = mips_env_get_cpu(env);
1199
1200 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1201
1202 // TODO: Halt TC / Restart (if allocated+active) TC.
1203 if (env->active_tc.CP0_TCHalt & 1) {
1204 mips_tc_sleep(cpu, env->current_tc);
1205 } else {
1206 mips_tc_wake(cpu, env->current_tc);
1207 }
1208 }
1209
1210 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1211 {
1212 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1213 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1214 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1215
1216 // TODO: Halt TC / Restart (if allocated+active) TC.
1217
1218 if (other_tc == other->current_tc)
1219 other->active_tc.CP0_TCHalt = arg1;
1220 else
1221 other->tcs[other_tc].CP0_TCHalt = arg1;
1222
1223 if (arg1 & 1) {
1224 mips_tc_sleep(other_cpu, other_tc);
1225 } else {
1226 mips_tc_wake(other_cpu, other_tc);
1227 }
1228 }
1229
1230 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1231 {
1232 env->active_tc.CP0_TCContext = arg1;
1233 }
1234
1235 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1236 {
1237 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1238 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1239
1240 if (other_tc == other->current_tc)
1241 other->active_tc.CP0_TCContext = arg1;
1242 else
1243 other->tcs[other_tc].CP0_TCContext = arg1;
1244 }
1245
1246 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1247 {
1248 env->active_tc.CP0_TCSchedule = arg1;
1249 }
1250
1251 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1252 {
1253 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1254 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1255
1256 if (other_tc == other->current_tc)
1257 other->active_tc.CP0_TCSchedule = arg1;
1258 else
1259 other->tcs[other_tc].CP0_TCSchedule = arg1;
1260 }
1261
1262 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1263 {
1264 env->active_tc.CP0_TCScheFBack = arg1;
1265 }
1266
1267 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1268 {
1269 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1270 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1271
1272 if (other_tc == other->current_tc)
1273 other->active_tc.CP0_TCScheFBack = arg1;
1274 else
1275 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1276 }
1277
1278 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1279 {
1280 /* 1k pages not implemented */
1281 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1282 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1283 | (rxi << (CP0EnLo_XI - 30));
1284 }
1285
1286 #if defined(TARGET_MIPS64)
1287 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1288 {
1289 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1290 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1291 }
1292 #endif
1293
1294 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1295 {
1296 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1297 }
1298
1299 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1300 {
1301 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1302 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1303 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1304 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1305 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1306 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1307 }
1308 }
1309
1310 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1311 {
1312 /* SmartMIPS not implemented */
1313 /* 1k pages not implemented */
1314 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1315 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1316 compute_hflags(env);
1317 restore_pamask(env);
1318 }
1319
1320 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1321 {
1322 if (env->insn_flags & ISA_MIPS32R6) {
1323 if (arg1 < env->tlb->nb_tlb) {
1324 env->CP0_Wired = arg1;
1325 }
1326 } else {
1327 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1328 }
1329 }
1330
1331 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1332 {
1333 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1334 }
1335
1336 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1337 {
1338 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1339 }
1340
1341 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1342 {
1343 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1344 }
1345
1346 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1347 {
1348 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1349 }
1350
1351 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1352 {
1353 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1354 }
1355
1356 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1357 {
1358 uint32_t mask = 0x0000000F;
1359
1360 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1361 (env->insn_flags & ISA_MIPS32R6)) {
1362 mask |= (1 << 4);
1363 }
1364 if (env->insn_flags & ISA_MIPS32R6) {
1365 mask |= (1 << 5);
1366 }
1367 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1368 mask |= (1 << 29);
1369
1370 if (arg1 & (1 << 29)) {
1371 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1372 } else {
1373 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1374 }
1375 }
1376
1377 env->CP0_HWREna = arg1 & mask;
1378 }
1379
1380 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1381 {
1382 cpu_mips_store_count(env, arg1);
1383 }
1384
1385 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1386 {
1387 target_ulong old, val, mask;
1388 mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1389 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1390 mask |= 1 << CP0EnHi_EHINV;
1391 }
1392
1393 /* 1k pages not implemented */
1394 #if defined(TARGET_MIPS64)
1395 if (env->insn_flags & ISA_MIPS32R6) {
1396 int entryhi_r = extract64(arg1, 62, 2);
1397 int config0_at = extract32(env->CP0_Config0, 13, 2);
1398 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1399 if ((entryhi_r == 2) ||
1400 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1401 /* skip EntryHi.R field if new value is reserved */
1402 mask &= ~(0x3ull << 62);
1403 }
1404 }
1405 mask &= env->SEGMask;
1406 #endif
1407 old = env->CP0_EntryHi;
1408 val = (arg1 & mask) | (old & ~mask);
1409 env->CP0_EntryHi = val;
1410 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1411 sync_c0_entryhi(env, env->current_tc);
1412 }
1413 /* If the ASID changes, flush qemu's TLB. */
1414 if ((old & 0xFF) != (val & 0xFF))
1415 cpu_mips_tlb_flush(env, 1);
1416 }
1417
1418 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1419 {
1420 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1421 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1422
1423 other->CP0_EntryHi = arg1;
1424 sync_c0_entryhi(other, other_tc);
1425 }
1426
1427 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1428 {
1429 cpu_mips_store_compare(env, arg1);
1430 }
1431
1432 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1433 {
1434 MIPSCPU *cpu = mips_env_get_cpu(env);
1435 uint32_t val, old;
1436
1437 old = env->CP0_Status;
1438 cpu_mips_store_status(env, arg1);
1439 val = env->CP0_Status;
1440
1441 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1442 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1443 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1444 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1445 env->CP0_Cause);
1446 switch (env->hflags & MIPS_HFLAG_KSU) {
1447 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1448 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1449 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1450 default:
1451 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1452 break;
1453 }
1454 }
1455 }
1456
1457 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1458 {
1459 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1460 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1461 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1462
1463 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1464 sync_c0_status(env, other, other_tc);
1465 }
1466
1467 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1468 {
1469 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1470 }
1471
1472 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1473 {
1474 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1475 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1476 }
1477
1478 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1479 {
1480 cpu_mips_store_cause(env, arg1);
1481 }
1482
1483 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1484 {
1485 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1486 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1487
1488 cpu_mips_store_cause(other, arg1);
1489 }
1490
1491 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1492 {
1493 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1494 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1495
1496 return other->CP0_EPC;
1497 }
1498
1499 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1500 {
1501 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1502 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1503
1504 return other->CP0_EBase;
1505 }
1506
1507 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1508 {
1509 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1510 }
1511
1512 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1513 {
1514 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1515 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1516 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1517 }
1518
1519 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1520 {
1521 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1522 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1523
1524 switch (idx) {
1525 case 0: return other->CP0_Config0;
1526 case 1: return other->CP0_Config1;
1527 case 2: return other->CP0_Config2;
1528 case 3: return other->CP0_Config3;
1529 /* 4 and 5 are reserved. */
1530 case 6: return other->CP0_Config6;
1531 case 7: return other->CP0_Config7;
1532 default:
1533 break;
1534 }
1535 return 0;
1536 }
1537
1538 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1539 {
1540 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1541 }
1542
1543 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1544 {
1545 /* tertiary/secondary caches not implemented */
1546 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1547 }
1548
1549 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1550 {
1551 if (env->insn_flags & ASE_MICROMIPS) {
1552 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1553 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1554 }
1555 }
1556
1557 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1558 {
1559 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1560 (arg1 & env->CP0_Config4_rw_bitmask);
1561 }
1562
1563 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1564 {
1565 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1566 (arg1 & env->CP0_Config5_rw_bitmask);
1567 compute_hflags(env);
1568 }
1569
1570 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1571 {
1572 target_long mask = env->CP0_LLAddr_rw_bitmask;
1573 arg1 = arg1 << env->CP0_LLAddr_shift;
1574 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1575 }
1576
1577 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1578 {
1579 /* Watch exceptions for instructions, data loads, data stores
1580 not implemented. */
1581 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1582 }
1583
1584 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1585 {
1586 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1587 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1588 }
1589
1590 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1591 {
1592 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1593 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1594 }
1595
1596 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1597 {
1598 env->CP0_Framemask = arg1; /* XXX */
1599 }
1600
1601 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1602 {
1603 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1604 if (arg1 & (1 << CP0DB_DM))
1605 env->hflags |= MIPS_HFLAG_DM;
1606 else
1607 env->hflags &= ~MIPS_HFLAG_DM;
1608 }
1609
1610 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1611 {
1612 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1613 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1614 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1615
1616 /* XXX: Might be wrong, check with EJTAG spec. */
1617 if (other_tc == other->current_tc)
1618 other->active_tc.CP0_Debug_tcstatus = val;
1619 else
1620 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1621 other->CP0_Debug = (other->CP0_Debug &
1622 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1623 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1624 }
1625
1626 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1627 {
1628 env->CP0_Performance0 = arg1 & 0x000007ff;
1629 }
1630
1631 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1632 {
1633 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1634 }
1635
1636 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1637 {
1638 env->CP0_DataLo = arg1; /* XXX */
1639 }
1640
1641 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1642 {
1643 env->CP0_TagHi = arg1; /* XXX */
1644 }
1645
1646 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1647 {
1648 env->CP0_DataHi = arg1; /* XXX */
1649 }
1650
1651 /* MIPS MT functions */
1652 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1653 {
1654 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1655 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1656
1657 if (other_tc == other->current_tc)
1658 return other->active_tc.gpr[sel];
1659 else
1660 return other->tcs[other_tc].gpr[sel];
1661 }
1662
1663 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1664 {
1665 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1666 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1667
1668 if (other_tc == other->current_tc)
1669 return other->active_tc.LO[sel];
1670 else
1671 return other->tcs[other_tc].LO[sel];
1672 }
1673
1674 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1675 {
1676 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1677 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1678
1679 if (other_tc == other->current_tc)
1680 return other->active_tc.HI[sel];
1681 else
1682 return other->tcs[other_tc].HI[sel];
1683 }
1684
1685 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1686 {
1687 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1688 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1689
1690 if (other_tc == other->current_tc)
1691 return other->active_tc.ACX[sel];
1692 else
1693 return other->tcs[other_tc].ACX[sel];
1694 }
1695
1696 target_ulong helper_mftdsp(CPUMIPSState *env)
1697 {
1698 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1699 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1700
1701 if (other_tc == other->current_tc)
1702 return other->active_tc.DSPControl;
1703 else
1704 return other->tcs[other_tc].DSPControl;
1705 }
1706
1707 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1708 {
1709 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1710 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1711
1712 if (other_tc == other->current_tc)
1713 other->active_tc.gpr[sel] = arg1;
1714 else
1715 other->tcs[other_tc].gpr[sel] = arg1;
1716 }
1717
1718 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1719 {
1720 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1721 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1722
1723 if (other_tc == other->current_tc)
1724 other->active_tc.LO[sel] = arg1;
1725 else
1726 other->tcs[other_tc].LO[sel] = arg1;
1727 }
1728
1729 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1730 {
1731 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1732 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1733
1734 if (other_tc == other->current_tc)
1735 other->active_tc.HI[sel] = arg1;
1736 else
1737 other->tcs[other_tc].HI[sel] = arg1;
1738 }
1739
1740 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1741 {
1742 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1743 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1744
1745 if (other_tc == other->current_tc)
1746 other->active_tc.ACX[sel] = arg1;
1747 else
1748 other->tcs[other_tc].ACX[sel] = arg1;
1749 }
1750
1751 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1752 {
1753 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1754 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1755
1756 if (other_tc == other->current_tc)
1757 other->active_tc.DSPControl = arg1;
1758 else
1759 other->tcs[other_tc].DSPControl = arg1;
1760 }
1761
1762 /* MIPS MT functions */
1763 target_ulong helper_dmt(void)
1764 {
1765 // TODO
1766 return 0;
1767 }
1768
1769 target_ulong helper_emt(void)
1770 {
1771 // TODO
1772 return 0;
1773 }
1774
1775 target_ulong helper_dvpe(CPUMIPSState *env)
1776 {
1777 CPUState *other_cs = first_cpu;
1778 target_ulong prev = env->mvp->CP0_MVPControl;
1779
1780 CPU_FOREACH(other_cs) {
1781 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1782 /* Turn off all VPEs except the one executing the dvpe. */
1783 if (&other_cpu->env != env) {
1784 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1785 mips_vpe_sleep(other_cpu);
1786 }
1787 }
1788 return prev;
1789 }
1790
1791 target_ulong helper_evpe(CPUMIPSState *env)
1792 {
1793 CPUState *other_cs = first_cpu;
1794 target_ulong prev = env->mvp->CP0_MVPControl;
1795
1796 CPU_FOREACH(other_cs) {
1797 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1798
1799 if (&other_cpu->env != env
1800 /* If the VPE is WFI, don't disturb its sleep. */
1801 && !mips_vpe_is_wfi(other_cpu)) {
1802 /* Enable the VPE. */
1803 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1804 mips_vpe_wake(other_cpu); /* And wake it up. */
1805 }
1806 }
1807 return prev;
1808 }
1809 #endif /* !CONFIG_USER_ONLY */
1810
1811 void helper_fork(target_ulong arg1, target_ulong arg2)
1812 {
1813 // arg1 = rt, arg2 = rs
1814 // TODO: store to TC register
1815 }
1816
1817 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1818 {
1819 target_long arg1 = arg;
1820
1821 if (arg1 < 0) {
1822 /* No scheduling policy implemented. */
1823 if (arg1 != -2) {
1824 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1825 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1826 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1827 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1828 do_raise_exception(env, EXCP_THREAD, GETPC());
1829 }
1830 }
1831 } else if (arg1 == 0) {
1832 if (0 /* TODO: TC underflow */) {
1833 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1834 do_raise_exception(env, EXCP_THREAD, GETPC());
1835 } else {
1836 // TODO: Deallocate TC
1837 }
1838 } else if (arg1 > 0) {
1839 /* Yield qualifier inputs not implemented. */
1840 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1841 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1842 do_raise_exception(env, EXCP_THREAD, GETPC());
1843 }
1844 return env->CP0_YQMask;
1845 }
1846
1847 #ifndef CONFIG_USER_ONLY
1848 /* TLB management */
1849 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1850 {
1851 MIPSCPU *cpu = mips_env_get_cpu(env);
1852
1853 /* Flush qemu's TLB and discard all shadowed entries. */
1854 tlb_flush(CPU(cpu), flush_global);
1855 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1856 }
1857
1858 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1859 {
1860 /* Discard entries from env->tlb[first] onwards. */
1861 while (env->tlb->tlb_in_use > first) {
1862 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1863 }
1864 }
1865
1866 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1867 {
1868 #if defined(TARGET_MIPS64)
1869 return extract64(entrylo, 6, 54);
1870 #else
1871 return extract64(entrylo, 6, 24) | /* PFN */
1872 (extract64(entrylo, 32, 32) << 24); /* PFNX */
1873 #endif
1874 }
1875
1876 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1877 {
1878 r4k_tlb_t *tlb;
1879
1880 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1881 tlb = &env->tlb->mmu.r4k.tlb[idx];
1882 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1883 tlb->EHINV = 1;
1884 return;
1885 }
1886 tlb->EHINV = 0;
1887 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1888 #if defined(TARGET_MIPS64)
1889 tlb->VPN &= env->SEGMask;
1890 #endif
1891 tlb->ASID = env->CP0_EntryHi & 0xFF;
1892 tlb->PageMask = env->CP0_PageMask;
1893 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1894 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1895 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1896 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1897 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1898 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1899 tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
1900 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1901 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1902 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1903 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1904 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1905 tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
1906 }
1907
1908 void r4k_helper_tlbinv(CPUMIPSState *env)
1909 {
1910 int idx;
1911 r4k_tlb_t *tlb;
1912 uint8_t ASID = env->CP0_EntryHi & 0xFF;
1913
1914 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1915 tlb = &env->tlb->mmu.r4k.tlb[idx];
1916 if (!tlb->G && tlb->ASID == ASID) {
1917 tlb->EHINV = 1;
1918 }
1919 }
1920 cpu_mips_tlb_flush(env, 1);
1921 }
1922
1923 void r4k_helper_tlbinvf(CPUMIPSState *env)
1924 {
1925 int idx;
1926
1927 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1928 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1929 }
1930 cpu_mips_tlb_flush(env, 1);
1931 }
1932
1933 void r4k_helper_tlbwi(CPUMIPSState *env)
1934 {
1935 r4k_tlb_t *tlb;
1936 int idx;
1937 target_ulong VPN;
1938 uint8_t ASID;
1939 bool G, V0, D0, V1, D1;
1940
1941 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1942 tlb = &env->tlb->mmu.r4k.tlb[idx];
1943 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1944 #if defined(TARGET_MIPS64)
1945 VPN &= env->SEGMask;
1946 #endif
1947 ASID = env->CP0_EntryHi & 0xff;
1948 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1949 V0 = (env->CP0_EntryLo0 & 2) != 0;
1950 D0 = (env->CP0_EntryLo0 & 4) != 0;
1951 V1 = (env->CP0_EntryLo1 & 2) != 0;
1952 D1 = (env->CP0_EntryLo1 & 4) != 0;
1953
1954 /* Discard cached TLB entries, unless tlbwi is just upgrading access
1955 permissions on the current entry. */
1956 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1957 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1958 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1959 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1960 }
1961
1962 r4k_invalidate_tlb(env, idx, 0);
1963 r4k_fill_tlb(env, idx);
1964 }
1965
1966 void r4k_helper_tlbwr(CPUMIPSState *env)
1967 {
1968 int r = cpu_mips_get_random(env);
1969
1970 r4k_invalidate_tlb(env, r, 1);
1971 r4k_fill_tlb(env, r);
1972 }
1973
1974 void r4k_helper_tlbp(CPUMIPSState *env)
1975 {
1976 r4k_tlb_t *tlb;
1977 target_ulong mask;
1978 target_ulong tag;
1979 target_ulong VPN;
1980 uint8_t ASID;
1981 int i;
1982
1983 ASID = env->CP0_EntryHi & 0xFF;
1984 for (i = 0; i < env->tlb->nb_tlb; i++) {
1985 tlb = &env->tlb->mmu.r4k.tlb[i];
1986 /* 1k pages are not supported. */
1987 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1988 tag = env->CP0_EntryHi & ~mask;
1989 VPN = tlb->VPN & ~mask;
1990 #if defined(TARGET_MIPS64)
1991 tag &= env->SEGMask;
1992 #endif
1993 /* Check ASID, virtual page number & size */
1994 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
1995 /* TLB match */
1996 env->CP0_Index = i;
1997 break;
1998 }
1999 }
2000 if (i == env->tlb->nb_tlb) {
2001 /* No match. Discard any shadow entries, if any of them match. */
2002 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2003 tlb = &env->tlb->mmu.r4k.tlb[i];
2004 /* 1k pages are not supported. */
2005 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2006 tag = env->CP0_EntryHi & ~mask;
2007 VPN = tlb->VPN & ~mask;
2008 #if defined(TARGET_MIPS64)
2009 tag &= env->SEGMask;
2010 #endif
2011 /* Check ASID, virtual page number & size */
2012 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2013 r4k_mips_tlb_flush_extra (env, i);
2014 break;
2015 }
2016 }
2017
2018 env->CP0_Index |= 0x80000000;
2019 }
2020 }
2021
2022 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2023 {
2024 #if defined(TARGET_MIPS64)
2025 return tlb_pfn << 6;
2026 #else
2027 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2028 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2029 #endif
2030 }
2031
2032 void r4k_helper_tlbr(CPUMIPSState *env)
2033 {
2034 r4k_tlb_t *tlb;
2035 uint8_t ASID;
2036 int idx;
2037
2038 ASID = env->CP0_EntryHi & 0xFF;
2039 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2040 tlb = &env->tlb->mmu.r4k.tlb[idx];
2041
2042 /* If this will change the current ASID, flush qemu's TLB. */
2043 if (ASID != tlb->ASID)
2044 cpu_mips_tlb_flush (env, 1);
2045
2046 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2047
2048 if (tlb->EHINV) {
2049 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2050 env->CP0_PageMask = 0;
2051 env->CP0_EntryLo0 = 0;
2052 env->CP0_EntryLo1 = 0;
2053 } else {
2054 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2055 env->CP0_PageMask = tlb->PageMask;
2056 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2057 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2058 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2059 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2060 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2061 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2062 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2063 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2064 }
2065 }
2066
2067 void helper_tlbwi(CPUMIPSState *env)
2068 {
2069 env->tlb->helper_tlbwi(env);
2070 }
2071
2072 void helper_tlbwr(CPUMIPSState *env)
2073 {
2074 env->tlb->helper_tlbwr(env);
2075 }
2076
2077 void helper_tlbp(CPUMIPSState *env)
2078 {
2079 env->tlb->helper_tlbp(env);
2080 }
2081
2082 void helper_tlbr(CPUMIPSState *env)
2083 {
2084 env->tlb->helper_tlbr(env);
2085 }
2086
2087 void helper_tlbinv(CPUMIPSState *env)
2088 {
2089 env->tlb->helper_tlbinv(env);
2090 }
2091
2092 void helper_tlbinvf(CPUMIPSState *env)
2093 {
2094 env->tlb->helper_tlbinvf(env);
2095 }
2096
2097 /* Specials */
2098 target_ulong helper_di(CPUMIPSState *env)
2099 {
2100 target_ulong t0 = env->CP0_Status;
2101
2102 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2103 return t0;
2104 }
2105
2106 target_ulong helper_ei(CPUMIPSState *env)
2107 {
2108 target_ulong t0 = env->CP0_Status;
2109
2110 env->CP0_Status = t0 | (1 << CP0St_IE);
2111 return t0;
2112 }
2113
2114 static void debug_pre_eret(CPUMIPSState *env)
2115 {
2116 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2117 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2118 env->active_tc.PC, env->CP0_EPC);
2119 if (env->CP0_Status & (1 << CP0St_ERL))
2120 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2121 if (env->hflags & MIPS_HFLAG_DM)
2122 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2123 qemu_log("\n");
2124 }
2125 }
2126
2127 static void debug_post_eret(CPUMIPSState *env)
2128 {
2129 MIPSCPU *cpu = mips_env_get_cpu(env);
2130
2131 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2132 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2133 env->active_tc.PC, env->CP0_EPC);
2134 if (env->CP0_Status & (1 << CP0St_ERL))
2135 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2136 if (env->hflags & MIPS_HFLAG_DM)
2137 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2138 switch (env->hflags & MIPS_HFLAG_KSU) {
2139 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2140 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2141 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2142 default:
2143 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2144 break;
2145 }
2146 }
2147 }
2148
2149 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2150 {
2151 env->active_tc.PC = error_pc & ~(target_ulong)1;
2152 if (error_pc & 1) {
2153 env->hflags |= MIPS_HFLAG_M16;
2154 } else {
2155 env->hflags &= ~(MIPS_HFLAG_M16);
2156 }
2157 }
2158
2159 static inline void exception_return(CPUMIPSState *env)
2160 {
2161 debug_pre_eret(env);
2162 if (env->CP0_Status & (1 << CP0St_ERL)) {
2163 set_pc(env, env->CP0_ErrorEPC);
2164 env->CP0_Status &= ~(1 << CP0St_ERL);
2165 } else {
2166 set_pc(env, env->CP0_EPC);
2167 env->CP0_Status &= ~(1 << CP0St_EXL);
2168 }
2169 compute_hflags(env);
2170 debug_post_eret(env);
2171 }
2172
2173 void helper_eret(CPUMIPSState *env)
2174 {
2175 exception_return(env);
2176 env->lladdr = 1;
2177 }
2178
2179 void helper_eretnc(CPUMIPSState *env)
2180 {
2181 exception_return(env);
2182 }
2183
2184 void helper_deret(CPUMIPSState *env)
2185 {
2186 debug_pre_eret(env);
2187 set_pc(env, env->CP0_DEPC);
2188
2189 env->hflags &= ~MIPS_HFLAG_DM;
2190 compute_hflags(env);
2191 debug_post_eret(env);
2192 }
2193 #endif /* !CONFIG_USER_ONLY */
2194
2195 static inline void check_hwrena(CPUMIPSState *env, int reg)
2196 {
2197 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2198 return;
2199 }
2200 do_raise_exception(env, EXCP_RI, GETPC());
2201 }
2202
2203 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2204 {
2205 check_hwrena(env, 0);
2206 return env->CP0_EBase & 0x3ff;
2207 }
2208
2209 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2210 {
2211 check_hwrena(env, 1);
2212 return env->SYNCI_Step;
2213 }
2214
2215 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2216 {
2217 check_hwrena(env, 2);
2218 #ifdef CONFIG_USER_ONLY
2219 return env->CP0_Count;
2220 #else
2221 return (int32_t)cpu_mips_get_count(env);
2222 #endif
2223 }
2224
2225 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2226 {
2227 check_hwrena(env, 3);
2228 return env->CCRes;
2229 }
2230
2231 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2232 {
2233 check_hwrena(env, 4);
2234 return env->CP0_Performance0;
2235 }
2236
2237 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2238 {
2239 check_hwrena(env, 5);
2240 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2241 }
2242
2243 void helper_pmon(CPUMIPSState *env, int function)
2244 {
2245 function /= 2;
2246 switch (function) {
2247 case 2: /* TODO: char inbyte(int waitflag); */
2248 if (env->active_tc.gpr[4] == 0)
2249 env->active_tc.gpr[2] = -1;
2250 /* Fall through */
2251 case 11: /* TODO: char inbyte (void); */
2252 env->active_tc.gpr[2] = -1;
2253 break;
2254 case 3:
2255 case 12:
2256 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2257 break;
2258 case 17:
2259 break;
2260 case 158:
2261 {
2262 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2263 printf("%s", fmt);
2264 }
2265 break;
2266 }
2267 }
2268
2269 void helper_wait(CPUMIPSState *env)
2270 {
2271 CPUState *cs = CPU(mips_env_get_cpu(env));
2272
2273 cs->halted = 1;
2274 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2275 /* Last instruction in the block, PC was updated before
2276 - no need to recover PC and icount */
2277 raise_exception(env, EXCP_HLT);
2278 }
2279
2280 #if !defined(CONFIG_USER_ONLY)
2281
2282 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2283 int access_type, int is_user,
2284 uintptr_t retaddr)
2285 {
2286 MIPSCPU *cpu = MIPS_CPU(cs);
2287 CPUMIPSState *env = &cpu->env;
2288 int error_code = 0;
2289 int excp;
2290
2291 env->CP0_BadVAddr = addr;
2292
2293 if (access_type == MMU_DATA_STORE) {
2294 excp = EXCP_AdES;
2295 } else {
2296 excp = EXCP_AdEL;
2297 if (access_type == MMU_INST_FETCH) {
2298 error_code |= EXCP_INST_NOTAVAIL;
2299 }
2300 }
2301
2302 do_raise_exception_err(env, excp, error_code, retaddr);
2303 }
2304
2305 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2306 uintptr_t retaddr)
2307 {
2308 int ret;
2309
2310 ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2311 if (ret) {
2312 MIPSCPU *cpu = MIPS_CPU(cs);
2313 CPUMIPSState *env = &cpu->env;
2314
2315 do_raise_exception_err(env, cs->exception_index,
2316 env->error_code, retaddr);
2317 }
2318 }
2319
2320 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2321 bool is_write, bool is_exec, int unused,
2322 unsigned size)
2323 {
2324 MIPSCPU *cpu = MIPS_CPU(cs);
2325 CPUMIPSState *env = &cpu->env;
2326
2327 /*
2328 * Raising an exception with KVM enabled will crash because it won't be from
2329 * the main execution loop so the longjmp won't have a matching setjmp.
2330 * Until we can trigger a bus error exception through KVM lets just ignore
2331 * the access.
2332 */
2333 if (kvm_enabled()) {
2334 return;
2335 }
2336
2337 if (is_exec) {
2338 raise_exception(env, EXCP_IBE);
2339 } else {
2340 raise_exception(env, EXCP_DBE);
2341 }
2342 }
2343 #endif /* !CONFIG_USER_ONLY */
2344
2345 /* Complex FPU operations which may need stack space. */
2346
2347 #define FLOAT_TWO32 make_float32(1 << 30)
2348 #define FLOAT_TWO64 make_float64(1ULL << 62)
2349 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2350 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2351
2352 /* convert MIPS rounding mode in FCR31 to IEEE library */
2353 unsigned int ieee_rm[] = {
2354 float_round_nearest_even,
2355 float_round_to_zero,
2356 float_round_up,
2357 float_round_down
2358 };
2359
2360 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2361 {
2362 target_ulong arg1 = 0;
2363
2364 switch (reg) {
2365 case 0:
2366 arg1 = (int32_t)env->active_fpu.fcr0;
2367 break;
2368 case 1:
2369 /* UFR Support - Read Status FR */
2370 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2371 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2372 arg1 = (int32_t)
2373 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2374 } else {
2375 do_raise_exception(env, EXCP_RI, GETPC());
2376 }
2377 }
2378 break;
2379 case 5:
2380 /* FRE Support - read Config5.FRE bit */
2381 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2382 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2383 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2384 } else {
2385 helper_raise_exception(env, EXCP_RI);
2386 }
2387 }
2388 break;
2389 case 25:
2390 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2391 break;
2392 case 26:
2393 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2394 break;
2395 case 28:
2396 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2397 break;
2398 default:
2399 arg1 = (int32_t)env->active_fpu.fcr31;
2400 break;
2401 }
2402
2403 return arg1;
2404 }
2405
2406 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2407 {
2408 switch (fs) {
2409 case 1:
2410 /* UFR Alias - Reset Status FR */
2411 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2412 return;
2413 }
2414 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2415 env->CP0_Status &= ~(1 << CP0St_FR);
2416 compute_hflags(env);
2417 } else {
2418 do_raise_exception(env, EXCP_RI, GETPC());
2419 }
2420 break;
2421 case 4:
2422 /* UNFR Alias - Set Status FR */
2423 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2424 return;
2425 }
2426 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2427 env->CP0_Status |= (1 << CP0St_FR);
2428 compute_hflags(env);
2429 } else {
2430 do_raise_exception(env, EXCP_RI, GETPC());
2431 }
2432 break;
2433 case 5:
2434 /* FRE Support - clear Config5.FRE bit */
2435 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2436 return;
2437 }
2438 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2439 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2440 compute_hflags(env);
2441 } else {
2442 helper_raise_exception(env, EXCP_RI);
2443 }
2444 break;
2445 case 6:
2446 /* FRE Support - set Config5.FRE bit */
2447 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2448 return;
2449 }
2450 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2451 env->CP0_Config5 |= (1 << CP0C5_FRE);
2452 compute_hflags(env);
2453 } else {
2454 helper_raise_exception(env, EXCP_RI);
2455 }
2456 break;
2457 case 25:
2458 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2459 return;
2460 }
2461 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2462 ((arg1 & 0x1) << 23);
2463 break;
2464 case 26:
2465 if (arg1 & 0x007c0000)
2466 return;
2467 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2468 break;
2469 case 28:
2470 if (arg1 & 0x007c0000)
2471 return;
2472 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2473 ((arg1 & 0x4) << 22);
2474 break;
2475 case 31:
2476 if (env->insn_flags & ISA_MIPS32R6) {
2477 uint32_t mask = 0xfefc0000;
2478 env->active_fpu.fcr31 = (arg1 & ~mask) |
2479 (env->active_fpu.fcr31 & mask);
2480 } else if (!(arg1 & 0x007c0000)) {
2481 env->active_fpu.fcr31 = arg1;
2482 }
2483 break;
2484 default:
2485 return;
2486 }
2487 /* set rounding mode */
2488 restore_rounding_mode(env);
2489 /* set flush-to-zero mode */
2490 restore_flush_mode(env);
2491 set_float_exception_flags(0, &env->active_fpu.fp_status);
2492 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2493 do_raise_exception(env, EXCP_FPE, GETPC());
2494 }
2495
2496 int ieee_ex_to_mips(int xcpt)
2497 {
2498 int ret = 0;
2499 if (xcpt) {
2500 if (xcpt & float_flag_invalid) {
2501 ret |= FP_INVALID;
2502 }
2503 if (xcpt & float_flag_overflow) {
2504 ret |= FP_OVERFLOW;
2505 }
2506 if (xcpt & float_flag_underflow) {
2507 ret |= FP_UNDERFLOW;
2508 }
2509 if (xcpt & float_flag_divbyzero) {
2510 ret |= FP_DIV0;
2511 }
2512 if (xcpt & float_flag_inexact) {
2513 ret |= FP_INEXACT;
2514 }
2515 }
2516 return ret;
2517 }
2518
2519 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2520 {
2521 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2522
2523 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2524
2525 if (tmp) {
2526 set_float_exception_flags(0, &env->active_fpu.fp_status);
2527
2528 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2529 do_raise_exception(env, EXCP_FPE, pc);
2530 } else {
2531 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2532 }
2533 }
2534 }
2535
2536 /* Float support.
2537 Single precition routines have a "s" suffix, double precision a
2538 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2539 paired single lower "pl", paired single upper "pu". */
2540
2541 /* unary operations, modifying fp status */
2542 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2543 {
2544 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2545 update_fcr31(env, GETPC());
2546 return fdt0;
2547 }
2548
2549 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2550 {
2551 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2552 update_fcr31(env, GETPC());
2553 return fst0;
2554 }
2555
2556 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2557 {
2558 uint64_t fdt2;
2559
2560 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2561 update_fcr31(env, GETPC());
2562 return fdt2;
2563 }
2564
2565 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2566 {
2567 uint64_t fdt2;
2568
2569 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2570 update_fcr31(env, GETPC());
2571 return fdt2;
2572 }
2573
2574 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2575 {
2576 uint64_t fdt2;
2577
2578 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2579 update_fcr31(env, GETPC());
2580 return fdt2;
2581 }
2582
2583 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2584 {
2585 uint64_t dt2;
2586
2587 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2588 if (get_float_exception_flags(&env->active_fpu.fp_status)
2589 & (float_flag_invalid | float_flag_overflow)) {
2590 dt2 = FP_TO_INT64_OVERFLOW;
2591 }
2592 update_fcr31(env, GETPC());
2593 return dt2;
2594 }
2595
2596 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2597 {
2598 uint64_t dt2;
2599
2600 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2601 if (get_float_exception_flags(&env->active_fpu.fp_status)
2602 & (float_flag_invalid | float_flag_overflow)) {
2603 dt2 = FP_TO_INT64_OVERFLOW;
2604 }
2605 update_fcr31(env, GETPC());
2606 return dt2;
2607 }
2608
2609 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2610 {
2611 uint32_t fst2;
2612 uint32_t fsth2;
2613
2614 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2615 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2616 update_fcr31(env, GETPC());
2617 return ((uint64_t)fsth2 << 32) | fst2;
2618 }
2619
2620 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2621 {
2622 uint32_t wt2;
2623 uint32_t wth2;
2624 int excp, excph;
2625
2626 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2627 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2628 if (excp & (float_flag_overflow | float_flag_invalid)) {
2629 wt2 = FP_TO_INT32_OVERFLOW;
2630 }
2631
2632 set_float_exception_flags(0, &env->active_fpu.fp_status);
2633 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2634 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2635 if (excph & (float_flag_overflow | float_flag_invalid)) {
2636 wth2 = FP_TO_INT32_OVERFLOW;
2637 }
2638
2639 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2640 update_fcr31(env, GETPC());
2641
2642 return ((uint64_t)wth2 << 32) | wt2;
2643 }
2644
2645 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2646 {
2647 uint32_t fst2;
2648
2649 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2650 update_fcr31(env, GETPC());
2651 return fst2;
2652 }
2653
2654 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2655 {
2656 uint32_t fst2;
2657
2658 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2659 update_fcr31(env, GETPC());
2660 return fst2;
2661 }
2662
2663 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2664 {
2665 uint32_t fst2;
2666
2667 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2668 update_fcr31(env, GETPC());
2669 return fst2;
2670 }
2671
2672 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2673 {
2674 uint32_t wt2;
2675
2676 wt2 = wt0;
2677 update_fcr31(env, GETPC());
2678 return wt2;
2679 }
2680
2681 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2682 {
2683 uint32_t wt2;
2684
2685 wt2 = wth0;
2686 update_fcr31(env, GETPC());
2687 return wt2;
2688 }
2689
2690 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2691 {
2692 uint32_t wt2;
2693
2694 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2695 if (get_float_exception_flags(&env->active_fpu.fp_status)
2696 & (float_flag_invalid | float_flag_overflow)) {
2697 wt2 = FP_TO_INT32_OVERFLOW;
2698 }
2699 update_fcr31(env, GETPC());
2700 return wt2;
2701 }
2702
2703 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2704 {
2705 uint32_t wt2;
2706
2707 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2708 if (get_float_exception_flags(&env->active_fpu.fp_status)
2709 & (float_flag_invalid | float_flag_overflow)) {
2710 wt2 = FP_TO_INT32_OVERFLOW;
2711 }
2712 update_fcr31(env, GETPC());
2713 return wt2;
2714 }
2715
2716 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2717 {
2718 uint64_t dt2;
2719
2720 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2721 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2722 restore_rounding_mode(env);
2723 if (get_float_exception_flags(&env->active_fpu.fp_status)
2724 & (float_flag_invalid | float_flag_overflow)) {
2725 dt2 = FP_TO_INT64_OVERFLOW;
2726 }
2727 update_fcr31(env, GETPC());
2728 return dt2;
2729 }
2730
2731 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2732 {
2733 uint64_t dt2;
2734
2735 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2736 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2737 restore_rounding_mode(env);
2738 if (get_float_exception_flags(&env->active_fpu.fp_status)
2739 & (float_flag_invalid | float_flag_overflow)) {
2740 dt2 = FP_TO_INT64_OVERFLOW;
2741 }
2742 update_fcr31(env, GETPC());
2743 return dt2;
2744 }
2745
2746 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2747 {
2748 uint32_t wt2;
2749
2750 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2751 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2752 restore_rounding_mode(env);
2753 if (get_float_exception_flags(&env->active_fpu.fp_status)
2754 & (float_flag_invalid | float_flag_overflow)) {
2755 wt2 = FP_TO_INT32_OVERFLOW;
2756 }
2757 update_fcr31(env, GETPC());
2758 return wt2;
2759 }
2760
2761 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2762 {
2763 uint32_t wt2;
2764
2765 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2766 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2767 restore_rounding_mode(env);
2768 if (get_float_exception_flags(&env->active_fpu.fp_status)
2769 & (float_flag_invalid | float_flag_overflow)) {
2770 wt2 = FP_TO_INT32_OVERFLOW;
2771 }
2772 update_fcr31(env, GETPC());
2773 return wt2;
2774 }
2775
2776 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2777 {
2778 uint64_t dt2;
2779
2780 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2781 if (get_float_exception_flags(&env->active_fpu.fp_status)
2782 & (float_flag_invalid | float_flag_overflow)) {
2783 dt2 = FP_TO_INT64_OVERFLOW;
2784 }
2785 update_fcr31(env, GETPC());
2786 return dt2;
2787 }
2788
2789 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2790 {
2791 uint64_t dt2;
2792
2793 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2794 if (get_float_exception_flags(&env->active_fpu.fp_status)
2795 & (float_flag_invalid | float_flag_overflow)) {
2796 dt2 = FP_TO_INT64_OVERFLOW;
2797 }
2798 update_fcr31(env, GETPC());
2799 return dt2;
2800 }
2801
2802 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2803 {
2804 uint32_t wt2;
2805
2806 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2807 if (get_float_exception_flags(&env->active_fpu.fp_status)
2808 & (float_flag_invalid | float_flag_overflow)) {
2809 wt2 = FP_TO_INT32_OVERFLOW;
2810 }
2811 update_fcr31(env, GETPC());
2812 return wt2;
2813 }
2814
2815 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2816 {
2817 uint32_t wt2;
2818
2819 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2820 if (get_float_exception_flags(&env->active_fpu.fp_status)
2821 & (float_flag_invalid | float_flag_overflow)) {
2822 wt2 = FP_TO_INT32_OVERFLOW;
2823 }
2824 update_fcr31(env, GETPC());
2825 return wt2;
2826 }
2827
2828 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2829 {
2830 uint64_t dt2;
2831
2832 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2833 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2834 restore_rounding_mode(env);
2835 if (get_float_exception_flags(&env->active_fpu.fp_status)
2836 & (float_flag_invalid | float_flag_overflow)) {
2837 dt2 = FP_TO_INT64_OVERFLOW;
2838 }
2839 update_fcr31(env, GETPC());
2840 return dt2;
2841 }
2842
2843 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2844 {
2845 uint64_t dt2;
2846
2847 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2848 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2849 restore_rounding_mode(env);
2850 if (get_float_exception_flags(&env->active_fpu.fp_status)
2851 & (float_flag_invalid | float_flag_overflow)) {
2852 dt2 = FP_TO_INT64_OVERFLOW;
2853 }
2854 update_fcr31(env, GETPC());
2855 return dt2;
2856 }
2857
2858 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2859 {
2860 uint32_t wt2;
2861
2862 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2863 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2864 restore_rounding_mode(env);
2865 if (get_float_exception_flags(&env->active_fpu.fp_status)
2866 & (float_flag_invalid | float_flag_overflow)) {
2867 wt2 = FP_TO_INT32_OVERFLOW;
2868 }
2869 update_fcr31(env, GETPC());
2870 return wt2;
2871 }
2872
2873 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2874 {
2875 uint32_t wt2;
2876
2877 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2878 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2879 restore_rounding_mode(env);
2880 if (get_float_exception_flags(&env->active_fpu.fp_status)
2881 & (float_flag_invalid | float_flag_overflow)) {
2882 wt2 = FP_TO_INT32_OVERFLOW;
2883 }
2884 update_fcr31(env, GETPC());
2885 return wt2;
2886 }
2887
2888 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2889 {
2890 uint64_t dt2;
2891
2892 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2893 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2894 restore_rounding_mode(env);
2895 if (get_float_exception_flags(&env->active_fpu.fp_status)
2896 & (float_flag_invalid | float_flag_overflow)) {
2897 dt2 = FP_TO_INT64_OVERFLOW;
2898 }
2899 update_fcr31(env, GETPC());
2900 return dt2;
2901 }
2902
2903 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2904 {
2905 uint64_t dt2;
2906
2907 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2908 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2909 restore_rounding_mode(env);
2910 if (get_float_exception_flags(&env->active_fpu.fp_status)
2911 & (float_flag_invalid | float_flag_overflow)) {
2912 dt2 = FP_TO_INT64_OVERFLOW;
2913 }
2914 update_fcr31(env, GETPC());
2915 return dt2;
2916 }
2917
2918 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2919 {
2920 uint32_t wt2;
2921
2922 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2923 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2924 restore_rounding_mode(env);
2925 if (get_float_exception_flags(&env->active_fpu.fp_status)
2926 & (float_flag_invalid | float_flag_overflow)) {
2927 wt2 = FP_TO_INT32_OVERFLOW;
2928 }
2929 update_fcr31(env, GETPC());
2930 return wt2;
2931 }
2932
2933 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2934 {
2935 uint32_t wt2;
2936
2937 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2938 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2939 restore_rounding_mode(env);
2940 if (get_float_exception_flags(&env->active_fpu.fp_status)
2941 & (float_flag_invalid | float_flag_overflow)) {
2942 wt2 = FP_TO_INT32_OVERFLOW;
2943 }
2944 update_fcr31(env, GETPC());
2945 return wt2;
2946 }
2947
2948 /* unary operations, not modifying fp status */
2949 #define FLOAT_UNOP(name) \
2950 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2951 { \
2952 return float64_ ## name(fdt0); \
2953 } \
2954 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2955 { \
2956 return float32_ ## name(fst0); \
2957 } \
2958 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2959 { \
2960 uint32_t wt0; \
2961 uint32_t wth0; \
2962 \
2963 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2964 wth0 = float32_ ## name(fdt0 >> 32); \
2965 return ((uint64_t)wth0 << 32) | wt0; \
2966 }
2967 FLOAT_UNOP(abs)
2968 FLOAT_UNOP(chs)
2969 #undef FLOAT_UNOP
2970
2971 /* MIPS specific unary operations */
2972 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2973 {
2974 uint64_t fdt2;
2975
2976 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2977 update_fcr31(env, GETPC());
2978 return fdt2;
2979 }
2980
2981 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2982 {
2983 uint32_t fst2;
2984
2985 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2986 update_fcr31(env, GETPC());
2987 return fst2;
2988 }
2989
2990 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2991 {
2992 uint64_t fdt2;
2993
2994 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2995 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2996 update_fcr31(env, GETPC());
2997 return fdt2;
2998 }
2999
3000 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3001 {
3002 uint32_t fst2;
3003
3004 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3005 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3006 update_fcr31(env, GETPC());
3007 return fst2;
3008 }
3009
3010 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3011 {
3012 uint64_t fdt2;
3013
3014 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3015 update_fcr31(env, GETPC());
3016 return fdt2;
3017 }
3018
3019 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3020 {
3021 uint32_t fst2;
3022
3023 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3024 update_fcr31(env, GETPC());
3025 return fst2;
3026 }
3027
3028 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3029 {
3030 uint32_t fst2;
3031 uint32_t fsth2;
3032
3033 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3034 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3035 update_fcr31(env, GETPC());
3036 return ((uint64_t)fsth2 << 32) | fst2;
3037 }
3038
3039 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3040 {
3041 uint64_t fdt2;
3042
3043 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3044 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3045 update_fcr31(env, GETPC());
3046 return fdt2;
3047 }
3048
3049 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3050 {
3051 uint32_t fst2;
3052
3053 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3054 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3055 update_fcr31(env, GETPC());
3056 return fst2;
3057 }
3058
3059 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3060 {
3061 uint32_t fst2;
3062 uint32_t fsth2;
3063
3064 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3065 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3066 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3067 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3068 update_fcr31(env, GETPC());
3069 return ((uint64_t)fsth2 << 32) | fst2;
3070 }
3071
3072 #define FLOAT_RINT(name, bits) \
3073 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3074 uint ## bits ## _t fs) \
3075 { \
3076 uint ## bits ## _t fdret; \
3077 \
3078 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3079 update_fcr31(env, GETPC()); \
3080 return fdret; \
3081 }
3082
3083 FLOAT_RINT(rint_s, 32)
3084 FLOAT_RINT(rint_d, 64)
3085 #undef FLOAT_RINT
3086
3087 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3088 #define FLOAT_CLASS_QUIET_NAN 0x002
3089 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3090 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3091 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3092 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3093 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3094 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3095 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3096 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3097
3098 #define FLOAT_CLASS(name, bits) \
3099 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
3100 { \
3101 if (float ## bits ## _is_signaling_nan(arg)) { \
3102 return FLOAT_CLASS_SIGNALING_NAN; \
3103 } else if (float ## bits ## _is_quiet_nan(arg)) { \
3104 return FLOAT_CLASS_QUIET_NAN; \
3105 } else if (float ## bits ## _is_neg(arg)) { \
3106 if (float ## bits ## _is_infinity(arg)) { \
3107 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3108 } else if (float ## bits ## _is_zero(arg)) { \
3109 return FLOAT_CLASS_NEGATIVE_ZERO; \
3110 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3111 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3112 } else { \
3113 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3114 } \
3115 } else { \
3116 if (float ## bits ## _is_infinity(arg)) { \
3117 return FLOAT_CLASS_POSITIVE_INFINITY; \
3118 } else if (float ## bits ## _is_zero(arg)) { \
3119 return FLOAT_CLASS_POSITIVE_ZERO; \
3120 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3121 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3122 } else { \
3123 return FLOAT_CLASS_POSITIVE_NORMAL; \
3124 } \
3125 } \
3126 }
3127
3128 FLOAT_CLASS(class_s, 32)
3129 FLOAT_CLASS(class_d, 64)
3130 #undef FLOAT_CLASS
3131
3132 /* binary operations */
3133 #define FLOAT_BINOP(name) \
3134 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3135 uint64_t fdt0, uint64_t fdt1) \
3136 { \
3137 uint64_t dt2; \
3138 \
3139 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3140 update_fcr31(env, GETPC()); \
3141 return dt2; \
3142 } \
3143 \
3144 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3145 uint32_t fst0, uint32_t fst1) \
3146 { \
3147 uint32_t wt2; \
3148 \
3149 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3150 update_fcr31(env, GETPC()); \
3151 return wt2; \
3152 } \
3153 \
3154 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3155 uint64_t fdt0, \
3156 uint64_t fdt1) \
3157 { \
3158 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3159 uint32_t fsth0 = fdt0 >> 32; \
3160 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3161 uint32_t fsth1 = fdt1 >> 32; \
3162 uint32_t wt2; \
3163 uint32_t wth2; \
3164 \
3165 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3166 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3167 update_fcr31(env, GETPC()); \
3168 return ((uint64_t)wth2 << 32) | wt2; \
3169 }
3170
3171 FLOAT_BINOP(add)
3172 FLOAT_BINOP(sub)
3173 FLOAT_BINOP(mul)
3174 FLOAT_BINOP(div)
3175 #undef FLOAT_BINOP
3176
3177 /* MIPS specific binary operations */
3178 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3179 {
3180 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3181 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3182 update_fcr31(env, GETPC());
3183 return fdt2;
3184 }
3185
3186 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3187 {
3188 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3189 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3190 update_fcr31(env, GETPC());
3191 return fst2;
3192 }
3193
3194 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3195 {
3196 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3197 uint32_t fsth0 = fdt0 >> 32;
3198 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3199 uint32_t fsth2 = fdt2 >> 32;
3200
3201 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3202 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3203 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3204 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3205 update_fcr31(env, GETPC());
3206 return ((uint64_t)fsth2 << 32) | fst2;
3207 }
3208
3209 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3210 {
3211 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3212 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3213 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3214 update_fcr31(env, GETPC());
3215 return fdt2;
3216 }
3217
3218 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3219 {
3220 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3221 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3222 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3223 update_fcr31(env, GETPC());
3224 return fst2;
3225 }
3226
3227 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3228 {
3229 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3230 uint32_t fsth0 = fdt0 >> 32;
3231 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3232 uint32_t fsth2 = fdt2 >> 32;
3233
3234 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3235 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3236 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3237 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3238 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3239 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3240 update_fcr31(env, GETPC());
3241 return ((uint64_t)fsth2 << 32) | fst2;
3242 }
3243
3244 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3245 {
3246 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3247 uint32_t fsth0 = fdt0 >> 32;
3248 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3249 uint32_t fsth1 = fdt1 >> 32;
3250 uint32_t fst2;
3251 uint32_t fsth2;
3252
3253 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3254 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3255 update_fcr31(env, GETPC());
3256 return ((uint64_t)fsth2 << 32) | fst2;
3257 }
3258
3259 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3260 {
3261 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3262 uint32_t fsth0 = fdt0 >> 32;
3263 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3264 uint32_t fsth1 = fdt1 >> 32;
3265 uint32_t fst2;
3266 uint32_t fsth2;
3267
3268 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3269 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3270 update_fcr31(env, GETPC());
3271 return ((uint64_t)fsth2 << 32) | fst2;
3272 }
3273
3274 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3275 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3276 uint ## bits ## _t fs, \
3277 uint ## bits ## _t ft) \
3278 { \
3279 uint ## bits ## _t fdret; \
3280 \
3281 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3282 &env->active_fpu.fp_status); \
3283 update_fcr31(env, GETPC()); \
3284 return fdret; \
3285 }
3286
3287 FLOAT_MINMAX(max_s, 32, maxnum)
3288 FLOAT_MINMAX(max_d, 64, maxnum)
3289 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3290 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3291
3292 FLOAT_MINMAX(min_s, 32, minnum)
3293 FLOAT_MINMAX(min_d, 64, minnum)
3294 FLOAT_MINMAX(mina_s, 32, minnummag)
3295 FLOAT_MINMAX(mina_d, 64, minnummag)
3296 #undef FLOAT_MINMAX
3297
3298 /* ternary operations */
3299 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3300 { \
3301 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3302 if ((flags) & float_muladd_negate_c) { \
3303 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3304 } else { \
3305 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3306 } \
3307 if ((flags) & float_muladd_negate_result) { \
3308 a = prefix##_chs(a); \
3309 } \
3310 }
3311
3312 /* FMA based operations */
3313 #define FLOAT_FMA(name, type) \
3314 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3315 uint64_t fdt0, uint64_t fdt1, \
3316 uint64_t fdt2) \
3317 { \
3318 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3319 update_fcr31(env, GETPC()); \
3320 return fdt0; \
3321 } \
3322 \
3323 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3324 uint32_t fst0, uint32_t fst1, \
3325 uint32_t fst2) \
3326 { \
3327 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3328 update_fcr31(env, GETPC()); \
3329 return fst0; \
3330 } \
3331 \
3332 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3333 uint64_t fdt0, uint64_t fdt1, \
3334 uint64_t fdt2) \
3335 { \
3336 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3337 uint32_t fsth0 = fdt0 >> 32; \
3338 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3339 uint32_t fsth1 = fdt1 >> 32; \
3340 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3341 uint32_t fsth2 = fdt2 >> 32; \
3342 \
3343 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3344 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3345 update_fcr31(env, GETPC()); \
3346 return ((uint64_t)fsth0 << 32) | fst0; \
3347 }
3348 FLOAT_FMA(madd, 0)
3349 FLOAT_FMA(msub, float_muladd_negate_c)
3350 FLOAT_FMA(nmadd, float_muladd_negate_result)
3351 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3352 #undef FLOAT_FMA
3353
3354 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3355 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3356 uint ## bits ## _t fs, \
3357 uint ## bits ## _t ft, \
3358 uint ## bits ## _t fd) \
3359 { \
3360 uint ## bits ## _t fdret; \
3361 \
3362 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3363 &env->active_fpu.fp_status); \
3364 update_fcr31(env, GETPC()); \
3365 return fdret; \
3366 }
3367
3368 FLOAT_FMADDSUB(maddf_s, 32, 0)
3369 FLOAT_FMADDSUB(maddf_d, 64, 0)
3370 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3371 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3372 #undef FLOAT_FMADDSUB
3373
3374 /* compare operations */
3375 #define FOP_COND_D(op, cond) \
3376 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3377 uint64_t fdt1, int cc) \
3378 { \
3379 int c; \
3380 c = cond; \
3381 update_fcr31(env, GETPC()); \
3382 if (c) \
3383 SET_FP_COND(cc, env->active_fpu); \
3384 else \
3385 CLEAR_FP_COND(cc, env->active_fpu); \
3386 } \
3387 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3388 uint64_t fdt1, int cc) \
3389 { \
3390 int c; \
3391 fdt0 = float64_abs(fdt0); \
3392 fdt1 = float64_abs(fdt1); \
3393 c = cond; \
3394 update_fcr31(env, GETPC()); \
3395 if (c) \
3396 SET_FP_COND(cc, env->active_fpu); \
3397 else \
3398 CLEAR_FP_COND(cc, env->active_fpu); \
3399 }
3400
3401 /* NOTE: the comma operator will make "cond" to eval to false,
3402 * but float64_unordered_quiet() is still called. */
3403 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3404 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3405 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3406 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3407 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3408 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3409 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3410 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3411 /* NOTE: the comma operator will make "cond" to eval to false,
3412 * but float64_unordered() is still called. */
3413 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3414 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3415 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3416 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3417 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3418 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3419 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3420 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3421
3422 #define FOP_COND_S(op, cond) \
3423 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3424 uint32_t fst1, int cc) \
3425 { \
3426 int c; \
3427 c = cond; \
3428 update_fcr31(env, GETPC()); \
3429 if (c) \
3430 SET_FP_COND(cc, env->active_fpu); \
3431 else \
3432 CLEAR_FP_COND(cc, env->active_fpu); \
3433 } \
3434 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3435 uint32_t fst1, int cc) \
3436 { \
3437 int c; \
3438 fst0 = float32_abs(fst0); \
3439 fst1 = float32_abs(fst1); \
3440 c = cond; \
3441 update_fcr31(env, GETPC()); \
3442 if (c) \
3443 SET_FP_COND(cc, env->active_fpu); \
3444 else \
3445 CLEAR_FP_COND(cc, env->active_fpu); \
3446 }
3447
3448 /* NOTE: the comma operator will make "cond" to eval to false,
3449 * but float32_unordered_quiet() is still called. */
3450 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3451 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3452 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3453 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3454 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3455 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3456 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3457 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3458 /* NOTE: the comma operator will make "cond" to eval to false,
3459 * but float32_unordered() is still called. */
3460 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3461 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3462 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3463 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3464 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3465 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3466 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3467 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3468
3469 #define FOP_COND_PS(op, condl, condh) \
3470 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3471 uint64_t fdt1, int cc) \
3472 { \
3473 uint32_t fst0, fsth0, fst1, fsth1; \
3474 int ch, cl; \
3475 fst0 = fdt0 & 0XFFFFFFFF; \
3476 fsth0 = fdt0 >> 32; \
3477 fst1 = fdt1 & 0XFFFFFFFF; \
3478 fsth1 = fdt1 >> 32; \
3479 cl = condl; \
3480 ch = condh; \
3481 update_fcr31(env, GETPC()); \
3482 if (cl) \
3483 SET_FP_COND(cc, env->active_fpu); \
3484 else \
3485 CLEAR_FP_COND(cc, env->active_fpu); \
3486 if (ch) \
3487 SET_FP_COND(cc + 1, env->active_fpu); \
3488 else \
3489 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3490 } \
3491 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3492 uint64_t fdt1, int cc) \
3493 { \
3494 uint32_t fst0, fsth0, fst1, fsth1; \
3495 int ch, cl; \
3496 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3497 fsth0 = float32_abs(fdt0 >> 32); \
3498 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3499 fsth1 = float32_abs(fdt1 >> 32); \
3500 cl = condl; \
3501 ch = condh; \
3502 update_fcr31(env, GETPC()); \
3503 if (cl) \
3504 SET_FP_COND(cc, env->active_fpu); \
3505 else \
3506 CLEAR_FP_COND(cc, env->active_fpu); \
3507 if (ch) \
3508 SET_FP_COND(cc + 1, env->active_fpu); \
3509 else \
3510 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3511 }
3512
3513 /* NOTE: the comma operator will make "cond" to eval to false,
3514 * but float32_unordered_quiet() is still called. */
3515 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3516 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3517 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3518 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3519 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3520 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3521 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3522 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3523 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3524 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3525 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3526 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3527 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3528 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3529 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3530 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3531 /* NOTE: the comma operator will make "cond" to eval to false,
3532 * but float32_unordered() is still called. */
3533 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3534 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3535 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3536 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3537 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3538 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3539 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3540 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3541 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3542 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3543 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3544 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3545 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
3546 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3547 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3548 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3549
3550 /* R6 compare operations */
3551 #define FOP_CONDN_D(op, cond) \
3552 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3553 uint64_t fdt1) \
3554 { \
3555 uint64_t c; \
3556 c = cond; \
3557 update_fcr31(env, GETPC()); \
3558 if (c) { \
3559 return -1; \
3560 } else { \
3561 return 0; \
3562 } \
3563 }
3564
3565 /* NOTE: the comma operator will make "cond" to eval to false,
3566 * but float64_unordered_quiet() is still called. */
3567 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3568 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3569 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3570 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3571 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3572 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3573 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3574 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3575 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3576 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3577 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3578 /* NOTE: the comma operator will make "cond" to eval to false,
3579 * but float64_unordered() is still called. */
3580 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3581 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3582 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3583 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3584 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3585 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3586 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3587 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3588 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3589 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3590 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3591 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3592 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3593 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3594 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3595 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3596 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3597 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3598 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3599 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3600 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3601 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3602 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3603 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3604 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3605
3606 #define FOP_CONDN_S(op, cond) \
3607 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
3608 uint32_t fst1) \
3609 { \
3610 uint64_t c; \
3611 c = cond; \
3612 update_fcr31(env, GETPC()); \
3613 if (c) { \
3614 return -1; \
3615 } else { \
3616 return 0; \
3617 } \
3618 }
3619
3620 /* NOTE: the comma operator will make "cond" to eval to false,
3621 * but float32_unordered_quiet() is still called. */
3622 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3623 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3624 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3625 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3626 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3627 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3628 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3629 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3630 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3631 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3632 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3633 /* NOTE: the comma operator will make "cond" to eval to false,
3634 * but float32_unordered() is still called. */
3635 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3636 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3637 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3638 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3639 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3640 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3641 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3642 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3643 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3644 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3645 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3646 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3647 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3648 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3649 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3650 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3651 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3652 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3653 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3654 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3655 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3656 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3657 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3658 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3659 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3660
3661 /* MSA */
3662 /* Data format min and max values */
3663 #define DF_BITS(df) (1 << ((df) + 3))
3664
3665 /* Element-by-element access macros */
3666 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3667
3668 #if !defined(CONFIG_USER_ONLY)
3669 #define MEMOP_IDX(DF) \
3670 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
3671 cpu_mmu_index(env, false));
3672 #else
3673 #define MEMOP_IDX(DF)
3674 #endif
3675
3676 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
3677 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3678 target_ulong addr) \
3679 { \
3680 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3681 wr_t wx; \
3682 int i; \
3683 MEMOP_IDX(DF) \
3684 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3685 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
3686 } \
3687 memcpy(pwd, &wx, sizeof(wr_t)); \
3688 }
3689
3690 #if !defined(CONFIG_USER_ONLY)
3691 MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETRA())
3692 MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETRA())
3693 MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETRA())
3694 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETRA())
3695 #else
3696 MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
3697 MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
3698 MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
3699 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3700 #endif
3701
3702 #define MSA_PAGESPAN(x) \
3703 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3704
3705 static inline void ensure_writable_pages(CPUMIPSState *env,
3706 target_ulong addr,
3707 int mmu_idx,
3708 uintptr_t retaddr)
3709 {
3710 #if !defined(CONFIG_USER_ONLY)
3711 target_ulong page_addr;
3712 if (unlikely(MSA_PAGESPAN(addr))) {
3713 /* first page */
3714 probe_write(env, addr, mmu_idx, retaddr);
3715 /* second page */
3716 page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3717 probe_write(env, page_addr, mmu_idx, retaddr);
3718 }
3719 #endif
3720 }
3721
3722 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
3723 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3724 target_ulong addr) \
3725 { \
3726 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3727 int mmu_idx = cpu_mmu_index(env, false); \
3728 int i; \
3729 MEMOP_IDX(DF) \
3730 ensure_writable_pages(env, addr, mmu_idx, GETRA()); \
3731 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3732 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
3733 } \
3734 }
3735
3736 #if !defined(CONFIG_USER_ONLY)
3737 MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETRA())
3738 MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETRA())
3739 MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETRA())
3740 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3741 #else
3742 MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
3743 MSA_ST_DF(DF_HALF, h, cpu_stw_data)
3744 MSA_ST_DF(DF_WORD, w, cpu_stl_data)
3745 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3746 #endif
CRIS target port of Qemu