include/exec/cpu-common.h

   1 #ifndef CPU_COMMON_H
   2 #define CPU_COMMON_H 1
   3
   4 /* CPU interfaces that are target independent.  */
   5
   6 #ifndef CONFIG_USER_ONLY
   7 #include "exec/hwaddr.h"
   8 #endif
   9
  10 #ifndef NEED_CPU_H
  11 #include "exec/poison.h"
  12 #endif
  13
  14 #include "qemu/bswap.h"
  15 #include "qemu/queue.h"
  16 #include "qemu/fprintf-fn.h"
  17 #include "qemu/typedefs.h"
  18
  19 /**
  20  * CPUListState:
  21  * @cpu_fprintf: Print function.
  22  * @file: File to print to using @cpu_fprint.
  23  *
  24  * State commonly used for iterating over CPU models.
  25  */
  26 typedef struct CPUListState {
  27     fprintf_function cpu_fprintf;
  28     FILE *file;
  29 } CPUListState;
  30
  31 typedef enum MMUAccessType {
  32     MMU_DATA_LOAD  = 0,
  33     MMU_DATA_STORE = 1,
  34     MMU_INST_FETCH = 2
  35 } MMUAccessType;
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 enum device_endian {
  40     DEVICE_NATIVE_ENDIAN,
  41     DEVICE_BIG_ENDIAN,
  42     DEVICE_LITTLE_ENDIAN,
  43 };
  44
  45 /* address in the RAM (different from a physical address) */
  46 #if defined(CONFIG_XEN_BACKEND)
  47 typedef uint64_t ram_addr_t;
  48 #  define RAM_ADDR_MAX UINT64_MAX
  49 #  define RAM_ADDR_FMT "%" PRIx64
  50 #else
  51 typedef uintptr_t ram_addr_t;
  52 #  define RAM_ADDR_MAX UINTPTR_MAX
  53 #  define RAM_ADDR_FMT "%" PRIxPTR
  54 #endif
  55
  56 extern ram_addr_t ram_size;
  57 ram_addr_t get_current_ram_size(void);
  58
  59 /* memory API */
  60
  61 typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
  62 typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
  63
  64 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
  65 /* This should not be used by devices.  */
  66 MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
  67 void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
  68 void qemu_ram_unset_idstr(ram_addr_t addr);
  69
  70 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
  71                             int len, int is_write);
  72 static inline void cpu_physical_memory_read(hwaddr addr,
  73                                             void *buf, int len)
  74 {
  75     cpu_physical_memory_rw(addr, buf, len, 0);
  76 }
  77 static inline void cpu_physical_memory_write(hwaddr addr,
  78                                              const void *buf, int len)
  79 {
  80     cpu_physical_memory_rw(addr, (void *)buf, len, 1);
  81 }
  82 void *cpu_physical_memory_map(hwaddr addr,
  83                               hwaddr *plen,
  84                               int is_write);
  85 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
  86                                int is_write, hwaddr access_len);
  87 void cpu_register_map_client(QEMUBH *bh);
  88 void cpu_unregister_map_client(QEMUBH *bh);
  89
  90 bool cpu_physical_memory_is_io(hwaddr phys_addr);
  91
  92 /* Coalesced MMIO regions are areas where write operations can be reordered.
  93  * This usually implies that write operations are side-effect free.  This allows
  94  * batching which can make a major impact on performance when using
  95  * virtualization.
  96  */
  97 void qemu_flush_coalesced_mmio_buffer(void);
  98
  99 uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
 100 uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr);
 101 uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr);
 102 uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
 103 uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
 104 uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
 105 uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
 106 void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 107 void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 108 void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 109 void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 110 void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 111 void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
 112 void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
 113
 114 #ifdef NEED_CPU_H
 115 uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
 116 uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
 117 uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
 118 void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
 119 void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 120 void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 121 void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
 122 #endif
 123
 124 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
 125                                    const uint8_t *buf, int len);
 126 void cpu_flush_icache_range(hwaddr start, int len);
 127
 128 extern struct MemoryRegion io_mem_rom;
 129 extern struct MemoryRegion io_mem_notdirty;
 130
 131 typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
 132     ram_addr_t offset, ram_addr_t length, void *opaque);
 133
 134 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
 135
 136 #endif
 137
 138 #endif /* !CPU_COMMON_H */