2 * TI OMAP general purpose memory controller emulation.
4 * Copyright (C) 2007-2009 Nokia Corporation
5 * Original code written by Andrzej Zaborowski <andrew@openedhand.com>
6 * Enhancements for OMAP3 and NAND support written by Juha Riihimäki
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) any later version of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "exec-memory.h"
27 /* General-Purpose Memory Controller */
37 uint32_t prefconfig
[2];
41 struct omap_gpmc_cs_file_s
{
44 MemoryRegion container
;
52 static void omap_gpmc_int_update(struct omap_gpmc_s
*s
)
54 qemu_set_irq(s
->irq
, s
->irqen
& s
->irqst
);
57 static void omap_gpmc_cs_map(struct omap_gpmc_s
*s
, int cs
)
59 struct omap_gpmc_cs_file_s
*f
= &s
->cs_file
[cs
];
60 uint32_t mask
= (f
->config
[6] >> 8) & 0xf;
61 uint32_t base
= f
->config
[6] & 0x3f;
68 if (!(f
->config
[6] & (1 << 6))) {
69 /* Do nothing unless CSVALID */
73 /* TODO: check for overlapping regions and report access errors */
74 if ((mask
!= 0x8 && mask
!= 0xc && mask
!= 0xe && mask
!= 0xf) ||
75 (base
& 0x0f & ~mask
)) {
76 fprintf(stderr
, "%s: wrong cs address mapping/decoding!\n",
82 size
= (0x0fffffff & ~(mask
<< 24)) + 1;
83 /* TODO: rather than setting the size of the mapping (which should be
84 * constant), the mask should cause wrapping of the address space, so
85 * that the same memory becomes accessible at every <i>size</i> bytes
86 * starting from <i>base</i>. */
87 memory_region_init(&f
->container
, "omap-gpmc-file", size
);
88 memory_region_add_subregion(&f
->container
, 0, f
->iomem
);
89 memory_region_add_subregion(get_system_memory(), base
,
93 static void omap_gpmc_cs_unmap(struct omap_gpmc_s
*s
, int cs
)
95 struct omap_gpmc_cs_file_s
*f
= &s
->cs_file
[cs
];
96 if (!(f
->config
[6] & (1 << 6))) {
97 /* Do nothing unless CSVALID */
104 memory_region_del_subregion(get_system_memory(), &f
->container
);
105 memory_region_del_subregion(&f
->container
, f
->iomem
);
106 memory_region_destroy(&f
->container
);
109 void omap_gpmc_reset(struct omap_gpmc_s
*s
)
116 omap_gpmc_int_update(s
);
119 s
->prefconfig
[0] = 0x00004000;
120 s
->prefconfig
[1] = 0x00000000;
124 for (i
= 0; i
< 8; i
++) {
125 omap_gpmc_cs_unmap(s
, i
);
126 s
->cs_file
[i
].config
[1] = 0x101001;
127 s
->cs_file
[i
].config
[2] = 0x020201;
128 s
->cs_file
[i
].config
[3] = 0x10031003;
129 s
->cs_file
[i
].config
[4] = 0x10f1111;
130 s
->cs_file
[i
].config
[5] = 0;
131 s
->cs_file
[i
].config
[6] = 0xf00 | (i
? 0 : 1 << 6);
133 s
->cs_file
[i
].config
[6] = 0xf00;
134 /* In theory we could probe attached devices for some CFG1
135 * bits here, but we just retain them across resets as they
136 * were set initially by omap_gpmc_attach().
139 s
->cs_file
[i
].config
[0] &= 0x00433e00;
140 s
->cs_file
[i
].config
[6] |= 1 << 6; /* CSVALID */
141 omap_gpmc_cs_map(s
, i
);
143 s
->cs_file
[i
].config
[0] &= 0x00403c00;
148 s
->ecc_cfg
= 0x3fcff000;
149 for (i
= 0; i
< 9; i
++)
150 ecc_reset(&s
->ecc
[i
]);
153 static uint64_t omap_gpmc_read(void *opaque
, target_phys_addr_t addr
,
156 struct omap_gpmc_s
*s
= (struct omap_gpmc_s
*) opaque
;
158 struct omap_gpmc_cs_file_s
*f
;
161 return omap_badwidth_read32(opaque
, addr
);
165 case 0x000: /* GPMC_REVISION */
168 case 0x010: /* GPMC_SYSCONFIG */
171 case 0x014: /* GPMC_SYSSTATUS */
172 return 1; /* RESETDONE */
174 case 0x018: /* GPMC_IRQSTATUS */
177 case 0x01c: /* GPMC_IRQENABLE */
180 case 0x040: /* GPMC_TIMEOUT_CONTROL */
183 case 0x044: /* GPMC_ERR_ADDRESS */
184 case 0x048: /* GPMC_ERR_TYPE */
187 case 0x050: /* GPMC_CONFIG */
190 case 0x054: /* GPMC_STATUS */
193 case 0x060 ... 0x1d4:
194 cs
= (addr
- 0x060) / 0x30;
198 case 0x60: /* GPMC_CONFIG1 */
200 case 0x64: /* GPMC_CONFIG2 */
202 case 0x68: /* GPMC_CONFIG3 */
204 case 0x6c: /* GPMC_CONFIG4 */
206 case 0x70: /* GPMC_CONFIG5 */
208 case 0x74: /* GPMC_CONFIG6 */
210 case 0x78: /* GPMC_CONFIG7 */
212 case 0x84: /* GPMC_NAND_DATA */
217 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
218 return s
->prefconfig
[0];
219 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
220 return s
->prefconfig
[1];
221 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
222 return s
->prefcontrol
;
223 case 0x1f0: /* GPMC_PREFETCH_STATUS */
224 return (s
->preffifo
<< 24) |
226 ((s
->prefconfig
[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
229 case 0x1f4: /* GPMC_ECC_CONFIG */
231 case 0x1f8: /* GPMC_ECC_CONTROL */
233 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
235 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
236 cs
= (addr
& 0x1f) >> 2;
237 /* TODO: check correctness */
239 ((s
->ecc
[cs
].cp
& 0x07) << 0) |
240 ((s
->ecc
[cs
].cp
& 0x38) << 13) |
241 ((s
->ecc
[cs
].lp
[0] & 0x1ff) << 3) |
242 ((s
->ecc
[cs
].lp
[1] & 0x1ff) << 19);
244 case 0x230: /* GPMC_TESTMODE_CTRL */
246 case 0x234: /* GPMC_PSA_LSB */
247 case 0x238: /* GPMC_PSA_MSB */
255 static void omap_gpmc_write(void *opaque
, target_phys_addr_t addr
,
256 uint64_t value
, unsigned size
)
258 struct omap_gpmc_s
*s
= (struct omap_gpmc_s
*) opaque
;
260 struct omap_gpmc_cs_file_s
*f
;
263 return omap_badwidth_write32(opaque
, addr
, value
);
267 case 0x000: /* GPMC_REVISION */
268 case 0x014: /* GPMC_SYSSTATUS */
269 case 0x054: /* GPMC_STATUS */
270 case 0x1f0: /* GPMC_PREFETCH_STATUS */
271 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
272 case 0x234: /* GPMC_PSA_LSB */
273 case 0x238: /* GPMC_PSA_MSB */
277 case 0x010: /* GPMC_SYSCONFIG */
278 if ((value
>> 3) == 0x3)
279 fprintf(stderr
, "%s: bad SDRAM idle mode %"PRIi64
"\n",
280 __FUNCTION__
, value
>> 3);
283 s
->sysconfig
= value
& 0x19;
286 case 0x018: /* GPMC_IRQSTATUS */
288 omap_gpmc_int_update(s
);
291 case 0x01c: /* GPMC_IRQENABLE */
292 s
->irqen
= value
& 0xf03;
293 omap_gpmc_int_update(s
);
296 case 0x040: /* GPMC_TIMEOUT_CONTROL */
297 s
->timeout
= value
& 0x1ff1;
300 case 0x044: /* GPMC_ERR_ADDRESS */
301 case 0x048: /* GPMC_ERR_TYPE */
304 case 0x050: /* GPMC_CONFIG */
305 s
->config
= value
& 0xf13;
308 case 0x060 ... 0x1d4:
309 cs
= (addr
- 0x060) / 0x30;
313 case 0x60: /* GPMC_CONFIG1 */
314 f
->config
[0] = value
& 0xffef3e13;
316 case 0x64: /* GPMC_CONFIG2 */
317 f
->config
[1] = value
& 0x001f1f8f;
319 case 0x68: /* GPMC_CONFIG3 */
320 f
->config
[2] = value
& 0x001f1f8f;
322 case 0x6c: /* GPMC_CONFIG4 */
323 f
->config
[3] = value
& 0x1f8f1f8f;
325 case 0x70: /* GPMC_CONFIG5 */
326 f
->config
[4] = value
& 0x0f1f1f1f;
328 case 0x74: /* GPMC_CONFIG6 */
329 f
->config
[5] = value
& 0x00000fcf;
331 case 0x78: /* GPMC_CONFIG7 */
332 if ((f
->config
[6] ^ value
) & 0xf7f) {
333 omap_gpmc_cs_unmap(s
, cs
);
334 f
->config
[6] = value
& 0x00000f7f;
335 omap_gpmc_cs_map(s
, cs
);
338 case 0x7c: /* GPMC_NAND_COMMAND */
339 case 0x80: /* GPMC_NAND_ADDRESS */
340 case 0x84: /* GPMC_NAND_DATA */
348 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
349 s
->prefconfig
[0] = value
& 0x7f8f7fbf;
350 /* TODO: update interrupts, fifos, dmas */
353 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
354 s
->prefconfig
[1] = value
& 0x3fff;
357 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
358 s
->prefcontrol
= value
& 1;
359 if (s
->prefcontrol
) {
360 if (s
->prefconfig
[0] & 1)
368 case 0x1f4: /* GPMC_ECC_CONFIG */
371 case 0x1f8: /* GPMC_ECC_CONTROL */
372 if (value
& (1 << 8))
373 for (cs
= 0; cs
< 9; cs
++)
374 ecc_reset(&s
->ecc
[cs
]);
375 s
->ecc_ptr
= value
& 0xf;
376 if (s
->ecc_ptr
== 0 || s
->ecc_ptr
> 9) {
381 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
382 s
->ecc_cfg
= value
& 0x3fcff1ff;
384 case 0x230: /* GPMC_TESTMODE_CTRL */
386 fprintf(stderr
, "%s: test mode enable attempt\n", __FUNCTION__
);
396 static const MemoryRegionOps omap_gpmc_ops
= {
397 .read
= omap_gpmc_read
,
398 .write
= omap_gpmc_write
,
399 .endianness
= DEVICE_NATIVE_ENDIAN
,
402 struct omap_gpmc_s
*omap_gpmc_init(target_phys_addr_t base
, qemu_irq irq
)
404 struct omap_gpmc_s
*s
= (struct omap_gpmc_s
*)
405 g_malloc0(sizeof(struct omap_gpmc_s
));
407 memory_region_init_io(&s
->iomem
, &omap_gpmc_ops
, s
, "omap-gpmc", 0x1000);
408 memory_region_add_subregion(get_system_memory(), base
, &s
->iomem
);
416 void omap_gpmc_attach(struct omap_gpmc_s
*s
, int cs
, MemoryRegion
*iomem
)
418 struct omap_gpmc_cs_file_s
*f
;
421 if (cs
< 0 || cs
>= 8) {
422 fprintf(stderr
, "%s: bad chip-select %i\n", __FUNCTION__
, cs
);
427 omap_gpmc_cs_unmap(s
, cs
);
429 omap_gpmc_cs_map(s
, cs
);