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xen-hvm: Constify string
[qemu/cris-port.git] / hw / mips / gt64xxx_pci.c
blob1f2fe5fab94c53b48c38c838f07dd906539d0005
1 /*
2 * QEMU GT64120 PCI host
3 *
4 * Copyright (c) 2006,2007 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "hw/hw.h"
26 #include "hw/mips/mips.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_host.h"
29 #include "hw/i386/pc.h"
30 #include "exec/address-spaces.h"
31
32 //#define DEBUG
33
34 #ifdef DEBUG
35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
36 #else
37 #define DPRINTF(fmt, ...)
38 #endif
39
40 #define GT_REGS (0x1000 >> 2)
41
42 /* CPU Configuration */
43 #define GT_CPU (0x000 >> 2)
44 #define GT_MULTI (0x120 >> 2)
45
46 /* CPU Address Decode */
47 #define GT_SCS10LD (0x008 >> 2)
48 #define GT_SCS10HD (0x010 >> 2)
49 #define GT_SCS32LD (0x018 >> 2)
50 #define GT_SCS32HD (0x020 >> 2)
51 #define GT_CS20LD (0x028 >> 2)
52 #define GT_CS20HD (0x030 >> 2)
53 #define GT_CS3BOOTLD (0x038 >> 2)
54 #define GT_CS3BOOTHD (0x040 >> 2)
55 #define GT_PCI0IOLD (0x048 >> 2)
56 #define GT_PCI0IOHD (0x050 >> 2)
57 #define GT_PCI0M0LD (0x058 >> 2)
58 #define GT_PCI0M0HD (0x060 >> 2)
59 #define GT_PCI0M1LD (0x080 >> 2)
60 #define GT_PCI0M1HD (0x088 >> 2)
61 #define GT_PCI1IOLD (0x090 >> 2)
62 #define GT_PCI1IOHD (0x098 >> 2)
63 #define GT_PCI1M0LD (0x0a0 >> 2)
64 #define GT_PCI1M0HD (0x0a8 >> 2)
65 #define GT_PCI1M1LD (0x0b0 >> 2)
66 #define GT_PCI1M1HD (0x0b8 >> 2)
67 #define GT_ISD (0x068 >> 2)
68
69 #define GT_SCS10AR (0x0d0 >> 2)
70 #define GT_SCS32AR (0x0d8 >> 2)
71 #define GT_CS20R (0x0e0 >> 2)
72 #define GT_CS3BOOTR (0x0e8 >> 2)
73
74 #define GT_PCI0IOREMAP (0x0f0 >> 2)
75 #define GT_PCI0M0REMAP (0x0f8 >> 2)
76 #define GT_PCI0M1REMAP (0x100 >> 2)
77 #define GT_PCI1IOREMAP (0x108 >> 2)
78 #define GT_PCI1M0REMAP (0x110 >> 2)
79 #define GT_PCI1M1REMAP (0x118 >> 2)
80
81 /* CPU Error Report */
82 #define GT_CPUERR_ADDRLO (0x070 >> 2)
83 #define GT_CPUERR_ADDRHI (0x078 >> 2)
84 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
85 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
86 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
87
88 /* CPU Sync Barrier */
89 #define GT_PCI0SYNC (0x0c0 >> 2)
90 #define GT_PCI1SYNC (0x0c8 >> 2)
91
92 /* SDRAM and Device Address Decode */
93 #define GT_SCS0LD (0x400 >> 2)
94 #define GT_SCS0HD (0x404 >> 2)
95 #define GT_SCS1LD (0x408 >> 2)
96 #define GT_SCS1HD (0x40c >> 2)
97 #define GT_SCS2LD (0x410 >> 2)
98 #define GT_SCS2HD (0x414 >> 2)
99 #define GT_SCS3LD (0x418 >> 2)
100 #define GT_SCS3HD (0x41c >> 2)
101 #define GT_CS0LD (0x420 >> 2)
102 #define GT_CS0HD (0x424 >> 2)
103 #define GT_CS1LD (0x428 >> 2)
104 #define GT_CS1HD (0x42c >> 2)
105 #define GT_CS2LD (0x430 >> 2)
106 #define GT_CS2HD (0x434 >> 2)
107 #define GT_CS3LD (0x438 >> 2)
108 #define GT_CS3HD (0x43c >> 2)
109 #define GT_BOOTLD (0x440 >> 2)
110 #define GT_BOOTHD (0x444 >> 2)
111 #define GT_ADERR (0x470 >> 2)
112
113 /* SDRAM Configuration */
114 #define GT_SDRAM_CFG (0x448 >> 2)
115 #define GT_SDRAM_OPMODE (0x474 >> 2)
116 #define GT_SDRAM_BM (0x478 >> 2)
117 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
118
119 /* SDRAM Parameters */
120 #define GT_SDRAM_B0 (0x44c >> 2)
121 #define GT_SDRAM_B1 (0x450 >> 2)
122 #define GT_SDRAM_B2 (0x454 >> 2)
123 #define GT_SDRAM_B3 (0x458 >> 2)
124
125 /* Device Parameters */
126 #define GT_DEV_B0 (0x45c >> 2)
127 #define GT_DEV_B1 (0x460 >> 2)
128 #define GT_DEV_B2 (0x464 >> 2)
129 #define GT_DEV_B3 (0x468 >> 2)
130 #define GT_DEV_BOOT (0x46c >> 2)
131
132 /* ECC */
133 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
134 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
135 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
136 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
137 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
138
139 /* DMA Record */
140 #define GT_DMA0_CNT (0x800 >> 2)
141 #define GT_DMA1_CNT (0x804 >> 2)
142 #define GT_DMA2_CNT (0x808 >> 2)
143 #define GT_DMA3_CNT (0x80c >> 2)
144 #define GT_DMA0_SA (0x810 >> 2)
145 #define GT_DMA1_SA (0x814 >> 2)
146 #define GT_DMA2_SA (0x818 >> 2)
147 #define GT_DMA3_SA (0x81c >> 2)
148 #define GT_DMA0_DA (0x820 >> 2)
149 #define GT_DMA1_DA (0x824 >> 2)
150 #define GT_DMA2_DA (0x828 >> 2)
151 #define GT_DMA3_DA (0x82c >> 2)
152 #define GT_DMA0_NEXT (0x830 >> 2)
153 #define GT_DMA1_NEXT (0x834 >> 2)
154 #define GT_DMA2_NEXT (0x838 >> 2)
155 #define GT_DMA3_NEXT (0x83c >> 2)
156 #define GT_DMA0_CUR (0x870 >> 2)
157 #define GT_DMA1_CUR (0x874 >> 2)
158 #define GT_DMA2_CUR (0x878 >> 2)
159 #define GT_DMA3_CUR (0x87c >> 2)
160
161 /* DMA Channel Control */
162 #define GT_DMA0_CTRL (0x840 >> 2)
163 #define GT_DMA1_CTRL (0x844 >> 2)
164 #define GT_DMA2_CTRL (0x848 >> 2)
165 #define GT_DMA3_CTRL (0x84c >> 2)
166
167 /* DMA Arbiter */
168 #define GT_DMA_ARB (0x860 >> 2)
169
170 /* Timer/Counter */
171 #define GT_TC0 (0x850 >> 2)
172 #define GT_TC1 (0x854 >> 2)
173 #define GT_TC2 (0x858 >> 2)
174 #define GT_TC3 (0x85c >> 2)
175 #define GT_TC_CONTROL (0x864 >> 2)
176
177 /* PCI Internal */
178 #define GT_PCI0_CMD (0xc00 >> 2)
179 #define GT_PCI0_TOR (0xc04 >> 2)
180 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
181 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
182 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
183 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
184 #define GT_PCI1_IACK (0xc30 >> 2)
185 #define GT_PCI0_IACK (0xc34 >> 2)
186 #define GT_PCI0_BARE (0xc3c >> 2)
187 #define GT_PCI0_PREFMBR (0xc40 >> 2)
188 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
189 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
190 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
191 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
192 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
193 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
194 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
195 #define GT_PCI1_CMD (0xc80 >> 2)
196 #define GT_PCI1_TOR (0xc84 >> 2)
197 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
198 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
199 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
200 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
201 #define GT_PCI1_BARE (0xcbc >> 2)
202 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
203 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
204 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
205 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
206 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
207 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
208 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
209 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
210 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
211 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
212 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
213 #define GT_PCI0_CFGDATA (0xcfc >> 2)
214
215 /* Interrupts */
216 #define GT_INTRCAUSE (0xc18 >> 2)
217 #define GT_INTRMASK (0xc1c >> 2)
218 #define GT_PCI0_ICMASK (0xc24 >> 2)
219 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
220 #define GT_CPU_INTSEL (0xc70 >> 2)
221 #define GT_PCI0_INTSEL (0xc74 >> 2)
222 #define GT_HINTRCAUSE (0xc98 >> 2)
223 #define GT_HINTRMASK (0xc9c >> 2)
224 #define GT_PCI0_HICMASK (0xca4 >> 2)
225 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
226
227 #define PCI_MAPPING_ENTRY(regname) \
228 hwaddr regname ##_start; \
229 hwaddr regname ##_length; \
230 MemoryRegion regname ##_mem
231
232 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
233
234 #define GT64120_PCI_HOST_BRIDGE(obj) \
235 OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE)
236
237 typedef struct GT64120State {
238 PCIHostState parent_obj;
239
240 uint32_t regs[GT_REGS];
241 PCI_MAPPING_ENTRY(PCI0IO);
242 PCI_MAPPING_ENTRY(ISD);
243 } GT64120State;
244
245 /* Adjust range to avoid touching space which isn't mappable via PCI */
246 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
247 0x1fc00000 - 0x1fd00000 */
248 static void check_reserved_space (hwaddr *start,
249 hwaddr *length)
250 {
251 hwaddr begin = *start;
252 hwaddr end = *start + *length;
253
254 if (end >= 0x1e000000LL && end < 0x1f100000LL)
255 end = 0x1e000000LL;
256 if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
257 begin = 0x1f100000LL;
258 if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
259 end = 0x1fc00000LL;
260 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
261 begin = 0x1fd00000LL;
262 /* XXX: This is broken when a reserved range splits the requested range */
263 if (end >= 0x1f100000LL && begin < 0x1e000000LL)
264 end = 0x1e000000LL;
265 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
266 end = 0x1fc00000LL;
267
268 *start = begin;
269 *length = end - begin;
270 }
271
272 static void gt64120_isd_mapping(GT64120State *s)
273 {
274 hwaddr start = s->regs[GT_ISD] << 21;
275 hwaddr length = 0x1000;
276
277 if (s->ISD_length) {
278 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
279 }
280 check_reserved_space(&start, &length);
281 length = 0x1000;
282 /* Map new address */
283 DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx
284 " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n",
285 s->ISD_length, s->ISD_start, length, start);
286 s->ISD_start = start;
287 s->ISD_length = length;
288 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
289 }
290
291 static void gt64120_pci_mapping(GT64120State *s)
292 {
293 /* Update IO mapping */
294 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
295 {
296 /* Unmap old IO address */
297 if (s->PCI0IO_length)
298 {
299 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
300 object_unparent(OBJECT(&s->PCI0IO_mem));
301 }
302 /* Map new IO address */
303 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
304 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
305 isa_mem_base = s->PCI0IO_start;
306 if (s->PCI0IO_length) {
307 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "isa_mmio",
308 get_system_io(), 0, s->PCI0IO_length);
309 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
310 &s->PCI0IO_mem);
311 }
312 }
313 }
314
315 static int gt64120_post_load(void *opaque, int version_id)
316 {
317 GT64120State *s = opaque;
318
319 gt64120_isd_mapping(s);
320 gt64120_pci_mapping(s);
321
322 return 0;
323 }
324
325 static const VMStateDescription vmstate_gt64120 = {
326 .name = "gt64120",
327 .version_id = 1,
328 .minimum_version_id = 1,
329 .post_load = gt64120_post_load,
330 .fields = (VMStateField[]) {
331 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
332 VMSTATE_END_OF_LIST()
333 }
334 };
335
336 static void gt64120_writel (void *opaque, hwaddr addr,
337 uint64_t val, unsigned size)
338 {
339 GT64120State *s = opaque;
340 PCIHostState *phb = PCI_HOST_BRIDGE(s);
341 uint32_t saddr;
342
343 if (!(s->regs[GT_CPU] & 0x00001000))
344 val = bswap32(val);
345
346 saddr = (addr & 0xfff) >> 2;
347 switch (saddr) {
348
349 /* CPU Configuration */
350 case GT_CPU:
351 s->regs[GT_CPU] = val;
352 break;
353 case GT_MULTI:
354 /* Read-only register as only one GT64xxx is present on the CPU bus */
355 break;
356
357 /* CPU Address Decode */
358 case GT_PCI0IOLD:
359 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
360 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
361 gt64120_pci_mapping(s);
362 break;
363 case GT_PCI0M0LD:
364 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
365 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
366 break;
367 case GT_PCI0M1LD:
368 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
369 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
370 break;
371 case GT_PCI1IOLD:
372 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
373 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
374 break;
375 case GT_PCI1M0LD:
376 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
377 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
378 break;
379 case GT_PCI1M1LD:
380 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
381 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
382 break;
383 case GT_PCI0IOHD:
384 s->regs[saddr] = val & 0x0000007f;
385 gt64120_pci_mapping(s);
386 break;
387 case GT_PCI0M0HD:
388 case GT_PCI0M1HD:
389 case GT_PCI1IOHD:
390 case GT_PCI1M0HD:
391 case GT_PCI1M1HD:
392 s->regs[saddr] = val & 0x0000007f;
393 break;
394 case GT_ISD:
395 s->regs[saddr] = val & 0x00007fff;
396 gt64120_isd_mapping(s);
397 break;
398
399 case GT_PCI0IOREMAP:
400 case GT_PCI0M0REMAP:
401 case GT_PCI0M1REMAP:
402 case GT_PCI1IOREMAP:
403 case GT_PCI1M0REMAP:
404 case GT_PCI1M1REMAP:
405 s->regs[saddr] = val & 0x000007ff;
406 break;
407
408 /* CPU Error Report */
409 case GT_CPUERR_ADDRLO:
410 case GT_CPUERR_ADDRHI:
411 case GT_CPUERR_DATALO:
412 case GT_CPUERR_DATAHI:
413 case GT_CPUERR_PARITY:
414 /* Read-only registers, do nothing */
415 break;
416
417 /* CPU Sync Barrier */
418 case GT_PCI0SYNC:
419 case GT_PCI1SYNC:
420 /* Read-only registers, do nothing */
421 break;
422
423 /* SDRAM and Device Address Decode */
424 case GT_SCS0LD:
425 case GT_SCS0HD:
426 case GT_SCS1LD:
427 case GT_SCS1HD:
428 case GT_SCS2LD:
429 case GT_SCS2HD:
430 case GT_SCS3LD:
431 case GT_SCS3HD:
432 case GT_CS0LD:
433 case GT_CS0HD:
434 case GT_CS1LD:
435 case GT_CS1HD:
436 case GT_CS2LD:
437 case GT_CS2HD:
438 case GT_CS3LD:
439 case GT_CS3HD:
440 case GT_BOOTLD:
441 case GT_BOOTHD:
442 case GT_ADERR:
443 /* SDRAM Configuration */
444 case GT_SDRAM_CFG:
445 case GT_SDRAM_OPMODE:
446 case GT_SDRAM_BM:
447 case GT_SDRAM_ADDRDECODE:
448 /* Accept and ignore SDRAM interleave configuration */
449 s->regs[saddr] = val;
450 break;
451
452 /* Device Parameters */
453 case GT_DEV_B0:
454 case GT_DEV_B1:
455 case GT_DEV_B2:
456 case GT_DEV_B3:
457 case GT_DEV_BOOT:
458 /* Not implemented */
459 DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
460 break;
461
462 /* ECC */
463 case GT_ECC_ERRDATALO:
464 case GT_ECC_ERRDATAHI:
465 case GT_ECC_MEM:
466 case GT_ECC_CALC:
467 case GT_ECC_ERRADDR:
468 /* Read-only registers, do nothing */
469 break;
470
471 /* DMA Record */
472 case GT_DMA0_CNT:
473 case GT_DMA1_CNT:
474 case GT_DMA2_CNT:
475 case GT_DMA3_CNT:
476 case GT_DMA0_SA:
477 case GT_DMA1_SA:
478 case GT_DMA2_SA:
479 case GT_DMA3_SA:
480 case GT_DMA0_DA:
481 case GT_DMA1_DA:
482 case GT_DMA2_DA:
483 case GT_DMA3_DA:
484 case GT_DMA0_NEXT:
485 case GT_DMA1_NEXT:
486 case GT_DMA2_NEXT:
487 case GT_DMA3_NEXT:
488 case GT_DMA0_CUR:
489 case GT_DMA1_CUR:
490 case GT_DMA2_CUR:
491 case GT_DMA3_CUR:
492 /* Not implemented */
493 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
494 break;
495
496 /* DMA Channel Control */
497 case GT_DMA0_CTRL:
498 case GT_DMA1_CTRL:
499 case GT_DMA2_CTRL:
500 case GT_DMA3_CTRL:
501 /* Not implemented */
502 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
503 break;
504
505 /* DMA Arbiter */
506 case GT_DMA_ARB:
507 /* Not implemented */
508 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
509 break;
510
511 /* Timer/Counter */
512 case GT_TC0:
513 case GT_TC1:
514 case GT_TC2:
515 case GT_TC3:
516 case GT_TC_CONTROL:
517 /* Not implemented */
518 DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
519 break;
520
521 /* PCI Internal */
522 case GT_PCI0_CMD:
523 case GT_PCI1_CMD:
524 s->regs[saddr] = val & 0x0401fc0f;
525 break;
526 case GT_PCI0_TOR:
527 case GT_PCI0_BS_SCS10:
528 case GT_PCI0_BS_SCS32:
529 case GT_PCI0_BS_CS20:
530 case GT_PCI0_BS_CS3BT:
531 case GT_PCI1_IACK:
532 case GT_PCI0_IACK:
533 case GT_PCI0_BARE:
534 case GT_PCI0_PREFMBR:
535 case GT_PCI0_SCS10_BAR:
536 case GT_PCI0_SCS32_BAR:
537 case GT_PCI0_CS20_BAR:
538 case GT_PCI0_CS3BT_BAR:
539 case GT_PCI0_SSCS10_BAR:
540 case GT_PCI0_SSCS32_BAR:
541 case GT_PCI0_SCS3BT_BAR:
542 case GT_PCI1_TOR:
543 case GT_PCI1_BS_SCS10:
544 case GT_PCI1_BS_SCS32:
545 case GT_PCI1_BS_CS20:
546 case GT_PCI1_BS_CS3BT:
547 case GT_PCI1_BARE:
548 case GT_PCI1_PREFMBR:
549 case GT_PCI1_SCS10_BAR:
550 case GT_PCI1_SCS32_BAR:
551 case GT_PCI1_CS20_BAR:
552 case GT_PCI1_CS3BT_BAR:
553 case GT_PCI1_SSCS10_BAR:
554 case GT_PCI1_SSCS32_BAR:
555 case GT_PCI1_SCS3BT_BAR:
556 case GT_PCI1_CFGADDR:
557 case GT_PCI1_CFGDATA:
558 /* not implemented */
559 break;
560 case GT_PCI0_CFGADDR:
561 phb->config_reg = val & 0x80fffffc;
562 break;
563 case GT_PCI0_CFGDATA:
564 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
565 val = bswap32(val);
566 }
567 if (phb->config_reg & (1u << 31)) {
568 pci_data_write(phb->bus, phb->config_reg, val, 4);
569 }
570 break;
571
572 /* Interrupts */
573 case GT_INTRCAUSE:
574 /* not really implemented */
575 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
576 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
577 DPRINTF("INTRCAUSE %" PRIx64 "\n", val);
578 break;
579 case GT_INTRMASK:
580 s->regs[saddr] = val & 0x3c3ffffe;
581 DPRINTF("INTRMASK %" PRIx64 "\n", val);
582 break;
583 case GT_PCI0_ICMASK:
584 s->regs[saddr] = val & 0x03fffffe;
585 DPRINTF("ICMASK %" PRIx64 "\n", val);
586 break;
587 case GT_PCI0_SERR0MASK:
588 s->regs[saddr] = val & 0x0000003f;
589 DPRINTF("SERR0MASK %" PRIx64 "\n", val);
590 break;
591
592 /* Reserved when only PCI_0 is configured. */
593 case GT_HINTRCAUSE:
594 case GT_CPU_INTSEL:
595 case GT_PCI0_INTSEL:
596 case GT_HINTRMASK:
597 case GT_PCI0_HICMASK:
598 case GT_PCI1_SERR1MASK:
599 /* not implemented */
600 break;
601
602 /* SDRAM Parameters */
603 case GT_SDRAM_B0:
604 case GT_SDRAM_B1:
605 case GT_SDRAM_B2:
606 case GT_SDRAM_B3:
607 /* We don't simulate electrical parameters of the SDRAM.
608 Accept, but ignore the values. */
609 s->regs[saddr] = val;
610 break;
611
612 default:
613 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
614 break;
615 }
616 }
617
618 static uint64_t gt64120_readl (void *opaque,
619 hwaddr addr, unsigned size)
620 {
621 GT64120State *s = opaque;
622 PCIHostState *phb = PCI_HOST_BRIDGE(s);
623 uint32_t val;
624 uint32_t saddr;
625
626 saddr = (addr & 0xfff) >> 2;
627 switch (saddr) {
628
629 /* CPU Configuration */
630 case GT_MULTI:
631 /* Only one GT64xxx is present on the CPU bus, return
632 the initial value */
633 val = s->regs[saddr];
634 break;
635
636 /* CPU Error Report */
637 case GT_CPUERR_ADDRLO:
638 case GT_CPUERR_ADDRHI:
639 case GT_CPUERR_DATALO:
640 case GT_CPUERR_DATAHI:
641 case GT_CPUERR_PARITY:
642 /* Emulated memory has no error, always return the initial
643 values */
644 val = s->regs[saddr];
645 break;
646
647 /* CPU Sync Barrier */
648 case GT_PCI0SYNC:
649 case GT_PCI1SYNC:
650 /* Reading those register should empty all FIFO on the PCI
651 bus, which are not emulated. The return value should be
652 a random value that should be ignored. */
653 val = 0xc000ffee;
654 break;
655
656 /* ECC */
657 case GT_ECC_ERRDATALO:
658 case GT_ECC_ERRDATAHI:
659 case GT_ECC_MEM:
660 case GT_ECC_CALC:
661 case GT_ECC_ERRADDR:
662 /* Emulated memory has no error, always return the initial
663 values */
664 val = s->regs[saddr];
665 break;
666
667 case GT_CPU:
668 case GT_SCS10LD:
669 case GT_SCS10HD:
670 case GT_SCS32LD:
671 case GT_SCS32HD:
672 case GT_CS20LD:
673 case GT_CS20HD:
674 case GT_CS3BOOTLD:
675 case GT_CS3BOOTHD:
676 case GT_SCS10AR:
677 case GT_SCS32AR:
678 case GT_CS20R:
679 case GT_CS3BOOTR:
680 case GT_PCI0IOLD:
681 case GT_PCI0M0LD:
682 case GT_PCI0M1LD:
683 case GT_PCI1IOLD:
684 case GT_PCI1M0LD:
685 case GT_PCI1M1LD:
686 case GT_PCI0IOHD:
687 case GT_PCI0M0HD:
688 case GT_PCI0M1HD:
689 case GT_PCI1IOHD:
690 case GT_PCI1M0HD:
691 case GT_PCI1M1HD:
692 case GT_PCI0IOREMAP:
693 case GT_PCI0M0REMAP:
694 case GT_PCI0M1REMAP:
695 case GT_PCI1IOREMAP:
696 case GT_PCI1M0REMAP:
697 case GT_PCI1M1REMAP:
698 case GT_ISD:
699 val = s->regs[saddr];
700 break;
701 case GT_PCI0_IACK:
702 /* Read the IRQ number */
703 val = pic_read_irq(isa_pic);
704 break;
705
706 /* SDRAM and Device Address Decode */
707 case GT_SCS0LD:
708 case GT_SCS0HD:
709 case GT_SCS1LD:
710 case GT_SCS1HD:
711 case GT_SCS2LD:
712 case GT_SCS2HD:
713 case GT_SCS3LD:
714 case GT_SCS3HD:
715 case GT_CS0LD:
716 case GT_CS0HD:
717 case GT_CS1LD:
718 case GT_CS1HD:
719 case GT_CS2LD:
720 case GT_CS2HD:
721 case GT_CS3LD:
722 case GT_CS3HD:
723 case GT_BOOTLD:
724 case GT_BOOTHD:
725 case GT_ADERR:
726 val = s->regs[saddr];
727 break;
728
729 /* SDRAM Configuration */
730 case GT_SDRAM_CFG:
731 case GT_SDRAM_OPMODE:
732 case GT_SDRAM_BM:
733 case GT_SDRAM_ADDRDECODE:
734 val = s->regs[saddr];
735 break;
736
737 /* SDRAM Parameters */
738 case GT_SDRAM_B0:
739 case GT_SDRAM_B1:
740 case GT_SDRAM_B2:
741 case GT_SDRAM_B3:
742 /* We don't simulate electrical parameters of the SDRAM.
743 Just return the last written value. */
744 val = s->regs[saddr];
745 break;
746
747 /* Device Parameters */
748 case GT_DEV_B0:
749 case GT_DEV_B1:
750 case GT_DEV_B2:
751 case GT_DEV_B3:
752 case GT_DEV_BOOT:
753 val = s->regs[saddr];
754 break;
755
756 /* DMA Record */
757 case GT_DMA0_CNT:
758 case GT_DMA1_CNT:
759 case GT_DMA2_CNT:
760 case GT_DMA3_CNT:
761 case GT_DMA0_SA:
762 case GT_DMA1_SA:
763 case GT_DMA2_SA:
764 case GT_DMA3_SA:
765 case GT_DMA0_DA:
766 case GT_DMA1_DA:
767 case GT_DMA2_DA:
768 case GT_DMA3_DA:
769 case GT_DMA0_NEXT:
770 case GT_DMA1_NEXT:
771 case GT_DMA2_NEXT:
772 case GT_DMA3_NEXT:
773 case GT_DMA0_CUR:
774 case GT_DMA1_CUR:
775 case GT_DMA2_CUR:
776 case GT_DMA3_CUR:
777 val = s->regs[saddr];
778 break;
779
780 /* DMA Channel Control */
781 case GT_DMA0_CTRL:
782 case GT_DMA1_CTRL:
783 case GT_DMA2_CTRL:
784 case GT_DMA3_CTRL:
785 val = s->regs[saddr];
786 break;
787
788 /* DMA Arbiter */
789 case GT_DMA_ARB:
790 val = s->regs[saddr];
791 break;
792
793 /* Timer/Counter */
794 case GT_TC0:
795 case GT_TC1:
796 case GT_TC2:
797 case GT_TC3:
798 case GT_TC_CONTROL:
799 val = s->regs[saddr];
800 break;
801
802 /* PCI Internal */
803 case GT_PCI0_CFGADDR:
804 val = phb->config_reg;
805 break;
806 case GT_PCI0_CFGDATA:
807 if (!(phb->config_reg & (1 << 31))) {
808 val = 0xffffffff;
809 } else {
810 val = pci_data_read(phb->bus, phb->config_reg, 4);
811 }
812 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
813 val = bswap32(val);
814 }
815 break;
816
817 case GT_PCI0_CMD:
818 case GT_PCI0_TOR:
819 case GT_PCI0_BS_SCS10:
820 case GT_PCI0_BS_SCS32:
821 case GT_PCI0_BS_CS20:
822 case GT_PCI0_BS_CS3BT:
823 case GT_PCI1_IACK:
824 case GT_PCI0_BARE:
825 case GT_PCI0_PREFMBR:
826 case GT_PCI0_SCS10_BAR:
827 case GT_PCI0_SCS32_BAR:
828 case GT_PCI0_CS20_BAR:
829 case GT_PCI0_CS3BT_BAR:
830 case GT_PCI0_SSCS10_BAR:
831 case GT_PCI0_SSCS32_BAR:
832 case GT_PCI0_SCS3BT_BAR:
833 case GT_PCI1_CMD:
834 case GT_PCI1_TOR:
835 case GT_PCI1_BS_SCS10:
836 case GT_PCI1_BS_SCS32:
837 case GT_PCI1_BS_CS20:
838 case GT_PCI1_BS_CS3BT:
839 case GT_PCI1_BARE:
840 case GT_PCI1_PREFMBR:
841 case GT_PCI1_SCS10_BAR:
842 case GT_PCI1_SCS32_BAR:
843 case GT_PCI1_CS20_BAR:
844 case GT_PCI1_CS3BT_BAR:
845 case GT_PCI1_SSCS10_BAR:
846 case GT_PCI1_SSCS32_BAR:
847 case GT_PCI1_SCS3BT_BAR:
848 case GT_PCI1_CFGADDR:
849 case GT_PCI1_CFGDATA:
850 val = s->regs[saddr];
851 break;
852
853 /* Interrupts */
854 case GT_INTRCAUSE:
855 val = s->regs[saddr];
856 DPRINTF("INTRCAUSE %x\n", val);
857 break;
858 case GT_INTRMASK:
859 val = s->regs[saddr];
860 DPRINTF("INTRMASK %x\n", val);
861 break;
862 case GT_PCI0_ICMASK:
863 val = s->regs[saddr];
864 DPRINTF("ICMASK %x\n", val);
865 break;
866 case GT_PCI0_SERR0MASK:
867 val = s->regs[saddr];
868 DPRINTF("SERR0MASK %x\n", val);
869 break;
870
871 /* Reserved when only PCI_0 is configured. */
872 case GT_HINTRCAUSE:
873 case GT_CPU_INTSEL:
874 case GT_PCI0_INTSEL:
875 case GT_HINTRMASK:
876 case GT_PCI0_HICMASK:
877 case GT_PCI1_SERR1MASK:
878 val = s->regs[saddr];
879 break;
880
881 default:
882 val = s->regs[saddr];
883 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
884 break;
885 }
886
887 if (!(s->regs[GT_CPU] & 0x00001000))
888 val = bswap32(val);
889
890 return val;
891 }
892
893 static const MemoryRegionOps isd_mem_ops = {
894 .read = gt64120_readl,
895 .write = gt64120_writel,
896 .endianness = DEVICE_NATIVE_ENDIAN,
897 };
898
899 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
900 {
901 int slot;
902
903 slot = (pci_dev->devfn >> 3);
904
905 switch (slot) {
906 /* PIIX4 USB */
907 case 10:
908 return 3;
909 /* AMD 79C973 Ethernet */
910 case 11:
911 return 1;
912 /* Crystal 4281 Sound */
913 case 12:
914 return 2;
915 /* PCI slot 1 to 4 */
916 case 18 ... 21:
917 return ((slot - 18) + irq_num) & 0x03;
918 /* Unknown device, don't do any translation */
919 default:
920 return irq_num;
921 }
922 }
923
924 static int pci_irq_levels[4];
925
926 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
927 {
928 int i, pic_irq, pic_level;
929 qemu_irq *pic = opaque;
930
931 pci_irq_levels[irq_num] = level;
932
933 /* now we change the pic irq level according to the piix irq mappings */
934 /* XXX: optimize */
935 pic_irq = piix4_dev->config[0x60 + irq_num];
936 if (pic_irq < 16) {
937 /* The pic level is the logical OR of all the PCI irqs mapped
938 to it */
939 pic_level = 0;
940 for (i = 0; i < 4; i++) {
941 if (pic_irq == piix4_dev->config[0x60 + i])
942 pic_level |= pci_irq_levels[i];
943 }
944 qemu_set_irq(pic[pic_irq], pic_level);
945 }
946 }
947
948
949 static void gt64120_reset(void *opaque)
950 {
951 GT64120State *s = opaque;
952
953 /* FIXME: Malta specific hw assumptions ahead */
954
955 /* CPU Configuration */
956 #ifdef TARGET_WORDS_BIGENDIAN
957 s->regs[GT_CPU] = 0x00000000;
958 #else
959 s->regs[GT_CPU] = 0x00001000;
960 #endif
961 s->regs[GT_MULTI] = 0x00000003;
962
963 /* CPU Address decode */
964 s->regs[GT_SCS10LD] = 0x00000000;
965 s->regs[GT_SCS10HD] = 0x00000007;
966 s->regs[GT_SCS32LD] = 0x00000008;
967 s->regs[GT_SCS32HD] = 0x0000000f;
968 s->regs[GT_CS20LD] = 0x000000e0;
969 s->regs[GT_CS20HD] = 0x00000070;
970 s->regs[GT_CS3BOOTLD] = 0x000000f8;
971 s->regs[GT_CS3BOOTHD] = 0x0000007f;
972
973 s->regs[GT_PCI0IOLD] = 0x00000080;
974 s->regs[GT_PCI0IOHD] = 0x0000000f;
975 s->regs[GT_PCI0M0LD] = 0x00000090;
976 s->regs[GT_PCI0M0HD] = 0x0000001f;
977 s->regs[GT_ISD] = 0x000000a0;
978 s->regs[GT_PCI0M1LD] = 0x00000790;
979 s->regs[GT_PCI0M1HD] = 0x0000001f;
980 s->regs[GT_PCI1IOLD] = 0x00000100;
981 s->regs[GT_PCI1IOHD] = 0x0000000f;
982 s->regs[GT_PCI1M0LD] = 0x00000110;
983 s->regs[GT_PCI1M0HD] = 0x0000001f;
984 s->regs[GT_PCI1M1LD] = 0x00000120;
985 s->regs[GT_PCI1M1HD] = 0x0000002f;
986
987 s->regs[GT_SCS10AR] = 0x00000000;
988 s->regs[GT_SCS32AR] = 0x00000008;
989 s->regs[GT_CS20R] = 0x000000e0;
990 s->regs[GT_CS3BOOTR] = 0x000000f8;
991
992 s->regs[GT_PCI0IOREMAP] = 0x00000080;
993 s->regs[GT_PCI0M0REMAP] = 0x00000090;
994 s->regs[GT_PCI0M1REMAP] = 0x00000790;
995 s->regs[GT_PCI1IOREMAP] = 0x00000100;
996 s->regs[GT_PCI1M0REMAP] = 0x00000110;
997 s->regs[GT_PCI1M1REMAP] = 0x00000120;
998
999 /* CPU Error Report */
1000 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1001 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1002 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1003 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1004 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1005
1006 /* CPU Sync Barrier */
1007 s->regs[GT_PCI0SYNC] = 0x00000000;
1008 s->regs[GT_PCI1SYNC] = 0x00000000;
1009
1010 /* SDRAM and Device Address Decode */
1011 s->regs[GT_SCS0LD] = 0x00000000;
1012 s->regs[GT_SCS0HD] = 0x00000007;
1013 s->regs[GT_SCS1LD] = 0x00000008;
1014 s->regs[GT_SCS1HD] = 0x0000000f;
1015 s->regs[GT_SCS2LD] = 0x00000010;
1016 s->regs[GT_SCS2HD] = 0x00000017;
1017 s->regs[GT_SCS3LD] = 0x00000018;
1018 s->regs[GT_SCS3HD] = 0x0000001f;
1019 s->regs[GT_CS0LD] = 0x000000c0;
1020 s->regs[GT_CS0HD] = 0x000000c7;
1021 s->regs[GT_CS1LD] = 0x000000c8;
1022 s->regs[GT_CS1HD] = 0x000000cf;
1023 s->regs[GT_CS2LD] = 0x000000d0;
1024 s->regs[GT_CS2HD] = 0x000000df;
1025 s->regs[GT_CS3LD] = 0x000000f0;
1026 s->regs[GT_CS3HD] = 0x000000fb;
1027 s->regs[GT_BOOTLD] = 0x000000fc;
1028 s->regs[GT_BOOTHD] = 0x000000ff;
1029 s->regs[GT_ADERR] = 0xffffffff;
1030
1031 /* SDRAM Configuration */
1032 s->regs[GT_SDRAM_CFG] = 0x00000200;
1033 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1034 s->regs[GT_SDRAM_BM] = 0x00000007;
1035 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1036
1037 /* SDRAM Parameters */
1038 s->regs[GT_SDRAM_B0] = 0x00000005;
1039 s->regs[GT_SDRAM_B1] = 0x00000005;
1040 s->regs[GT_SDRAM_B2] = 0x00000005;
1041 s->regs[GT_SDRAM_B3] = 0x00000005;
1042
1043 /* ECC */
1044 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1045 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1046 s->regs[GT_ECC_MEM] = 0x00000000;
1047 s->regs[GT_ECC_CALC] = 0x00000000;
1048 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1049
1050 /* Device Parameters */
1051 s->regs[GT_DEV_B0] = 0x386fffff;
1052 s->regs[GT_DEV_B1] = 0x386fffff;
1053 s->regs[GT_DEV_B2] = 0x386fffff;
1054 s->regs[GT_DEV_B3] = 0x386fffff;
1055 s->regs[GT_DEV_BOOT] = 0x146fffff;
1056
1057 /* DMA registers are all zeroed at reset */
1058
1059 /* Timer/Counter */
1060 s->regs[GT_TC0] = 0xffffffff;
1061 s->regs[GT_TC1] = 0x00ffffff;
1062 s->regs[GT_TC2] = 0x00ffffff;
1063 s->regs[GT_TC3] = 0x00ffffff;
1064 s->regs[GT_TC_CONTROL] = 0x00000000;
1065
1066 /* PCI Internal */
1067 #ifdef TARGET_WORDS_BIGENDIAN
1068 s->regs[GT_PCI0_CMD] = 0x00000000;
1069 #else
1070 s->regs[GT_PCI0_CMD] = 0x00010001;
1071 #endif
1072 s->regs[GT_PCI0_TOR] = 0x0000070f;
1073 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1074 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1075 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1076 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1077 s->regs[GT_PCI1_IACK] = 0x00000000;
1078 s->regs[GT_PCI0_IACK] = 0x00000000;
1079 s->regs[GT_PCI0_BARE] = 0x0000000f;
1080 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1081 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1082 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1083 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1084 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1085 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1086 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1087 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1088 #ifdef TARGET_WORDS_BIGENDIAN
1089 s->regs[GT_PCI1_CMD] = 0x00000000;
1090 #else
1091 s->regs[GT_PCI1_CMD] = 0x00010001;
1092 #endif
1093 s->regs[GT_PCI1_TOR] = 0x0000070f;
1094 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1095 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1096 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1097 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1098 s->regs[GT_PCI1_BARE] = 0x0000000f;
1099 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1100 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1101 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1102 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1103 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1104 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1105 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1106 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1107 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1108 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1109 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1110
1111 /* Interrupt registers are all zeroed at reset */
1112
1113 gt64120_isd_mapping(s);
1114 gt64120_pci_mapping(s);
1115 }
1116
1117 PCIBus *gt64120_register(qemu_irq *pic)
1118 {
1119 GT64120State *d;
1120 PCIHostState *phb;
1121 DeviceState *dev;
1122
1123 dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
1124 qdev_init_nofail(dev);
1125 d = GT64120_PCI_HOST_BRIDGE(dev);
1126 phb = PCI_HOST_BRIDGE(dev);
1127 phb->bus = pci_register_bus(dev, "pci",
1128 gt64120_pci_set_irq, gt64120_pci_map_irq,
1129 pic,
1130 get_system_memory(),
1131 get_system_io(),
1132 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
1133 memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000);
1134
1135 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1136 return phb->bus;
1137 }
1138
1139 static int gt64120_init(SysBusDevice *dev)
1140 {
1141 GT64120State *s;
1142
1143 s = GT64120_PCI_HOST_BRIDGE(dev);
1144
1145 /* FIXME: This value is computed from registers during reset, but some
1146 devices (e.g. VGA card) need to know it when they are registered.
1147 This also mean that changing the register to change the mapping
1148 does not fully work. */
1149 isa_mem_base = 0x10000000;
1150 qemu_register_reset(gt64120_reset, s);
1151 return 0;
1152 }
1153
1154 static int gt64120_pci_init(PCIDevice *d)
1155 {
1156 /* FIXME: Malta specific hw assumptions ahead */
1157 pci_set_word(d->config + PCI_COMMAND, 0);
1158 pci_set_word(d->config + PCI_STATUS,
1159 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1160 pci_config_set_prog_interface(d->config, 0);
1161 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1162 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1163 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1164 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1165 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1166 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1167 pci_set_byte(d->config + 0x3d, 0x01);
1168
1169 return 0;
1170 }
1171
1172 static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1173 {
1174 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1175 DeviceClass *dc = DEVICE_CLASS(klass);
1176
1177 k->init = gt64120_pci_init;
1178 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1179 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1180 k->revision = 0x10;
1181 k->class_id = PCI_CLASS_BRIDGE_HOST;
1182 /*
1183 * PCI-facing part of the host bridge, not usable without the
1184 * host-facing part, which can't be device_add'ed, yet.
1185 */
1186 dc->cannot_instantiate_with_device_add_yet = true;
1187 }
1188
1189 static const TypeInfo gt64120_pci_info = {
1190 .name = "gt64120_pci",
1191 .parent = TYPE_PCI_DEVICE,
1192 .instance_size = sizeof(PCIDevice),
1193 .class_init = gt64120_pci_class_init,
1194 };
1195
1196 static void gt64120_class_init(ObjectClass *klass, void *data)
1197 {
1198 DeviceClass *dc = DEVICE_CLASS(klass);
1199 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1200
1201 sdc->init = gt64120_init;
1202 dc->vmsd = &vmstate_gt64120;
1203 }
1204
1205 static const TypeInfo gt64120_info = {
1206 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1207 .parent = TYPE_PCI_HOST_BRIDGE,
1208 .instance_size = sizeof(GT64120State),
1209 .class_init = gt64120_class_init,
1210 };
1211
1212 static void gt64120_pci_register_types(void)
1213 {
1214 type_register_static(&gt64120_info);
1215 type_register_static(&gt64120_pci_info);
1216 }
1217
1218 type_init(gt64120_pci_register_types)
CRIS target port of Qemu