2 * i.MX31 Vectored Interrupt Controller
4 * Note this is NOT the PL192 provided by ARM, but
5 * a custom implementation by Freescale.
7 * Copyright (c) 2008 OKL
8 * Copyright (c) 2011 NICTA Pty Ltd
9 * Originally written by Hans Jiang
10 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
12 * This code is licensed under the GPL version 2 or later. See
13 * the COPYING file in the top-level directory.
15 * TODO: implement vectors.
18 #include "hw/intc/imx_avic.h"
21 #undef DEBUG_INT /* comment out for debugging */
24 #define DPRINTF(fmt, args...) \
25 do { printf("%s: " fmt , TYPE_IMX_AVIC, ##args); } while (0)
27 #define DPRINTF(fmt, args...) do {} while (0)
31 * Define to 1 for messages about attempts to
32 * access unimplemented registers or similar.
34 #define DEBUG_IMPLEMENTATION 1
35 #if DEBUG_IMPLEMENTATION
36 # define IPRINTF(fmt, args...) \
37 do { fprintf(stderr, "%s: " fmt, TYPE_IMX_AVIC, ##args); } while (0)
39 # define IPRINTF(fmt, args...) do {} while (0)
42 static const VMStateDescription vmstate_imx_avic
= {
43 .name
= TYPE_IMX_AVIC
,
45 .minimum_version_id
= 1,
46 .fields
= (VMStateField
[]) {
47 VMSTATE_UINT64(pending
, IMXAVICState
),
48 VMSTATE_UINT64(enabled
, IMXAVICState
),
49 VMSTATE_UINT64(is_fiq
, IMXAVICState
),
50 VMSTATE_UINT32(intcntl
, IMXAVICState
),
51 VMSTATE_UINT32(intmask
, IMXAVICState
),
52 VMSTATE_UINT32_ARRAY(prio
, IMXAVICState
, PRIO_WORDS
),
57 static inline int imx_avic_prio(IMXAVICState
*s
, int irq
)
59 uint32_t word
= irq
/ PRIO_PER_WORD
;
60 uint32_t part
= 4 * (irq
% PRIO_PER_WORD
);
61 return 0xf & (s
->prio
[word
] >> part
);
64 /* Update interrupts. */
65 static void imx_avic_update(IMXAVICState
*s
)
68 uint64_t new = s
->pending
& s
->enabled
;
71 flags
= new & s
->is_fiq
;
72 qemu_set_irq(s
->fiq
, !!flags
);
74 flags
= new & ~s
->is_fiq
;
75 if (!flags
|| (s
->intmask
== 0x1f)) {
76 qemu_set_irq(s
->irq
, !!flags
);
81 * Take interrupt if there's a pending interrupt with
82 * priority higher than the value of intmask
84 for (i
= 0; i
< IMX_AVIC_NUM_IRQS
; i
++) {
85 if (flags
& (1UL << i
)) {
86 if (imx_avic_prio(s
, i
) > s
->intmask
) {
87 qemu_set_irq(s
->irq
, 1);
92 qemu_set_irq(s
->irq
, 0);
95 static void imx_avic_set_irq(void *opaque
, int irq
, int level
)
97 IMXAVICState
*s
= (IMXAVICState
*)opaque
;
100 DPRINTF("Raising IRQ %d, prio %d\n",
101 irq
, imx_avic_prio(s
, irq
));
102 s
->pending
|= (1ULL << irq
);
104 DPRINTF("Clearing IRQ %d, prio %d\n",
105 irq
, imx_avic_prio(s
, irq
));
106 s
->pending
&= ~(1ULL << irq
);
113 static uint64_t imx_avic_read(void *opaque
,
114 hwaddr offset
, unsigned size
)
116 IMXAVICState
*s
= (IMXAVICState
*)opaque
;
119 DPRINTF("read(offset = 0x%x)\n", offset
>> 2);
120 switch (offset
>> 2) {
121 case 0: /* INTCNTL */
124 case 1: /* Normal Interrupt Mask Register, NIMASK */
127 case 2: /* Interrupt Enable Number Register, INTENNUM */
128 case 3: /* Interrupt Disable Number Register, INTDISNUM */
131 case 4: /* Interrupt Enabled Number Register High */
132 return s
->enabled
>> 32;
134 case 5: /* Interrupt Enabled Number Register Low */
135 return s
->enabled
& 0xffffffffULL
;
137 case 6: /* Interrupt Type Register High */
138 return s
->is_fiq
>> 32;
140 case 7: /* Interrupt Type Register Low */
141 return s
->is_fiq
& 0xffffffffULL
;
143 case 8: /* Normal Interrupt Priority Register 7 */
144 case 9: /* Normal Interrupt Priority Register 6 */
145 case 10:/* Normal Interrupt Priority Register 5 */
146 case 11:/* Normal Interrupt Priority Register 4 */
147 case 12:/* Normal Interrupt Priority Register 3 */
148 case 13:/* Normal Interrupt Priority Register 2 */
149 case 14:/* Normal Interrupt Priority Register 1 */
150 case 15:/* Normal Interrupt Priority Register 0 */
151 return s
->prio
[15-(offset
>>2)];
153 case 16: /* Normal interrupt vector and status register */
156 * This returns the highest priority
157 * outstanding interrupt. Where there is more than
158 * one pending IRQ with the same priority,
159 * take the highest numbered one.
161 uint64_t flags
= s
->pending
& s
->enabled
& ~s
->is_fiq
;
165 for (i
= 63; i
>= 0; --i
) {
166 if (flags
& (1ULL<<i
)) {
167 int irq_prio
= imx_avic_prio(s
, i
);
168 if (irq_prio
> prio
) {
175 imx_avic_set_irq(s
, irq
, 0);
176 return irq
<< 16 | prio
;
178 return 0xffffffffULL
;
180 case 17:/* Fast Interrupt vector and status register */
182 uint64_t flags
= s
->pending
& s
->enabled
& s
->is_fiq
;
183 int i
= ctz64(flags
);
185 imx_avic_set_irq(opaque
, i
, 0);
188 return 0xffffffffULL
;
190 case 18:/* Interrupt source register high */
191 return s
->pending
>> 32;
193 case 19:/* Interrupt source register low */
194 return s
->pending
& 0xffffffffULL
;
196 case 20:/* Interrupt Force Register high */
197 case 21:/* Interrupt Force Register low */
200 case 22:/* Normal Interrupt Pending Register High */
201 return (s
->pending
& s
->enabled
& ~s
->is_fiq
) >> 32;
203 case 23:/* Normal Interrupt Pending Register Low */
204 return (s
->pending
& s
->enabled
& ~s
->is_fiq
) & 0xffffffffULL
;
206 case 24: /* Fast Interrupt Pending Register High */
207 return (s
->pending
& s
->enabled
& s
->is_fiq
) >> 32;
209 case 25: /* Fast Interrupt Pending Register Low */
210 return (s
->pending
& s
->enabled
& s
->is_fiq
) & 0xffffffffULL
;
212 case 0x40: /* AVIC vector 0, use for WFI WAR */
216 IPRINTF("%s: Bad offset 0x%x\n", __func__
, (int)offset
);
221 static void imx_avic_write(void *opaque
, hwaddr offset
,
222 uint64_t val
, unsigned size
)
224 IMXAVICState
*s
= (IMXAVICState
*)opaque
;
226 /* Vector Registers not yet supported */
227 if (offset
>= 0x100 && offset
<= 0x2fc) {
228 IPRINTF("%s to vector register %d ignored\n", __func__
,
229 (unsigned int)((offset
- 0x100) >> 2));
233 DPRINTF("%s(0x%x) = %x\n", __func__
,
234 (unsigned int)offset
>>2, (unsigned int)val
);
235 switch (offset
>> 2) {
236 case 0: /* Interrupt Control Register, INTCNTL */
237 s
->intcntl
= val
& (ABFEN
| NIDIS
| FIDIS
| NIAD
| FIAD
| NM
);
238 if (s
->intcntl
& ABFEN
) {
239 s
->intcntl
&= ~(val
& ABFLAG
);
243 case 1: /* Normal Interrupt Mask Register, NIMASK */
244 s
->intmask
= val
& 0x1f;
247 case 2: /* Interrupt Enable Number Register, INTENNUM */
248 DPRINTF("enable(%d)\n", (int)val
);
250 s
->enabled
|= (1ULL << val
);
253 case 3: /* Interrupt Disable Number Register, INTDISNUM */
254 DPRINTF("disable(%d)\n", (int)val
);
256 s
->enabled
&= ~(1ULL << val
);
259 case 4: /* Interrupt Enable Number Register High */
260 s
->enabled
= (s
->enabled
& 0xffffffffULL
) | (val
<< 32);
263 case 5: /* Interrupt Enable Number Register Low */
264 s
->enabled
= (s
->enabled
& 0xffffffff00000000ULL
) | val
;
267 case 6: /* Interrupt Type Register High */
268 s
->is_fiq
= (s
->is_fiq
& 0xffffffffULL
) | (val
<< 32);
271 case 7: /* Interrupt Type Register Low */
272 s
->is_fiq
= (s
->is_fiq
& 0xffffffff00000000ULL
) | val
;
275 case 8: /* Normal Interrupt Priority Register 7 */
276 case 9: /* Normal Interrupt Priority Register 6 */
277 case 10:/* Normal Interrupt Priority Register 5 */
278 case 11:/* Normal Interrupt Priority Register 4 */
279 case 12:/* Normal Interrupt Priority Register 3 */
280 case 13:/* Normal Interrupt Priority Register 2 */
281 case 14:/* Normal Interrupt Priority Register 1 */
282 case 15:/* Normal Interrupt Priority Register 0 */
283 s
->prio
[15-(offset
>>2)] = val
;
286 /* Read-only registers, writes ignored */
287 case 16:/* Normal Interrupt Vector and Status register */
288 case 17:/* Fast Interrupt vector and status register */
289 case 18:/* Interrupt source register high */
290 case 19:/* Interrupt source register low */
293 case 20:/* Interrupt Force Register high */
294 s
->pending
= (s
->pending
& 0xffffffffULL
) | (val
<< 32);
297 case 21:/* Interrupt Force Register low */
298 s
->pending
= (s
->pending
& 0xffffffff00000000ULL
) | val
;
301 case 22:/* Normal Interrupt Pending Register High */
302 case 23:/* Normal Interrupt Pending Register Low */
303 case 24: /* Fast Interrupt Pending Register High */
304 case 25: /* Fast Interrupt Pending Register Low */
308 IPRINTF("%s: Bad offset %x\n", __func__
, (int)offset
);
313 static const MemoryRegionOps imx_avic_ops
= {
314 .read
= imx_avic_read
,
315 .write
= imx_avic_write
,
316 .endianness
= DEVICE_NATIVE_ENDIAN
,
319 static void imx_avic_reset(DeviceState
*dev
)
321 IMXAVICState
*s
= IMX_AVIC(dev
);
328 memset(s
->prio
, 0, sizeof s
->prio
);
331 static int imx_avic_init(SysBusDevice
*sbd
)
333 DeviceState
*dev
= DEVICE(sbd
);
334 IMXAVICState
*s
= IMX_AVIC(dev
);
336 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_avic_ops
, s
,
337 TYPE_IMX_AVIC
, 0x1000);
338 sysbus_init_mmio(sbd
, &s
->iomem
);
340 qdev_init_gpio_in(dev
, imx_avic_set_irq
, IMX_AVIC_NUM_IRQS
);
341 sysbus_init_irq(sbd
, &s
->irq
);
342 sysbus_init_irq(sbd
, &s
->fiq
);
348 static void imx_avic_class_init(ObjectClass
*klass
, void *data
)
350 DeviceClass
*dc
= DEVICE_CLASS(klass
);
351 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
352 k
->init
= imx_avic_init
;
353 dc
->vmsd
= &vmstate_imx_avic
;
354 dc
->reset
= imx_avic_reset
;
355 dc
->desc
= "i.MX Advanced Vector Interrupt Controller";
358 static const TypeInfo imx_avic_info
= {
359 .name
= TYPE_IMX_AVIC
,
360 .parent
= TYPE_SYS_BUS_DEVICE
,
361 .instance_size
= sizeof(IMXAVICState
),
362 .class_init
= imx_avic_class_init
,
365 static void imx_avic_register_types(void)
367 type_register_static(&imx_avic_info
);
370 type_init(imx_avic_register_types
)