4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
26 #include "exec/cpu_ldst.h"
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
31 #include "trace-tcg.h"
35 //#define DEBUG_DISPATCH 1
37 /* Fake floating point. */
38 #define tcg_gen_mov_f64 tcg_gen_mov_i64
39 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
40 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
42 #define DEFO32(name, offset) static TCGv QREG_##name;
43 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
44 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
50 static TCGv_i32 cpu_halted
;
51 static TCGv_i32 cpu_exception_index
;
53 static TCGv_env cpu_env
;
55 static char cpu_reg_names
[3*8*3 + 5*4];
56 static TCGv cpu_dregs
[8];
57 static TCGv cpu_aregs
[8];
58 static TCGv_i64 cpu_fregs
[8];
59 static TCGv_i64 cpu_macc
[4];
61 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
62 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
63 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
64 #define MACREG(acc) cpu_macc[acc]
65 #define QREG_SP cpu_aregs[7]
67 static TCGv NULL_QREG
;
68 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
69 /* Used to distinguish stores from bad addressing modes. */
70 static TCGv store_dummy
;
72 #include "exec/gen-icount.h"
74 void m68k_tcg_init(void)
79 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
81 #define DEFO32(name, offset) \
82 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
83 offsetof(CPUM68KState, offset), #name);
84 #define DEFO64(name, offset) \
85 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
86 offsetof(CPUM68KState, offset), #name);
87 #define DEFF64(name, offset) DEFO64(name, offset)
93 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
94 -offsetof(M68kCPU
, env
) +
95 offsetof(CPUState
, halted
), "HALTED");
96 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
97 -offsetof(M68kCPU
, env
) +
98 offsetof(CPUState
, exception_index
),
102 for (i
= 0; i
< 8; i
++) {
103 sprintf(p
, "D%d", i
);
104 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
105 offsetof(CPUM68KState
, dregs
[i
]), p
);
107 sprintf(p
, "A%d", i
);
108 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
109 offsetof(CPUM68KState
, aregs
[i
]), p
);
111 sprintf(p
, "F%d", i
);
112 cpu_fregs
[i
] = tcg_global_mem_new_i64(cpu_env
,
113 offsetof(CPUM68KState
, fregs
[i
]), p
);
116 for (i
= 0; i
< 4; i
++) {
117 sprintf(p
, "ACC%d", i
);
118 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
119 offsetof(CPUM68KState
, macc
[i
]), p
);
123 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
124 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
127 /* internal defines */
128 typedef struct DisasContext
{
130 target_ulong insn_pc
; /* Start of the current instruction. */
136 struct TranslationBlock
*tb
;
137 int singlestep_enabled
;
142 #define DISAS_JUMP_NEXT 4
144 #if defined(CONFIG_USER_ONLY)
147 #define IS_USER(s) s->user
150 /* XXX: move that elsewhere */
151 /* ??? Fix exceptions. */
152 static void *gen_throws_exception
;
153 #define gen_last_qop NULL
161 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
163 #ifdef DEBUG_DISPATCH
164 #define DISAS_INSN(name) \
165 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
167 static void disas_##name(CPUM68KState *env, DisasContext *s, \
170 qemu_log("Dispatch " #name "\n"); \
171 real_disas_##name(s, env, insn); \
173 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
176 #define DISAS_INSN(name) \
177 static void disas_##name(CPUM68KState *env, DisasContext *s, \
181 /* Generate a load from the specified address. Narrow values are
182 sign extended to full register width. */
183 static inline TCGv
gen_load(DisasContext
* s
, int opsize
, TCGv addr
, int sign
)
186 int index
= IS_USER(s
);
187 tmp
= tcg_temp_new_i32();
191 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
193 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
197 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
199 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
203 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
206 g_assert_not_reached();
208 gen_throws_exception
= gen_last_qop
;
212 static inline TCGv_i64
gen_load64(DisasContext
* s
, TCGv addr
)
215 int index
= IS_USER(s
);
216 tmp
= tcg_temp_new_i64();
217 tcg_gen_qemu_ldf64(tmp
, addr
, index
);
218 gen_throws_exception
= gen_last_qop
;
222 /* Generate a store. */
223 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
)
225 int index
= IS_USER(s
);
228 tcg_gen_qemu_st8(val
, addr
, index
);
231 tcg_gen_qemu_st16(val
, addr
, index
);
235 tcg_gen_qemu_st32(val
, addr
, index
);
238 g_assert_not_reached();
240 gen_throws_exception
= gen_last_qop
;
243 static inline void gen_store64(DisasContext
*s
, TCGv addr
, TCGv_i64 val
)
245 int index
= IS_USER(s
);
246 tcg_gen_qemu_stf64(val
, addr
, index
);
247 gen_throws_exception
= gen_last_qop
;
256 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
257 otherwise generate a store. */
258 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
261 if (what
== EA_STORE
) {
262 gen_store(s
, opsize
, addr
, val
);
265 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
);
269 /* Read a 32-bit immediate constant. */
270 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
273 im
= ((uint32_t)cpu_lduw_code(env
, s
->pc
)) << 16;
275 im
|= cpu_lduw_code(env
, s
->pc
);
280 /* Calculate and address index. */
281 static TCGv
gen_addr_index(uint16_t ext
, TCGv tmp
)
286 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
287 if ((ext
& 0x800) == 0) {
288 tcg_gen_ext16s_i32(tmp
, add
);
291 scale
= (ext
>> 9) & 3;
293 tcg_gen_shli_i32(tmp
, add
, scale
);
299 /* Handle a base + index + displacement effective addresss.
300 A NULL_QREG base means pc-relative. */
301 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
310 ext
= cpu_lduw_code(env
, s
->pc
);
313 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
317 /* full extension word format */
318 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
321 if ((ext
& 0x30) > 0x10) {
322 /* base displacement */
323 if ((ext
& 0x30) == 0x20) {
324 bd
= (int16_t)cpu_lduw_code(env
, s
->pc
);
327 bd
= read_im32(env
, s
);
332 tmp
= tcg_temp_new();
333 if ((ext
& 0x44) == 0) {
335 add
= gen_addr_index(ext
, tmp
);
339 if ((ext
& 0x80) == 0) {
340 /* base not suppressed */
341 if (IS_NULL_QREG(base
)) {
342 base
= tcg_const_i32(offset
+ bd
);
345 if (!IS_NULL_QREG(add
)) {
346 tcg_gen_add_i32(tmp
, add
, base
);
352 if (!IS_NULL_QREG(add
)) {
354 tcg_gen_addi_i32(tmp
, add
, bd
);
358 add
= tcg_const_i32(bd
);
360 if ((ext
& 3) != 0) {
361 /* memory indirect */
362 base
= gen_load(s
, OS_LONG
, add
, 0);
363 if ((ext
& 0x44) == 4) {
364 add
= gen_addr_index(ext
, tmp
);
365 tcg_gen_add_i32(tmp
, add
, base
);
371 /* outer displacement */
372 if ((ext
& 3) == 2) {
373 od
= (int16_t)cpu_lduw_code(env
, s
->pc
);
376 od
= read_im32(env
, s
);
382 tcg_gen_addi_i32(tmp
, add
, od
);
387 /* brief extension word format */
388 tmp
= tcg_temp_new();
389 add
= gen_addr_index(ext
, tmp
);
390 if (!IS_NULL_QREG(base
)) {
391 tcg_gen_add_i32(tmp
, add
, base
);
393 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
395 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
402 /* Update the CPU env CC_OP state. */
403 static inline void gen_flush_cc_op(DisasContext
*s
)
405 if (s
->cc_op
!= CC_OP_DYNAMIC
)
406 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
409 /* Evaluate all the CC flags. */
410 static inline void gen_flush_flags(DisasContext
*s
)
412 if (s
->cc_op
== CC_OP_FLAGS
)
415 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
416 s
->cc_op
= CC_OP_FLAGS
;
419 static void gen_logic_cc(DisasContext
*s
, TCGv val
)
421 tcg_gen_mov_i32(QREG_CC_DEST
, val
);
422 s
->cc_op
= CC_OP_LOGIC
;
425 static void gen_update_cc_add(TCGv dest
, TCGv src
)
427 tcg_gen_mov_i32(QREG_CC_DEST
, dest
);
428 tcg_gen_mov_i32(QREG_CC_SRC
, src
);
431 static inline int opsize_bytes(int opsize
)
434 case OS_BYTE
: return 1;
435 case OS_WORD
: return 2;
436 case OS_LONG
: return 4;
437 case OS_SINGLE
: return 4;
438 case OS_DOUBLE
: return 8;
440 g_assert_not_reached();
444 /* Assign value to a register. If the width is less than the register width
445 only the low part of the register is set. */
446 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
451 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
452 tmp
= tcg_temp_new();
453 tcg_gen_ext8u_i32(tmp
, val
);
454 tcg_gen_or_i32(reg
, reg
, tmp
);
457 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
458 tmp
= tcg_temp_new();
459 tcg_gen_ext16u_i32(tmp
, val
);
460 tcg_gen_or_i32(reg
, reg
, tmp
);
464 tcg_gen_mov_i32(reg
, val
);
467 g_assert_not_reached();
471 /* Sign or zero extend a value. */
472 static inline TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
478 tmp
= tcg_temp_new();
480 tcg_gen_ext8s_i32(tmp
, val
);
482 tcg_gen_ext8u_i32(tmp
, val
);
485 tmp
= tcg_temp_new();
487 tcg_gen_ext16s_i32(tmp
, val
);
489 tcg_gen_ext16u_i32(tmp
, val
);
496 g_assert_not_reached();
501 /* Generate code for an "effective address". Does not adjust the base
502 register for autoincrement addressing modes. */
503 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
511 switch ((insn
>> 3) & 7) {
512 case 0: /* Data register direct. */
513 case 1: /* Address register direct. */
515 case 2: /* Indirect register */
516 case 3: /* Indirect postincrement. */
517 return AREG(insn
, 0);
518 case 4: /* Indirect predecrememnt. */
520 tmp
= tcg_temp_new();
521 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
523 case 5: /* Indirect displacement. */
525 tmp
= tcg_temp_new();
526 ext
= cpu_lduw_code(env
, s
->pc
);
528 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
530 case 6: /* Indirect index + displacement. */
532 return gen_lea_indexed(env
, s
, reg
);
535 case 0: /* Absolute short. */
536 offset
= cpu_ldsw_code(env
, s
->pc
);
538 return tcg_const_i32(offset
);
539 case 1: /* Absolute long. */
540 offset
= read_im32(env
, s
);
541 return tcg_const_i32(offset
);
542 case 2: /* pc displacement */
544 offset
+= cpu_ldsw_code(env
, s
->pc
);
546 return tcg_const_i32(offset
);
547 case 3: /* pc index+displacement. */
548 return gen_lea_indexed(env
, s
, NULL_QREG
);
549 case 4: /* Immediate. */
554 /* Should never happen. */
558 /* Helper function for gen_ea. Reuse the computed address between the
559 for read/write operands. */
560 static inline TCGv
gen_ea_once(CPUM68KState
*env
, DisasContext
*s
,
561 uint16_t insn
, int opsize
, TCGv val
,
562 TCGv
*addrp
, ea_what what
)
566 if (addrp
&& what
== EA_STORE
) {
569 tmp
= gen_lea(env
, s
, insn
, opsize
);
570 if (IS_NULL_QREG(tmp
))
575 return gen_ldst(s
, opsize
, tmp
, val
, what
);
578 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
579 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
580 ADDRP is non-null for readwrite operands. */
581 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
582 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
588 switch ((insn
>> 3) & 7) {
589 case 0: /* Data register direct. */
591 if (what
== EA_STORE
) {
592 gen_partset_reg(opsize
, reg
, val
);
595 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
597 case 1: /* Address register direct. */
599 if (what
== EA_STORE
) {
600 tcg_gen_mov_i32(reg
, val
);
603 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
605 case 2: /* Indirect register */
607 return gen_ldst(s
, opsize
, reg
, val
, what
);
608 case 3: /* Indirect postincrement. */
610 result
= gen_ldst(s
, opsize
, reg
, val
, what
);
611 /* ??? This is not exception safe. The instruction may still
612 fault after this point. */
613 if (what
== EA_STORE
|| !addrp
)
614 tcg_gen_addi_i32(reg
, reg
, opsize_bytes(opsize
));
616 case 4: /* Indirect predecrememnt. */
619 if (addrp
&& what
== EA_STORE
) {
622 tmp
= gen_lea(env
, s
, insn
, opsize
);
623 if (IS_NULL_QREG(tmp
))
628 result
= gen_ldst(s
, opsize
, tmp
, val
, what
);
629 /* ??? This is not exception safe. The instruction may still
630 fault after this point. */
631 if (what
== EA_STORE
|| !addrp
) {
633 tcg_gen_mov_i32(reg
, tmp
);
637 case 5: /* Indirect displacement. */
638 case 6: /* Indirect index + displacement. */
639 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
642 case 0: /* Absolute short. */
643 case 1: /* Absolute long. */
644 case 2: /* pc displacement */
645 case 3: /* pc index+displacement. */
646 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
647 case 4: /* Immediate. */
648 /* Sign extend values for consistency. */
651 if (what
== EA_LOADS
) {
652 offset
= cpu_ldsb_code(env
, s
->pc
+ 1);
654 offset
= cpu_ldub_code(env
, s
->pc
+ 1);
659 if (what
== EA_LOADS
) {
660 offset
= cpu_ldsw_code(env
, s
->pc
);
662 offset
= cpu_lduw_code(env
, s
->pc
);
667 offset
= read_im32(env
, s
);
670 g_assert_not_reached();
672 return tcg_const_i32(offset
);
677 /* Should never happen. */
681 /* This generates a conditional branch, clobbering all temporaries. */
682 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
686 /* TODO: Optimize compare/branch pairs rather than always flushing
687 flag state to CC_OP_FLAGS. */
695 case 2: /* HI (!C && !Z) */
696 tmp
= tcg_temp_new();
697 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_C
| CCF_Z
);
698 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
700 case 3: /* LS (C || Z) */
701 tmp
= tcg_temp_new();
702 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_C
| CCF_Z
);
703 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
705 case 4: /* CC (!C) */
706 tmp
= tcg_temp_new();
707 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_C
);
708 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
711 tmp
= tcg_temp_new();
712 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_C
);
713 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
715 case 6: /* NE (!Z) */
716 tmp
= tcg_temp_new();
717 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_Z
);
718 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
721 tmp
= tcg_temp_new();
722 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_Z
);
723 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
725 case 8: /* VC (!V) */
726 tmp
= tcg_temp_new();
727 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_V
);
728 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
731 tmp
= tcg_temp_new();
732 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_V
);
733 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
735 case 10: /* PL (!N) */
736 tmp
= tcg_temp_new();
737 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_N
);
738 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
740 case 11: /* MI (N) */
741 tmp
= tcg_temp_new();
742 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_N
);
743 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
745 case 12: /* GE (!(N ^ V)) */
746 tmp
= tcg_temp_new();
747 assert(CCF_V
== (CCF_N
>> 2));
748 tcg_gen_shri_i32(tmp
, QREG_CC_DEST
, 2);
749 tcg_gen_xor_i32(tmp
, tmp
, QREG_CC_DEST
);
750 tcg_gen_andi_i32(tmp
, tmp
, CCF_V
);
751 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
753 case 13: /* LT (N ^ V) */
754 tmp
= tcg_temp_new();
755 assert(CCF_V
== (CCF_N
>> 2));
756 tcg_gen_shri_i32(tmp
, QREG_CC_DEST
, 2);
757 tcg_gen_xor_i32(tmp
, tmp
, QREG_CC_DEST
);
758 tcg_gen_andi_i32(tmp
, tmp
, CCF_V
);
759 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
761 case 14: /* GT (!(Z || (N ^ V))) */
762 tmp
= tcg_temp_new();
763 assert(CCF_V
== (CCF_N
>> 2));
764 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_N
);
765 tcg_gen_shri_i32(tmp
, tmp
, 2);
766 tcg_gen_xor_i32(tmp
, tmp
, QREG_CC_DEST
);
767 tcg_gen_andi_i32(tmp
, tmp
, CCF_V
| CCF_Z
);
768 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, l1
);
770 case 15: /* LE (Z || (N ^ V)) */
771 tmp
= tcg_temp_new();
772 assert(CCF_V
== (CCF_N
>> 2));
773 tcg_gen_andi_i32(tmp
, QREG_CC_DEST
, CCF_N
);
774 tcg_gen_shri_i32(tmp
, tmp
, 2);
775 tcg_gen_xor_i32(tmp
, tmp
, QREG_CC_DEST
);
776 tcg_gen_andi_i32(tmp
, tmp
, CCF_V
| CCF_Z
);
777 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, l1
);
780 /* Should ever happen. */
791 l1
= gen_new_label();
792 cond
= (insn
>> 8) & 0xf;
794 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
795 /* This is safe because we modify the reg directly, with no other values
797 gen_jmpcc(s
, cond
^ 1, l1
);
798 tcg_gen_ori_i32(reg
, reg
, 0xff);
802 /* Force a TB lookup after an instruction that changes the CPU state. */
803 static void gen_lookup_tb(DisasContext
*s
)
806 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
807 s
->is_jmp
= DISAS_UPDATE
;
810 /* Generate a jump to an immediate address. */
811 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
814 tcg_gen_movi_i32(QREG_PC
, dest
);
815 s
->is_jmp
= DISAS_JUMP
;
818 /* Generate a jump to the address in qreg DEST. */
819 static void gen_jmp(DisasContext
*s
, TCGv dest
)
822 tcg_gen_mov_i32(QREG_PC
, dest
);
823 s
->is_jmp
= DISAS_JUMP
;
826 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
829 gen_jmp_im(s
, where
);
830 gen_helper_raise_exception(cpu_env
, tcg_const_i32(nr
));
833 static inline void gen_addr_fault(DisasContext
*s
)
835 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
838 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
839 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
840 op_sign ? EA_LOADS : EA_LOADU); \
841 if (IS_NULL_QREG(result)) { \
847 #define DEST_EA(env, insn, opsize, val, addrp) do { \
848 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
849 if (IS_NULL_QREG(ea_result)) { \
855 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
857 #ifndef CONFIG_USER_ONLY
858 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
859 (s
->insn_pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
865 /* Generate a jump to an immediate address. */
866 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
868 if (unlikely(s
->singlestep_enabled
)) {
869 gen_exception(s
, dest
, EXCP_DEBUG
);
870 } else if (use_goto_tb(s
, dest
)) {
872 tcg_gen_movi_i32(QREG_PC
, dest
);
873 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
878 s
->is_jmp
= DISAS_TB_JUMP
;
881 DISAS_INSN(undef_mac
)
883 gen_exception(s
, s
->pc
- 2, EXCP_LINEA
);
886 DISAS_INSN(undef_fpu
)
888 gen_exception(s
, s
->pc
- 2, EXCP_LINEF
);
893 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
895 gen_exception(s
, s
->pc
- 2, EXCP_UNSUPPORTED
);
896 cpu_abort(CPU(cpu
), "Illegal instruction: %04x @ %08x", insn
, s
->pc
- 2);
906 sign
= (insn
& 0x100) != 0;
908 tmp
= tcg_temp_new();
910 tcg_gen_ext16s_i32(tmp
, reg
);
912 tcg_gen_ext16u_i32(tmp
, reg
);
913 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
914 tcg_gen_mul_i32(tmp
, tmp
, src
);
915 tcg_gen_mov_i32(reg
, tmp
);
916 /* Unlike m68k, coldfire always clears the overflow bit. */
917 gen_logic_cc(s
, tmp
);
927 sign
= (insn
& 0x100) != 0;
930 tcg_gen_ext16s_i32(QREG_DIV1
, reg
);
932 tcg_gen_ext16u_i32(QREG_DIV1
, reg
);
934 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
935 tcg_gen_mov_i32(QREG_DIV2
, src
);
937 gen_helper_divs(cpu_env
, tcg_const_i32(1));
939 gen_helper_divu(cpu_env
, tcg_const_i32(1));
942 tmp
= tcg_temp_new();
943 src
= tcg_temp_new();
944 tcg_gen_ext16u_i32(tmp
, QREG_DIV1
);
945 tcg_gen_shli_i32(src
, QREG_DIV2
, 16);
946 tcg_gen_or_i32(reg
, tmp
, src
);
947 s
->cc_op
= CC_OP_FLAGS
;
957 ext
= cpu_lduw_code(env
, s
->pc
);
960 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
965 tcg_gen_mov_i32(QREG_DIV1
, num
);
966 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
967 tcg_gen_mov_i32(QREG_DIV2
, den
);
969 gen_helper_divs(cpu_env
, tcg_const_i32(0));
971 gen_helper_divu(cpu_env
, tcg_const_i32(0));
973 if ((ext
& 7) == ((ext
>> 12) & 7)) {
975 tcg_gen_mov_i32 (reg
, QREG_DIV1
);
978 tcg_gen_mov_i32 (reg
, QREG_DIV2
);
980 s
->cc_op
= CC_OP_FLAGS
;
992 add
= (insn
& 0x4000) != 0;
994 dest
= tcg_temp_new();
996 SRC_EA(env
, tmp
, OS_LONG
, 0, &addr
);
1000 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1003 tcg_gen_add_i32(dest
, tmp
, src
);
1004 gen_helper_xflag_lt(QREG_CC_X
, dest
, src
);
1005 s
->cc_op
= CC_OP_ADD
;
1007 gen_helper_xflag_lt(QREG_CC_X
, tmp
, src
);
1008 tcg_gen_sub_i32(dest
, tmp
, src
);
1009 s
->cc_op
= CC_OP_SUB
;
1011 gen_update_cc_add(dest
, src
);
1013 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1015 tcg_gen_mov_i32(reg
, dest
);
1020 /* Reverse the order of the bits in REG. */
1024 reg
= DREG(insn
, 0);
1025 gen_helper_bitrev(reg
, reg
);
1028 DISAS_INSN(bitop_reg
)
1038 if ((insn
& 0x38) != 0)
1042 op
= (insn
>> 6) & 3;
1043 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1044 src2
= DREG(insn
, 9);
1045 dest
= tcg_temp_new();
1048 tmp
= tcg_temp_new();
1049 if (opsize
== OS_BYTE
)
1050 tcg_gen_andi_i32(tmp
, src2
, 7);
1052 tcg_gen_andi_i32(tmp
, src2
, 31);
1054 tmp
= tcg_temp_new();
1055 tcg_gen_shr_i32(tmp
, src1
, src2
);
1056 tcg_gen_andi_i32(tmp
, tmp
, 1);
1057 tcg_gen_shli_i32(tmp
, tmp
, 2);
1058 /* Clear CCF_Z if bit set. */
1059 tcg_gen_ori_i32(QREG_CC_DEST
, QREG_CC_DEST
, CCF_Z
);
1060 tcg_gen_xor_i32(QREG_CC_DEST
, QREG_CC_DEST
, tmp
);
1062 tcg_gen_shl_i32(tmp
, tcg_const_i32(1), src2
);
1065 tcg_gen_xor_i32(dest
, src1
, tmp
);
1068 tcg_gen_not_i32(tmp
, tmp
);
1069 tcg_gen_and_i32(dest
, src1
, tmp
);
1072 tcg_gen_or_i32(dest
, src1
, tmp
);
1078 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1084 reg
= DREG(insn
, 0);
1086 gen_helper_sats(reg
, reg
, QREG_CC_DEST
);
1087 gen_logic_cc(s
, reg
);
1090 static void gen_push(DisasContext
*s
, TCGv val
)
1094 tmp
= tcg_temp_new();
1095 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1096 gen_store(s
, OS_LONG
, tmp
, val
);
1097 tcg_gen_mov_i32(QREG_SP
, tmp
);
1109 mask
= cpu_lduw_code(env
, s
->pc
);
1111 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1112 if (IS_NULL_QREG(tmp
)) {
1116 addr
= tcg_temp_new();
1117 tcg_gen_mov_i32(addr
, tmp
);
1118 is_load
= ((insn
& 0x0400) != 0);
1119 for (i
= 0; i
< 16; i
++, mask
>>= 1) {
1126 tmp
= gen_load(s
, OS_LONG
, addr
, 0);
1127 tcg_gen_mov_i32(reg
, tmp
);
1129 gen_store(s
, OS_LONG
, addr
, reg
);
1132 tcg_gen_addi_i32(addr
, addr
, 4);
1137 DISAS_INSN(bitop_im
)
1147 if ((insn
& 0x38) != 0)
1151 op
= (insn
>> 6) & 3;
1153 bitnum
= cpu_lduw_code(env
, s
->pc
);
1155 if (bitnum
& 0xff00) {
1156 disas_undef(env
, s
, insn
);
1160 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1163 if (opsize
== OS_BYTE
)
1169 tmp
= tcg_temp_new();
1170 assert (CCF_Z
== (1 << 2));
1172 tcg_gen_shri_i32(tmp
, src1
, bitnum
- 2);
1173 else if (bitnum
< 2)
1174 tcg_gen_shli_i32(tmp
, src1
, 2 - bitnum
);
1176 tcg_gen_mov_i32(tmp
, src1
);
1177 tcg_gen_andi_i32(tmp
, tmp
, CCF_Z
);
1178 /* Clear CCF_Z if bit set. */
1179 tcg_gen_ori_i32(QREG_CC_DEST
, QREG_CC_DEST
, CCF_Z
);
1180 tcg_gen_xor_i32(QREG_CC_DEST
, QREG_CC_DEST
, tmp
);
1184 tcg_gen_xori_i32(tmp
, src1
, mask
);
1187 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
1190 tcg_gen_ori_i32(tmp
, src1
, mask
);
1195 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
1199 DISAS_INSN(arith_im
)
1207 op
= (insn
>> 9) & 7;
1208 SRC_EA(env
, src1
, OS_LONG
, 0, (op
== 6) ? NULL
: &addr
);
1209 im
= read_im32(env
, s
);
1210 dest
= tcg_temp_new();
1213 tcg_gen_ori_i32(dest
, src1
, im
);
1214 gen_logic_cc(s
, dest
);
1217 tcg_gen_andi_i32(dest
, src1
, im
);
1218 gen_logic_cc(s
, dest
);
1221 tcg_gen_mov_i32(dest
, src1
);
1222 gen_helper_xflag_lt(QREG_CC_X
, dest
, tcg_const_i32(im
));
1223 tcg_gen_subi_i32(dest
, dest
, im
);
1224 gen_update_cc_add(dest
, tcg_const_i32(im
));
1225 s
->cc_op
= CC_OP_SUB
;
1228 tcg_gen_mov_i32(dest
, src1
);
1229 tcg_gen_addi_i32(dest
, dest
, im
);
1230 gen_update_cc_add(dest
, tcg_const_i32(im
));
1231 gen_helper_xflag_lt(QREG_CC_X
, dest
, tcg_const_i32(im
));
1232 s
->cc_op
= CC_OP_ADD
;
1235 tcg_gen_xori_i32(dest
, src1
, im
);
1236 gen_logic_cc(s
, dest
);
1239 tcg_gen_mov_i32(dest
, src1
);
1240 tcg_gen_subi_i32(dest
, dest
, im
);
1241 gen_update_cc_add(dest
, tcg_const_i32(im
));
1242 s
->cc_op
= CC_OP_SUB
;
1248 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1256 reg
= DREG(insn
, 0);
1257 tcg_gen_bswap32_i32(reg
, reg
);
1267 switch (insn
>> 12) {
1268 case 1: /* move.b */
1271 case 2: /* move.l */
1274 case 3: /* move.w */
1280 SRC_EA(env
, src
, opsize
, 1, NULL
);
1281 op
= (insn
>> 6) & 7;
1284 /* The value will already have been sign extended. */
1285 dest
= AREG(insn
, 9);
1286 tcg_gen_mov_i32(dest
, src
);
1290 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
1291 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
1292 /* This will be correct because loads sign extend. */
1293 gen_logic_cc(s
, src
);
1302 reg
= DREG(insn
, 0);
1303 gen_helper_subx_cc(reg
, cpu_env
, tcg_const_i32(0), reg
);
1311 reg
= AREG(insn
, 9);
1312 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1313 if (IS_NULL_QREG(tmp
)) {
1317 tcg_gen_mov_i32(reg
, tmp
);
1324 switch ((insn
>> 6) & 3) {
1337 DEST_EA(env
, insn
, opsize
, tcg_const_i32(0), NULL
);
1338 gen_logic_cc(s
, tcg_const_i32(0));
1341 static TCGv
gen_get_ccr(DisasContext
*s
)
1346 dest
= tcg_temp_new();
1347 tcg_gen_shli_i32(dest
, QREG_CC_X
, 4);
1348 tcg_gen_or_i32(dest
, dest
, QREG_CC_DEST
);
1352 DISAS_INSN(move_from_ccr
)
1357 ccr
= gen_get_ccr(s
);
1358 reg
= DREG(insn
, 0);
1359 gen_partset_reg(OS_WORD
, reg
, ccr
);
1367 reg
= DREG(insn
, 0);
1368 src1
= tcg_temp_new();
1369 tcg_gen_mov_i32(src1
, reg
);
1370 tcg_gen_neg_i32(reg
, src1
);
1371 s
->cc_op
= CC_OP_SUB
;
1372 gen_update_cc_add(reg
, src1
);
1373 gen_helper_xflag_lt(QREG_CC_X
, tcg_const_i32(0), src1
);
1374 s
->cc_op
= CC_OP_SUB
;
1377 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
1379 tcg_gen_movi_i32(QREG_CC_DEST
, val
& 0xf);
1380 tcg_gen_movi_i32(QREG_CC_X
, (val
& 0x10) >> 4);
1382 gen_helper_set_sr(cpu_env
, tcg_const_i32(val
& 0xff00));
1386 static void gen_set_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1392 s
->cc_op
= CC_OP_FLAGS
;
1393 if ((insn
& 0x38) == 0)
1395 tmp
= tcg_temp_new();
1396 reg
= DREG(insn
, 0);
1397 tcg_gen_andi_i32(QREG_CC_DEST
, reg
, 0xf);
1398 tcg_gen_shri_i32(tmp
, reg
, 4);
1399 tcg_gen_andi_i32(QREG_CC_X
, tmp
, 1);
1401 gen_helper_set_sr(cpu_env
, reg
);
1404 else if ((insn
& 0x3f) == 0x3c)
1407 val
= cpu_lduw_code(env
, s
->pc
);
1409 gen_set_sr_im(s
, val
, ccr_only
);
1412 disas_undef(env
, s
, insn
);
1415 DISAS_INSN(move_to_ccr
)
1417 gen_set_sr(env
, s
, insn
, 1);
1424 reg
= DREG(insn
, 0);
1425 tcg_gen_not_i32(reg
, reg
);
1426 gen_logic_cc(s
, reg
);
1435 src1
= tcg_temp_new();
1436 src2
= tcg_temp_new();
1437 reg
= DREG(insn
, 0);
1438 tcg_gen_shli_i32(src1
, reg
, 16);
1439 tcg_gen_shri_i32(src2
, reg
, 16);
1440 tcg_gen_or_i32(reg
, src1
, src2
);
1441 gen_logic_cc(s
, reg
);
1448 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1449 if (IS_NULL_QREG(tmp
)) {
1462 reg
= DREG(insn
, 0);
1463 op
= (insn
>> 6) & 7;
1464 tmp
= tcg_temp_new();
1466 tcg_gen_ext16s_i32(tmp
, reg
);
1468 tcg_gen_ext8s_i32(tmp
, reg
);
1470 gen_partset_reg(OS_WORD
, reg
, tmp
);
1472 tcg_gen_mov_i32(reg
, tmp
);
1473 gen_logic_cc(s
, tmp
);
1481 switch ((insn
>> 6) & 3) {
1494 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
1495 gen_logic_cc(s
, tmp
);
1500 /* Implemented as a NOP. */
1505 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
1508 /* ??? This should be atomic. */
1515 dest
= tcg_temp_new();
1516 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
1517 gen_logic_cc(s
, src1
);
1518 tcg_gen_ori_i32(dest
, src1
, 0x80);
1519 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1529 /* The upper 32 bits of the product are discarded, so
1530 muls.l and mulu.l are functionally equivalent. */
1531 ext
= cpu_lduw_code(env
, s
->pc
);
1534 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1537 reg
= DREG(ext
, 12);
1538 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
1539 dest
= tcg_temp_new();
1540 tcg_gen_mul_i32(dest
, src1
, reg
);
1541 tcg_gen_mov_i32(reg
, dest
);
1542 /* Unlike m68k, coldfire always clears the overflow bit. */
1543 gen_logic_cc(s
, dest
);
1552 offset
= cpu_ldsw_code(env
, s
->pc
);
1554 reg
= AREG(insn
, 0);
1555 tmp
= tcg_temp_new();
1556 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1557 gen_store(s
, OS_LONG
, tmp
, reg
);
1558 if ((insn
& 7) != 7)
1559 tcg_gen_mov_i32(reg
, tmp
);
1560 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
1569 src
= tcg_temp_new();
1570 reg
= AREG(insn
, 0);
1571 tcg_gen_mov_i32(src
, reg
);
1572 tmp
= gen_load(s
, OS_LONG
, src
, 0);
1573 tcg_gen_mov_i32(reg
, tmp
);
1574 tcg_gen_addi_i32(QREG_SP
, src
, 4);
1585 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
1586 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
1594 /* Load the target address first to ensure correct exception
1596 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1597 if (IS_NULL_QREG(tmp
)) {
1601 if ((insn
& 0x40) == 0) {
1603 gen_push(s
, tcg_const_i32(s
->pc
));
1616 SRC_EA(env
, src1
, OS_LONG
, 0, &addr
);
1617 val
= (insn
>> 9) & 7;
1620 dest
= tcg_temp_new();
1621 tcg_gen_mov_i32(dest
, src1
);
1622 if ((insn
& 0x38) == 0x08) {
1623 /* Don't update condition codes if the destination is an
1624 address register. */
1625 if (insn
& 0x0100) {
1626 tcg_gen_subi_i32(dest
, dest
, val
);
1628 tcg_gen_addi_i32(dest
, dest
, val
);
1631 src2
= tcg_const_i32(val
);
1632 if (insn
& 0x0100) {
1633 gen_helper_xflag_lt(QREG_CC_X
, dest
, src2
);
1634 tcg_gen_subi_i32(dest
, dest
, val
);
1635 s
->cc_op
= CC_OP_SUB
;
1637 tcg_gen_addi_i32(dest
, dest
, val
);
1638 gen_helper_xflag_lt(QREG_CC_X
, dest
, src2
);
1639 s
->cc_op
= CC_OP_ADD
;
1641 gen_update_cc_add(dest
, src2
);
1643 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1649 case 2: /* One extension word. */
1652 case 3: /* Two extension words. */
1655 case 4: /* No extension words. */
1658 disas_undef(env
, s
, insn
);
1670 op
= (insn
>> 8) & 0xf;
1671 offset
= (int8_t)insn
;
1673 offset
= cpu_ldsw_code(env
, s
->pc
);
1675 } else if (offset
== -1) {
1676 offset
= read_im32(env
, s
);
1680 gen_push(s
, tcg_const_i32(s
->pc
));
1685 l1
= gen_new_label();
1686 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
1687 gen_jmp_tb(s
, 1, base
+ offset
);
1689 gen_jmp_tb(s
, 0, s
->pc
);
1691 /* Unconditional branch. */
1692 gen_jmp_tb(s
, 0, base
+ offset
);
1701 tcg_gen_movi_i32(DREG(insn
, 9), val
);
1702 gen_logic_cc(s
, tcg_const_i32(val
));
1715 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
1716 reg
= DREG(insn
, 9);
1717 tcg_gen_mov_i32(reg
, src
);
1718 gen_logic_cc(s
, src
);
1728 reg
= DREG(insn
, 9);
1729 dest
= tcg_temp_new();
1731 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1732 tcg_gen_or_i32(dest
, src
, reg
);
1733 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1735 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1736 tcg_gen_or_i32(dest
, src
, reg
);
1737 tcg_gen_mov_i32(reg
, dest
);
1739 gen_logic_cc(s
, dest
);
1747 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1748 reg
= AREG(insn
, 9);
1749 tcg_gen_sub_i32(reg
, reg
, src
);
1758 reg
= DREG(insn
, 9);
1759 src
= DREG(insn
, 0);
1760 gen_helper_subx_cc(reg
, cpu_env
, reg
, src
);
1768 val
= (insn
>> 9) & 7;
1771 src
= tcg_const_i32(val
);
1772 gen_logic_cc(s
, src
);
1773 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
1784 op
= (insn
>> 6) & 3;
1788 s
->cc_op
= CC_OP_CMPB
;
1792 s
->cc_op
= CC_OP_CMPW
;
1796 s
->cc_op
= CC_OP_SUB
;
1801 SRC_EA(env
, src
, opsize
, 1, NULL
);
1802 reg
= DREG(insn
, 9);
1803 dest
= tcg_temp_new();
1804 tcg_gen_sub_i32(dest
, reg
, src
);
1805 gen_update_cc_add(dest
, src
);
1820 SRC_EA(env
, src
, opsize
, 1, NULL
);
1821 reg
= AREG(insn
, 9);
1822 dest
= tcg_temp_new();
1823 tcg_gen_sub_i32(dest
, reg
, src
);
1824 gen_update_cc_add(dest
, src
);
1825 s
->cc_op
= CC_OP_SUB
;
1835 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1836 reg
= DREG(insn
, 9);
1837 dest
= tcg_temp_new();
1838 tcg_gen_xor_i32(dest
, src
, reg
);
1839 gen_logic_cc(s
, dest
);
1840 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1850 reg
= DREG(insn
, 9);
1851 dest
= tcg_temp_new();
1853 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1854 tcg_gen_and_i32(dest
, src
, reg
);
1855 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1857 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1858 tcg_gen_and_i32(dest
, src
, reg
);
1859 tcg_gen_mov_i32(reg
, dest
);
1861 gen_logic_cc(s
, dest
);
1869 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1870 reg
= AREG(insn
, 9);
1871 tcg_gen_add_i32(reg
, reg
, src
);
1880 reg
= DREG(insn
, 9);
1881 src
= DREG(insn
, 0);
1882 gen_helper_addx_cc(reg
, cpu_env
, reg
, src
);
1883 s
->cc_op
= CC_OP_FLAGS
;
1886 /* TODO: This could be implemented without helper functions. */
1887 DISAS_INSN(shift_im
)
1893 reg
= DREG(insn
, 0);
1894 tmp
= (insn
>> 9) & 7;
1897 shift
= tcg_const_i32(tmp
);
1898 /* No need to flush flags becuse we know we will set C flag. */
1900 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
1903 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
1905 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
1908 s
->cc_op
= CC_OP_SHIFT
;
1911 DISAS_INSN(shift_reg
)
1916 reg
= DREG(insn
, 0);
1917 shift
= DREG(insn
, 9);
1918 /* Shift by zero leaves C flag unmodified. */
1921 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
1924 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
1926 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
1929 s
->cc_op
= CC_OP_SHIFT
;
1935 reg
= DREG(insn
, 0);
1936 gen_logic_cc(s
, reg
);
1937 gen_helper_ff1(reg
, reg
);
1940 static TCGv
gen_get_sr(DisasContext
*s
)
1945 ccr
= gen_get_ccr(s
);
1946 sr
= tcg_temp_new();
1947 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
1948 tcg_gen_or_i32(sr
, sr
, ccr
);
1958 ext
= cpu_lduw_code(env
, s
->pc
);
1960 if (ext
!= 0x46FC) {
1961 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
1964 ext
= cpu_lduw_code(env
, s
->pc
);
1966 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
1967 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
1970 gen_push(s
, gen_get_sr(s
));
1971 gen_set_sr_im(s
, ext
, 0);
1974 DISAS_INSN(move_from_sr
)
1980 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
1984 reg
= DREG(insn
, 0);
1985 gen_partset_reg(OS_WORD
, reg
, sr
);
1988 DISAS_INSN(move_to_sr
)
1991 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
1994 gen_set_sr(env
, s
, insn
, 0);
1998 DISAS_INSN(move_from_usp
)
2001 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2004 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
2005 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2008 DISAS_INSN(move_to_usp
)
2011 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2014 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
2015 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2020 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
2028 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2032 ext
= cpu_lduw_code(env
, s
->pc
);
2035 gen_set_sr_im(s
, ext
, 0);
2036 tcg_gen_movi_i32(cpu_halted
, 1);
2037 gen_exception(s
, s
->pc
, EXCP_HLT
);
2043 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2046 gen_exception(s
, s
->pc
- 2, EXCP_RTE
);
2055 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2059 ext
= cpu_lduw_code(env
, s
->pc
);
2063 reg
= AREG(ext
, 12);
2065 reg
= DREG(ext
, 12);
2067 gen_helper_movec(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
2074 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2077 /* ICache fetch. Implement as no-op. */
2083 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2086 /* Cache push/invalidate. Implement as no-op. */
2091 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2096 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2099 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2102 /* TODO: Implement wdebug. */
2103 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
2108 gen_exception(s
, s
->pc
- 2, EXCP_TRAP0
+ (insn
& 0xf));
2111 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2112 immediately before the next FP instruction is executed. */
2126 ext
= cpu_lduw_code(env
, s
->pc
);
2128 opmode
= ext
& 0x7f;
2129 switch ((ext
>> 13) & 7) {
2134 case 3: /* fmove out */
2136 tmp32
= tcg_temp_new_i32();
2138 /* ??? TODO: Proper behavior on overflow. */
2139 switch ((ext
>> 10) & 7) {
2142 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2146 gen_helper_f64_to_f32(tmp32
, cpu_env
, src
);
2150 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2152 case 5: /* OS_DOUBLE */
2153 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2154 switch ((insn
>> 3) & 7) {
2159 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2162 offset
= cpu_ldsw_code(env
, s
->pc
);
2164 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2169 gen_store64(s
, tmp32
, src
);
2170 switch ((insn
>> 3) & 7) {
2172 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2173 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2176 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2179 tcg_temp_free_i32(tmp32
);
2183 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2188 DEST_EA(env
, insn
, opsize
, tmp32
, NULL
);
2189 tcg_temp_free_i32(tmp32
);
2191 case 4: /* fmove to control register. */
2192 switch ((ext
>> 10) & 7) {
2194 /* Not implemented. Ignore writes. */
2199 cpu_abort(NULL
, "Unimplemented: fmove to control %d",
2203 case 5: /* fmove from control register. */
2204 switch ((ext
>> 10) & 7) {
2206 /* Not implemented. Always return zero. */
2207 tmp32
= tcg_const_i32(0);
2212 cpu_abort(NULL
, "Unimplemented: fmove from control %d",
2216 DEST_EA(env
, insn
, OS_LONG
, tmp32
, NULL
);
2218 case 6: /* fmovem */
2224 if ((ext
& 0x1f00) != 0x1000 || (ext
& 0xff) == 0)
2226 tmp32
= gen_lea(env
, s
, insn
, OS_LONG
);
2227 if (IS_NULL_QREG(tmp32
)) {
2231 addr
= tcg_temp_new_i32();
2232 tcg_gen_mov_i32(addr
, tmp32
);
2234 for (i
= 0; i
< 8; i
++) {
2237 if (ext
& (1 << 13)) {
2239 tcg_gen_qemu_stf64(dest
, addr
, IS_USER(s
));
2242 tcg_gen_qemu_ldf64(dest
, addr
, IS_USER(s
));
2244 if (ext
& (mask
- 1))
2245 tcg_gen_addi_i32(addr
, addr
, 8);
2249 tcg_temp_free_i32(addr
);
2253 if (ext
& (1 << 14)) {
2254 /* Source effective address. */
2255 switch ((ext
>> 10) & 7) {
2256 case 0: opsize
= OS_LONG
; break;
2257 case 1: opsize
= OS_SINGLE
; break;
2258 case 4: opsize
= OS_WORD
; break;
2259 case 5: opsize
= OS_DOUBLE
; break;
2260 case 6: opsize
= OS_BYTE
; break;
2264 if (opsize
== OS_DOUBLE
) {
2265 tmp32
= tcg_temp_new_i32();
2266 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2267 switch ((insn
>> 3) & 7) {
2272 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2275 offset
= cpu_ldsw_code(env
, s
->pc
);
2277 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2280 offset
= cpu_ldsw_code(env
, s
->pc
);
2281 offset
+= s
->pc
- 2;
2283 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2288 src
= gen_load64(s
, tmp32
);
2289 switch ((insn
>> 3) & 7) {
2291 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2292 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2295 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2298 tcg_temp_free_i32(tmp32
);
2300 SRC_EA(env
, tmp32
, opsize
, 1, NULL
);
2301 src
= tcg_temp_new_i64();
2306 gen_helper_i32_to_f64(src
, cpu_env
, tmp32
);
2309 gen_helper_f32_to_f64(src
, cpu_env
, tmp32
);
2314 /* Source register. */
2315 src
= FREG(ext
, 10);
2317 dest
= FREG(ext
, 7);
2318 res
= tcg_temp_new_i64();
2320 tcg_gen_mov_f64(res
, dest
);
2324 case 0: case 0x40: case 0x44: /* fmove */
2325 tcg_gen_mov_f64(res
, src
);
2328 gen_helper_iround_f64(res
, cpu_env
, src
);
2331 case 3: /* fintrz */
2332 gen_helper_itrunc_f64(res
, cpu_env
, src
);
2335 case 4: case 0x41: case 0x45: /* fsqrt */
2336 gen_helper_sqrt_f64(res
, cpu_env
, src
);
2338 case 0x18: case 0x58: case 0x5c: /* fabs */
2339 gen_helper_abs_f64(res
, src
);
2341 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2342 gen_helper_chs_f64(res
, src
);
2344 case 0x20: case 0x60: case 0x64: /* fdiv */
2345 gen_helper_div_f64(res
, cpu_env
, res
, src
);
2347 case 0x22: case 0x62: case 0x66: /* fadd */
2348 gen_helper_add_f64(res
, cpu_env
, res
, src
);
2350 case 0x23: case 0x63: case 0x67: /* fmul */
2351 gen_helper_mul_f64(res
, cpu_env
, res
, src
);
2353 case 0x28: case 0x68: case 0x6c: /* fsub */
2354 gen_helper_sub_f64(res
, cpu_env
, res
, src
);
2356 case 0x38: /* fcmp */
2357 gen_helper_sub_cmp_f64(res
, cpu_env
, res
, src
);
2361 case 0x3a: /* ftst */
2362 tcg_gen_mov_f64(res
, src
);
2369 if (ext
& (1 << 14)) {
2370 tcg_temp_free_i64(src
);
2373 if (opmode
& 0x40) {
2374 if ((opmode
& 0x4) != 0)
2376 } else if ((s
->fpcr
& M68K_FPCR_PREC
) == 0) {
2381 TCGv tmp
= tcg_temp_new_i32();
2382 gen_helper_f64_to_f32(tmp
, cpu_env
, res
);
2383 gen_helper_f32_to_f64(res
, cpu_env
, tmp
);
2384 tcg_temp_free_i32(tmp
);
2386 tcg_gen_mov_f64(QREG_FP_RESULT
, res
);
2388 tcg_gen_mov_f64(dest
, res
);
2390 tcg_temp_free_i64(res
);
2393 /* FIXME: Is this right for offset addressing modes? */
2395 disas_undef_fpu(env
, s
, insn
);
2406 offset
= cpu_ldsw_code(env
, s
->pc
);
2408 if (insn
& (1 << 6)) {
2409 offset
= (offset
<< 16) | cpu_lduw_code(env
, s
->pc
);
2413 l1
= gen_new_label();
2414 /* TODO: Raise BSUN exception. */
2415 flag
= tcg_temp_new();
2416 gen_helper_compare_f64(flag
, cpu_env
, QREG_FP_RESULT
);
2417 /* Jump to l1 if condition is true. */
2418 switch (insn
& 0xf) {
2421 case 1: /* eq (=0) */
2422 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2424 case 2: /* ogt (=1) */
2425 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(1), l1
);
2427 case 3: /* oge (=0 or =1) */
2428 tcg_gen_brcond_i32(TCG_COND_LEU
, flag
, tcg_const_i32(1), l1
);
2430 case 4: /* olt (=-1) */
2431 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(0), l1
);
2433 case 5: /* ole (=-1 or =0) */
2434 tcg_gen_brcond_i32(TCG_COND_LE
, flag
, tcg_const_i32(0), l1
);
2436 case 6: /* ogl (=-1 or =1) */
2437 tcg_gen_andi_i32(flag
, flag
, 1);
2438 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2440 case 7: /* or (=2) */
2441 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(2), l1
);
2443 case 8: /* un (<2) */
2444 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(2), l1
);
2446 case 9: /* ueq (=0 or =2) */
2447 tcg_gen_andi_i32(flag
, flag
, 1);
2448 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2450 case 10: /* ugt (>0) */
2451 tcg_gen_brcond_i32(TCG_COND_GT
, flag
, tcg_const_i32(0), l1
);
2453 case 11: /* uge (>=0) */
2454 tcg_gen_brcond_i32(TCG_COND_GE
, flag
, tcg_const_i32(0), l1
);
2456 case 12: /* ult (=-1 or =2) */
2457 tcg_gen_brcond_i32(TCG_COND_GEU
, flag
, tcg_const_i32(2), l1
);
2459 case 13: /* ule (!=1) */
2460 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(1), l1
);
2462 case 14: /* ne (!=0) */
2463 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2469 gen_jmp_tb(s
, 0, s
->pc
);
2471 gen_jmp_tb(s
, 1, addr
+ offset
);
2474 DISAS_INSN(frestore
)
2476 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2478 /* TODO: Implement frestore. */
2479 cpu_abort(CPU(cpu
), "FRESTORE not implemented");
2484 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2486 /* TODO: Implement fsave. */
2487 cpu_abort(CPU(cpu
), "FSAVE not implemented");
2490 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
2492 TCGv tmp
= tcg_temp_new();
2493 if (s
->env
->macsr
& MACSR_FI
) {
2495 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
2497 tcg_gen_shli_i32(tmp
, val
, 16);
2498 } else if (s
->env
->macsr
& MACSR_SU
) {
2500 tcg_gen_sari_i32(tmp
, val
, 16);
2502 tcg_gen_ext16s_i32(tmp
, val
);
2505 tcg_gen_shri_i32(tmp
, val
, 16);
2507 tcg_gen_ext16u_i32(tmp
, val
);
2512 static void gen_mac_clear_flags(void)
2514 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
2515 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
2531 s
->mactmp
= tcg_temp_new_i64();
2535 ext
= cpu_lduw_code(env
, s
->pc
);
2538 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
2539 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
2540 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
2541 disas_undef(env
, s
, insn
);
2545 /* MAC with load. */
2546 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2547 addr
= tcg_temp_new();
2548 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
2549 /* Load the value now to ensure correct exception behavior.
2550 Perform writeback after reading the MAC inputs. */
2551 loadval
= gen_load(s
, OS_LONG
, addr
, 0);
2554 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
2555 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
2557 loadval
= addr
= NULL_QREG
;
2558 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2559 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2562 gen_mac_clear_flags();
2565 /* Disabled because conditional branches clobber temporary vars. */
2566 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
2567 /* Skip the multiply if we know we will ignore it. */
2568 l1
= gen_new_label();
2569 tmp
= tcg_temp_new();
2570 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
2571 gen_op_jmp_nz32(tmp
, l1
);
2575 if ((ext
& 0x0800) == 0) {
2577 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
2578 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
2580 if (s
->env
->macsr
& MACSR_FI
) {
2581 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
2583 if (s
->env
->macsr
& MACSR_SU
)
2584 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
2586 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
2587 switch ((ext
>> 9) & 3) {
2589 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
2592 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
2598 /* Save the overflow flag from the multiply. */
2599 saved_flags
= tcg_temp_new();
2600 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
2602 saved_flags
= NULL_QREG
;
2606 /* Disabled because conditional branches clobber temporary vars. */
2607 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
2608 /* Skip the accumulate if the value is already saturated. */
2609 l1
= gen_new_label();
2610 tmp
= tcg_temp_new();
2611 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
2612 gen_op_jmp_nz32(tmp
, l1
);
2617 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2619 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2621 if (s
->env
->macsr
& MACSR_FI
)
2622 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
2623 else if (s
->env
->macsr
& MACSR_SU
)
2624 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
2626 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
2629 /* Disabled because conditional branches clobber temporary vars. */
2635 /* Dual accumulate variant. */
2636 acc
= (ext
>> 2) & 3;
2637 /* Restore the overflow flag from the multiplier. */
2638 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
2640 /* Disabled because conditional branches clobber temporary vars. */
2641 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
2642 /* Skip the accumulate if the value is already saturated. */
2643 l1
= gen_new_label();
2644 tmp
= tcg_temp_new();
2645 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
2646 gen_op_jmp_nz32(tmp
, l1
);
2650 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2652 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2653 if (s
->env
->macsr
& MACSR_FI
)
2654 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
2655 else if (s
->env
->macsr
& MACSR_SU
)
2656 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
2658 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
2660 /* Disabled because conditional branches clobber temporary vars. */
2665 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
2669 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2670 tcg_gen_mov_i32(rw
, loadval
);
2671 /* FIXME: Should address writeback happen with the masked or
2673 switch ((insn
>> 3) & 7) {
2674 case 3: /* Post-increment. */
2675 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
2677 case 4: /* Pre-decrement. */
2678 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2683 DISAS_INSN(from_mac
)
2689 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2690 accnum
= (insn
>> 9) & 3;
2691 acc
= MACREG(accnum
);
2692 if (s
->env
->macsr
& MACSR_FI
) {
2693 gen_helper_get_macf(rx
, cpu_env
, acc
);
2694 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
2695 tcg_gen_extrl_i64_i32(rx
, acc
);
2696 } else if (s
->env
->macsr
& MACSR_SU
) {
2697 gen_helper_get_macs(rx
, acc
);
2699 gen_helper_get_macu(rx
, acc
);
2702 tcg_gen_movi_i64(acc
, 0);
2703 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
2707 DISAS_INSN(move_mac
)
2709 /* FIXME: This can be done without a helper. */
2713 dest
= tcg_const_i32((insn
>> 9) & 3);
2714 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
2715 gen_mac_clear_flags();
2716 gen_helper_mac_set_flags(cpu_env
, dest
);
2719 DISAS_INSN(from_macsr
)
2723 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2724 tcg_gen_mov_i32(reg
, QREG_MACSR
);
2727 DISAS_INSN(from_mask
)
2730 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2731 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
2734 DISAS_INSN(from_mext
)
2738 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2739 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
2740 if (s
->env
->macsr
& MACSR_FI
)
2741 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
2743 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
2746 DISAS_INSN(macsr_to_ccr
)
2748 tcg_gen_movi_i32(QREG_CC_X
, 0);
2749 tcg_gen_andi_i32(QREG_CC_DEST
, QREG_MACSR
, 0xf);
2750 s
->cc_op
= CC_OP_FLAGS
;
2758 accnum
= (insn
>> 9) & 3;
2759 acc
= MACREG(accnum
);
2760 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2761 if (s
->env
->macsr
& MACSR_FI
) {
2762 tcg_gen_ext_i32_i64(acc
, val
);
2763 tcg_gen_shli_i64(acc
, acc
, 8);
2764 } else if (s
->env
->macsr
& MACSR_SU
) {
2765 tcg_gen_ext_i32_i64(acc
, val
);
2767 tcg_gen_extu_i32_i64(acc
, val
);
2769 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
2770 gen_mac_clear_flags();
2771 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
2774 DISAS_INSN(to_macsr
)
2777 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2778 gen_helper_set_macsr(cpu_env
, val
);
2785 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2786 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
2793 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2794 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
2795 if (s
->env
->macsr
& MACSR_FI
)
2796 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
2797 else if (s
->env
->macsr
& MACSR_SU
)
2798 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
2800 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
2803 static disas_proc opcode_table
[65536];
2806 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
2812 /* Sanity check. All set bits must be included in the mask. */
2813 if (opcode
& ~mask
) {
2815 "qemu internal error: bogus opcode definition %04x/%04x\n",
2819 /* This could probably be cleverer. For now just optimize the case where
2820 the top bits are known. */
2821 /* Find the first zero bit in the mask. */
2823 while ((i
& mask
) != 0)
2825 /* Iterate over all combinations of this and lower bits. */
2830 from
= opcode
& ~(i
- 1);
2832 for (i
= from
; i
< to
; i
++) {
2833 if ((i
& mask
) == opcode
)
2834 opcode_table
[i
] = proc
;
2838 /* Register m68k opcode handlers. Order is important.
2839 Later insn override earlier ones. */
2840 void register_m68k_insns (CPUM68KState
*env
)
2842 #define INSN(name, opcode, mask, feature) do { \
2843 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2844 register_opcode(disas_##name, 0x##opcode, 0x##mask); \
2846 INSN(undef
, 0000, 0000, CF_ISA_A
);
2847 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
2848 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
2849 INSN(bitop_reg
, 0100, f1c0
, CF_ISA_A
);
2850 INSN(bitop_reg
, 0140, f1c0
, CF_ISA_A
);
2851 INSN(bitop_reg
, 0180, f1c0
, CF_ISA_A
);
2852 INSN(bitop_reg
, 01c0
, f1c0
, CF_ISA_A
);
2853 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
2854 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
2855 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
2856 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
2857 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
2858 INSN(bitop_im
, 0800, ffc0
, CF_ISA_A
);
2859 INSN(bitop_im
, 0840, ffc0
, CF_ISA_A
);
2860 INSN(bitop_im
, 0880, ffc0
, CF_ISA_A
);
2861 INSN(bitop_im
, 08c0
, ffc0
, CF_ISA_A
);
2862 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
2863 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
2864 INSN(move
, 1000, f000
, CF_ISA_A
);
2865 INSN(move
, 2000, f000
, CF_ISA_A
);
2866 INSN(move
, 3000, f000
, CF_ISA_A
);
2867 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
2868 INSN(negx
, 4080, fff8
, CF_ISA_A
);
2869 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
2870 INSN(lea
, 41c0
, f1c0
, CF_ISA_A
);
2871 INSN(clr
, 4200, ff00
, CF_ISA_A
);
2872 INSN(undef
, 42c0
, ffc0
, CF_ISA_A
);
2873 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
2874 INSN(neg
, 4480, fff8
, CF_ISA_A
);
2875 INSN(move_to_ccr
, 44c0
, ffc0
, CF_ISA_A
);
2876 INSN(not, 4680, fff8
, CF_ISA_A
);
2877 INSN(move_to_sr
, 46c0
, ffc0
, CF_ISA_A
);
2878 INSN(pea
, 4840, ffc0
, CF_ISA_A
);
2879 INSN(swap
, 4840, fff8
, CF_ISA_A
);
2880 INSN(movem
, 48c0
, fbc0
, CF_ISA_A
);
2881 INSN(ext
, 4880, fff8
, CF_ISA_A
);
2882 INSN(ext
, 48c0
, fff8
, CF_ISA_A
);
2883 INSN(ext
, 49c0
, fff8
, CF_ISA_A
);
2884 INSN(tst
, 4a00
, ff00
, CF_ISA_A
);
2885 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
2886 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
2887 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
2888 INSN(illegal
, 4afc
, ffff
, CF_ISA_A
);
2889 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
2890 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
2891 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
2892 INSN(trap
, 4e40
, fff0
, CF_ISA_A
);
2893 INSN(link
, 4e50
, fff8
, CF_ISA_A
);
2894 INSN(unlk
, 4e58
, fff8
, CF_ISA_A
);
2895 INSN(move_to_usp
, 4e60
, fff8
, USP
);
2896 INSN(move_from_usp
, 4e68
, fff8
, USP
);
2897 INSN(nop
, 4e71
, ffff
, CF_ISA_A
);
2898 INSN(stop
, 4e72
, ffff
, CF_ISA_A
);
2899 INSN(rte
, 4e73
, ffff
, CF_ISA_A
);
2900 INSN(rts
, 4e75
, ffff
, CF_ISA_A
);
2901 INSN(movec
, 4e7b
, ffff
, CF_ISA_A
);
2902 INSN(jump
, 4e80
, ffc0
, CF_ISA_A
);
2903 INSN(jump
, 4ec0
, ffc0
, CF_ISA_A
);
2904 INSN(addsubq
, 5180, f1c0
, CF_ISA_A
);
2905 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
);
2906 INSN(addsubq
, 5080, f1c0
, CF_ISA_A
);
2907 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
2909 /* Branch instructions. */
2910 INSN(branch
, 6000, f000
, CF_ISA_A
);
2911 /* Disable long branch instructions, then add back the ones we want. */
2912 INSN(undef
, 60ff
, f0ff
, CF_ISA_A
); /* All long branches. */
2913 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
2914 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
2915 INSN(branch
, 60ff
, ffff
, BRAL
);
2917 INSN(moveq
, 7000, f100
, CF_ISA_A
);
2918 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
2919 INSN(or, 8000, f000
, CF_ISA_A
);
2920 INSN(divw
, 80c0
, f0c0
, CF_ISA_A
);
2921 INSN(addsub
, 9000, f000
, CF_ISA_A
);
2922 INSN(subx
, 9180, f1f8
, CF_ISA_A
);
2923 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
2925 INSN(undef_mac
, a000
, f000
, CF_ISA_A
);
2926 INSN(mac
, a000
, f100
, CF_EMAC
);
2927 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
2928 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
2929 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
2930 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
2931 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
2932 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
2933 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
2934 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
2935 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
2936 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
2938 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
2939 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
2940 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
2941 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
2942 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
2943 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
2944 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
2945 INSN(and, c000
, f000
, CF_ISA_A
);
2946 INSN(mulw
, c0c0
, f0c0
, CF_ISA_A
);
2947 INSN(addsub
, d000
, f000
, CF_ISA_A
);
2948 INSN(addx
, d180
, f1f8
, CF_ISA_A
);
2949 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
2950 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
2951 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
2952 INSN(undef_fpu
, f000
, f000
, CF_ISA_A
);
2953 INSN(fpu
, f200
, ffc0
, CF_FPU
);
2954 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
2955 INSN(frestore
, f340
, ffc0
, CF_FPU
);
2956 INSN(fsave
, f340
, ffc0
, CF_FPU
);
2957 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
2958 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
2959 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
2960 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
2964 /* ??? Some of this implementation is not exception safe. We should always
2965 write back the result to memory before setting the condition codes. */
2966 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
2970 insn
= cpu_lduw_code(env
, s
->pc
);
2973 opcode_table
[insn
](env
, s
, insn
);
2976 /* generate intermediate code for basic block 'tb'. */
2977 void gen_intermediate_code(CPUM68KState
*env
, TranslationBlock
*tb
)
2979 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2980 CPUState
*cs
= CPU(cpu
);
2981 DisasContext dc1
, *dc
= &dc1
;
2982 target_ulong pc_start
;
2987 /* generate intermediate code */
2993 dc
->is_jmp
= DISAS_NEXT
;
2995 dc
->cc_op
= CC_OP_DYNAMIC
;
2996 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
2997 dc
->fpcr
= env
->fpcr
;
2998 dc
->user
= (env
->sr
& SR_S
) == 0;
3001 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3002 if (max_insns
== 0) {
3003 max_insns
= CF_COUNT_MASK
;
3005 if (max_insns
> TCG_MAX_INSNS
) {
3006 max_insns
= TCG_MAX_INSNS
;
3011 pc_offset
= dc
->pc
- pc_start
;
3012 gen_throws_exception
= NULL
;
3013 tcg_gen_insn_start(dc
->pc
);
3016 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
3017 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
3018 dc
->is_jmp
= DISAS_JUMP
;
3019 /* The address covered by the breakpoint must be included in
3020 [tb->pc, tb->pc + tb->size) in order to for it to be
3021 properly cleared -- thus we increment the PC here so that
3022 the logic setting tb->size below does the right thing. */
3027 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3031 dc
->insn_pc
= dc
->pc
;
3032 disas_m68k_insn(env
, dc
);
3033 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
3034 !cs
->singlestep_enabled
&&
3036 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
3037 num_insns
< max_insns
);
3039 if (tb
->cflags
& CF_LAST_IO
)
3041 if (unlikely(cs
->singlestep_enabled
)) {
3042 /* Make sure the pc is updated, and raise a debug exception. */
3044 gen_flush_cc_op(dc
);
3045 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
3047 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
3049 switch(dc
->is_jmp
) {
3051 gen_flush_cc_op(dc
);
3052 gen_jmp_tb(dc
, 0, dc
->pc
);
3057 gen_flush_cc_op(dc
);
3058 /* indicate that the hash table must be used to find the next TB */
3062 /* nothing more to generate */
3066 gen_tb_end(tb
, num_insns
);
3069 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
3070 qemu_log("----------------\n");
3071 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3072 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
3076 tb
->size
= dc
->pc
- pc_start
;
3077 tb
->icount
= num_insns
;
3080 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3083 M68kCPU
*cpu
= M68K_CPU(cs
);
3084 CPUM68KState
*env
= &cpu
->env
;
3088 for (i
= 0; i
< 8; i
++)
3090 u
.d
= env
->fregs
[i
];
3091 cpu_fprintf (f
, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3092 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
3093 i
, u
.l
.upper
, u
.l
.lower
, *(double *)&u
.d
);
3095 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
3097 cpu_fprintf (f
, "SR = %04x %c%c%c%c%c ", sr
, (sr
& 0x10) ? 'X' : '-',
3098 (sr
& CCF_N
) ? 'N' : '-', (sr
& CCF_Z
) ? 'Z' : '-',
3099 (sr
& CCF_V
) ? 'V' : '-', (sr
& CCF_C
) ? 'C' : '-');
3100 cpu_fprintf (f
, "FPRESULT = %12g\n", *(double *)&env
->fp_result
);
3103 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,