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ide: Update ide_drive_get to be HBA agnostic
[qemu/cris-port.git] / hw / ide / core.c
blobae85428864b0699cf97099b0a6a4970bae93cd0b
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/isa/isa.h>
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33 #include "hw/block/block.h"
34 #include "sysemu/blockdev.h"
35
36 #include <hw/ide/internal.h>
37
38 /* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40 static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
56 };
57
58 static int ide_handle_rw_error(IDEState *s, int error, int op);
59 static void ide_dummy_transfer_stop(IDEState *s);
60
61 static void padstr(char *str, const char *src, int len)
62 {
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69 str[i^1] = v;
70 }
71 }
72
73 static void put_le16(uint16_t *p, unsigned int v)
74 {
75 *p = cpu_to_le16(v);
76 }
77
78 static void ide_identify_size(IDEState *s)
79 {
80 uint16_t *p = (uint16_t *)s->identify_data;
81 put_le16(p + 60, s->nb_sectors);
82 put_le16(p + 61, s->nb_sectors >> 16);
83 put_le16(p + 100, s->nb_sectors);
84 put_le16(p + 101, s->nb_sectors >> 16);
85 put_le16(p + 102, s->nb_sectors >> 32);
86 put_le16(p + 103, s->nb_sectors >> 48);
87 }
88
89 static void ide_identify(IDEState *s)
90 {
91 uint16_t *p;
92 unsigned int oldsize;
93 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
94
95 p = (uint16_t *)s->identify_data;
96 if (s->identify_set) {
97 goto fill_buffer;
98 }
99 memset(p, 0, sizeof(s->identify_data));
100
101 put_le16(p + 0, 0x0040);
102 put_le16(p + 1, s->cylinders);
103 put_le16(p + 3, s->heads);
104 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
105 put_le16(p + 5, 512); /* XXX: retired, remove ? */
106 put_le16(p + 6, s->sectors);
107 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
108 put_le16(p + 20, 3); /* XXX: retired, remove ? */
109 put_le16(p + 21, 512); /* cache size in sectors */
110 put_le16(p + 22, 4); /* ecc bytes */
111 padstr((char *)(p + 23), s->version, 8); /* firmware version */
112 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
113 #if MAX_MULT_SECTORS > 1
114 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
115 #endif
116 put_le16(p + 48, 1); /* dword I/O */
117 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
118 put_le16(p + 51, 0x200); /* PIO transfer cycle */
119 put_le16(p + 52, 0x200); /* DMA transfer cycle */
120 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
121 put_le16(p + 54, s->cylinders);
122 put_le16(p + 55, s->heads);
123 put_le16(p + 56, s->sectors);
124 oldsize = s->cylinders * s->heads * s->sectors;
125 put_le16(p + 57, oldsize);
126 put_le16(p + 58, oldsize >> 16);
127 if (s->mult_sectors)
128 put_le16(p + 59, 0x100 | s->mult_sectors);
129 /* *(p + 60) := nb_sectors -- see ide_identify_size */
130 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
131 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
132 put_le16(p + 63, 0x07); /* mdma0-2 supported */
133 put_le16(p + 64, 0x03); /* pio3-4 supported */
134 put_le16(p + 65, 120);
135 put_le16(p + 66, 120);
136 put_le16(p + 67, 120);
137 put_le16(p + 68, 120);
138 if (dev && dev->conf.discard_granularity) {
139 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
140 }
141
142 if (s->ncq_queues) {
143 put_le16(p + 75, s->ncq_queues - 1);
144 /* NCQ supported */
145 put_le16(p + 76, (1 << 8));
146 }
147
148 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
149 put_le16(p + 81, 0x16); /* conforms to ata5 */
150 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
151 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
153 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
154 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
155 if (s->wwn) {
156 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
157 } else {
158 put_le16(p + 84, (1 << 14) | 0);
159 }
160 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
161 if (bdrv_enable_write_cache(s->bs))
162 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
163 else
164 put_le16(p + 85, (1 << 14) | 1);
165 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
166 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
167 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
168 if (s->wwn) {
169 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
170 } else {
171 put_le16(p + 87, (1 << 14) | 0);
172 }
173 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
174 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
175 /* *(p + 100) := nb_sectors -- see ide_identify_size */
176 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
177 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
178 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
179
180 if (dev && dev->conf.physical_block_size)
181 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
182 if (s->wwn) {
183 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
184 put_le16(p + 108, s->wwn >> 48);
185 put_le16(p + 109, s->wwn >> 32);
186 put_le16(p + 110, s->wwn >> 16);
187 put_le16(p + 111, s->wwn);
188 }
189 if (dev && dev->conf.discard_granularity) {
190 put_le16(p + 169, 1); /* TRIM support */
191 }
192
193 ide_identify_size(s);
194 s->identify_set = 1;
195
196 fill_buffer:
197 memcpy(s->io_buffer, p, sizeof(s->identify_data));
198 }
199
200 static void ide_atapi_identify(IDEState *s)
201 {
202 uint16_t *p;
203
204 p = (uint16_t *)s->identify_data;
205 if (s->identify_set) {
206 goto fill_buffer;
207 }
208 memset(p, 0, sizeof(s->identify_data));
209
210 /* Removable CDROM, 50us response, 12 byte packets */
211 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
212 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
213 put_le16(p + 20, 3); /* buffer type */
214 put_le16(p + 21, 512); /* cache size in sectors */
215 put_le16(p + 22, 4); /* ecc bytes */
216 padstr((char *)(p + 23), s->version, 8); /* firmware version */
217 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
218 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
219 #ifdef USE_DMA_CDROM
220 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
221 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
222 put_le16(p + 62, 7); /* single word dma0-2 supported */
223 put_le16(p + 63, 7); /* mdma0-2 supported */
224 #else
225 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
226 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
227 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
228 #endif
229 put_le16(p + 64, 3); /* pio3-4 supported */
230 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
231 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
232 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
233 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
234
235 put_le16(p + 71, 30); /* in ns */
236 put_le16(p + 72, 30); /* in ns */
237
238 if (s->ncq_queues) {
239 put_le16(p + 75, s->ncq_queues - 1);
240 /* NCQ supported */
241 put_le16(p + 76, (1 << 8));
242 }
243
244 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
245 if (s->wwn) {
246 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
247 put_le16(p + 87, (1 << 8)); /* WWN enabled */
248 }
249
250 #ifdef USE_DMA_CDROM
251 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
252 #endif
253
254 if (s->wwn) {
255 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
256 put_le16(p + 108, s->wwn >> 48);
257 put_le16(p + 109, s->wwn >> 32);
258 put_le16(p + 110, s->wwn >> 16);
259 put_le16(p + 111, s->wwn);
260 }
261
262 s->identify_set = 1;
263
264 fill_buffer:
265 memcpy(s->io_buffer, p, sizeof(s->identify_data));
266 }
267
268 static void ide_cfata_identify_size(IDEState *s)
269 {
270 uint16_t *p = (uint16_t *)s->identify_data;
271 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
272 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
273 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
274 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
275 }
276
277 static void ide_cfata_identify(IDEState *s)
278 {
279 uint16_t *p;
280 uint32_t cur_sec;
281
282 p = (uint16_t *)s->identify_data;
283 if (s->identify_set) {
284 goto fill_buffer;
285 }
286 memset(p, 0, sizeof(s->identify_data));
287
288 cur_sec = s->cylinders * s->heads * s->sectors;
289
290 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
291 put_le16(p + 1, s->cylinders); /* Default cylinders */
292 put_le16(p + 3, s->heads); /* Default heads */
293 put_le16(p + 6, s->sectors); /* Default sectors per track */
294 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
295 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
296 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
297 put_le16(p + 22, 0x0004); /* ECC bytes */
298 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
299 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
300 #if MAX_MULT_SECTORS > 1
301 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
302 #else
303 put_le16(p + 47, 0x0000);
304 #endif
305 put_le16(p + 49, 0x0f00); /* Capabilities */
306 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
307 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
308 put_le16(p + 53, 0x0003); /* Translation params valid */
309 put_le16(p + 54, s->cylinders); /* Current cylinders */
310 put_le16(p + 55, s->heads); /* Current heads */
311 put_le16(p + 56, s->sectors); /* Current sectors */
312 put_le16(p + 57, cur_sec); /* Current capacity */
313 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
314 if (s->mult_sectors) /* Multiple sector setting */
315 put_le16(p + 59, 0x100 | s->mult_sectors);
316 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
317 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
318 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
319 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
320 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
321 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
322 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
323 put_le16(p + 82, 0x400c); /* Command Set supported */
324 put_le16(p + 83, 0x7068); /* Command Set supported */
325 put_le16(p + 84, 0x4000); /* Features supported */
326 put_le16(p + 85, 0x000c); /* Command Set enabled */
327 put_le16(p + 86, 0x7044); /* Command Set enabled */
328 put_le16(p + 87, 0x4000); /* Features enabled */
329 put_le16(p + 91, 0x4060); /* Current APM level */
330 put_le16(p + 129, 0x0002); /* Current features option */
331 put_le16(p + 130, 0x0005); /* Reassigned sectors */
332 put_le16(p + 131, 0x0001); /* Initial power mode */
333 put_le16(p + 132, 0x0000); /* User signature */
334 put_le16(p + 160, 0x8100); /* Power requirement */
335 put_le16(p + 161, 0x8001); /* CF command set */
336
337 ide_cfata_identify_size(s);
338 s->identify_set = 1;
339
340 fill_buffer:
341 memcpy(s->io_buffer, p, sizeof(s->identify_data));
342 }
343
344 static void ide_set_signature(IDEState *s)
345 {
346 s->select &= 0xf0; /* clear head */
347 /* put signature */
348 s->nsector = 1;
349 s->sector = 1;
350 if (s->drive_kind == IDE_CD) {
351 s->lcyl = 0x14;
352 s->hcyl = 0xeb;
353 } else if (s->bs) {
354 s->lcyl = 0;
355 s->hcyl = 0;
356 } else {
357 s->lcyl = 0xff;
358 s->hcyl = 0xff;
359 }
360 }
361
362 typedef struct TrimAIOCB {
363 BlockDriverAIOCB common;
364 QEMUBH *bh;
365 int ret;
366 QEMUIOVector *qiov;
367 BlockDriverAIOCB *aiocb;
368 int i, j;
369 } TrimAIOCB;
370
371 static void trim_aio_cancel(BlockDriverAIOCB *acb)
372 {
373 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
374
375 /* Exit the loop so ide_issue_trim_cb will not continue */
376 iocb->j = iocb->qiov->niov - 1;
377 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
378
379 iocb->ret = -ECANCELED;
380
381 if (iocb->aiocb) {
382 bdrv_aio_cancel_async(iocb->aiocb);
383 iocb->aiocb = NULL;
384 }
385 }
386
387 static const AIOCBInfo trim_aiocb_info = {
388 .aiocb_size = sizeof(TrimAIOCB),
389 .cancel_async = trim_aio_cancel,
390 };
391
392 static void ide_trim_bh_cb(void *opaque)
393 {
394 TrimAIOCB *iocb = opaque;
395
396 iocb->common.cb(iocb->common.opaque, iocb->ret);
397
398 qemu_bh_delete(iocb->bh);
399 iocb->bh = NULL;
400 qemu_aio_unref(iocb);
401 }
402
403 static void ide_issue_trim_cb(void *opaque, int ret)
404 {
405 TrimAIOCB *iocb = opaque;
406 if (ret >= 0) {
407 while (iocb->j < iocb->qiov->niov) {
408 int j = iocb->j;
409 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
410 int i = iocb->i;
411 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
412
413 /* 6-byte LBA + 2-byte range per entry */
414 uint64_t entry = le64_to_cpu(buffer[i]);
415 uint64_t sector = entry & 0x0000ffffffffffffULL;
416 uint16_t count = entry >> 48;
417
418 if (count == 0) {
419 continue;
420 }
421
422 /* Got an entry! Submit and exit. */
423 iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count,
424 ide_issue_trim_cb, opaque);
425 return;
426 }
427
428 iocb->j++;
429 iocb->i = -1;
430 }
431 } else {
432 iocb->ret = ret;
433 }
434
435 iocb->aiocb = NULL;
436 if (iocb->bh) {
437 qemu_bh_schedule(iocb->bh);
438 }
439 }
440
441 BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
442 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
443 BlockDriverCompletionFunc *cb, void *opaque)
444 {
445 TrimAIOCB *iocb;
446
447 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque);
448 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
449 iocb->ret = 0;
450 iocb->qiov = qiov;
451 iocb->i = -1;
452 iocb->j = 0;
453 ide_issue_trim_cb(iocb, 0);
454 return &iocb->common;
455 }
456
457 static inline void ide_abort_command(IDEState *s)
458 {
459 ide_transfer_stop(s);
460 s->status = READY_STAT | ERR_STAT;
461 s->error = ABRT_ERR;
462 }
463
464 /* prepare data transfer and tell what to do after */
465 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
466 EndTransferFunc *end_transfer_func)
467 {
468 s->end_transfer_func = end_transfer_func;
469 s->data_ptr = buf;
470 s->data_end = buf + size;
471 if (!(s->status & ERR_STAT)) {
472 s->status |= DRQ_STAT;
473 }
474 if (s->bus->dma->ops->start_transfer) {
475 s->bus->dma->ops->start_transfer(s->bus->dma);
476 }
477 }
478
479 static void ide_cmd_done(IDEState *s)
480 {
481 if (s->bus->dma->ops->cmd_done) {
482 s->bus->dma->ops->cmd_done(s->bus->dma);
483 }
484 }
485
486 void ide_transfer_stop(IDEState *s)
487 {
488 s->end_transfer_func = ide_transfer_stop;
489 s->data_ptr = s->io_buffer;
490 s->data_end = s->io_buffer;
491 s->status &= ~DRQ_STAT;
492 ide_cmd_done(s);
493 }
494
495 int64_t ide_get_sector(IDEState *s)
496 {
497 int64_t sector_num;
498 if (s->select & 0x40) {
499 /* lba */
500 if (!s->lba48) {
501 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
502 (s->lcyl << 8) | s->sector;
503 } else {
504 sector_num = ((int64_t)s->hob_hcyl << 40) |
505 ((int64_t) s->hob_lcyl << 32) |
506 ((int64_t) s->hob_sector << 24) |
507 ((int64_t) s->hcyl << 16) |
508 ((int64_t) s->lcyl << 8) | s->sector;
509 }
510 } else {
511 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
512 (s->select & 0x0f) * s->sectors + (s->sector - 1);
513 }
514 return sector_num;
515 }
516
517 void ide_set_sector(IDEState *s, int64_t sector_num)
518 {
519 unsigned int cyl, r;
520 if (s->select & 0x40) {
521 if (!s->lba48) {
522 s->select = (s->select & 0xf0) | (sector_num >> 24);
523 s->hcyl = (sector_num >> 16);
524 s->lcyl = (sector_num >> 8);
525 s->sector = (sector_num);
526 } else {
527 s->sector = sector_num;
528 s->lcyl = sector_num >> 8;
529 s->hcyl = sector_num >> 16;
530 s->hob_sector = sector_num >> 24;
531 s->hob_lcyl = sector_num >> 32;
532 s->hob_hcyl = sector_num >> 40;
533 }
534 } else {
535 cyl = sector_num / (s->heads * s->sectors);
536 r = sector_num % (s->heads * s->sectors);
537 s->hcyl = cyl >> 8;
538 s->lcyl = cyl;
539 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
540 s->sector = (r % s->sectors) + 1;
541 }
542 }
543
544 static void ide_rw_error(IDEState *s) {
545 ide_abort_command(s);
546 ide_set_irq(s->bus);
547 }
548
549 static bool ide_sect_range_ok(IDEState *s,
550 uint64_t sector, uint64_t nb_sectors)
551 {
552 uint64_t total_sectors;
553
554 bdrv_get_geometry(s->bs, &total_sectors);
555 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
556 return false;
557 }
558 return true;
559 }
560
561 static void ide_sector_read_cb(void *opaque, int ret)
562 {
563 IDEState *s = opaque;
564 int n;
565
566 s->pio_aiocb = NULL;
567 s->status &= ~BUSY_STAT;
568
569 if (ret == -ECANCELED) {
570 return;
571 }
572 block_acct_done(bdrv_get_stats(s->bs), &s->acct);
573 if (ret != 0) {
574 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
575 IDE_RETRY_READ)) {
576 return;
577 }
578 }
579
580 n = s->nsector;
581 if (n > s->req_nb_sectors) {
582 n = s->req_nb_sectors;
583 }
584
585 /* Allow the guest to read the io_buffer */
586 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
587
588 ide_set_irq(s->bus);
589
590 ide_set_sector(s, ide_get_sector(s) + n);
591 s->nsector -= n;
592 }
593
594 void ide_sector_read(IDEState *s)
595 {
596 int64_t sector_num;
597 int n;
598
599 s->status = READY_STAT | SEEK_STAT;
600 s->error = 0; /* not needed by IDE spec, but needed by Windows */
601 sector_num = ide_get_sector(s);
602 n = s->nsector;
603
604 if (n == 0) {
605 ide_transfer_stop(s);
606 return;
607 }
608
609 s->status |= BUSY_STAT;
610
611 if (n > s->req_nb_sectors) {
612 n = s->req_nb_sectors;
613 }
614
615 #if defined(DEBUG_IDE)
616 printf("sector=%" PRId64 "\n", sector_num);
617 #endif
618
619 if (!ide_sect_range_ok(s, sector_num, n)) {
620 ide_rw_error(s);
621 return;
622 }
623
624 s->iov.iov_base = s->io_buffer;
625 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
626 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
627
628 block_acct_start(bdrv_get_stats(s->bs), &s->acct,
629 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
630 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n,
631 ide_sector_read_cb, s);
632 }
633
634 static void dma_buf_commit(IDEState *s)
635 {
636 qemu_sglist_destroy(&s->sg);
637 }
638
639 void ide_set_inactive(IDEState *s, bool more)
640 {
641 s->bus->dma->aiocb = NULL;
642 if (s->bus->dma->ops->set_inactive) {
643 s->bus->dma->ops->set_inactive(s->bus->dma, more);
644 }
645 ide_cmd_done(s);
646 }
647
648 void ide_dma_error(IDEState *s)
649 {
650 ide_abort_command(s);
651 ide_set_inactive(s, false);
652 ide_set_irq(s->bus);
653 }
654
655 static int ide_handle_rw_error(IDEState *s, int error, int op)
656 {
657 bool is_read = (op & IDE_RETRY_READ) != 0;
658 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error);
659
660 if (action == BLOCK_ERROR_ACTION_STOP) {
661 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
662 s->bus->error_status = op;
663 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
664 if (op & IDE_RETRY_DMA) {
665 dma_buf_commit(s);
666 ide_dma_error(s);
667 } else {
668 ide_rw_error(s);
669 }
670 }
671 bdrv_error_action(s->bs, action, is_read, error);
672 return action != BLOCK_ERROR_ACTION_IGNORE;
673 }
674
675 void ide_dma_cb(void *opaque, int ret)
676 {
677 IDEState *s = opaque;
678 int n;
679 int64_t sector_num;
680 bool stay_active = false;
681
682 if (ret == -ECANCELED) {
683 return;
684 }
685 if (ret < 0) {
686 int op = IDE_RETRY_DMA;
687
688 if (s->dma_cmd == IDE_DMA_READ)
689 op |= IDE_RETRY_READ;
690 else if (s->dma_cmd == IDE_DMA_TRIM)
691 op |= IDE_RETRY_TRIM;
692
693 if (ide_handle_rw_error(s, -ret, op)) {
694 return;
695 }
696 }
697
698 n = s->io_buffer_size >> 9;
699 if (n > s->nsector) {
700 /* The PRDs were longer than needed for this request. Shorten them so
701 * we don't get a negative remainder. The Active bit must remain set
702 * after the request completes. */
703 n = s->nsector;
704 stay_active = true;
705 }
706
707 sector_num = ide_get_sector(s);
708 if (n > 0) {
709 dma_buf_commit(s);
710 sector_num += n;
711 ide_set_sector(s, sector_num);
712 s->nsector -= n;
713 }
714
715 /* end of transfer ? */
716 if (s->nsector == 0) {
717 s->status = READY_STAT | SEEK_STAT;
718 ide_set_irq(s->bus);
719 goto eot;
720 }
721
722 /* launch next transfer */
723 n = s->nsector;
724 s->io_buffer_index = 0;
725 s->io_buffer_size = n * 512;
726 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
727 /* The PRDs were too short. Reset the Active bit, but don't raise an
728 * interrupt. */
729 s->status = READY_STAT | SEEK_STAT;
730 goto eot;
731 }
732
733 #ifdef DEBUG_AIO
734 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
735 sector_num, n, s->dma_cmd);
736 #endif
737
738 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
739 !ide_sect_range_ok(s, sector_num, n)) {
740 dma_buf_commit(s);
741 ide_dma_error(s);
742 return;
743 }
744
745 switch (s->dma_cmd) {
746 case IDE_DMA_READ:
747 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
748 ide_dma_cb, s);
749 break;
750 case IDE_DMA_WRITE:
751 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
752 ide_dma_cb, s);
753 break;
754 case IDE_DMA_TRIM:
755 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
756 ide_issue_trim, ide_dma_cb, s,
757 DMA_DIRECTION_TO_DEVICE);
758 break;
759 }
760 return;
761
762 eot:
763 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
764 block_acct_done(bdrv_get_stats(s->bs), &s->acct);
765 }
766 ide_set_inactive(s, stay_active);
767 }
768
769 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
770 {
771 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
772 s->io_buffer_index = 0;
773 s->io_buffer_size = 0;
774 s->dma_cmd = dma_cmd;
775
776 switch (dma_cmd) {
777 case IDE_DMA_READ:
778 block_acct_start(bdrv_get_stats(s->bs), &s->acct,
779 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
780 break;
781 case IDE_DMA_WRITE:
782 block_acct_start(bdrv_get_stats(s->bs), &s->acct,
783 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
784 break;
785 default:
786 break;
787 }
788
789 ide_start_dma(s, ide_dma_cb);
790 }
791
792 void ide_start_dma(IDEState *s, BlockDriverCompletionFunc *cb)
793 {
794 if (s->bus->dma->ops->start_dma) {
795 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
796 }
797 }
798
799 static void ide_sector_write_timer_cb(void *opaque)
800 {
801 IDEState *s = opaque;
802 ide_set_irq(s->bus);
803 }
804
805 static void ide_sector_write_cb(void *opaque, int ret)
806 {
807 IDEState *s = opaque;
808 int n;
809
810 if (ret == -ECANCELED) {
811 return;
812 }
813 block_acct_done(bdrv_get_stats(s->bs), &s->acct);
814
815 s->pio_aiocb = NULL;
816 s->status &= ~BUSY_STAT;
817
818 if (ret != 0) {
819 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
820 return;
821 }
822 }
823
824 n = s->nsector;
825 if (n > s->req_nb_sectors) {
826 n = s->req_nb_sectors;
827 }
828 s->nsector -= n;
829 if (s->nsector == 0) {
830 /* no more sectors to write */
831 ide_transfer_stop(s);
832 } else {
833 int n1 = s->nsector;
834 if (n1 > s->req_nb_sectors) {
835 n1 = s->req_nb_sectors;
836 }
837 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
838 ide_sector_write);
839 }
840 ide_set_sector(s, ide_get_sector(s) + n);
841
842 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
843 /* It seems there is a bug in the Windows 2000 installer HDD
844 IDE driver which fills the disk with empty logs when the
845 IDE write IRQ comes too early. This hack tries to correct
846 that at the expense of slower write performances. Use this
847 option _only_ to install Windows 2000. You must disable it
848 for normal use. */
849 timer_mod(s->sector_write_timer,
850 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
851 } else {
852 ide_set_irq(s->bus);
853 }
854 }
855
856 void ide_sector_write(IDEState *s)
857 {
858 int64_t sector_num;
859 int n;
860
861 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
862 sector_num = ide_get_sector(s);
863 #if defined(DEBUG_IDE)
864 printf("sector=%" PRId64 "\n", sector_num);
865 #endif
866 n = s->nsector;
867 if (n > s->req_nb_sectors) {
868 n = s->req_nb_sectors;
869 }
870
871 if (!ide_sect_range_ok(s, sector_num, n)) {
872 ide_rw_error(s);
873 return;
874 }
875
876 s->iov.iov_base = s->io_buffer;
877 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
878 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
879
880 block_acct_start(bdrv_get_stats(s->bs), &s->acct,
881 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
882 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n,
883 ide_sector_write_cb, s);
884 }
885
886 static void ide_flush_cb(void *opaque, int ret)
887 {
888 IDEState *s = opaque;
889
890 s->pio_aiocb = NULL;
891
892 if (ret == -ECANCELED) {
893 return;
894 }
895 if (ret < 0) {
896 /* XXX: What sector number to set here? */
897 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
898 return;
899 }
900 }
901
902 if (s->bs) {
903 block_acct_done(bdrv_get_stats(s->bs), &s->acct);
904 }
905 s->status = READY_STAT | SEEK_STAT;
906 ide_cmd_done(s);
907 ide_set_irq(s->bus);
908 }
909
910 void ide_flush_cache(IDEState *s)
911 {
912 if (s->bs == NULL) {
913 ide_flush_cb(s, 0);
914 return;
915 }
916
917 s->status |= BUSY_STAT;
918 block_acct_start(bdrv_get_stats(s->bs), &s->acct, 0, BLOCK_ACCT_FLUSH);
919 s->pio_aiocb = bdrv_aio_flush(s->bs, ide_flush_cb, s);
920 }
921
922 static void ide_cfata_metadata_inquiry(IDEState *s)
923 {
924 uint16_t *p;
925 uint32_t spd;
926
927 p = (uint16_t *) s->io_buffer;
928 memset(p, 0, 0x200);
929 spd = ((s->mdata_size - 1) >> 9) + 1;
930
931 put_le16(p + 0, 0x0001); /* Data format revision */
932 put_le16(p + 1, 0x0000); /* Media property: silicon */
933 put_le16(p + 2, s->media_changed); /* Media status */
934 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
935 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
936 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
937 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
938 }
939
940 static void ide_cfata_metadata_read(IDEState *s)
941 {
942 uint16_t *p;
943
944 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
945 s->status = ERR_STAT;
946 s->error = ABRT_ERR;
947 return;
948 }
949
950 p = (uint16_t *) s->io_buffer;
951 memset(p, 0, 0x200);
952
953 put_le16(p + 0, s->media_changed); /* Media status */
954 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
955 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
956 s->nsector << 9), 0x200 - 2));
957 }
958
959 static void ide_cfata_metadata_write(IDEState *s)
960 {
961 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
962 s->status = ERR_STAT;
963 s->error = ABRT_ERR;
964 return;
965 }
966
967 s->media_changed = 0;
968
969 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
970 s->io_buffer + 2,
971 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
972 s->nsector << 9), 0x200 - 2));
973 }
974
975 /* called when the inserted state of the media has changed */
976 static void ide_cd_change_cb(void *opaque, bool load)
977 {
978 IDEState *s = opaque;
979 uint64_t nb_sectors;
980
981 s->tray_open = !load;
982 bdrv_get_geometry(s->bs, &nb_sectors);
983 s->nb_sectors = nb_sectors;
984
985 /*
986 * First indicate to the guest that a CD has been removed. That's
987 * done on the next command the guest sends us.
988 *
989 * Then we set UNIT_ATTENTION, by which the guest will
990 * detect a new CD in the drive. See ide_atapi_cmd() for details.
991 */
992 s->cdrom_changed = 1;
993 s->events.new_media = true;
994 s->events.eject_request = false;
995 ide_set_irq(s->bus);
996 }
997
998 static void ide_cd_eject_request_cb(void *opaque, bool force)
999 {
1000 IDEState *s = opaque;
1001
1002 s->events.eject_request = true;
1003 if (force) {
1004 s->tray_locked = false;
1005 }
1006 ide_set_irq(s->bus);
1007 }
1008
1009 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1010 {
1011 s->lba48 = lba48;
1012
1013 /* handle the 'magic' 0 nsector count conversion here. to avoid
1014 * fiddling with the rest of the read logic, we just store the
1015 * full sector count in ->nsector and ignore ->hob_nsector from now
1016 */
1017 if (!s->lba48) {
1018 if (!s->nsector)
1019 s->nsector = 256;
1020 } else {
1021 if (!s->nsector && !s->hob_nsector)
1022 s->nsector = 65536;
1023 else {
1024 int lo = s->nsector;
1025 int hi = s->hob_nsector;
1026
1027 s->nsector = (hi << 8) | lo;
1028 }
1029 }
1030 }
1031
1032 static void ide_clear_hob(IDEBus *bus)
1033 {
1034 /* any write clears HOB high bit of device control register */
1035 bus->ifs[0].select &= ~(1 << 7);
1036 bus->ifs[1].select &= ~(1 << 7);
1037 }
1038
1039 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1040 {
1041 IDEBus *bus = opaque;
1042
1043 #ifdef DEBUG_IDE
1044 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1045 #endif
1046
1047 addr &= 7;
1048
1049 /* ignore writes to command block while busy with previous command */
1050 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
1051 return;
1052
1053 switch(addr) {
1054 case 0:
1055 break;
1056 case 1:
1057 ide_clear_hob(bus);
1058 /* NOTE: data is written to the two drives */
1059 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1060 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1061 bus->ifs[0].feature = val;
1062 bus->ifs[1].feature = val;
1063 break;
1064 case 2:
1065 ide_clear_hob(bus);
1066 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1067 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1068 bus->ifs[0].nsector = val;
1069 bus->ifs[1].nsector = val;
1070 break;
1071 case 3:
1072 ide_clear_hob(bus);
1073 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1074 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1075 bus->ifs[0].sector = val;
1076 bus->ifs[1].sector = val;
1077 break;
1078 case 4:
1079 ide_clear_hob(bus);
1080 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1081 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1082 bus->ifs[0].lcyl = val;
1083 bus->ifs[1].lcyl = val;
1084 break;
1085 case 5:
1086 ide_clear_hob(bus);
1087 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1088 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1089 bus->ifs[0].hcyl = val;
1090 bus->ifs[1].hcyl = val;
1091 break;
1092 case 6:
1093 /* FIXME: HOB readback uses bit 7 */
1094 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1095 bus->ifs[1].select = (val | 0x10) | 0xa0;
1096 /* select drive */
1097 bus->unit = (val >> 4) & 1;
1098 break;
1099 default:
1100 case 7:
1101 /* command */
1102 ide_exec_cmd(bus, val);
1103 break;
1104 }
1105 }
1106
1107 static bool cmd_nop(IDEState *s, uint8_t cmd)
1108 {
1109 return true;
1110 }
1111
1112 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1113 {
1114 switch (s->feature) {
1115 case DSM_TRIM:
1116 if (s->bs) {
1117 ide_sector_start_dma(s, IDE_DMA_TRIM);
1118 return false;
1119 }
1120 break;
1121 }
1122
1123 ide_abort_command(s);
1124 return true;
1125 }
1126
1127 static bool cmd_identify(IDEState *s, uint8_t cmd)
1128 {
1129 if (s->bs && s->drive_kind != IDE_CD) {
1130 if (s->drive_kind != IDE_CFATA) {
1131 ide_identify(s);
1132 } else {
1133 ide_cfata_identify(s);
1134 }
1135 s->status = READY_STAT | SEEK_STAT;
1136 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1137 ide_set_irq(s->bus);
1138 return false;
1139 } else {
1140 if (s->drive_kind == IDE_CD) {
1141 ide_set_signature(s);
1142 }
1143 ide_abort_command(s);
1144 }
1145
1146 return true;
1147 }
1148
1149 static bool cmd_verify(IDEState *s, uint8_t cmd)
1150 {
1151 bool lba48 = (cmd == WIN_VERIFY_EXT);
1152
1153 /* do sector number check ? */
1154 ide_cmd_lba48_transform(s, lba48);
1155
1156 return true;
1157 }
1158
1159 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1160 {
1161 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1162 /* Disable Read and Write Multiple */
1163 s->mult_sectors = 0;
1164 } else if ((s->nsector & 0xff) != 0 &&
1165 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1166 (s->nsector & (s->nsector - 1)) != 0)) {
1167 ide_abort_command(s);
1168 } else {
1169 s->mult_sectors = s->nsector & 0xff;
1170 }
1171
1172 return true;
1173 }
1174
1175 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1176 {
1177 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1178
1179 if (!s->bs || !s->mult_sectors) {
1180 ide_abort_command(s);
1181 return true;
1182 }
1183
1184 ide_cmd_lba48_transform(s, lba48);
1185 s->req_nb_sectors = s->mult_sectors;
1186 ide_sector_read(s);
1187 return false;
1188 }
1189
1190 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1191 {
1192 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1193 int n;
1194
1195 if (!s->bs || !s->mult_sectors) {
1196 ide_abort_command(s);
1197 return true;
1198 }
1199
1200 ide_cmd_lba48_transform(s, lba48);
1201
1202 s->req_nb_sectors = s->mult_sectors;
1203 n = MIN(s->nsector, s->req_nb_sectors);
1204
1205 s->status = SEEK_STAT | READY_STAT;
1206 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1207
1208 s->media_changed = 1;
1209
1210 return false;
1211 }
1212
1213 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1214 {
1215 bool lba48 = (cmd == WIN_READ_EXT);
1216
1217 if (s->drive_kind == IDE_CD) {
1218 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1219 ide_abort_command(s);
1220 return true;
1221 }
1222
1223 if (!s->bs) {
1224 ide_abort_command(s);
1225 return true;
1226 }
1227
1228 ide_cmd_lba48_transform(s, lba48);
1229 s->req_nb_sectors = 1;
1230 ide_sector_read(s);
1231
1232 return false;
1233 }
1234
1235 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1236 {
1237 bool lba48 = (cmd == WIN_WRITE_EXT);
1238
1239 if (!s->bs) {
1240 ide_abort_command(s);
1241 return true;
1242 }
1243
1244 ide_cmd_lba48_transform(s, lba48);
1245
1246 s->req_nb_sectors = 1;
1247 s->status = SEEK_STAT | READY_STAT;
1248 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1249
1250 s->media_changed = 1;
1251
1252 return false;
1253 }
1254
1255 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1256 {
1257 bool lba48 = (cmd == WIN_READDMA_EXT);
1258
1259 if (!s->bs) {
1260 ide_abort_command(s);
1261 return true;
1262 }
1263
1264 ide_cmd_lba48_transform(s, lba48);
1265 ide_sector_start_dma(s, IDE_DMA_READ);
1266
1267 return false;
1268 }
1269
1270 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1271 {
1272 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1273
1274 if (!s->bs) {
1275 ide_abort_command(s);
1276 return true;
1277 }
1278
1279 ide_cmd_lba48_transform(s, lba48);
1280 ide_sector_start_dma(s, IDE_DMA_WRITE);
1281
1282 s->media_changed = 1;
1283
1284 return false;
1285 }
1286
1287 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1288 {
1289 ide_flush_cache(s);
1290 return false;
1291 }
1292
1293 static bool cmd_seek(IDEState *s, uint8_t cmd)
1294 {
1295 /* XXX: Check that seek is within bounds */
1296 return true;
1297 }
1298
1299 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1300 {
1301 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1302
1303 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1304 if (s->nb_sectors == 0) {
1305 ide_abort_command(s);
1306 return true;
1307 }
1308
1309 ide_cmd_lba48_transform(s, lba48);
1310 ide_set_sector(s, s->nb_sectors - 1);
1311
1312 return true;
1313 }
1314
1315 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1316 {
1317 s->nsector = 0xff; /* device active or idle */
1318 return true;
1319 }
1320
1321 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1322 {
1323 uint16_t *identify_data;
1324
1325 if (!s->bs) {
1326 ide_abort_command(s);
1327 return true;
1328 }
1329
1330 /* XXX: valid for CDROM ? */
1331 switch (s->feature) {
1332 case 0x02: /* write cache enable */
1333 bdrv_set_enable_write_cache(s->bs, true);
1334 identify_data = (uint16_t *)s->identify_data;
1335 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1336 return true;
1337 case 0x82: /* write cache disable */
1338 bdrv_set_enable_write_cache(s->bs, false);
1339 identify_data = (uint16_t *)s->identify_data;
1340 put_le16(identify_data + 85, (1 << 14) | 1);
1341 ide_flush_cache(s);
1342 return false;
1343 case 0xcc: /* reverting to power-on defaults enable */
1344 case 0x66: /* reverting to power-on defaults disable */
1345 case 0xaa: /* read look-ahead enable */
1346 case 0x55: /* read look-ahead disable */
1347 case 0x05: /* set advanced power management mode */
1348 case 0x85: /* disable advanced power management mode */
1349 case 0x69: /* NOP */
1350 case 0x67: /* NOP */
1351 case 0x96: /* NOP */
1352 case 0x9a: /* NOP */
1353 case 0x42: /* enable Automatic Acoustic Mode */
1354 case 0xc2: /* disable Automatic Acoustic Mode */
1355 return true;
1356 case 0x03: /* set transfer mode */
1357 {
1358 uint8_t val = s->nsector & 0x07;
1359 identify_data = (uint16_t *)s->identify_data;
1360
1361 switch (s->nsector >> 3) {
1362 case 0x00: /* pio default */
1363 case 0x01: /* pio mode */
1364 put_le16(identify_data + 62, 0x07);
1365 put_le16(identify_data + 63, 0x07);
1366 put_le16(identify_data + 88, 0x3f);
1367 break;
1368 case 0x02: /* sigle word dma mode*/
1369 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1370 put_le16(identify_data + 63, 0x07);
1371 put_le16(identify_data + 88, 0x3f);
1372 break;
1373 case 0x04: /* mdma mode */
1374 put_le16(identify_data + 62, 0x07);
1375 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1376 put_le16(identify_data + 88, 0x3f);
1377 break;
1378 case 0x08: /* udma mode */
1379 put_le16(identify_data + 62, 0x07);
1380 put_le16(identify_data + 63, 0x07);
1381 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1382 break;
1383 default:
1384 goto abort_cmd;
1385 }
1386 return true;
1387 }
1388 }
1389
1390 abort_cmd:
1391 ide_abort_command(s);
1392 return true;
1393 }
1394
1395
1396 /*** ATAPI commands ***/
1397
1398 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1399 {
1400 ide_atapi_identify(s);
1401 s->status = READY_STAT | SEEK_STAT;
1402 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1403 ide_set_irq(s->bus);
1404 return false;
1405 }
1406
1407 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1408 {
1409 ide_set_signature(s);
1410
1411 if (s->drive_kind == IDE_CD) {
1412 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1413 * devices to return a clear status register
1414 * with READY_STAT *not* set. */
1415 s->error = 0x01;
1416 } else {
1417 s->status = READY_STAT | SEEK_STAT;
1418 /* The bits of the error register are not as usual for this command!
1419 * They are part of the regular output (this is why ERR_STAT isn't set)
1420 * Device 0 passed, Device 1 passed or not present. */
1421 s->error = 0x01;
1422 ide_set_irq(s->bus);
1423 }
1424
1425 return false;
1426 }
1427
1428 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1429 {
1430 ide_set_signature(s);
1431 s->status = 0x00; /* NOTE: READY is _not_ set */
1432 s->error = 0x01;
1433
1434 return false;
1435 }
1436
1437 static bool cmd_packet(IDEState *s, uint8_t cmd)
1438 {
1439 /* overlapping commands not supported */
1440 if (s->feature & 0x02) {
1441 ide_abort_command(s);
1442 return true;
1443 }
1444
1445 s->status = READY_STAT | SEEK_STAT;
1446 s->atapi_dma = s->feature & 1;
1447 s->nsector = 1;
1448 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1449 ide_atapi_cmd);
1450 return false;
1451 }
1452
1453
1454 /*** CF-ATA commands ***/
1455
1456 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1457 {
1458 s->error = 0x09; /* miscellaneous error */
1459 s->status = READY_STAT | SEEK_STAT;
1460 ide_set_irq(s->bus);
1461
1462 return false;
1463 }
1464
1465 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1466 {
1467 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1468 * required for Windows 8 to work with AHCI */
1469
1470 if (cmd == CFA_WEAR_LEVEL) {
1471 s->nsector = 0;
1472 }
1473
1474 if (cmd == CFA_ERASE_SECTORS) {
1475 s->media_changed = 1;
1476 }
1477
1478 return true;
1479 }
1480
1481 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1482 {
1483 s->status = READY_STAT | SEEK_STAT;
1484
1485 memset(s->io_buffer, 0, 0x200);
1486 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1487 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1488 s->io_buffer[0x02] = s->select; /* Head */
1489 s->io_buffer[0x03] = s->sector; /* Sector */
1490 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1491 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1492 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1493 s->io_buffer[0x13] = 0x00; /* Erase flag */
1494 s->io_buffer[0x18] = 0x00; /* Hot count */
1495 s->io_buffer[0x19] = 0x00; /* Hot count */
1496 s->io_buffer[0x1a] = 0x01; /* Hot count */
1497
1498 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1499 ide_set_irq(s->bus);
1500
1501 return false;
1502 }
1503
1504 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1505 {
1506 switch (s->feature) {
1507 case 0x02: /* Inquiry Metadata Storage */
1508 ide_cfata_metadata_inquiry(s);
1509 break;
1510 case 0x03: /* Read Metadata Storage */
1511 ide_cfata_metadata_read(s);
1512 break;
1513 case 0x04: /* Write Metadata Storage */
1514 ide_cfata_metadata_write(s);
1515 break;
1516 default:
1517 ide_abort_command(s);
1518 return true;
1519 }
1520
1521 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1522 s->status = 0x00; /* NOTE: READY is _not_ set */
1523 ide_set_irq(s->bus);
1524
1525 return false;
1526 }
1527
1528 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1529 {
1530 switch (s->feature) {
1531 case 0x01: /* sense temperature in device */
1532 s->nsector = 0x50; /* +20 C */
1533 break;
1534 default:
1535 ide_abort_command(s);
1536 return true;
1537 }
1538
1539 return true;
1540 }
1541
1542
1543 /*** SMART commands ***/
1544
1545 static bool cmd_smart(IDEState *s, uint8_t cmd)
1546 {
1547 int n;
1548
1549 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1550 goto abort_cmd;
1551 }
1552
1553 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1554 goto abort_cmd;
1555 }
1556
1557 switch (s->feature) {
1558 case SMART_DISABLE:
1559 s->smart_enabled = 0;
1560 return true;
1561
1562 case SMART_ENABLE:
1563 s->smart_enabled = 1;
1564 return true;
1565
1566 case SMART_ATTR_AUTOSAVE:
1567 switch (s->sector) {
1568 case 0x00:
1569 s->smart_autosave = 0;
1570 break;
1571 case 0xf1:
1572 s->smart_autosave = 1;
1573 break;
1574 default:
1575 goto abort_cmd;
1576 }
1577 return true;
1578
1579 case SMART_STATUS:
1580 if (!s->smart_errors) {
1581 s->hcyl = 0xc2;
1582 s->lcyl = 0x4f;
1583 } else {
1584 s->hcyl = 0x2c;
1585 s->lcyl = 0xf4;
1586 }
1587 return true;
1588
1589 case SMART_READ_THRESH:
1590 memset(s->io_buffer, 0, 0x200);
1591 s->io_buffer[0] = 0x01; /* smart struct version */
1592
1593 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1594 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1595 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1596 }
1597
1598 /* checksum */
1599 for (n = 0; n < 511; n++) {
1600 s->io_buffer[511] += s->io_buffer[n];
1601 }
1602 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1603
1604 s->status = READY_STAT | SEEK_STAT;
1605 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1606 ide_set_irq(s->bus);
1607 return false;
1608
1609 case SMART_READ_DATA:
1610 memset(s->io_buffer, 0, 0x200);
1611 s->io_buffer[0] = 0x01; /* smart struct version */
1612
1613 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1614 int i;
1615 for (i = 0; i < 11; i++) {
1616 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1617 }
1618 }
1619
1620 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1621 if (s->smart_selftest_count == 0) {
1622 s->io_buffer[363] = 0;
1623 } else {
1624 s->io_buffer[363] =
1625 s->smart_selftest_data[3 +
1626 (s->smart_selftest_count - 1) *
1627 24];
1628 }
1629 s->io_buffer[364] = 0x20;
1630 s->io_buffer[365] = 0x01;
1631 /* offline data collection capacity: execute + self-test*/
1632 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1633 s->io_buffer[368] = 0x03; /* smart capability (1) */
1634 s->io_buffer[369] = 0x00; /* smart capability (2) */
1635 s->io_buffer[370] = 0x01; /* error logging supported */
1636 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1637 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1638 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1639
1640 for (n = 0; n < 511; n++) {
1641 s->io_buffer[511] += s->io_buffer[n];
1642 }
1643 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1644
1645 s->status = READY_STAT | SEEK_STAT;
1646 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1647 ide_set_irq(s->bus);
1648 return false;
1649
1650 case SMART_READ_LOG:
1651 switch (s->sector) {
1652 case 0x01: /* summary smart error log */
1653 memset(s->io_buffer, 0, 0x200);
1654 s->io_buffer[0] = 0x01;
1655 s->io_buffer[1] = 0x00; /* no error entries */
1656 s->io_buffer[452] = s->smart_errors & 0xff;
1657 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1658
1659 for (n = 0; n < 511; n++) {
1660 s->io_buffer[511] += s->io_buffer[n];
1661 }
1662 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1663 break;
1664 case 0x06: /* smart self test log */
1665 memset(s->io_buffer, 0, 0x200);
1666 s->io_buffer[0] = 0x01;
1667 if (s->smart_selftest_count == 0) {
1668 s->io_buffer[508] = 0;
1669 } else {
1670 s->io_buffer[508] = s->smart_selftest_count;
1671 for (n = 2; n < 506; n++) {
1672 s->io_buffer[n] = s->smart_selftest_data[n];
1673 }
1674 }
1675
1676 for (n = 0; n < 511; n++) {
1677 s->io_buffer[511] += s->io_buffer[n];
1678 }
1679 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1680 break;
1681 default:
1682 goto abort_cmd;
1683 }
1684 s->status = READY_STAT | SEEK_STAT;
1685 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1686 ide_set_irq(s->bus);
1687 return false;
1688
1689 case SMART_EXECUTE_OFFLINE:
1690 switch (s->sector) {
1691 case 0: /* off-line routine */
1692 case 1: /* short self test */
1693 case 2: /* extended self test */
1694 s->smart_selftest_count++;
1695 if (s->smart_selftest_count > 21) {
1696 s->smart_selftest_count = 1;
1697 }
1698 n = 2 + (s->smart_selftest_count - 1) * 24;
1699 s->smart_selftest_data[n] = s->sector;
1700 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1701 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1702 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1703 break;
1704 default:
1705 goto abort_cmd;
1706 }
1707 return true;
1708 }
1709
1710 abort_cmd:
1711 ide_abort_command(s);
1712 return true;
1713 }
1714
1715 #define HD_OK (1u << IDE_HD)
1716 #define CD_OK (1u << IDE_CD)
1717 #define CFA_OK (1u << IDE_CFATA)
1718 #define HD_CFA_OK (HD_OK | CFA_OK)
1719 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1720
1721 /* Set the Disk Seek Completed status bit during completion */
1722 #define SET_DSC (1u << 8)
1723
1724 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1725 static const struct {
1726 /* Returns true if the completion code should be run */
1727 bool (*handler)(IDEState *s, uint8_t cmd);
1728 int flags;
1729 } ide_cmd_table[0x100] = {
1730 /* NOP not implemented, mandatory for CD */
1731 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1732 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
1733 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1734 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1735 [WIN_READ] = { cmd_read_pio, ALL_OK },
1736 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1737 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1738 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1739 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1740 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1741 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1742 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1743 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1744 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1745 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1746 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1747 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1748 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1749 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1750 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1751 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1752 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1753 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1754 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1755 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1756 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1757 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1758 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
1759 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1760 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
1761 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1762 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
1763 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
1764 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1765 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
1766 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1767 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1768 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1769 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1770 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1771 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1772 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
1773 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1774 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1775 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1776 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1777 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
1778 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1779 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
1780 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1781 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1782 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1783 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
1784 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1785 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
1786 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
1787 };
1788
1789 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1790 {
1791 return cmd < ARRAY_SIZE(ide_cmd_table)
1792 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1793 }
1794
1795 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1796 {
1797 IDEState *s;
1798 bool complete;
1799
1800 #if defined(DEBUG_IDE)
1801 printf("ide: CMD=%02x\n", val);
1802 #endif
1803 s = idebus_active_if(bus);
1804 /* ignore commands to non existent slave */
1805 if (s != bus->ifs && !s->bs)
1806 return;
1807
1808 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1809 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1810 return;
1811
1812 if (!ide_cmd_permitted(s, val)) {
1813 ide_abort_command(s);
1814 ide_set_irq(s->bus);
1815 return;
1816 }
1817
1818 s->status = READY_STAT | BUSY_STAT;
1819 s->error = 0;
1820
1821 complete = ide_cmd_table[val].handler(s, val);
1822 if (complete) {
1823 s->status &= ~BUSY_STAT;
1824 assert(!!s->error == !!(s->status & ERR_STAT));
1825
1826 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1827 s->status |= SEEK_STAT;
1828 }
1829
1830 ide_cmd_done(s);
1831 ide_set_irq(s->bus);
1832 }
1833 }
1834
1835 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1836 {
1837 IDEBus *bus = opaque;
1838 IDEState *s = idebus_active_if(bus);
1839 uint32_t addr;
1840 int ret, hob;
1841
1842 addr = addr1 & 7;
1843 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1844 //hob = s->select & (1 << 7);
1845 hob = 0;
1846 switch(addr) {
1847 case 0:
1848 ret = 0xff;
1849 break;
1850 case 1:
1851 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1852 (s != bus->ifs && !s->bs))
1853 ret = 0;
1854 else if (!hob)
1855 ret = s->error;
1856 else
1857 ret = s->hob_feature;
1858 break;
1859 case 2:
1860 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1861 ret = 0;
1862 else if (!hob)
1863 ret = s->nsector & 0xff;
1864 else
1865 ret = s->hob_nsector;
1866 break;
1867 case 3:
1868 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1869 ret = 0;
1870 else if (!hob)
1871 ret = s->sector;
1872 else
1873 ret = s->hob_sector;
1874 break;
1875 case 4:
1876 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1877 ret = 0;
1878 else if (!hob)
1879 ret = s->lcyl;
1880 else
1881 ret = s->hob_lcyl;
1882 break;
1883 case 5:
1884 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1885 ret = 0;
1886 else if (!hob)
1887 ret = s->hcyl;
1888 else
1889 ret = s->hob_hcyl;
1890 break;
1891 case 6:
1892 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1893 ret = 0;
1894 else
1895 ret = s->select;
1896 break;
1897 default:
1898 case 7:
1899 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1900 (s != bus->ifs && !s->bs))
1901 ret = 0;
1902 else
1903 ret = s->status;
1904 qemu_irq_lower(bus->irq);
1905 break;
1906 }
1907 #ifdef DEBUG_IDE
1908 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1909 #endif
1910 return ret;
1911 }
1912
1913 uint32_t ide_status_read(void *opaque, uint32_t addr)
1914 {
1915 IDEBus *bus = opaque;
1916 IDEState *s = idebus_active_if(bus);
1917 int ret;
1918
1919 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1920 (s != bus->ifs && !s->bs))
1921 ret = 0;
1922 else
1923 ret = s->status;
1924 #ifdef DEBUG_IDE
1925 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1926 #endif
1927 return ret;
1928 }
1929
1930 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1931 {
1932 IDEBus *bus = opaque;
1933 IDEState *s;
1934 int i;
1935
1936 #ifdef DEBUG_IDE
1937 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1938 #endif
1939 /* common for both drives */
1940 if (!(bus->cmd & IDE_CMD_RESET) &&
1941 (val & IDE_CMD_RESET)) {
1942 /* reset low to high */
1943 for(i = 0;i < 2; i++) {
1944 s = &bus->ifs[i];
1945 s->status = BUSY_STAT | SEEK_STAT;
1946 s->error = 0x01;
1947 }
1948 } else if ((bus->cmd & IDE_CMD_RESET) &&
1949 !(val & IDE_CMD_RESET)) {
1950 /* high to low */
1951 for(i = 0;i < 2; i++) {
1952 s = &bus->ifs[i];
1953 if (s->drive_kind == IDE_CD)
1954 s->status = 0x00; /* NOTE: READY is _not_ set */
1955 else
1956 s->status = READY_STAT | SEEK_STAT;
1957 ide_set_signature(s);
1958 }
1959 }
1960
1961 bus->cmd = val;
1962 }
1963
1964 /*
1965 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1966 * transferred from the device to the guest), false if it's a PIO in
1967 */
1968 static bool ide_is_pio_out(IDEState *s)
1969 {
1970 if (s->end_transfer_func == ide_sector_write ||
1971 s->end_transfer_func == ide_atapi_cmd) {
1972 return false;
1973 } else if (s->end_transfer_func == ide_sector_read ||
1974 s->end_transfer_func == ide_transfer_stop ||
1975 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1976 s->end_transfer_func == ide_dummy_transfer_stop) {
1977 return true;
1978 }
1979
1980 abort();
1981 }
1982
1983 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1984 {
1985 IDEBus *bus = opaque;
1986 IDEState *s = idebus_active_if(bus);
1987 uint8_t *p;
1988
1989 /* PIO data access allowed only when DRQ bit is set. The result of a write
1990 * during PIO out is indeterminate, just ignore it. */
1991 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1992 return;
1993 }
1994
1995 p = s->data_ptr;
1996 *(uint16_t *)p = le16_to_cpu(val);
1997 p += 2;
1998 s->data_ptr = p;
1999 if (p >= s->data_end)
2000 s->end_transfer_func(s);
2001 }
2002
2003 uint32_t ide_data_readw(void *opaque, uint32_t addr)
2004 {
2005 IDEBus *bus = opaque;
2006 IDEState *s = idebus_active_if(bus);
2007 uint8_t *p;
2008 int ret;
2009
2010 /* PIO data access allowed only when DRQ bit is set. The result of a read
2011 * during PIO in is indeterminate, return 0 and don't move forward. */
2012 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2013 return 0;
2014 }
2015
2016 p = s->data_ptr;
2017 ret = cpu_to_le16(*(uint16_t *)p);
2018 p += 2;
2019 s->data_ptr = p;
2020 if (p >= s->data_end)
2021 s->end_transfer_func(s);
2022 return ret;
2023 }
2024
2025 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2026 {
2027 IDEBus *bus = opaque;
2028 IDEState *s = idebus_active_if(bus);
2029 uint8_t *p;
2030
2031 /* PIO data access allowed only when DRQ bit is set. The result of a write
2032 * during PIO out is indeterminate, just ignore it. */
2033 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2034 return;
2035 }
2036
2037 p = s->data_ptr;
2038 *(uint32_t *)p = le32_to_cpu(val);
2039 p += 4;
2040 s->data_ptr = p;
2041 if (p >= s->data_end)
2042 s->end_transfer_func(s);
2043 }
2044
2045 uint32_t ide_data_readl(void *opaque, uint32_t addr)
2046 {
2047 IDEBus *bus = opaque;
2048 IDEState *s = idebus_active_if(bus);
2049 uint8_t *p;
2050 int ret;
2051
2052 /* PIO data access allowed only when DRQ bit is set. The result of a read
2053 * during PIO in is indeterminate, return 0 and don't move forward. */
2054 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2055 return 0;
2056 }
2057
2058 p = s->data_ptr;
2059 ret = cpu_to_le32(*(uint32_t *)p);
2060 p += 4;
2061 s->data_ptr = p;
2062 if (p >= s->data_end)
2063 s->end_transfer_func(s);
2064 return ret;
2065 }
2066
2067 static void ide_dummy_transfer_stop(IDEState *s)
2068 {
2069 s->data_ptr = s->io_buffer;
2070 s->data_end = s->io_buffer;
2071 s->io_buffer[0] = 0xff;
2072 s->io_buffer[1] = 0xff;
2073 s->io_buffer[2] = 0xff;
2074 s->io_buffer[3] = 0xff;
2075 }
2076
2077 static void ide_reset(IDEState *s)
2078 {
2079 #ifdef DEBUG_IDE
2080 printf("ide: reset\n");
2081 #endif
2082
2083 if (s->pio_aiocb) {
2084 bdrv_aio_cancel(s->pio_aiocb);
2085 s->pio_aiocb = NULL;
2086 }
2087
2088 if (s->drive_kind == IDE_CFATA)
2089 s->mult_sectors = 0;
2090 else
2091 s->mult_sectors = MAX_MULT_SECTORS;
2092 /* ide regs */
2093 s->feature = 0;
2094 s->error = 0;
2095 s->nsector = 0;
2096 s->sector = 0;
2097 s->lcyl = 0;
2098 s->hcyl = 0;
2099
2100 /* lba48 */
2101 s->hob_feature = 0;
2102 s->hob_sector = 0;
2103 s->hob_nsector = 0;
2104 s->hob_lcyl = 0;
2105 s->hob_hcyl = 0;
2106
2107 s->select = 0xa0;
2108 s->status = READY_STAT | SEEK_STAT;
2109
2110 s->lba48 = 0;
2111
2112 /* ATAPI specific */
2113 s->sense_key = 0;
2114 s->asc = 0;
2115 s->cdrom_changed = 0;
2116 s->packet_transfer_size = 0;
2117 s->elementary_transfer_size = 0;
2118 s->io_buffer_index = 0;
2119 s->cd_sector_size = 0;
2120 s->atapi_dma = 0;
2121 s->tray_locked = 0;
2122 s->tray_open = 0;
2123 /* ATA DMA state */
2124 s->io_buffer_size = 0;
2125 s->req_nb_sectors = 0;
2126
2127 ide_set_signature(s);
2128 /* init the transfer handler so that 0xffff is returned on data
2129 accesses */
2130 s->end_transfer_func = ide_dummy_transfer_stop;
2131 ide_dummy_transfer_stop(s);
2132 s->media_changed = 0;
2133 }
2134
2135 void ide_bus_reset(IDEBus *bus)
2136 {
2137 bus->unit = 0;
2138 bus->cmd = 0;
2139 ide_reset(&bus->ifs[0]);
2140 ide_reset(&bus->ifs[1]);
2141 ide_clear_hob(bus);
2142
2143 /* pending async DMA */
2144 if (bus->dma->aiocb) {
2145 #ifdef DEBUG_AIO
2146 printf("aio_cancel\n");
2147 #endif
2148 bdrv_aio_cancel(bus->dma->aiocb);
2149 bus->dma->aiocb = NULL;
2150 }
2151
2152 /* reset dma provider too */
2153 if (bus->dma->ops->reset) {
2154 bus->dma->ops->reset(bus->dma);
2155 }
2156 }
2157
2158 static bool ide_cd_is_tray_open(void *opaque)
2159 {
2160 return ((IDEState *)opaque)->tray_open;
2161 }
2162
2163 static bool ide_cd_is_medium_locked(void *opaque)
2164 {
2165 return ((IDEState *)opaque)->tray_locked;
2166 }
2167
2168 static void ide_resize_cb(void *opaque)
2169 {
2170 IDEState *s = opaque;
2171 uint64_t nb_sectors;
2172
2173 if (!s->identify_set) {
2174 return;
2175 }
2176
2177 bdrv_get_geometry(s->bs, &nb_sectors);
2178 s->nb_sectors = nb_sectors;
2179
2180 /* Update the identify data buffer. */
2181 if (s->drive_kind == IDE_CFATA) {
2182 ide_cfata_identify_size(s);
2183 } else {
2184 /* IDE_CD uses a different set of callbacks entirely. */
2185 assert(s->drive_kind != IDE_CD);
2186 ide_identify_size(s);
2187 }
2188 }
2189
2190 static const BlockDevOps ide_cd_block_ops = {
2191 .change_media_cb = ide_cd_change_cb,
2192 .eject_request_cb = ide_cd_eject_request_cb,
2193 .is_tray_open = ide_cd_is_tray_open,
2194 .is_medium_locked = ide_cd_is_medium_locked,
2195 };
2196
2197 static const BlockDevOps ide_hd_block_ops = {
2198 .resize_cb = ide_resize_cb,
2199 };
2200
2201 int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
2202 const char *version, const char *serial, const char *model,
2203 uint64_t wwn,
2204 uint32_t cylinders, uint32_t heads, uint32_t secs,
2205 int chs_trans)
2206 {
2207 uint64_t nb_sectors;
2208
2209 s->bs = bs;
2210 s->drive_kind = kind;
2211
2212 bdrv_get_geometry(bs, &nb_sectors);
2213 s->cylinders = cylinders;
2214 s->heads = heads;
2215 s->sectors = secs;
2216 s->chs_trans = chs_trans;
2217 s->nb_sectors = nb_sectors;
2218 s->wwn = wwn;
2219 /* The SMART values should be preserved across power cycles
2220 but they aren't. */
2221 s->smart_enabled = 1;
2222 s->smart_autosave = 1;
2223 s->smart_errors = 0;
2224 s->smart_selftest_count = 0;
2225 if (kind == IDE_CD) {
2226 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
2227 bdrv_set_guest_block_size(bs, 2048);
2228 } else {
2229 if (!bdrv_is_inserted(s->bs)) {
2230 error_report("Device needs media, but drive is empty");
2231 return -1;
2232 }
2233 if (bdrv_is_read_only(bs)) {
2234 error_report("Can't use a read-only drive");
2235 return -1;
2236 }
2237 bdrv_set_dev_ops(bs, &ide_hd_block_ops, s);
2238 }
2239 if (serial) {
2240 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2241 } else {
2242 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2243 "QM%05d", s->drive_serial);
2244 }
2245 if (model) {
2246 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2247 } else {
2248 switch (kind) {
2249 case IDE_CD:
2250 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2251 break;
2252 case IDE_CFATA:
2253 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2254 break;
2255 default:
2256 strcpy(s->drive_model_str, "QEMU HARDDISK");
2257 break;
2258 }
2259 }
2260
2261 if (version) {
2262 pstrcpy(s->version, sizeof(s->version), version);
2263 } else {
2264 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
2265 }
2266
2267 ide_reset(s);
2268 bdrv_iostatus_enable(bs);
2269 return 0;
2270 }
2271
2272 static void ide_init1(IDEBus *bus, int unit)
2273 {
2274 static int drive_serial = 1;
2275 IDEState *s = &bus->ifs[unit];
2276
2277 s->bus = bus;
2278 s->unit = unit;
2279 s->drive_serial = drive_serial++;
2280 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2281 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2282 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2283 memset(s->io_buffer, 0, s->io_buffer_total_len);
2284
2285 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
2286 memset(s->smart_selftest_data, 0, 512);
2287
2288 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2289 ide_sector_write_timer_cb, s);
2290 }
2291
2292 static int ide_nop_int(IDEDMA *dma, int x)
2293 {
2294 return 0;
2295 }
2296
2297 static void ide_nop_restart(void *opaque, int x, RunState y)
2298 {
2299 }
2300
2301 static const IDEDMAOps ide_dma_nop_ops = {
2302 .prepare_buf = ide_nop_int,
2303 .rw_buf = ide_nop_int,
2304 .set_unit = ide_nop_int,
2305 .restart_cb = ide_nop_restart,
2306 };
2307
2308 static IDEDMA ide_dma_nop = {
2309 .ops = &ide_dma_nop_ops,
2310 .aiocb = NULL,
2311 };
2312
2313 void ide_init2(IDEBus *bus, qemu_irq irq)
2314 {
2315 int i;
2316
2317 for(i = 0; i < 2; i++) {
2318 ide_init1(bus, i);
2319 ide_reset(&bus->ifs[i]);
2320 }
2321 bus->irq = irq;
2322 bus->dma = &ide_dma_nop;
2323 }
2324
2325 static const MemoryRegionPortio ide_portio_list[] = {
2326 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2327 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2328 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2329 PORTIO_END_OF_LIST(),
2330 };
2331
2332 static const MemoryRegionPortio ide_portio2_list[] = {
2333 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2334 PORTIO_END_OF_LIST(),
2335 };
2336
2337 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2338 {
2339 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2340 bridge has been setup properly to always register with ISA. */
2341 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2342
2343 if (iobase2) {
2344 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2345 }
2346 }
2347
2348 static bool is_identify_set(void *opaque, int version_id)
2349 {
2350 IDEState *s = opaque;
2351
2352 return s->identify_set != 0;
2353 }
2354
2355 static EndTransferFunc* transfer_end_table[] = {
2356 ide_sector_read,
2357 ide_sector_write,
2358 ide_transfer_stop,
2359 ide_atapi_cmd_reply_end,
2360 ide_atapi_cmd,
2361 ide_dummy_transfer_stop,
2362 };
2363
2364 static int transfer_end_table_idx(EndTransferFunc *fn)
2365 {
2366 int i;
2367
2368 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2369 if (transfer_end_table[i] == fn)
2370 return i;
2371
2372 return -1;
2373 }
2374
2375 static int ide_drive_post_load(void *opaque, int version_id)
2376 {
2377 IDEState *s = opaque;
2378
2379 if (s->identify_set) {
2380 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5)));
2381 }
2382 return 0;
2383 }
2384
2385 static int ide_drive_pio_post_load(void *opaque, int version_id)
2386 {
2387 IDEState *s = opaque;
2388
2389 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2390 return -EINVAL;
2391 }
2392 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2393 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2394 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2395
2396 return 0;
2397 }
2398
2399 static void ide_drive_pio_pre_save(void *opaque)
2400 {
2401 IDEState *s = opaque;
2402 int idx;
2403
2404 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2405 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2406
2407 idx = transfer_end_table_idx(s->end_transfer_func);
2408 if (idx == -1) {
2409 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2410 __func__);
2411 s->end_transfer_fn_idx = 2;
2412 } else {
2413 s->end_transfer_fn_idx = idx;
2414 }
2415 }
2416
2417 static bool ide_drive_pio_state_needed(void *opaque)
2418 {
2419 IDEState *s = opaque;
2420
2421 return ((s->status & DRQ_STAT) != 0)
2422 || (s->bus->error_status & IDE_RETRY_PIO);
2423 }
2424
2425 static bool ide_tray_state_needed(void *opaque)
2426 {
2427 IDEState *s = opaque;
2428
2429 return s->tray_open || s->tray_locked;
2430 }
2431
2432 static bool ide_atapi_gesn_needed(void *opaque)
2433 {
2434 IDEState *s = opaque;
2435
2436 return s->events.new_media || s->events.eject_request;
2437 }
2438
2439 static bool ide_error_needed(void *opaque)
2440 {
2441 IDEBus *bus = opaque;
2442
2443 return (bus->error_status != 0);
2444 }
2445
2446 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2447 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2448 .name ="ide_drive/atapi/gesn_state",
2449 .version_id = 1,
2450 .minimum_version_id = 1,
2451 .fields = (VMStateField[]) {
2452 VMSTATE_BOOL(events.new_media, IDEState),
2453 VMSTATE_BOOL(events.eject_request, IDEState),
2454 VMSTATE_END_OF_LIST()
2455 }
2456 };
2457
2458 static const VMStateDescription vmstate_ide_tray_state = {
2459 .name = "ide_drive/tray_state",
2460 .version_id = 1,
2461 .minimum_version_id = 1,
2462 .fields = (VMStateField[]) {
2463 VMSTATE_BOOL(tray_open, IDEState),
2464 VMSTATE_BOOL(tray_locked, IDEState),
2465 VMSTATE_END_OF_LIST()
2466 }
2467 };
2468
2469 static const VMStateDescription vmstate_ide_drive_pio_state = {
2470 .name = "ide_drive/pio_state",
2471 .version_id = 1,
2472 .minimum_version_id = 1,
2473 .pre_save = ide_drive_pio_pre_save,
2474 .post_load = ide_drive_pio_post_load,
2475 .fields = (VMStateField[]) {
2476 VMSTATE_INT32(req_nb_sectors, IDEState),
2477 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2478 vmstate_info_uint8, uint8_t),
2479 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2480 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2481 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2482 VMSTATE_INT32(elementary_transfer_size, IDEState),
2483 VMSTATE_INT32(packet_transfer_size, IDEState),
2484 VMSTATE_END_OF_LIST()
2485 }
2486 };
2487
2488 const VMStateDescription vmstate_ide_drive = {
2489 .name = "ide_drive",
2490 .version_id = 3,
2491 .minimum_version_id = 0,
2492 .post_load = ide_drive_post_load,
2493 .fields = (VMStateField[]) {
2494 VMSTATE_INT32(mult_sectors, IDEState),
2495 VMSTATE_INT32(identify_set, IDEState),
2496 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2497 VMSTATE_UINT8(feature, IDEState),
2498 VMSTATE_UINT8(error, IDEState),
2499 VMSTATE_UINT32(nsector, IDEState),
2500 VMSTATE_UINT8(sector, IDEState),
2501 VMSTATE_UINT8(lcyl, IDEState),
2502 VMSTATE_UINT8(hcyl, IDEState),
2503 VMSTATE_UINT8(hob_feature, IDEState),
2504 VMSTATE_UINT8(hob_sector, IDEState),
2505 VMSTATE_UINT8(hob_nsector, IDEState),
2506 VMSTATE_UINT8(hob_lcyl, IDEState),
2507 VMSTATE_UINT8(hob_hcyl, IDEState),
2508 VMSTATE_UINT8(select, IDEState),
2509 VMSTATE_UINT8(status, IDEState),
2510 VMSTATE_UINT8(lba48, IDEState),
2511 VMSTATE_UINT8(sense_key, IDEState),
2512 VMSTATE_UINT8(asc, IDEState),
2513 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2514 VMSTATE_END_OF_LIST()
2515 },
2516 .subsections = (VMStateSubsection []) {
2517 {
2518 .vmsd = &vmstate_ide_drive_pio_state,
2519 .needed = ide_drive_pio_state_needed,
2520 }, {
2521 .vmsd = &vmstate_ide_tray_state,
2522 .needed = ide_tray_state_needed,
2523 }, {
2524 .vmsd = &vmstate_ide_atapi_gesn_state,
2525 .needed = ide_atapi_gesn_needed,
2526 }, {
2527 /* empty */
2528 }
2529 }
2530 };
2531
2532 static const VMStateDescription vmstate_ide_error_status = {
2533 .name ="ide_bus/error",
2534 .version_id = 1,
2535 .minimum_version_id = 1,
2536 .fields = (VMStateField[]) {
2537 VMSTATE_INT32(error_status, IDEBus),
2538 VMSTATE_END_OF_LIST()
2539 }
2540 };
2541
2542 const VMStateDescription vmstate_ide_bus = {
2543 .name = "ide_bus",
2544 .version_id = 1,
2545 .minimum_version_id = 1,
2546 .fields = (VMStateField[]) {
2547 VMSTATE_UINT8(cmd, IDEBus),
2548 VMSTATE_UINT8(unit, IDEBus),
2549 VMSTATE_END_OF_LIST()
2550 },
2551 .subsections = (VMStateSubsection []) {
2552 {
2553 .vmsd = &vmstate_ide_error_status,
2554 .needed = ide_error_needed,
2555 }, {
2556 /* empty */
2557 }
2558 }
2559 };
2560
2561 void ide_drive_get(DriveInfo **hd, int n)
2562 {
2563 int i;
2564 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2565 int max_devs = drive_get_max_devs(IF_IDE);
2566 int n_buses = max_devs ? (n / max_devs) : n;
2567
2568 /*
2569 * Note: The number of actual buses available is not known.
2570 * We compute this based on the size of the DriveInfo* array, n.
2571 * If it is less than max_devs * <num_real_buses>,
2572 * We will stop looking for drives prematurely instead of overfilling
2573 * the array.
2574 */
2575
2576 if (highest_bus > n_buses) {
2577 error_report("Too many IDE buses defined (%d > %d)",
2578 highest_bus, n_buses);
2579 exit(1);
2580 }
2581
2582 for (i = 0; i < n; i++) {
2583 hd[i] = drive_get_by_index(IF_IDE, i);
2584 }
2585 }
CRIS target port of Qemu