hw/ide/piix.c

   1 /*
   2  * QEMU IDE Emulation: PCI PIIX3/4 support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include <hw/hw.h>
  27 #include <hw/i386/pc.h>
  28 #include <hw/pci/pci.h>
  29 #include <hw/isa/isa.h>
  30 #include "sysemu/blockdev.h"
  31 #include "sysemu/sysemu.h"
  32 #include "sysemu/dma.h"
  33
  34 #include <hw/ide/pci.h>
  35
  36 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
  37 {
  38     BMDMAState *bm = opaque;
  39     uint32_t val;
  40
  41     if (size != 1) {
  42         return ((uint64_t)1 << (size * 8)) - 1;
  43     }
  44
  45     switch(addr & 3) {
  46     case 0:
  47         val = bm->cmd;
  48         break;
  49     case 2:
  50         val = bm->status;
  51         break;
  52     default:
  53         val = 0xff;
  54         break;
  55     }
  56 #ifdef DEBUG_IDE
  57     printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val);
  58 #endif
  59     return val;
  60 }
  61
  62 static void bmdma_write(void *opaque, hwaddr addr,
  63                         uint64_t val, unsigned size)
  64 {
  65     BMDMAState *bm = opaque;
  66
  67     if (size != 1) {
  68         return;
  69     }
  70
  71 #ifdef DEBUG_IDE
  72     printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val);
  73 #endif
  74     switch(addr & 3) {
  75     case 0:
  76         bmdma_cmd_writeb(bm, val);
  77         break;
  78     case 2:
  79         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
  80         break;
  81     }
  82 }
  83
  84 static const MemoryRegionOps piix_bmdma_ops = {
  85     .read = bmdma_read,
  86     .write = bmdma_write,
  87 };
  88
  89 static void bmdma_setup_bar(PCIIDEState *d)
  90 {
  91     int i;
  92
  93     memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
  94     for(i = 0;i < 2; i++) {
  95         BMDMAState *bm = &d->bmdma[i];
  96
  97         memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
  98                               "piix-bmdma", 4);
  99         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 100         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 101                               &bmdma_addr_ioport_ops, bm, "bmdma", 4);
 102         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 103     }
 104 }
 105
 106 static void piix3_reset(void *opaque)
 107 {
 108     PCIIDEState *d = opaque;
 109     PCIDevice *pd = PCI_DEVICE(d);
 110     uint8_t *pci_conf = pd->config;
 111     int i;
 112
 113     for (i = 0; i < 2; i++) {
 114         ide_bus_reset(&d->bus[i]);
 115     }
 116
 117     /* TODO: this is the default. do not override. */
 118     pci_conf[PCI_COMMAND] = 0x00;
 119     /* TODO: this is the default. do not override. */
 120     pci_conf[PCI_COMMAND + 1] = 0x00;
 121     /* TODO: use pci_set_word */
 122     pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
 123     pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
 124     pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
 125 }
 126
 127 static void pci_piix_init_ports(PCIIDEState *d) {
 128     static const struct {
 129         int iobase;
 130         int iobase2;
 131         int isairq;
 132     } port_info[] = {
 133         {0x1f0, 0x3f6, 14},
 134         {0x170, 0x376, 15},
 135     };
 136     int i;
 137
 138     for (i = 0; i < 2; i++) {
 139         ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
 140         ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
 141                         port_info[i].iobase2);
 142         ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
 143
 144         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 145         d->bmdma[i].bus = &d->bus[i];
 146         qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
 147                                          &d->bmdma[i].dma);
 148     }
 149 }
 150
 151 static int pci_piix_ide_initfn(PCIDevice *dev)
 152 {
 153     PCIIDEState *d = PCI_IDE(dev);
 154     uint8_t *pci_conf = dev->config;
 155
 156     pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
 157
 158     qemu_register_reset(piix3_reset, d);
 159
 160     bmdma_setup_bar(d);
 161     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 162
 163     vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
 164
 165     pci_piix_init_ports(d);
 166
 167     return 0;
 168 }
 169
 170 int pci_piix3_xen_ide_unplug(DeviceState *dev)
 171 {
 172     PCIIDEState *pci_ide;
 173     DriveInfo *di;
 174     int i = 0;
 175
 176     pci_ide = PCI_IDE(dev);
 177
 178     for (; i < 3; i++) {
 179         di = drive_get_by_index(IF_IDE, i);
 180         if (di != NULL && !di->media_cd) {
 181             DeviceState *ds = bdrv_get_attached_dev(di->bdrv);
 182             if (ds) {
 183                 bdrv_detach_dev(di->bdrv, ds);
 184             }
 185             bdrv_close(di->bdrv);
 186             pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
 187             drive_del(di);
 188         }
 189     }
 190     qdev_reset_all(DEVICE(dev));
 191     return 0;
 192 }
 193
 194 PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
 195 {
 196     PCIDevice *dev;
 197
 198     dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
 199     pci_ide_create_devs(dev, hd_table);
 200     return dev;
 201 }
 202
 203 static void pci_piix_ide_exitfn(PCIDevice *dev)
 204 {
 205     PCIIDEState *d = PCI_IDE(dev);
 206     unsigned i;
 207
 208     for (i = 0; i < 2; ++i) {
 209         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 210         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 211     }
 212 }
 213
 214 /* hd_table must contain 4 block drivers */
 215 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
 216 PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
 217 {
 218     PCIDevice *dev;
 219
 220     dev = pci_create_simple(bus, devfn, "piix3-ide");
 221     pci_ide_create_devs(dev, hd_table);
 222     return dev;
 223 }
 224
 225 /* hd_table must contain 4 block drivers */
 226 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
 227 PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
 228 {
 229     PCIDevice *dev;
 230
 231     dev = pci_create_simple(bus, devfn, "piix4-ide");
 232     pci_ide_create_devs(dev, hd_table);
 233     return dev;
 234 }
 235
 236 static void piix3_ide_class_init(ObjectClass *klass, void *data)
 237 {
 238     DeviceClass *dc = DEVICE_CLASS(klass);
 239     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 240
 241     k->init = pci_piix_ide_initfn;
 242     k->exit = pci_piix_ide_exitfn;
 243     k->vendor_id = PCI_VENDOR_ID_INTEL;
 244     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
 245     k->class_id = PCI_CLASS_STORAGE_IDE;
 246     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 247     dc->hotpluggable = false;
 248 }
 249
 250 static const TypeInfo piix3_ide_info = {
 251     .name          = "piix3-ide",
 252     .parent        = TYPE_PCI_IDE,
 253     .class_init    = piix3_ide_class_init,
 254 };
 255
 256 static void piix3_ide_xen_class_init(ObjectClass *klass, void *data)
 257 {
 258     DeviceClass *dc = DEVICE_CLASS(klass);
 259     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 260
 261     k->init = pci_piix_ide_initfn;
 262     k->vendor_id = PCI_VENDOR_ID_INTEL;
 263     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
 264     k->class_id = PCI_CLASS_STORAGE_IDE;
 265     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 266 }
 267
 268 static const TypeInfo piix3_ide_xen_info = {
 269     .name          = "piix3-ide-xen",
 270     .parent        = TYPE_PCI_IDE,
 271     .class_init    = piix3_ide_xen_class_init,
 272 };
 273
 274 static void piix4_ide_class_init(ObjectClass *klass, void *data)
 275 {
 276     DeviceClass *dc = DEVICE_CLASS(klass);
 277     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 278
 279     k->init = pci_piix_ide_initfn;
 280     k->exit = pci_piix_ide_exitfn;
 281     k->vendor_id = PCI_VENDOR_ID_INTEL;
 282     k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
 283     k->class_id = PCI_CLASS_STORAGE_IDE;
 284     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 285     dc->hotpluggable = false;
 286 }
 287
 288 static const TypeInfo piix4_ide_info = {
 289     .name          = "piix4-ide",
 290     .parent        = TYPE_PCI_IDE,
 291     .class_init    = piix4_ide_class_init,
 292 };
 293
 294 static void piix_ide_register_types(void)
 295 {
 296     type_register_static(&piix3_ide_info);
 297     type_register_static(&piix3_ide_xen_info);
 298     type_register_static(&piix4_ide_info);
 299 }
 300
 301 type_init(piix_ide_register_types)