tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "qemu/bitops.h"
  30 #include "tcg-target.h"
  31
  32 #define CPU_TEMP_BUF_NLONGS 128
  33
  34 /* Default target word size to pointer size.  */
  35 #ifndef TCG_TARGET_REG_BITS
  36 # if UINTPTR_MAX == UINT32_MAX
  37 #  define TCG_TARGET_REG_BITS 32
  38 # elif UINTPTR_MAX == UINT64_MAX
  39 #  define TCG_TARGET_REG_BITS 64
  40 # else
  41 #  error Unknown pointer size for tcg target
  42 # endif
  43 #endif
  44
  45 #if TCG_TARGET_REG_BITS == 32
  46 typedef int32_t tcg_target_long;
  47 typedef uint32_t tcg_target_ulong;
  48 #define TCG_PRIlx PRIx32
  49 #define TCG_PRIld PRId32
  50 #elif TCG_TARGET_REG_BITS == 64
  51 typedef int64_t tcg_target_long;
  52 typedef uint64_t tcg_target_ulong;
  53 #define TCG_PRIlx PRIx64
  54 #define TCG_PRIld PRId64
  55 #else
  56 #error unsupported
  57 #endif
  58
  59 #if TCG_TARGET_NB_REGS <= 32
  60 typedef uint32_t TCGRegSet;
  61 #elif TCG_TARGET_NB_REGS <= 64
  62 typedef uint64_t TCGRegSet;
  63 #else
  64 #error unsupported
  65 #endif
  66
  67 #if TCG_TARGET_REG_BITS == 32
  68 /* Turn some undef macros into false macros.  */
  69 #define TCG_TARGET_HAS_extrl_i64_i32    0
  70 #define TCG_TARGET_HAS_extrh_i64_i32    0
  71 #define TCG_TARGET_HAS_div_i64          0
  72 #define TCG_TARGET_HAS_rem_i64          0
  73 #define TCG_TARGET_HAS_div2_i64         0
  74 #define TCG_TARGET_HAS_rot_i64          0
  75 #define TCG_TARGET_HAS_ext8s_i64        0
  76 #define TCG_TARGET_HAS_ext16s_i64       0
  77 #define TCG_TARGET_HAS_ext32s_i64       0
  78 #define TCG_TARGET_HAS_ext8u_i64        0
  79 #define TCG_TARGET_HAS_ext16u_i64       0
  80 #define TCG_TARGET_HAS_ext32u_i64       0
  81 #define TCG_TARGET_HAS_bswap16_i64      0
  82 #define TCG_TARGET_HAS_bswap32_i64      0
  83 #define TCG_TARGET_HAS_bswap64_i64      0
  84 #define TCG_TARGET_HAS_neg_i64          0
  85 #define TCG_TARGET_HAS_not_i64          0
  86 #define TCG_TARGET_HAS_andc_i64         0
  87 #define TCG_TARGET_HAS_orc_i64          0
  88 #define TCG_TARGET_HAS_eqv_i64          0
  89 #define TCG_TARGET_HAS_nand_i64         0
  90 #define TCG_TARGET_HAS_nor_i64          0
  91 #define TCG_TARGET_HAS_deposit_i64      0
  92 #define TCG_TARGET_HAS_movcond_i64      0
  93 #define TCG_TARGET_HAS_add2_i64         0
  94 #define TCG_TARGET_HAS_sub2_i64         0
  95 #define TCG_TARGET_HAS_mulu2_i64        0
  96 #define TCG_TARGET_HAS_muls2_i64        0
  97 #define TCG_TARGET_HAS_muluh_i64        0
  98 #define TCG_TARGET_HAS_mulsh_i64        0
  99 /* Turn some undef macros into true macros.  */
 100 #define TCG_TARGET_HAS_add2_i32         1
 101 #define TCG_TARGET_HAS_sub2_i32         1
 102 #endif
 103
 104 #ifndef TCG_TARGET_deposit_i32_valid
 105 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 106 #endif
 107 #ifndef TCG_TARGET_deposit_i64_valid
 108 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 109 #endif
 110
 111 /* Only one of DIV or DIV2 should be defined.  */
 112 #if defined(TCG_TARGET_HAS_div_i32)
 113 #define TCG_TARGET_HAS_div2_i32         0
 114 #elif defined(TCG_TARGET_HAS_div2_i32)
 115 #define TCG_TARGET_HAS_div_i32          0
 116 #define TCG_TARGET_HAS_rem_i32          0
 117 #endif
 118 #if defined(TCG_TARGET_HAS_div_i64)
 119 #define TCG_TARGET_HAS_div2_i64         0
 120 #elif defined(TCG_TARGET_HAS_div2_i64)
 121 #define TCG_TARGET_HAS_div_i64          0
 122 #define TCG_TARGET_HAS_rem_i64          0
 123 #endif
 124
 125 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 126 #if TCG_TARGET_REG_BITS == 32 \
 127     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 128          || defined(TCG_TARGET_HAS_muluh_i32))
 129 # error "Missing unsigned widening multiply"
 130 #endif
 131
 132 #ifndef TARGET_INSN_START_EXTRA_WORDS
 133 # define TARGET_INSN_START_WORDS 1
 134 #else
 135 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 136 #endif
 137
 138 typedef enum TCGOpcode {
 139 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 140 #include "tcg-opc.h"
 141 #undef DEF
 142     NB_OPS,
 143 } TCGOpcode;
 144
 145 #define tcg_regset_clear(d) (d) = 0
 146 #define tcg_regset_set(d, s) (d) = (s)
 147 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
 148 #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
 149 #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
 150 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
 151 #define tcg_regset_or(d, a, b) (d) = (a) | (b)
 152 #define tcg_regset_and(d, a, b) (d) = (a) & (b)
 153 #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b)
 154 #define tcg_regset_not(d, a) (d) = ~(a)
 155
 156 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 157 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 158 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 159 typedef uint8_t tcg_insn_unit;
 160 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 161 typedef uint16_t tcg_insn_unit;
 162 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 163 typedef uint32_t tcg_insn_unit;
 164 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 165 typedef uint64_t tcg_insn_unit;
 166 #else
 167 /* The port better have done this.  */
 168 #endif
 169
 170
 171 typedef struct TCGRelocation {
 172     struct TCGRelocation *next;
 173     int type;
 174     tcg_insn_unit *ptr;
 175     intptr_t addend;
 176 } TCGRelocation;
 177
 178 typedef struct TCGLabel {
 179     unsigned has_value : 1;
 180     unsigned id : 31;
 181     union {
 182         uintptr_t value;
 183         tcg_insn_unit *value_ptr;
 184         TCGRelocation *first_reloc;
 185     } u;
 186 } TCGLabel;
 187
 188 typedef struct TCGPool {
 189     struct TCGPool *next;
 190     int size;
 191     uint8_t data[0] __attribute__ ((aligned));
 192 } TCGPool;
 193
 194 #define TCG_POOL_CHUNK_SIZE 32768
 195
 196 #define TCG_MAX_TEMPS 512
 197 #define TCG_MAX_INSNS 512
 198
 199 /* when the size of the arguments of a called function is smaller than
 200    this value, they are statically allocated in the TB stack frame */
 201 #define TCG_STATIC_CALL_ARGS_SIZE 128
 202
 203 typedef enum TCGType {
 204     TCG_TYPE_I32,
 205     TCG_TYPE_I64,
 206     TCG_TYPE_COUNT, /* number of different types */
 207
 208     /* An alias for the size of the host register.  */
 209 #if TCG_TARGET_REG_BITS == 32
 210     TCG_TYPE_REG = TCG_TYPE_I32,
 211 #else
 212     TCG_TYPE_REG = TCG_TYPE_I64,
 213 #endif
 214
 215     /* An alias for the size of the native pointer.  */
 216 #if UINTPTR_MAX == UINT32_MAX
 217     TCG_TYPE_PTR = TCG_TYPE_I32,
 218 #else
 219     TCG_TYPE_PTR = TCG_TYPE_I64,
 220 #endif
 221
 222     /* An alias for the size of the target "long", aka register.  */
 223 #if TARGET_LONG_BITS == 64
 224     TCG_TYPE_TL = TCG_TYPE_I64,
 225 #else
 226     TCG_TYPE_TL = TCG_TYPE_I32,
 227 #endif
 228 } TCGType;
 229
 230 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 231 typedef enum TCGMemOp {
 232     MO_8     = 0,
 233     MO_16    = 1,
 234     MO_32    = 2,
 235     MO_64    = 3,
 236     MO_SIZE  = 3,   /* Mask for the above.  */
 237
 238     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 239
 240     MO_BSWAP = 8,   /* Host reverse endian.  */
 241 #ifdef HOST_WORDS_BIGENDIAN
 242     MO_LE    = MO_BSWAP,
 243     MO_BE    = 0,
 244 #else
 245     MO_LE    = 0,
 246     MO_BE    = MO_BSWAP,
 247 #endif
 248 #ifdef TARGET_WORDS_BIGENDIAN
 249     MO_TE    = MO_BE,
 250 #else
 251     MO_TE    = MO_LE,
 252 #endif
 253
 254     /* MO_UNALN accesses are never checked for alignment.
 255        MO_ALIGN accesses will result in a call to the CPU's
 256        do_unaligned_access hook if the guest address is not aligned.
 257        The default depends on whether the target CPU defines ALIGNED_ONLY.  */
 258     MO_AMASK = 16,
 259 #ifdef ALIGNED_ONLY
 260     MO_ALIGN = 0,
 261     MO_UNALN = MO_AMASK,
 262 #else
 263     MO_ALIGN = MO_AMASK,
 264     MO_UNALN = 0,
 265 #endif
 266
 267     /* Combinations of the above, for ease of use.  */
 268     MO_UB    = MO_8,
 269     MO_UW    = MO_16,
 270     MO_UL    = MO_32,
 271     MO_SB    = MO_SIGN | MO_8,
 272     MO_SW    = MO_SIGN | MO_16,
 273     MO_SL    = MO_SIGN | MO_32,
 274     MO_Q     = MO_64,
 275
 276     MO_LEUW  = MO_LE | MO_UW,
 277     MO_LEUL  = MO_LE | MO_UL,
 278     MO_LESW  = MO_LE | MO_SW,
 279     MO_LESL  = MO_LE | MO_SL,
 280     MO_LEQ   = MO_LE | MO_Q,
 281
 282     MO_BEUW  = MO_BE | MO_UW,
 283     MO_BEUL  = MO_BE | MO_UL,
 284     MO_BESW  = MO_BE | MO_SW,
 285     MO_BESL  = MO_BE | MO_SL,
 286     MO_BEQ   = MO_BE | MO_Q,
 287
 288     MO_TEUW  = MO_TE | MO_UW,
 289     MO_TEUL  = MO_TE | MO_UL,
 290     MO_TESW  = MO_TE | MO_SW,
 291     MO_TESL  = MO_TE | MO_SL,
 292     MO_TEQ   = MO_TE | MO_Q,
 293
 294     MO_SSIZE = MO_SIZE | MO_SIGN,
 295 } TCGMemOp;
 296
 297 typedef tcg_target_ulong TCGArg;
 298
 299 /* Define a type and accessor macros for variables.  Using pointer types
 300    is nice because it gives some level of type safely.  Converting to and
 301    from intptr_t rather than int reduces the number of sign-extension
 302    instructions that get implied on 64-bit hosts.  Users of tcg_gen_* don't
 303    need to know about any of this, and should treat TCGv as an opaque type.
 304    In addition we do typechecking for different types of variables.  TCGv_i32
 305    and TCGv_i64 are 32/64-bit variables respectively.  TCGv and TCGv_ptr
 306    are aliases for target_ulong and host pointer sized values respectively.  */
 307
 308 typedef struct TCGv_i32_d *TCGv_i32;
 309 typedef struct TCGv_i64_d *TCGv_i64;
 310 typedef struct TCGv_ptr_d *TCGv_ptr;
 311 typedef TCGv_ptr TCGv_env;
 312 #if TARGET_LONG_BITS == 32
 313 #define TCGv TCGv_i32
 314 #elif TARGET_LONG_BITS == 64
 315 #define TCGv TCGv_i64
 316 #else
 317 #error Unhandled TARGET_LONG_BITS value
 318 #endif
 319
 320 static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i)
 321 {
 322     return (TCGv_i32)i;
 323 }
 324
 325 static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i)
 326 {
 327     return (TCGv_i64)i;
 328 }
 329
 330 static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i)
 331 {
 332     return (TCGv_ptr)i;
 333 }
 334
 335 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t)
 336 {
 337     return (intptr_t)t;
 338 }
 339
 340 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t)
 341 {
 342     return (intptr_t)t;
 343 }
 344
 345 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
 346 {
 347     return (intptr_t)t;
 348 }
 349
 350 #if TCG_TARGET_REG_BITS == 32
 351 #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
 352 #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
 353 #endif
 354
 355 #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
 356 #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
 357 #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
 358
 359 /* Dummy definition to avoid compiler warnings.  */
 360 #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
 361 #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
 362 #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
 363
 364 #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
 365 #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
 366 #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
 367
 368 /* call flags */
 369 /* Helper does not read globals (either directly or through an exception). It
 370    implies TCG_CALL_NO_WRITE_GLOBALS. */
 371 #define TCG_CALL_NO_READ_GLOBALS    0x0010
 372 /* Helper does not write globals */
 373 #define TCG_CALL_NO_WRITE_GLOBALS   0x0020
 374 /* Helper can be safely suppressed if the return value is not used. */
 375 #define TCG_CALL_NO_SIDE_EFFECTS    0x0040
 376
 377 /* convenience version of most used call flags */
 378 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 379 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 380 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 381 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 382 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 383
 384 /* used to align parameters */
 385 #define TCG_CALL_DUMMY_TCGV     MAKE_TCGV_I32(-1)
 386 #define TCG_CALL_DUMMY_ARG      ((TCGArg)(-1))
 387
 388 /* Conditions.  Note that these are laid out for easy manipulation by
 389    the functions below:
 390      bit 0 is used for inverting;
 391      bit 1 is signed,
 392      bit 2 is unsigned,
 393      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 394 typedef enum {
 395     /* non-signed */
 396     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 397     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 398     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 399     TCG_COND_NE     = 8 | 0 | 0 | 1,
 400     /* signed */
 401     TCG_COND_LT     = 0 | 0 | 2 | 0,
 402     TCG_COND_GE     = 0 | 0 | 2 | 1,
 403     TCG_COND_LE     = 8 | 0 | 2 | 0,
 404     TCG_COND_GT     = 8 | 0 | 2 | 1,
 405     /* unsigned */
 406     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 407     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 408     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 409     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 410 } TCGCond;
 411
 412 /* Invert the sense of the comparison.  */
 413 static inline TCGCond tcg_invert_cond(TCGCond c)
 414 {
 415     return (TCGCond)(c ^ 1);
 416 }
 417
 418 /* Swap the operands in a comparison.  */
 419 static inline TCGCond tcg_swap_cond(TCGCond c)
 420 {
 421     return c & 6 ? (TCGCond)(c ^ 9) : c;
 422 }
 423
 424 /* Create an "unsigned" version of a "signed" comparison.  */
 425 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 426 {
 427     return c & 2 ? (TCGCond)(c ^ 6) : c;
 428 }
 429
 430 /* Must a comparison be considered unsigned?  */
 431 static inline bool is_unsigned_cond(TCGCond c)
 432 {
 433     return (c & 4) != 0;
 434 }
 435
 436 /* Create a "high" version of a double-word comparison.
 437    This removes equality from a LTE or GTE comparison.  */
 438 static inline TCGCond tcg_high_cond(TCGCond c)
 439 {
 440     switch (c) {
 441     case TCG_COND_GE:
 442     case TCG_COND_LE:
 443     case TCG_COND_GEU:
 444     case TCG_COND_LEU:
 445         return (TCGCond)(c ^ 8);
 446     default:
 447         return c;
 448     }
 449 }
 450
 451 typedef enum TCGTempVal {
 452     TEMP_VAL_DEAD,
 453     TEMP_VAL_REG,
 454     TEMP_VAL_MEM,
 455     TEMP_VAL_CONST,
 456 } TCGTempVal;
 457
 458 typedef struct TCGTemp {
 459     TCGReg reg:8;
 460     TCGTempVal val_type:8;
 461     TCGType base_type:8;
 462     TCGType type:8;
 463     unsigned int fixed_reg:1;
 464     unsigned int indirect_reg:1;
 465     unsigned int indirect_base:1;
 466     unsigned int mem_coherent:1;
 467     unsigned int mem_allocated:1;
 468     unsigned int temp_local:1; /* If true, the temp is saved across
 469                                   basic blocks. Otherwise, it is not
 470                                   preserved across basic blocks. */
 471     unsigned int temp_allocated:1; /* never used for code gen */
 472
 473     tcg_target_long val;
 474     struct TCGTemp *mem_base;
 475     intptr_t mem_offset;
 476     const char *name;
 477 } TCGTemp;
 478
 479 typedef struct TCGContext TCGContext;
 480
 481 typedef struct TCGTempSet {
 482     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 483 } TCGTempSet;
 484
 485 typedef struct TCGOp {
 486     TCGOpcode opc   : 8;
 487
 488     /* The number of out and in parameter for a call.  */
 489     unsigned callo  : 2;
 490     unsigned calli  : 6;
 491
 492     /* Index of the arguments for this op, or -1 for zero-operand ops.  */
 493     signed args     : 16;
 494
 495     /* Index of the prex/next op, or -1 for the end of the list.  */
 496     signed prev     : 16;
 497     signed next     : 16;
 498 } TCGOp;
 499
 500 QEMU_BUILD_BUG_ON(NB_OPS > 0xff);
 501 QEMU_BUILD_BUG_ON(OPC_BUF_SIZE >= 0x7fff);
 502 QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE >= 0x7fff);
 503
 504 struct TCGContext {
 505     uint8_t *pool_cur, *pool_end;
 506     TCGPool *pool_first, *pool_current, *pool_first_large;
 507     int nb_labels;
 508     int nb_globals;
 509     int nb_temps;
 510
 511     /* goto_tb support */
 512     tcg_insn_unit *code_buf;
 513     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 514     uint16_t *tb_jmp_insn_offset; /* tb->jmp_insn_offset if USE_DIRECT_JUMP */
 515     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_JUMP */
 516
 517     /* liveness analysis */
 518     uint16_t *op_dead_args; /* for each operation, each bit tells if the
 519                                corresponding argument is dead */
 520     uint8_t *op_sync_args;  /* for each operation, each bit tells if the
 521                                corresponding output argument needs to be
 522                                sync to memory. */
 523
 524     TCGRegSet reserved_regs;
 525     intptr_t current_frame_offset;
 526     intptr_t frame_start;
 527     intptr_t frame_end;
 528     TCGTemp *frame_temp;
 529
 530     tcg_insn_unit *code_ptr;
 531
 532     GHashTable *helpers;
 533
 534 #ifdef CONFIG_PROFILER
 535     /* profiling info */
 536     int64_t tb_count1;
 537     int64_t tb_count;
 538     int64_t op_count; /* total insn count */
 539     int op_count_max; /* max insn per TB */
 540     int64_t temp_count;
 541     int temp_count_max;
 542     int64_t del_op_count;
 543     int64_t code_in_len;
 544     int64_t code_out_len;
 545     int64_t search_out_len;
 546     int64_t interm_time;
 547     int64_t code_time;
 548     int64_t la_time;
 549     int64_t opt_time;
 550     int64_t restore_count;
 551     int64_t restore_time;
 552 #endif
 553
 554 #ifdef CONFIG_DEBUG_TCG
 555     int temps_in_use;
 556     int goto_tb_issue_mask;
 557 #endif
 558
 559     int gen_first_op_idx;
 560     int gen_last_op_idx;
 561     int gen_next_op_idx;
 562     int gen_next_parm_idx;
 563
 564     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 565        here, because there's too much arithmetic throughout that relies
 566        on addition and subtraction working on bytes.  Rely on the GCC
 567        extension that allows arithmetic on void*.  */
 568     int code_gen_max_blocks;
 569     void *code_gen_prologue;
 570     void *code_gen_buffer;
 571     size_t code_gen_buffer_size;
 572     void *code_gen_ptr;
 573
 574     /* Threshold to flush the translated code buffer.  */
 575     void *code_gen_highwater;
 576
 577     TBContext tb_ctx;
 578
 579     /* The TCGBackendData structure is private to tcg-target.inc.c.  */
 580     struct TCGBackendData *be;
 581
 582     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 583     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 584
 585     /* Tells which temporary holds a given register.
 586        It does not take into account fixed registers */
 587     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 588
 589     TCGOp gen_op_buf[OPC_BUF_SIZE];
 590     TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
 591
 592     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 593     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 594 };
 595
 596 extern TCGContext tcg_ctx;
 597
 598 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
 599 {
 600     int op_argi = tcg_ctx.gen_op_buf[op_idx].args;
 601     tcg_ctx.gen_opparam_buf[op_argi + arg] = v;
 602 }
 603
 604 /* The number of opcodes emitted so far.  */
 605 static inline int tcg_op_buf_count(void)
 606 {
 607     return tcg_ctx.gen_next_op_idx;
 608 }
 609
 610 /* Test for whether to terminate the TB for using too many opcodes.  */
 611 static inline bool tcg_op_buf_full(void)
 612 {
 613     return tcg_op_buf_count() >= OPC_MAX_SIZE;
 614 }
 615
 616 /* pool based memory allocation */
 617
 618 void *tcg_malloc_internal(TCGContext *s, int size);
 619 void tcg_pool_reset(TCGContext *s);
 620 void tcg_pool_delete(TCGContext *s);
 621
 622 void tb_lock(void);
 623 void tb_unlock(void);
 624 void tb_lock_reset(void);
 625
 626 static inline void *tcg_malloc(int size)
 627 {
 628     TCGContext *s = &tcg_ctx;
 629     uint8_t *ptr, *ptr_end;
 630     size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1);
 631     ptr = s->pool_cur;
 632     ptr_end = ptr + size;
 633     if (unlikely(ptr_end > s->pool_end)) {
 634         return tcg_malloc_internal(&tcg_ctx, size);
 635     } else {
 636         s->pool_cur = ptr_end;
 637         return ptr;
 638     }
 639 }
 640
 641 void tcg_context_init(TCGContext *s);
 642 void tcg_prologue_init(TCGContext *s);
 643 void tcg_func_start(TCGContext *s);
 644
 645 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 646
 647 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 648
 649 int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *);
 650
 651 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name);
 652 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name);
 653
 654 TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
 655 TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
 656
 657 void tcg_temp_free_i32(TCGv_i32 arg);
 658 void tcg_temp_free_i64(TCGv_i64 arg);
 659
 660 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 661                                               const char *name)
 662 {
 663     int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 664     return MAKE_TCGV_I32(idx);
 665 }
 666
 667 static inline TCGv_i32 tcg_temp_new_i32(void)
 668 {
 669     return tcg_temp_new_internal_i32(0);
 670 }
 671
 672 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 673 {
 674     return tcg_temp_new_internal_i32(1);
 675 }
 676
 677 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 678                                               const char *name)
 679 {
 680     int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 681     return MAKE_TCGV_I64(idx);
 682 }
 683
 684 static inline TCGv_i64 tcg_temp_new_i64(void)
 685 {
 686     return tcg_temp_new_internal_i64(0);
 687 }
 688
 689 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 690 {
 691     return tcg_temp_new_internal_i64(1);
 692 }
 693
 694 #if defined(CONFIG_DEBUG_TCG)
 695 /* If you call tcg_clear_temp_count() at the start of a section of
 696  * code which is not supposed to leak any TCG temporaries, then
 697  * calling tcg_check_temp_count() at the end of the section will
 698  * return 1 if the section did in fact leak a temporary.
 699  */
 700 void tcg_clear_temp_count(void);
 701 int tcg_check_temp_count(void);
 702 #else
 703 #define tcg_clear_temp_count() do { } while (0)
 704 #define tcg_check_temp_count() 0
 705 #endif
 706
 707 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
 708 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
 709
 710 #define TCG_CT_ALIAS  0x80
 711 #define TCG_CT_IALIAS 0x40
 712 #define TCG_CT_REG    0x01
 713 #define TCG_CT_CONST  0x02 /* any constant of register size */
 714
 715 typedef struct TCGArgConstraint {
 716     uint16_t ct;
 717     uint8_t alias_index;
 718     union {
 719         TCGRegSet regs;
 720     } u;
 721 } TCGArgConstraint;
 722
 723 #define TCG_MAX_OP_ARGS 16
 724
 725 /* Bits for TCGOpDef->flags, 8 bits available.  */
 726 enum {
 727     /* Instruction defines the end of a basic block.  */
 728     TCG_OPF_BB_END       = 0x01,
 729     /* Instruction clobbers call registers and potentially update globals.  */
 730     TCG_OPF_CALL_CLOBBER = 0x02,
 731     /* Instruction has side effects: it cannot be removed if its outputs
 732        are not used, and might trigger exceptions.  */
 733     TCG_OPF_SIDE_EFFECTS = 0x04,
 734     /* Instruction operands are 64-bits (otherwise 32-bits).  */
 735     TCG_OPF_64BIT        = 0x08,
 736     /* Instruction is optional and not implemented by the host, or insn
 737        is generic and should not be implemened by the host.  */
 738     TCG_OPF_NOT_PRESENT  = 0x10,
 739 };
 740
 741 typedef struct TCGOpDef {
 742     const char *name;
 743     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
 744     uint8_t flags;
 745     TCGArgConstraint *args_ct;
 746     int *sorted_args;
 747 #if defined(CONFIG_DEBUG_TCG)
 748     int used;
 749 #endif
 750 } TCGOpDef;
 751
 752 extern TCGOpDef tcg_op_defs[];
 753 extern const size_t tcg_op_defs_max;
 754
 755 typedef struct TCGTargetOpDef {
 756     TCGOpcode op;
 757     const char *args_ct_str[TCG_MAX_OP_ARGS];
 758 } TCGTargetOpDef;
 759
 760 #define tcg_abort() \
 761 do {\
 762     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
 763     abort();\
 764 } while (0)
 765
 766 #ifdef CONFIG_DEBUG_TCG
 767 # define tcg_debug_assert(X) do { assert(X); } while (0)
 768 #elif QEMU_GNUC_PREREQ(4, 5)
 769 # define tcg_debug_assert(X) \
 770     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 771 #else
 772 # define tcg_debug_assert(X) do { (void)(X); } while (0)
 773 #endif
 774
 775 void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs);
 776
 777 #if UINTPTR_MAX == UINT32_MAX
 778 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
 779 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
 780
 781 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
 782 #define tcg_global_reg_new_ptr(R, N) \
 783     TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
 784 #define tcg_global_mem_new_ptr(R, O, N) \
 785     TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
 786 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
 787 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
 788 #else
 789 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
 790 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
 791
 792 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
 793 #define tcg_global_reg_new_ptr(R, N) \
 794     TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
 795 #define tcg_global_mem_new_ptr(R, O, N) \
 796     TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
 797 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
 798 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
 799 #endif
 800
 801 void tcg_gen_callN(TCGContext *s, void *func,
 802                    TCGArg ret, int nargs, TCGArg *args);
 803
 804 void tcg_op_remove(TCGContext *s, TCGOp *op);
 805 void tcg_optimize(TCGContext *s);
 806
 807 /* only used for debugging purposes */
 808 void tcg_dump_ops(TCGContext *s);
 809
 810 void dump_ops(const uint16_t *opc_buf, const TCGArg *opparam_buf);
 811 TCGv_i32 tcg_const_i32(int32_t val);
 812 TCGv_i64 tcg_const_i64(int64_t val);
 813 TCGv_i32 tcg_const_local_i32(int32_t val);
 814 TCGv_i64 tcg_const_local_i64(int64_t val);
 815
 816 TCGLabel *gen_new_label(void);
 817
 818 /**
 819  * label_arg
 820  * @l: label
 821  *
 822  * Encode a label for storage in the TCG opcode stream.
 823  */
 824
 825 static inline TCGArg label_arg(TCGLabel *l)
 826 {
 827     return (uintptr_t)l;
 828 }
 829
 830 /**
 831  * arg_label
 832  * @i: value
 833  *
 834  * The opposite of label_arg.  Retrieve a label from the
 835  * encoding of the TCG opcode stream.
 836  */
 837
 838 static inline TCGLabel *arg_label(TCGArg i)
 839 {
 840     return (TCGLabel *)(uintptr_t)i;
 841 }
 842
 843 /**
 844  * tcg_ptr_byte_diff
 845  * @a, @b: addresses to be differenced
 846  *
 847  * There are many places within the TCG backends where we need a byte
 848  * difference between two pointers.  While this can be accomplished
 849  * with local casting, it's easy to get wrong -- especially if one is
 850  * concerned with the signedness of the result.
 851  *
 852  * This version relies on GCC's void pointer arithmetic to get the
 853  * correct result.
 854  */
 855
 856 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
 857 {
 858     return a - b;
 859 }
 860
 861 /**
 862  * tcg_pcrel_diff
 863  * @s: the tcg context
 864  * @target: address of the target
 865  *
 866  * Produce a pc-relative difference, from the current code_ptr
 867  * to the destination address.
 868  */
 869
 870 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
 871 {
 872     return tcg_ptr_byte_diff(target, s->code_ptr);
 873 }
 874
 875 /**
 876  * tcg_current_code_size
 877  * @s: the tcg context
 878  *
 879  * Compute the current code size within the translation block.
 880  * This is used to fill in qemu's data structures for goto_tb.
 881  */
 882
 883 static inline size_t tcg_current_code_size(TCGContext *s)
 884 {
 885     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
 886 }
 887
 888 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
 889 typedef uint32_t TCGMemOpIdx;
 890
 891 /**
 892  * make_memop_idx
 893  * @op: memory operation
 894  * @idx: mmu index
 895  *
 896  * Encode these values into a single parameter.
 897  */
 898 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
 899 {
 900     tcg_debug_assert(idx <= 15);
 901     return (op << 4) | idx;
 902 }
 903
 904 /**
 905  * get_memop
 906  * @oi: combined op/idx parameter
 907  *
 908  * Extract the memory operation from the combined value.
 909  */
 910 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
 911 {
 912     return oi >> 4;
 913 }
 914
 915 /**
 916  * get_mmuidx
 917  * @oi: combined op/idx parameter
 918  *
 919  * Extract the mmu index from the combined value.
 920  */
 921 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
 922 {
 923     return oi & 15;
 924 }
 925
 926 /**
 927  * tcg_qemu_tb_exec:
 928  * @env: pointer to CPUArchState for the CPU
 929  * @tb_ptr: address of generated code for the TB to execute
 930  *
 931  * Start executing code from a given translation block.
 932  * Where translation blocks have been linked, execution
 933  * may proceed from the given TB into successive ones.
 934  * Control eventually returns only when some action is needed
 935  * from the top-level loop: either control must pass to a TB
 936  * which has not yet been directly linked, or an asynchronous
 937  * event such as an interrupt needs handling.
 938  *
 939  * Return: The return value is the value passed to the corresponding
 940  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
 941  * The value is either zero or a 4-byte aligned pointer to that TB combined
 942  * with additional information in its two least significant bits. The
 943  * additional information is encoded as follows:
 944  *  0, 1: the link between this TB and the next is via the specified
 945  *        TB index (0 or 1). That is, we left the TB via (the equivalent
 946  *        of) "goto_tb <index>". The main loop uses this to determine
 947  *        how to link the TB just executed to the next.
 948  *  2:    we are using instruction counting code generation, and we
 949  *        did not start executing this TB because the instruction counter
 950  *        would hit zero midway through it. In this case the pointer
 951  *        returned is the TB we were about to execute, and the caller must
 952  *        arrange to execute the remaining count of instructions.
 953  *  3:    we stopped because the CPU's exit_request flag was set
 954  *        (usually meaning that there is an interrupt that needs to be
 955  *        handled). The pointer returned is the TB we were about to execute
 956  *        when we noticed the pending exit request.
 957  *
 958  * If the bottom two bits indicate an exit-via-index then the CPU
 959  * state is correctly synchronised and ready for execution of the next
 960  * TB (and in particular the guest PC is the address to execute next).
 961  * Otherwise, we gave up on execution of this TB before it started, and
 962  * the caller must fix up the CPU state by calling the CPU's
 963  * synchronize_from_tb() method with the TB pointer we return (falling
 964  * back to calling the CPU's set_pc method with tb->pb if no
 965  * synchronize_from_tb() method exists).
 966  *
 967  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
 968  * to this default (which just calls the prologue.code emitted by
 969  * tcg_target_qemu_prologue()).
 970  */
 971 #define TB_EXIT_MASK 3
 972 #define TB_EXIT_IDX0 0
 973 #define TB_EXIT_IDX1 1
 974 #define TB_EXIT_ICOUNT_EXPIRED 2
 975 #define TB_EXIT_REQUESTED 3
 976
 977 #ifdef HAVE_TCG_QEMU_TB_EXEC
 978 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
 979 #else
 980 # define tcg_qemu_tb_exec(env, tb_ptr) \
 981     ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
 982 #endif
 983
 984 void tcg_register_jit(void *buf, size_t buf_size);
 985
 986 /*
 987  * Memory helpers that will be used by TCG generated code.
 988  */
 989 #ifdef CONFIG_SOFTMMU
 990 /* Value zero-extended to tcg register size.  */
 991 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
 992                                      TCGMemOpIdx oi, uintptr_t retaddr);
 993 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
 994                                     TCGMemOpIdx oi, uintptr_t retaddr);
 995 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
 996                                     TCGMemOpIdx oi, uintptr_t retaddr);
 997 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
 998                            TCGMemOpIdx oi, uintptr_t retaddr);
 999 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1000                                     TCGMemOpIdx oi, uintptr_t retaddr);
1001 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1002                                     TCGMemOpIdx oi, uintptr_t retaddr);
1003 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1004                            TCGMemOpIdx oi, uintptr_t retaddr);
1005
1006 /* Value sign-extended to tcg register size.  */
1007 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1008                                      TCGMemOpIdx oi, uintptr_t retaddr);
1009 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1010                                     TCGMemOpIdx oi, uintptr_t retaddr);
1011 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1012                                     TCGMemOpIdx oi, uintptr_t retaddr);
1013 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1014                                     TCGMemOpIdx oi, uintptr_t retaddr);
1015 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1016                                     TCGMemOpIdx oi, uintptr_t retaddr);
1017
1018 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1019                         TCGMemOpIdx oi, uintptr_t retaddr);
1020 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1021                        TCGMemOpIdx oi, uintptr_t retaddr);
1022 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1023                        TCGMemOpIdx oi, uintptr_t retaddr);
1024 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1025                        TCGMemOpIdx oi, uintptr_t retaddr);
1026 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1027                        TCGMemOpIdx oi, uintptr_t retaddr);
1028 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1029                        TCGMemOpIdx oi, uintptr_t retaddr);
1030 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1031                        TCGMemOpIdx oi, uintptr_t retaddr);
1032
1033 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1034                             TCGMemOpIdx oi, uintptr_t retaddr);
1035 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1036                             TCGMemOpIdx oi, uintptr_t retaddr);
1037 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1038                             TCGMemOpIdx oi, uintptr_t retaddr);
1039 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1040                             TCGMemOpIdx oi, uintptr_t retaddr);
1041 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1042                             TCGMemOpIdx oi, uintptr_t retaddr);
1043 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1044                             TCGMemOpIdx oi, uintptr_t retaddr);
1045 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1046                             TCGMemOpIdx oi, uintptr_t retaddr);
1047
1048 /* Temporary aliases until backends are converted.  */
1049 #ifdef TARGET_WORDS_BIGENDIAN
1050 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1051 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1052 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1053 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1054 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1055 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1056 # define helper_ret_stw_mmu   helper_be_stw_mmu
1057 # define helper_ret_stl_mmu   helper_be_stl_mmu
1058 # define helper_ret_stq_mmu   helper_be_stq_mmu
1059 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1060 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1061 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1062 #else
1063 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1064 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1065 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1066 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1067 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1068 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1069 # define helper_ret_stw_mmu   helper_le_stw_mmu
1070 # define helper_ret_stl_mmu   helper_le_stl_mmu
1071 # define helper_ret_stq_mmu   helper_le_stq_mmu
1072 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1073 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1074 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1075 #endif
1076
1077 #endif /* CONFIG_SOFTMMU */
1078
1079 #endif /* TCG_H */