2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25 #include "qemu/error-report.h"
26 #include "sysemu/kvm.h"
28 #include "mmu-hash64.h"
34 # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
36 # define LOG_SLB(...) do { } while (0)
40 * Used to indicate that a CPU has its hash page table (HPT) managed
41 * within the host kernel
43 #define MMU_HASH64_KVM_MANAGED_HPT ((void *)-1)
49 static ppc_slb_t
*slb_lookup(PowerPCCPU
*cpu
, target_ulong eaddr
)
51 CPUPPCState
*env
= &cpu
->env
;
52 uint64_t esid_256M
, esid_1T
;
55 LOG_SLB("%s: eaddr " TARGET_FMT_lx
"\n", __func__
, eaddr
);
57 esid_256M
= (eaddr
& SEGMENT_MASK_256M
) | SLB_ESID_V
;
58 esid_1T
= (eaddr
& SEGMENT_MASK_1T
) | SLB_ESID_V
;
60 for (n
= 0; n
< env
->slb_nr
; n
++) {
61 ppc_slb_t
*slb
= &env
->slb
[n
];
63 LOG_SLB("%s: slot %d %016" PRIx64
" %016"
64 PRIx64
"\n", __func__
, n
, slb
->esid
, slb
->vsid
);
65 /* We check for 1T matches on all MMUs here - if the MMU
66 * doesn't have 1T segment support, we will have prevented 1T
67 * entries from being inserted in the slbmte code. */
68 if (((slb
->esid
== esid_256M
) &&
69 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_256M
))
70 || ((slb
->esid
== esid_1T
) &&
71 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_1T
))) {
79 void dump_slb(FILE *f
, fprintf_function cpu_fprintf
, PowerPCCPU
*cpu
)
81 CPUPPCState
*env
= &cpu
->env
;
85 cpu_synchronize_state(CPU(cpu
));
87 cpu_fprintf(f
, "SLB\tESID\t\t\tVSID\n");
88 for (i
= 0; i
< env
->slb_nr
; i
++) {
89 slbe
= env
->slb
[i
].esid
;
90 slbv
= env
->slb
[i
].vsid
;
91 if (slbe
== 0 && slbv
== 0) {
94 cpu_fprintf(f
, "%d\t0x%016" PRIx64
"\t0x%016" PRIx64
"\n",
99 void helper_slbia(CPUPPCState
*env
)
103 /* XXX: Warning: slbia never invalidates the first segment */
104 for (n
= 1; n
< env
->slb_nr
; n
++) {
105 ppc_slb_t
*slb
= &env
->slb
[n
];
107 if (slb
->esid
& SLB_ESID_V
) {
108 slb
->esid
&= ~SLB_ESID_V
;
109 /* XXX: given the fact that segment size is 256 MB or 1TB,
110 * and we still don't have a tlb_flush_mask(env, n, mask)
111 * in QEMU, we just invalidate all TLBs
113 env
->tlb_need_flush
= 1;
118 void helper_slbie(CPUPPCState
*env
, target_ulong addr
)
120 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
123 slb
= slb_lookup(cpu
, addr
);
128 if (slb
->esid
& SLB_ESID_V
) {
129 slb
->esid
&= ~SLB_ESID_V
;
131 /* XXX: given the fact that segment size is 256 MB or 1TB,
132 * and we still don't have a tlb_flush_mask(env, n, mask)
133 * in QEMU, we just invalidate all TLBs
135 env
->tlb_need_flush
= 1;
139 int ppc_store_slb(PowerPCCPU
*cpu
, target_ulong slot
,
140 target_ulong esid
, target_ulong vsid
)
142 CPUPPCState
*env
= &cpu
->env
;
143 ppc_slb_t
*slb
= &env
->slb
[slot
];
144 const struct ppc_one_seg_page_size
*sps
= NULL
;
147 if (slot
>= env
->slb_nr
) {
148 return -1; /* Bad slot number */
150 if (esid
& ~(SLB_ESID_ESID
| SLB_ESID_V
)) {
151 return -1; /* Reserved bits set */
153 if (vsid
& (SLB_VSID_B
& ~SLB_VSID_B_1T
)) {
154 return -1; /* Bad segment size */
156 if ((vsid
& SLB_VSID_B
) && !(env
->mmu_model
& POWERPC_MMU_1TSEG
)) {
157 return -1; /* 1T segment on MMU that doesn't support it */
160 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
161 const struct ppc_one_seg_page_size
*sps1
= &env
->sps
.sps
[i
];
163 if (!sps1
->page_shift
) {
167 if ((vsid
& SLB_VSID_LLP_MASK
) == sps1
->slb_enc
) {
174 error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
175 " esid 0x"TARGET_FMT_lx
" vsid 0x"TARGET_FMT_lx
,
184 LOG_SLB("%s: %d " TARGET_FMT_lx
" - " TARGET_FMT_lx
" => %016" PRIx64
185 " %016" PRIx64
"\n", __func__
, slot
, esid
, vsid
,
186 slb
->esid
, slb
->vsid
);
191 static int ppc_load_slb_esid(PowerPCCPU
*cpu
, target_ulong rb
,
194 CPUPPCState
*env
= &cpu
->env
;
195 int slot
= rb
& 0xfff;
196 ppc_slb_t
*slb
= &env
->slb
[slot
];
198 if (slot
>= env
->slb_nr
) {
206 static int ppc_load_slb_vsid(PowerPCCPU
*cpu
, target_ulong rb
,
209 CPUPPCState
*env
= &cpu
->env
;
210 int slot
= rb
& 0xfff;
211 ppc_slb_t
*slb
= &env
->slb
[slot
];
213 if (slot
>= env
->slb_nr
) {
221 static int ppc_find_slb_vsid(PowerPCCPU
*cpu
, target_ulong rb
,
224 CPUPPCState
*env
= &cpu
->env
;
227 if (!msr_is_64bit(env
, env
->msr
)) {
230 slb
= slb_lookup(cpu
, rb
);
232 *rt
= (target_ulong
)-1ul;
239 void helper_store_slb(CPUPPCState
*env
, target_ulong rb
, target_ulong rs
)
241 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
243 if (ppc_store_slb(cpu
, rb
& 0xfff, rb
& ~0xfffULL
, rs
) < 0) {
244 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
249 target_ulong
helper_load_slb_esid(CPUPPCState
*env
, target_ulong rb
)
251 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
254 if (ppc_load_slb_esid(cpu
, rb
, &rt
) < 0) {
255 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
261 target_ulong
helper_find_slb_vsid(CPUPPCState
*env
, target_ulong rb
)
263 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
266 if (ppc_find_slb_vsid(cpu
, rb
, &rt
) < 0) {
267 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
273 target_ulong
helper_load_slb_vsid(CPUPPCState
*env
, target_ulong rb
)
275 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
278 if (ppc_load_slb_vsid(cpu
, rb
, &rt
) < 0) {
279 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
286 * 64-bit hash table MMU handling
288 void ppc_hash64_set_sdr1(PowerPCCPU
*cpu
, target_ulong value
,
291 CPUPPCState
*env
= &cpu
->env
;
292 target_ulong htabsize
= value
& SDR_64_HTABSIZE
;
294 env
->spr
[SPR_SDR1
] = value
;
297 "Invalid HTABSIZE 0x" TARGET_FMT_lx
" stored in SDR1",
301 env
->htab_mask
= (1ULL << (htabsize
+ 18 - 7)) - 1;
302 env
->htab_base
= value
& SDR_64_HTABORG
;
305 void ppc_hash64_set_external_hpt(PowerPCCPU
*cpu
, void *hpt
, int shift
,
308 CPUPPCState
*env
= &cpu
->env
;
309 Error
*local_err
= NULL
;
312 env
->external_htab
= hpt
;
314 env
->external_htab
= MMU_HASH64_KVM_MANAGED_HPT
;
316 ppc_hash64_set_sdr1(cpu
, (target_ulong
)(uintptr_t)hpt
| (shift
- 18),
319 error_propagate(errp
, local_err
);
323 /* Not strictly necessary, but makes it clearer that an external
324 * htab is in use when debugging */
328 if (kvmppc_put_books_sregs(cpu
) < 0) {
329 error_setg(errp
, "Unable to update SDR1 in KVM");
334 static int ppc_hash64_pte_prot(PowerPCCPU
*cpu
,
335 ppc_slb_t
*slb
, ppc_hash_pte64_t pte
)
337 CPUPPCState
*env
= &cpu
->env
;
339 /* Some pp bit combinations have undefined behaviour, so default
340 * to no access in those cases */
343 key
= !!(msr_pr
? (slb
->vsid
& SLB_VSID_KP
)
344 : (slb
->vsid
& SLB_VSID_KS
));
345 pp
= (pte
.pte1
& HPTE64_R_PP
) | ((pte
.pte1
& HPTE64_R_PP0
) >> 61);
352 prot
= PAGE_READ
| PAGE_WRITE
;
373 prot
= PAGE_READ
| PAGE_WRITE
;
378 /* No execute if either noexec or guarded bits set */
379 if (!(pte
.pte1
& HPTE64_R_N
) || (pte
.pte1
& HPTE64_R_G
)
380 || (slb
->vsid
& SLB_VSID_N
)) {
387 static int ppc_hash64_amr_prot(PowerPCCPU
*cpu
, ppc_hash_pte64_t pte
)
389 CPUPPCState
*env
= &cpu
->env
;
391 int prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
393 /* Only recent MMUs implement Virtual Page Class Key Protection */
394 if (!(env
->mmu_model
& POWERPC_MMU_AMR
)) {
398 key
= HPTE64_R_KEY(pte
.pte1
);
399 amrbits
= (env
->spr
[SPR_AMR
] >> 2*(31 - key
)) & 0x3;
401 /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
402 /* env->spr[SPR_AMR]); */
405 * A store is permitted if the AMR bit is 0. Remove write
406 * protection if it is set.
412 * A load is permitted if the AMR bit is 0. Remove read
413 * protection if it is set.
422 uint64_t ppc_hash64_start_access(PowerPCCPU
*cpu
, target_ulong pte_index
)
427 pte_offset
= pte_index
* HASH_PTE_SIZE_64
;
428 if (cpu
->env
.external_htab
== MMU_HASH64_KVM_MANAGED_HPT
) {
430 * HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
432 token
= kvmppc_hash64_read_pteg(cpu
, pte_index
);
433 } else if (cpu
->env
.external_htab
) {
435 * HTAB is controlled by QEMU. Just point to the internally
438 token
= (uint64_t)(uintptr_t) cpu
->env
.external_htab
+ pte_offset
;
439 } else if (cpu
->env
.htab_base
) {
440 token
= cpu
->env
.htab_base
+ pte_offset
;
445 void ppc_hash64_stop_access(PowerPCCPU
*cpu
, uint64_t token
)
447 if (cpu
->env
.external_htab
== MMU_HASH64_KVM_MANAGED_HPT
) {
448 kvmppc_hash64_free_pteg(token
);
452 static unsigned hpte_page_shift(const struct ppc_one_seg_page_size
*sps
,
453 uint64_t pte0
, uint64_t pte1
)
457 if (!(pte0
& HPTE64_V_LARGE
)) {
458 if (sps
->page_shift
!= 12) {
459 /* 4kiB page in a non 4kiB segment */
462 /* Normal 4kiB page */
466 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
467 const struct ppc_one_page_size
*ps
= &sps
->enc
[i
];
470 if (!ps
->page_shift
) {
474 if (ps
->page_shift
== 12) {
475 /* L bit is set so this can't be a 4kiB page */
479 mask
= ((1ULL << ps
->page_shift
) - 1) & HPTE64_R_RPN
;
481 if ((pte1
& mask
) == ((uint64_t)ps
->pte_enc
<< HPTE64_R_RPN_SHIFT
)) {
482 return ps
->page_shift
;
486 return 0; /* Bad page size encoding */
489 static hwaddr
ppc_hash64_pteg_search(PowerPCCPU
*cpu
, hwaddr hash
,
490 const struct ppc_one_seg_page_size
*sps
,
492 ppc_hash_pte64_t
*pte
, unsigned *pshift
)
494 CPUPPCState
*env
= &cpu
->env
;
497 target_ulong pte0
, pte1
;
498 target_ulong pte_index
;
500 pte_index
= (hash
& env
->htab_mask
) * HPTES_PER_GROUP
;
501 token
= ppc_hash64_start_access(cpu
, pte_index
);
505 for (i
= 0; i
< HPTES_PER_GROUP
; i
++) {
506 pte0
= ppc_hash64_load_hpte0(cpu
, token
, i
);
507 pte1
= ppc_hash64_load_hpte1(cpu
, token
, i
);
509 /* This compares V, B, H (secondary) and the AVPN */
510 if (HPTE64_V_COMPARE(pte0
, ptem
)) {
511 *pshift
= hpte_page_shift(sps
, pte0
, pte1
);
513 * If there is no match, ignore the PTE, it could simply
514 * be for a different segment size encoding and the
515 * architecture specifies we should not match. Linux will
516 * potentially leave behind PTEs for the wrong base page
517 * size when demoting segments.
522 /* We don't do anything with pshift yet as qemu TLB only deals
523 * with 4K pages anyway
527 ppc_hash64_stop_access(cpu
, token
);
528 return (pte_index
+ i
) * HASH_PTE_SIZE_64
;
531 ppc_hash64_stop_access(cpu
, token
);
533 * We didn't find a valid entry.
538 static hwaddr
ppc_hash64_htab_lookup(PowerPCCPU
*cpu
,
539 ppc_slb_t
*slb
, target_ulong eaddr
,
540 ppc_hash_pte64_t
*pte
, unsigned *pshift
)
542 CPUPPCState
*env
= &cpu
->env
;
545 uint64_t vsid
, epnmask
, epn
, ptem
;
546 const struct ppc_one_seg_page_size
*sps
= slb
->sps
;
548 /* The SLB store path should prevent any bad page size encodings
549 * getting in there, so: */
552 /* If ISL is set in LPCR we need to clamp the page size to 4K */
553 if (env
->spr
[SPR_LPCR
] & LPCR_ISL
) {
554 /* We assume that when using TCG, 4k is first entry of SPS */
555 sps
= &env
->sps
.sps
[0];
556 assert(sps
->page_shift
== 12);
559 epnmask
= ~((1ULL << sps
->page_shift
) - 1);
561 if (slb
->vsid
& SLB_VSID_B
) {
563 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT_1T
;
564 epn
= (eaddr
& ~SEGMENT_MASK_1T
) & epnmask
;
565 hash
= vsid
^ (vsid
<< 25) ^ (epn
>> sps
->page_shift
);
568 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT
;
569 epn
= (eaddr
& ~SEGMENT_MASK_256M
) & epnmask
;
570 hash
= vsid
^ (epn
>> sps
->page_shift
);
572 ptem
= (slb
->vsid
& SLB_VSID_PTEM
) | ((epn
>> 16) & HPTE64_V_AVPN
);
573 ptem
|= HPTE64_V_VALID
;
575 /* Page address translation */
576 qemu_log_mask(CPU_LOG_MMU
,
577 "htab_base " TARGET_FMT_plx
" htab_mask " TARGET_FMT_plx
578 " hash " TARGET_FMT_plx
"\n",
579 env
->htab_base
, env
->htab_mask
, hash
);
581 /* Primary PTEG lookup */
582 qemu_log_mask(CPU_LOG_MMU
,
583 "0 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
584 " vsid=" TARGET_FMT_lx
" ptem=" TARGET_FMT_lx
585 " hash=" TARGET_FMT_plx
"\n",
586 env
->htab_base
, env
->htab_mask
, vsid
, ptem
, hash
);
587 pte_offset
= ppc_hash64_pteg_search(cpu
, hash
, sps
, ptem
, pte
, pshift
);
589 if (pte_offset
== -1) {
590 /* Secondary PTEG lookup */
591 ptem
|= HPTE64_V_SECONDARY
;
592 qemu_log_mask(CPU_LOG_MMU
,
593 "1 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
594 " vsid=" TARGET_FMT_lx
" api=" TARGET_FMT_lx
595 " hash=" TARGET_FMT_plx
"\n", env
->htab_base
,
596 env
->htab_mask
, vsid
, ptem
, ~hash
);
598 pte_offset
= ppc_hash64_pteg_search(cpu
, ~hash
, sps
, ptem
, pte
, pshift
);
604 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU
*cpu
,
605 uint64_t pte0
, uint64_t pte1
)
607 CPUPPCState
*env
= &cpu
->env
;
610 if (!(pte0
& HPTE64_V_LARGE
)) {
615 * The encodings in env->sps need to be carefully chosen so that
616 * this gives an unambiguous result.
618 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
619 const struct ppc_one_seg_page_size
*sps
= &env
->sps
.sps
[i
];
622 if (!sps
->page_shift
) {
626 shift
= hpte_page_shift(sps
, pte0
, pte1
);
635 static void ppc_hash64_set_isi(CPUState
*cs
, CPUPPCState
*env
,
641 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM1
);
643 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM0
);
645 if (vpm
&& !msr_hv
) {
646 cs
->exception_index
= POWERPC_EXCP_HISI
;
648 cs
->exception_index
= POWERPC_EXCP_ISI
;
650 env
->error_code
= error_code
;
653 static void ppc_hash64_set_dsi(CPUState
*cs
, CPUPPCState
*env
, uint64_t dar
,
659 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM1
);
661 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM0
);
663 if (vpm
&& !msr_hv
) {
664 cs
->exception_index
= POWERPC_EXCP_HDSI
;
665 env
->spr
[SPR_HDAR
] = dar
;
666 env
->spr
[SPR_HDSISR
] = dsisr
;
668 cs
->exception_index
= POWERPC_EXCP_DSI
;
669 env
->spr
[SPR_DAR
] = dar
;
670 env
->spr
[SPR_DSISR
] = dsisr
;
676 int ppc_hash64_handle_mmu_fault(PowerPCCPU
*cpu
, vaddr eaddr
,
677 int rwx
, int mmu_idx
)
679 CPUState
*cs
= CPU(cpu
);
680 CPUPPCState
*env
= &cpu
->env
;
684 ppc_hash_pte64_t pte
;
685 int pp_prot
, amr_prot
, prot
;
686 uint64_t new_pte1
, dsisr
;
687 const int need_prot
[] = {PAGE_READ
, PAGE_WRITE
, PAGE_EXEC
};
690 assert((rwx
== 0) || (rwx
== 1) || (rwx
== 2));
692 /* Note on LPCR usage: 970 uses HID4, but our special variant
693 * of store_spr copies relevant fields into env->spr[SPR_LPCR].
694 * Similarily we filter unimplemented bits when storing into
695 * LPCR depending on the MMU version. This code can thus just
696 * use the LPCR "as-is".
699 /* 1. Handle real mode accesses */
700 if (((rwx
== 2) && (msr_ir
== 0)) || ((rwx
!= 2) && (msr_dr
== 0))) {
701 /* Translation is supposedly "off" */
702 /* In real mode the top 4 effective address bits are (mostly) ignored */
703 raddr
= eaddr
& 0x0FFFFFFFFFFFFFFFULL
;
705 /* In HV mode, add HRMOR if top EA bit is clear */
706 if (msr_hv
|| !env
->has_hv_mode
) {
707 if (!(eaddr
>> 63)) {
708 raddr
|= env
->spr
[SPR_HRMOR
];
711 /* Otherwise, check VPM for RMA vs VRMA */
712 if (env
->spr
[SPR_LPCR
] & LPCR_VPM0
) {
713 slb
= &env
->vrma_slb
;
715 goto skip_slb_search
;
717 /* Not much else to do here */
718 cs
->exception_index
= POWERPC_EXCP_MCHECK
;
721 } else if (raddr
< env
->rmls
) {
722 /* RMA. Check bounds in RMLS */
723 raddr
|= env
->spr
[SPR_RMOR
];
725 /* The access failed, generate the approriate interrupt */
727 ppc_hash64_set_isi(cs
, env
, 0x08000000);
733 ppc_hash64_set_dsi(cs
, env
, eaddr
, dsisr
);
738 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
739 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
, mmu_idx
,
744 /* 2. Translation is on, so look up the SLB */
745 slb
= slb_lookup(cpu
, eaddr
);
748 cs
->exception_index
= POWERPC_EXCP_ISEG
;
751 cs
->exception_index
= POWERPC_EXCP_DSEG
;
753 env
->spr
[SPR_DAR
] = eaddr
;
760 /* 3. Check for segment level no-execute violation */
761 if ((rwx
== 2) && (slb
->vsid
& SLB_VSID_N
)) {
762 ppc_hash64_set_isi(cs
, env
, 0x10000000);
766 /* 4. Locate the PTE in the hash table */
767 pte_offset
= ppc_hash64_htab_lookup(cpu
, slb
, eaddr
, &pte
, &apshift
);
768 if (pte_offset
== -1) {
771 ppc_hash64_set_isi(cs
, env
, dsisr
);
776 ppc_hash64_set_dsi(cs
, env
, eaddr
, dsisr
);
780 qemu_log_mask(CPU_LOG_MMU
,
781 "found PTE at offset %08" HWADDR_PRIx
"\n", pte_offset
);
783 /* 5. Check access permissions */
785 pp_prot
= ppc_hash64_pte_prot(cpu
, slb
, pte
);
786 amr_prot
= ppc_hash64_amr_prot(cpu
, pte
);
787 prot
= pp_prot
& amr_prot
;
789 if ((need_prot
[rwx
] & ~prot
) != 0) {
790 /* Access right violation */
791 qemu_log_mask(CPU_LOG_MMU
, "PTE access rejected\n");
793 ppc_hash64_set_isi(cs
, env
, 0x08000000);
796 if (need_prot
[rwx
] & ~pp_prot
) {
802 if (need_prot
[rwx
] & ~amr_prot
) {
805 ppc_hash64_set_dsi(cs
, env
, eaddr
, dsisr
);
810 qemu_log_mask(CPU_LOG_MMU
, "PTE access granted !\n");
812 /* 6. Update PTE referenced and changed bits if necessary */
814 new_pte1
= pte
.pte1
| HPTE64_R_R
; /* set referenced bit */
816 new_pte1
|= HPTE64_R_C
; /* set changed (dirty) bit */
818 /* Treat the page as read-only for now, so that a later write
819 * will pass through this function again to set the C bit */
823 if (new_pte1
!= pte
.pte1
) {
824 ppc_hash64_store_hpte(cpu
, pte_offset
/ HASH_PTE_SIZE_64
,
828 /* 7. Determine the real address from the PTE */
830 raddr
= deposit64(pte
.pte1
& HPTE64_R_RPN
, 0, apshift
, eaddr
);
832 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
833 prot
, mmu_idx
, 1ULL << apshift
);
838 hwaddr
ppc_hash64_get_phys_page_debug(PowerPCCPU
*cpu
, target_ulong addr
)
840 CPUPPCState
*env
= &cpu
->env
;
842 hwaddr pte_offset
, raddr
;
843 ppc_hash_pte64_t pte
;
846 /* Handle real mode */
848 /* In real mode the top 4 effective address bits are ignored */
849 raddr
= addr
& 0x0FFFFFFFFFFFFFFFULL
;
851 /* In HV mode, add HRMOR if top EA bit is clear */
852 if ((msr_hv
|| !env
->has_hv_mode
) && !(addr
>> 63)) {
853 return raddr
| env
->spr
[SPR_HRMOR
];
856 /* Otherwise, check VPM for RMA vs VRMA */
857 if (env
->spr
[SPR_LPCR
] & LPCR_VPM0
) {
858 slb
= &env
->vrma_slb
;
862 } else if (raddr
< env
->rmls
) {
863 /* RMA. Check bounds in RMLS */
864 return raddr
| env
->spr
[SPR_RMOR
];
869 slb
= slb_lookup(cpu
, addr
);
875 pte_offset
= ppc_hash64_htab_lookup(cpu
, slb
, addr
, &pte
, &apshift
);
876 if (pte_offset
== -1) {
880 return deposit64(pte
.pte1
& HPTE64_R_RPN
, 0, apshift
, addr
)
884 void ppc_hash64_store_hpte(PowerPCCPU
*cpu
,
885 target_ulong pte_index
,
886 target_ulong pte0
, target_ulong pte1
)
888 CPUPPCState
*env
= &cpu
->env
;
890 if (env
->external_htab
== MMU_HASH64_KVM_MANAGED_HPT
) {
891 kvmppc_hash64_write_pte(env
, pte_index
, pte0
, pte1
);
895 pte_index
*= HASH_PTE_SIZE_64
;
896 if (env
->external_htab
) {
897 stq_p(env
->external_htab
+ pte_index
, pte0
);
898 stq_p(env
->external_htab
+ pte_index
+ HASH_PTE_SIZE_64
/ 2, pte1
);
900 stq_phys(CPU(cpu
)->as
, env
->htab_base
+ pte_index
, pte0
);
901 stq_phys(CPU(cpu
)->as
,
902 env
->htab_base
+ pte_index
+ HASH_PTE_SIZE_64
/ 2, pte1
);
906 void ppc_hash64_tlb_flush_hpte(PowerPCCPU
*cpu
,
907 target_ulong pte_index
,
908 target_ulong pte0
, target_ulong pte1
)
911 * XXX: given the fact that there are too many segments to
912 * invalidate, and we still don't have a tlb_flush_mask(env, n,
913 * mask) in QEMU, we just invalidate all TLBs
915 tlb_flush(CPU(cpu
), 1);
918 void ppc_hash64_update_rmls(CPUPPCState
*env
)
920 uint64_t lpcr
= env
->spr
[SPR_LPCR
];
923 * This is the full 4 bits encoding of POWER8. Previous
924 * CPUs only support a subset of these but the filtering
925 * is done when writing LPCR
927 switch ((lpcr
& LPCR_RMLS
) >> LPCR_RMLS_SHIFT
) {
929 env
->rmls
= 0x2000000ull
;
932 env
->rmls
= 0x4000000ull
;
934 case 0x7: /* 128MB */
935 env
->rmls
= 0x8000000ull
;
937 case 0x4: /* 256MB */
938 env
->rmls
= 0x10000000ull
;
941 env
->rmls
= 0x40000000ull
;
944 env
->rmls
= 0x400000000ull
;
947 /* What to do here ??? */
952 void ppc_hash64_update_vrma(CPUPPCState
*env
)
954 const struct ppc_one_seg_page_size
*sps
= NULL
;
955 target_ulong esid
, vsid
, lpcr
;
956 ppc_slb_t
*slb
= &env
->vrma_slb
;
961 slb
->esid
= slb
->vsid
= 0;
964 /* Is VRMA enabled ? */
965 lpcr
= env
->spr
[SPR_LPCR
];
966 if (!(lpcr
& LPCR_VPM0
)) {
970 /* Make one up. Mostly ignore the ESID which will not be
971 * needed for translation
973 vsid
= SLB_VSID_VRMA
;
974 vrmasd
= (lpcr
& LPCR_VRMASD
) >> LPCR_VRMASD_SHIFT
;
975 vsid
|= (vrmasd
<< 4) & (SLB_VSID_L
| SLB_VSID_LP
);
978 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
979 const struct ppc_one_seg_page_size
*sps1
= &env
->sps
.sps
[i
];
981 if (!sps1
->page_shift
) {
985 if ((vsid
& SLB_VSID_LLP_MASK
) == sps1
->slb_enc
) {
992 error_report("Bad page size encoding esid 0x"TARGET_FMT_lx
993 " vsid 0x"TARGET_FMT_lx
, esid
, vsid
);
1002 void helper_store_lpcr(CPUPPCState
*env
, target_ulong val
)
1006 /* Filter out bits */
1007 switch (env
->mmu_model
) {
1008 case POWERPC_MMU_64B
: /* 970 */
1012 if (val
& 0x8000000000000000ull
) {
1016 lpcr
|= (0x4ull
<< LPCR_RMLS_SHIFT
);
1018 if (val
& 0x4000000000000000ull
) {
1019 lpcr
|= (0x2ull
<< LPCR_RMLS_SHIFT
);
1021 if (val
& 0x2000000000000000ull
) {
1022 lpcr
|= (0x1ull
<< LPCR_RMLS_SHIFT
);
1024 env
->spr
[SPR_RMOR
] = ((lpcr
>> 41) & 0xffffull
) << 26;
1026 /* XXX We could also write LPID from HID4 here
1027 * but since we don't tag any translation on it
1028 * it doesn't actually matter
1030 /* XXX For proper emulation of 970 we also need
1031 * to dig HRMOR out of HID5
1034 case POWERPC_MMU_2_03
: /* P5p */
1035 lpcr
= val
& (LPCR_RMLS
| LPCR_ILE
|
1036 LPCR_LPES0
| LPCR_LPES1
|
1037 LPCR_RMI
| LPCR_HDICE
);
1039 case POWERPC_MMU_2_06
: /* P7 */
1040 lpcr
= val
& (LPCR_VPM0
| LPCR_VPM1
| LPCR_ISL
| LPCR_DPFD
|
1041 LPCR_VRMASD
| LPCR_RMLS
| LPCR_ILE
|
1042 LPCR_P7_PECE0
| LPCR_P7_PECE1
| LPCR_P7_PECE2
|
1043 LPCR_MER
| LPCR_TC
|
1044 LPCR_LPES0
| LPCR_LPES1
| LPCR_HDICE
);
1046 case POWERPC_MMU_2_07
: /* P8 */
1047 lpcr
= val
& (LPCR_VPM0
| LPCR_VPM1
| LPCR_ISL
| LPCR_KBV
|
1048 LPCR_DPFD
| LPCR_VRMASD
| LPCR_RMLS
| LPCR_ILE
|
1049 LPCR_AIL
| LPCR_ONL
| LPCR_P8_PECE0
| LPCR_P8_PECE1
|
1050 LPCR_P8_PECE2
| LPCR_P8_PECE3
| LPCR_P8_PECE4
|
1051 LPCR_MER
| LPCR_TC
| LPCR_LPES0
| LPCR_HDICE
);
1056 env
->spr
[SPR_LPCR
] = lpcr
;
1057 ppc_hash64_update_rmls(env
);
1058 ppc_hash64_update_vrma(env
);