hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7
   8 /* PCI includes legacy ISA access.  */
   9 #include "isa.h"
  10
  11 /* PCI bus */
  12
  13 extern target_phys_addr_t pci_mem_base;
  14
  15 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  16 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  17 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  18
  19 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  20 #include "pci_ids.h"
  21
  22 /* QEMU-specific Vendor and Device ID definitions */
  23
  24 /* IBM (0x1014) */
  25 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  26 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  27
  28 /* Hitachi (0x1054) */
  29 #define PCI_VENDOR_ID_HITACHI            0x1054
  30 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  31
  32 /* Apple (0x106b) */
  33 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  34 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  35 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  37 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  38
  39 /* Realtek (0x10ec) */
  40 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  41
  42 /* Xilinx (0x10ee) */
  43 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  44
  45 /* Marvell (0x11ab) */
  46 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  47
  48 /* QEMU/Bochs VGA (0x1234) */
  49 #define PCI_VENDOR_ID_QEMU               0x1234
  50 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  51
  52 /* VMWare (0x15ad) */
  53 #define PCI_VENDOR_ID_VMWARE             0x15ad
  54 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  55 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  56 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  57 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  58 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  59
  60 /* Intel (0x8086) */
  61 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  62 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  63
  64 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  65 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  66 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  67 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  68
  69 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  70 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  71 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  72 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  73
  74 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  75                                 uint32_t address, uint32_t data, int len);
  76 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  77                                    uint32_t address, int len);
  78 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  79                                 uint32_t addr, uint32_t size, int type);
  80 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  81
  82 #define PCI_ADDRESS_SPACE_MEM           0x00
  83 #define PCI_ADDRESS_SPACE_IO            0x01
  84 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
  85
  86 typedef struct PCIIORegion {
  87     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
  88     uint32_t size;
  89     uint8_t type;
  90     PCIMapIORegionFunc *map_func;
  91 } PCIIORegion;
  92
  93 #define PCI_ROM_SLOT 6
  94 #define PCI_NUM_REGIONS 7
  95
  96 /* Declarations from linux/pci_regs.h */
  97 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  98 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  99 #define PCI_COMMAND             0x04    /* 16 bits */
 100 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 101 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 102 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus master */
 103 #define PCI_STATUS              0x06    /* 16 bits */
 104 #define PCI_REVISION_ID         0x08    /* 8 bits  */
 105 #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
 106 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 107 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
 108 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
 109 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
 110 #define  PCI_HEADER_TYPE_NORMAL         0
 111 #define  PCI_HEADER_TYPE_BRIDGE         1
 112 #define  PCI_HEADER_TYPE_CARDBUS        2
 113 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 114 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
 115 #define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
 116 #define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
 117 #define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
 118 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
 119 #define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
 120 #define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
 121 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 122 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 123 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 124 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 125
 126 /* Capability lists */
 127 #define PCI_CAP_LIST_ID         0       /* Capability ID */
 128 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 129
 130 #define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
 131 #define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
 132 #define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */
 133
 134 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 135 #define PCI_STATUS_RESERVED1    0x007
 136 #define PCI_STATUS_INT_STATUS   0x008
 137 #define PCI_STATUS_CAP_LIST     0x010
 138 #define PCI_STATUS_66MHZ        0x020
 139 #define PCI_STATUS_RESERVED2    0x040
 140 #define PCI_STATUS_FAST_BACK    0x080
 141 #define PCI_STATUS_DEVSEL       0x600
 142
 143 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 144                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 145                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 146
 147 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 148
 149 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 150 #define PCI_COMMAND_RESERVED    0xf800
 151
 152 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 153
 154 /* Size of the standard PCI config header */
 155 #define PCI_CONFIG_HEADER_SIZE 0x40
 156 /* Size of the standard PCI config space */
 157 #define PCI_CONFIG_SPACE_SIZE 0x100
 158
 159 /* Bits in cap_present field. */
 160 enum {
 161     QEMU_PCI_CAP_MSIX = 0x1,
 162 };
 163
 164 struct PCIDevice {
 165     DeviceState qdev;
 166     /* PCI config space */
 167     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 168
 169     /* Used to enable config checks on load. Note that writeable bits are
 170      * never checked even if set in cmask. */
 171     uint8_t cmask[PCI_CONFIG_SPACE_SIZE];
 172
 173     /* Used to implement R/W bytes */
 174     uint8_t wmask[PCI_CONFIG_SPACE_SIZE];
 175
 176     /* Used to allocate config space for capabilities. */
 177     uint8_t used[PCI_CONFIG_SPACE_SIZE];
 178
 179     /* the following fields are read only */
 180     PCIBus *bus;
 181     uint32_t devfn;
 182     char name[64];
 183     PCIIORegion io_regions[PCI_NUM_REGIONS];
 184
 185     /* do not access the following fields */
 186     PCIConfigReadFunc *config_read;
 187     PCIConfigWriteFunc *config_write;
 188     PCIUnregisterFunc *unregister;
 189
 190     /* IRQ objects for the INTA-INTD pins.  */
 191     qemu_irq *irq;
 192
 193     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 194     int irq_state[4];
 195
 196     /* Capability bits */
 197     uint32_t cap_present;
 198
 199     /* Offset of MSI-X capability in config space */
 200     uint8_t msix_cap;
 201
 202     /* MSI-X entries */
 203     int msix_entries_nr;
 204
 205     /* Space to store MSIX table */
 206     uint8_t *msix_table_page;
 207     /* MMIO index used to map MSIX table and pending bit entries. */
 208     int msix_mmio_index;
 209     /* Reference-count for entries actually in use by driver. */
 210     unsigned *msix_entry_used;
 211     /* Region including the MSI-X table */
 212     uint32_t msix_bar_size;
 213     /* Version id needed for VMState */
 214     int32_t version_id;
 215     /* How much space does an MSIX table need. */
 216     /* The spec requires giving the table structure
 217      * a 4K aligned region all by itself. Align it to
 218      * target pages so that drivers can do passthrough
 219      * on the rest of the region. */
 220     target_phys_addr_t msix_page_size;
 221 };
 222
 223 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 224                                int instance_size, int devfn,
 225                                PCIConfigReadFunc *config_read,
 226                                PCIConfigWriteFunc *config_write);
 227 int pci_unregister_device(PCIDevice *pci_dev);
 228
 229 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 230                             uint32_t size, int type,
 231                             PCIMapIORegionFunc *map_func);
 232
 233 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 234
 235 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 236
 237 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 238
 239 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 240
 241
 242 uint32_t pci_default_read_config(PCIDevice *d,
 243                                  uint32_t address, int len);
 244 void pci_default_write_config(PCIDevice *d,
 245                               uint32_t address, uint32_t val, int len);
 246 void pci_device_save(PCIDevice *s, QEMUFile *f);
 247 int pci_device_load(PCIDevice *s, QEMUFile *f);
 248
 249 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 250 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 251 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 252                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 253                          void *irq_opaque, int devfn_min, int nirq);
 254
 255 int pci_nic_supported(const char *model);
 256 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 257                         const char *default_devaddr);
 258 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 259 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 260 int pci_bus_num(PCIBus *s);
 261 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 262 PCIBus *pci_find_bus(int bus_num);
 263 PCIDevice *pci_find_device(int bus_num, int slot, int function);
 264
 265 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 266                      unsigned *slotp);
 267
 268 void pci_info(Monitor *mon);
 269 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 270                         pci_map_irq_fn map_irq, const char *name);
 271
 272 static inline void
 273 pci_set_byte(uint8_t *config, uint8_t val)
 274 {
 275     *config = val;
 276 }
 277
 278 static inline uint8_t
 279 pci_get_byte(uint8_t *config)
 280 {
 281     return *config;
 282 }
 283
 284 static inline void
 285 pci_set_word(uint8_t *config, uint16_t val)
 286 {
 287     cpu_to_le16wu((uint16_t *)config, val);
 288 }
 289
 290 static inline uint16_t
 291 pci_get_word(uint8_t *config)
 292 {
 293     return le16_to_cpupu((uint16_t *)config);
 294 }
 295
 296 static inline void
 297 pci_set_long(uint8_t *config, uint32_t val)
 298 {
 299     cpu_to_le32wu((uint32_t *)config, val);
 300 }
 301
 302 static inline uint32_t
 303 pci_get_long(uint8_t *config)
 304 {
 305     return le32_to_cpupu((uint32_t *)config);
 306 }
 307
 308 static inline void
 309 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 310 {
 311     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 312 }
 313
 314 static inline void
 315 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 316 {
 317     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 318 }
 319
 320 static inline void
 321 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 322 {
 323     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 324 }
 325
 326 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 327 typedef struct {
 328     DeviceInfo qdev;
 329     pci_qdev_initfn init;
 330     PCIConfigReadFunc *config_read;
 331     PCIConfigWriteFunc *config_write;
 332 } PCIDeviceInfo;
 333
 334 void pci_qdev_register(PCIDeviceInfo *info);
 335 void pci_qdev_register_many(PCIDeviceInfo *info);
 336
 337 PCIDevice *pci_create(const char *name, const char *devaddr);
 338 PCIDevice *pci_create_noinit(PCIBus *bus, int devfn, const char *name);
 339 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 340
 341 /* lsi53c895a.c */
 342 #define LSI_MAX_DEVS 7
 343
 344 /* vmware_vga.c */
 345 void pci_vmsvga_init(PCIBus *bus);
 346
 347 /* usb-uhci.c */
 348 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 349 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 350
 351 /* usb-ohci.c */
 352 void usb_ohci_init_pci(struct PCIBus *bus, int devfn);
 353
 354 /* prep_pci.c */
 355 PCIBus *pci_prep_init(qemu_irq *pic);
 356
 357 /* apb_pci.c */
 358 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 359                      target_phys_addr_t mem_base,
 360                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 361
 362 /* sh_pci.c */
 363 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 364                             void *pic, int devfn_min, int nirq);
 365
 366 #endif