?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
pc: exit QEMU if compat machine doesn't support memory hotlpug
[qemu/cris-port.git] / target-ppc / translate_init.c
blob85581c953762affcf24d417be1a6129ea1a1af32
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31 #include "qapi/visitor.h"
32 #include "hw/qdev-properties.h"
33
34 //#define PPC_DUMP_CPU
35 //#define PPC_DEBUG_SPR
36 //#define PPC_DUMP_SPR_ACCESSES
37
38 /* For user-mode emulation, we don't emulate any IRQ controller */
39 #if defined(CONFIG_USER_ONLY)
40 #define PPC_IRQ_INIT_FN(name) \
41 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42 { \
43 }
44 #else
45 #define PPC_IRQ_INIT_FN(name) \
46 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47 #endif
48
49 PPC_IRQ_INIT_FN(40x);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52 PPC_IRQ_INIT_FN(POWER7);
53 PPC_IRQ_INIT_FN(e500);
54
55 /* Generic callbacks:
56 * do nothing but store/retrieve spr value
57 */
58 static void spr_load_dump_spr(int sprn)
59 {
60 #ifdef PPC_DUMP_SPR_ACCESSES
61 TCGv_i32 t0 = tcg_const_i32(sprn);
62 gen_helper_load_dump_spr(cpu_env, t0);
63 tcg_temp_free_i32(t0);
64 #endif
65 }
66
67 static void spr_read_generic (void *opaque, int gprn, int sprn)
68 {
69 gen_load_spr(cpu_gpr[gprn], sprn);
70 spr_load_dump_spr(sprn);
71 }
72
73 static void spr_store_dump_spr(int sprn)
74 {
75 #ifdef PPC_DUMP_SPR_ACCESSES
76 TCGv_i32 t0 = tcg_const_i32(sprn);
77 gen_helper_store_dump_spr(cpu_env, t0);
78 tcg_temp_free_i32(t0);
79 #endif
80 }
81
82 static void spr_write_generic (void *opaque, int sprn, int gprn)
83 {
84 gen_store_spr(sprn, cpu_gpr[gprn]);
85 spr_store_dump_spr(sprn);
86 }
87
88 #if !defined(CONFIG_USER_ONLY)
89 static void spr_write_generic32(void *opaque, int sprn, int gprn)
90 {
91 #ifdef TARGET_PPC64
92 TCGv t0 = tcg_temp_new();
93 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
94 gen_store_spr(sprn, t0);
95 tcg_temp_free(t0);
96 spr_store_dump_spr(sprn);
97 #else
98 spr_write_generic(opaque, sprn, gprn);
99 #endif
100 }
101
102 static void spr_write_clear (void *opaque, int sprn, int gprn)
103 {
104 TCGv t0 = tcg_temp_new();
105 TCGv t1 = tcg_temp_new();
106 gen_load_spr(t0, sprn);
107 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
108 tcg_gen_and_tl(t0, t0, t1);
109 gen_store_spr(sprn, t0);
110 tcg_temp_free(t0);
111 tcg_temp_free(t1);
112 }
113
114 static void spr_access_nop(void *opaque, int sprn, int gprn)
115 {
116 }
117
118 #endif
119
120 /* SPR common to all PowerPC */
121 /* XER */
122 static void spr_read_xer (void *opaque, int gprn, int sprn)
123 {
124 gen_read_xer(cpu_gpr[gprn]);
125 }
126
127 static void spr_write_xer (void *opaque, int sprn, int gprn)
128 {
129 gen_write_xer(cpu_gpr[gprn]);
130 }
131
132 /* LR */
133 static void spr_read_lr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
136 }
137
138 static void spr_write_lr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
141 }
142
143 /* CFAR */
144 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
145 static void spr_read_cfar (void *opaque, int gprn, int sprn)
146 {
147 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
148 }
149
150 static void spr_write_cfar (void *opaque, int sprn, int gprn)
151 {
152 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
153 }
154 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
155
156 /* CTR */
157 static void spr_read_ctr (void *opaque, int gprn, int sprn)
158 {
159 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
160 }
161
162 static void spr_write_ctr (void *opaque, int sprn, int gprn)
163 {
164 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
165 }
166
167 /* User read access to SPR */
168 /* USPRx */
169 /* UMMCRx */
170 /* UPMCx */
171 /* USIA */
172 /* UDECR */
173 static void spr_read_ureg (void *opaque, int gprn, int sprn)
174 {
175 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
176 }
177
178 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
179 static void spr_write_ureg(void *opaque, int sprn, int gprn)
180 {
181 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
182 }
183 #endif
184
185 /* SPR common to all non-embedded PowerPC */
186 /* DECR */
187 #if !defined(CONFIG_USER_ONLY)
188 static void spr_read_decr (void *opaque, int gprn, int sprn)
189 {
190 if (use_icount) {
191 gen_io_start();
192 }
193 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
194 if (use_icount) {
195 gen_io_end();
196 gen_stop_exception(opaque);
197 }
198 }
199
200 static void spr_write_decr (void *opaque, int sprn, int gprn)
201 {
202 if (use_icount) {
203 gen_io_start();
204 }
205 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
206 if (use_icount) {
207 gen_io_end();
208 gen_stop_exception(opaque);
209 }
210 }
211 #endif
212
213 /* SPR common to all non-embedded PowerPC, except 601 */
214 /* Time base */
215 static void spr_read_tbl (void *opaque, int gprn, int sprn)
216 {
217 if (use_icount) {
218 gen_io_start();
219 }
220 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
221 if (use_icount) {
222 gen_io_end();
223 gen_stop_exception(opaque);
224 }
225 }
226
227 static void spr_read_tbu (void *opaque, int gprn, int sprn)
228 {
229 if (use_icount) {
230 gen_io_start();
231 }
232 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
233 if (use_icount) {
234 gen_io_end();
235 gen_stop_exception(opaque);
236 }
237 }
238
239 __attribute__ (( unused ))
240 static void spr_read_atbl (void *opaque, int gprn, int sprn)
241 {
242 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
243 }
244
245 __attribute__ (( unused ))
246 static void spr_read_atbu (void *opaque, int gprn, int sprn)
247 {
248 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
249 }
250
251 #if !defined(CONFIG_USER_ONLY)
252 static void spr_write_tbl (void *opaque, int sprn, int gprn)
253 {
254 if (use_icount) {
255 gen_io_start();
256 }
257 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
258 if (use_icount) {
259 gen_io_end();
260 gen_stop_exception(opaque);
261 }
262 }
263
264 static void spr_write_tbu (void *opaque, int sprn, int gprn)
265 {
266 if (use_icount) {
267 gen_io_start();
268 }
269 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
270 if (use_icount) {
271 gen_io_end();
272 gen_stop_exception(opaque);
273 }
274 }
275
276 __attribute__ (( unused ))
277 static void spr_write_atbl (void *opaque, int sprn, int gprn)
278 {
279 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
280 }
281
282 __attribute__ (( unused ))
283 static void spr_write_atbu (void *opaque, int sprn, int gprn)
284 {
285 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
286 }
287
288 #if defined(TARGET_PPC64)
289 __attribute__ (( unused ))
290 static void spr_read_purr (void *opaque, int gprn, int sprn)
291 {
292 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
293 }
294 #endif
295 #endif
296
297 #if !defined(CONFIG_USER_ONLY)
298 /* IBAT0U...IBAT0U */
299 /* IBAT0L...IBAT7L */
300 static void spr_read_ibat (void *opaque, int gprn, int sprn)
301 {
302 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
303 }
304
305 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
306 {
307 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
308 }
309
310 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
311 {
312 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
313 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
314 tcg_temp_free_i32(t0);
315 }
316
317 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
318 {
319 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
320 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
321 tcg_temp_free_i32(t0);
322 }
323
324 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
325 {
326 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
327 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
328 tcg_temp_free_i32(t0);
329 }
330
331 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
332 {
333 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
334 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
335 tcg_temp_free_i32(t0);
336 }
337
338 /* DBAT0U...DBAT7U */
339 /* DBAT0L...DBAT7L */
340 static void spr_read_dbat (void *opaque, int gprn, int sprn)
341 {
342 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
343 }
344
345 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
346 {
347 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
348 }
349
350 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
351 {
352 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
353 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
354 tcg_temp_free_i32(t0);
355 }
356
357 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
358 {
359 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
360 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
361 tcg_temp_free_i32(t0);
362 }
363
364 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
365 {
366 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
367 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
368 tcg_temp_free_i32(t0);
369 }
370
371 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
372 {
373 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
374 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
375 tcg_temp_free_i32(t0);
376 }
377
378 /* SDR1 */
379 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
380 {
381 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
382 }
383
384 /* 64 bits PowerPC specific SPRs */
385 #if defined(TARGET_PPC64)
386 static void spr_read_hior (void *opaque, int gprn, int sprn)
387 {
388 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
389 }
390
391 static void spr_write_hior (void *opaque, int sprn, int gprn)
392 {
393 TCGv t0 = tcg_temp_new();
394 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
395 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
396 tcg_temp_free(t0);
397 }
398 #endif
399 #endif
400
401 /* PowerPC 601 specific registers */
402 /* RTC */
403 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
404 {
405 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
406 }
407
408 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
409 {
410 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
411 }
412
413 #if !defined(CONFIG_USER_ONLY)
414 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
415 {
416 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
417 }
418
419 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
420 {
421 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
422 }
423
424 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
425 {
426 DisasContext *ctx = opaque;
427
428 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
429 /* Must stop the translation as endianness may have changed */
430 gen_stop_exception(ctx);
431 }
432 #endif
433
434 /* Unified bats */
435 #if !defined(CONFIG_USER_ONLY)
436 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
437 {
438 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
439 }
440
441 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
442 {
443 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
444 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
445 tcg_temp_free_i32(t0);
446 }
447
448 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
449 {
450 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
451 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
452 tcg_temp_free_i32(t0);
453 }
454 #endif
455
456 /* PowerPC 40x specific registers */
457 #if !defined(CONFIG_USER_ONLY)
458 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
459 {
460 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
461 }
462
463 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
464 {
465 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
466 }
467
468 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
469 {
470 DisasContext *ctx = opaque;
471
472 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
473 /* We must stop translation as we may have rebooted */
474 gen_stop_exception(ctx);
475 }
476
477 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
478 {
479 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
480 }
481
482 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
483 {
484 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
485 }
486
487 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
488 {
489 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
490 }
491 #endif
492
493 /* PowerPC 403 specific registers */
494 /* PBL1 / PBU1 / PBL2 / PBU2 */
495 #if !defined(CONFIG_USER_ONLY)
496 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
497 {
498 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
499 }
500
501 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
502 {
503 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
504 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
505 tcg_temp_free_i32(t0);
506 }
507
508 static void spr_write_pir (void *opaque, int sprn, int gprn)
509 {
510 TCGv t0 = tcg_temp_new();
511 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
512 gen_store_spr(SPR_PIR, t0);
513 tcg_temp_free(t0);
514 }
515 #endif
516
517 /* SPE specific registers */
518 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
519 {
520 TCGv_i32 t0 = tcg_temp_new_i32();
521 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
522 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
523 tcg_temp_free_i32(t0);
524 }
525
526 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
527 {
528 TCGv_i32 t0 = tcg_temp_new_i32();
529 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
530 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
531 tcg_temp_free_i32(t0);
532 }
533
534 #if !defined(CONFIG_USER_ONLY)
535 /* Callback used to write the exception vector base */
536 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
537 {
538 TCGv t0 = tcg_temp_new();
539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
542 gen_store_spr(sprn, t0);
543 tcg_temp_free(t0);
544 }
545
546 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
547 {
548 DisasContext *ctx = opaque;
549 int sprn_offs;
550
551 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
552 sprn_offs = sprn - SPR_BOOKE_IVOR0;
553 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
554 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
555 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
556 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
557 } else {
558 printf("Trying to write an unknown exception vector %d %03x\n",
559 sprn, sprn);
560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
561 return;
562 }
563
564 TCGv t0 = tcg_temp_new();
565 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
566 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
567 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
568 gen_store_spr(sprn, t0);
569 tcg_temp_free(t0);
570 }
571 #endif
572
573 static inline void vscr_init (CPUPPCState *env, uint32_t val)
574 {
575 env->vscr = val;
576 /* Altivec always uses round-to-nearest */
577 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
578 set_flush_to_zero(vscr_nj, &env->vec_status);
579 }
580
581 #ifdef CONFIG_USER_ONLY
582 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
583 oea_read, oea_write, one_reg_id, initial_value) \
584 _spr_register(env, num, name, uea_read, uea_write, initial_value)
585 #else
586 #if !defined(CONFIG_KVM)
587 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
588 oea_read, oea_write, one_reg_id, initial_value) \
589 _spr_register(env, num, name, uea_read, uea_write, \
590 oea_read, oea_write, initial_value)
591 #else
592 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
593 oea_read, oea_write, one_reg_id, initial_value) \
594 _spr_register(env, num, name, uea_read, uea_write, \
595 oea_read, oea_write, one_reg_id, initial_value)
596 #endif
597 #endif
598
599 #define spr_register(env, num, name, uea_read, uea_write, \
600 oea_read, oea_write, initial_value) \
601 spr_register_kvm(env, num, name, uea_read, uea_write, \
602 oea_read, oea_write, 0, initial_value)
603
604 static inline void _spr_register(CPUPPCState *env, int num,
605 const char *name,
606 void (*uea_read)(void *opaque, int gprn, int sprn),
607 void (*uea_write)(void *opaque, int sprn, int gprn),
608 #if !defined(CONFIG_USER_ONLY)
609
610 void (*oea_read)(void *opaque, int gprn, int sprn),
611 void (*oea_write)(void *opaque, int sprn, int gprn),
612 #endif
613 #if defined(CONFIG_KVM)
614 uint64_t one_reg_id,
615 #endif
616 target_ulong initial_value)
617 {
618 ppc_spr_t *spr;
619
620 spr = &env->spr_cb[num];
621 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
622 #if !defined(CONFIG_USER_ONLY)
623 spr->oea_read != NULL || spr->oea_write != NULL ||
624 #endif
625 spr->uea_read != NULL || spr->uea_write != NULL) {
626 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
627 exit(1);
628 }
629 #if defined(PPC_DEBUG_SPR)
630 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
631 name, initial_value);
632 #endif
633 spr->name = name;
634 spr->uea_read = uea_read;
635 spr->uea_write = uea_write;
636 #if !defined(CONFIG_USER_ONLY)
637 spr->oea_read = oea_read;
638 spr->oea_write = oea_write;
639 #endif
640 #if defined(CONFIG_KVM)
641 spr->one_reg_id = one_reg_id,
642 #endif
643 env->spr[num] = spr->default_value = initial_value;
644 }
645
646 /* Generic PowerPC SPRs */
647 static void gen_spr_generic (CPUPPCState *env)
648 {
649 /* Integer processing */
650 spr_register(env, SPR_XER, "XER",
651 &spr_read_xer, &spr_write_xer,
652 &spr_read_xer, &spr_write_xer,
653 0x00000000);
654 /* Branch contol */
655 spr_register(env, SPR_LR, "LR",
656 &spr_read_lr, &spr_write_lr,
657 &spr_read_lr, &spr_write_lr,
658 0x00000000);
659 spr_register(env, SPR_CTR, "CTR",
660 &spr_read_ctr, &spr_write_ctr,
661 &spr_read_ctr, &spr_write_ctr,
662 0x00000000);
663 /* Interrupt processing */
664 spr_register(env, SPR_SRR0, "SRR0",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_generic, &spr_write_generic,
667 0x00000000);
668 spr_register(env, SPR_SRR1, "SRR1",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672 /* Processor control */
673 spr_register(env, SPR_SPRG0, "SPRG0",
674 SPR_NOACCESS, SPR_NOACCESS,
675 &spr_read_generic, &spr_write_generic,
676 0x00000000);
677 spr_register(env, SPR_SPRG1, "SPRG1",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_generic, &spr_write_generic,
680 0x00000000);
681 spr_register(env, SPR_SPRG2, "SPRG2",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 0x00000000);
685 spr_register(env, SPR_SPRG3, "SPRG3",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_generic, &spr_write_generic,
688 0x00000000);
689 }
690
691 /* SPR common to all non-embedded PowerPC, including 601 */
692 static void gen_spr_ne_601 (CPUPPCState *env)
693 {
694 /* Exception processing */
695 spr_register_kvm(env, SPR_DSISR, "DSISR",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_generic, &spr_write_generic,
698 KVM_REG_PPC_DSISR, 0x00000000);
699 spr_register_kvm(env, SPR_DAR, "DAR",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, &spr_write_generic,
702 KVM_REG_PPC_DAR, 0x00000000);
703 /* Timer */
704 spr_register(env, SPR_DECR, "DECR",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_decr, &spr_write_decr,
707 0x00000000);
708 /* Memory management */
709 spr_register(env, SPR_SDR1, "SDR1",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_sdr1,
712 0x00000000);
713 }
714
715 /* BATs 0-3 */
716 static void gen_low_BATs (CPUPPCState *env)
717 {
718 #if !defined(CONFIG_USER_ONLY)
719 spr_register(env, SPR_IBAT0U, "IBAT0U",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_ibat, &spr_write_ibatu,
722 0x00000000);
723 spr_register(env, SPR_IBAT0L, "IBAT0L",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_ibat, &spr_write_ibatl,
726 0x00000000);
727 spr_register(env, SPR_IBAT1U, "IBAT1U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_ibat, &spr_write_ibatu,
730 0x00000000);
731 spr_register(env, SPR_IBAT1L, "IBAT1L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_ibat, &spr_write_ibatl,
734 0x00000000);
735 spr_register(env, SPR_IBAT2U, "IBAT2U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_ibat, &spr_write_ibatu,
738 0x00000000);
739 spr_register(env, SPR_IBAT2L, "IBAT2L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_ibat, &spr_write_ibatl,
742 0x00000000);
743 spr_register(env, SPR_IBAT3U, "IBAT3U",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_ibat, &spr_write_ibatu,
746 0x00000000);
747 spr_register(env, SPR_IBAT3L, "IBAT3L",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_ibat, &spr_write_ibatl,
750 0x00000000);
751 spr_register(env, SPR_DBAT0U, "DBAT0U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_dbat, &spr_write_dbatu,
754 0x00000000);
755 spr_register(env, SPR_DBAT0L, "DBAT0L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_dbat, &spr_write_dbatl,
758 0x00000000);
759 spr_register(env, SPR_DBAT1U, "DBAT1U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_dbat, &spr_write_dbatu,
762 0x00000000);
763 spr_register(env, SPR_DBAT1L, "DBAT1L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_dbat, &spr_write_dbatl,
766 0x00000000);
767 spr_register(env, SPR_DBAT2U, "DBAT2U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_dbat, &spr_write_dbatu,
770 0x00000000);
771 spr_register(env, SPR_DBAT2L, "DBAT2L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_dbat, &spr_write_dbatl,
774 0x00000000);
775 spr_register(env, SPR_DBAT3U, "DBAT3U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_dbat, &spr_write_dbatu,
778 0x00000000);
779 spr_register(env, SPR_DBAT3L, "DBAT3L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_dbat, &spr_write_dbatl,
782 0x00000000);
783 env->nb_BATs += 4;
784 #endif
785 }
786
787 /* BATs 4-7 */
788 static void gen_high_BATs (CPUPPCState *env)
789 {
790 #if !defined(CONFIG_USER_ONLY)
791 spr_register(env, SPR_IBAT4U, "IBAT4U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_ibat_h, &spr_write_ibatu_h,
794 0x00000000);
795 spr_register(env, SPR_IBAT4L, "IBAT4L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_ibat_h, &spr_write_ibatl_h,
798 0x00000000);
799 spr_register(env, SPR_IBAT5U, "IBAT5U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_ibat_h, &spr_write_ibatu_h,
802 0x00000000);
803 spr_register(env, SPR_IBAT5L, "IBAT5L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_ibat_h, &spr_write_ibatl_h,
806 0x00000000);
807 spr_register(env, SPR_IBAT6U, "IBAT6U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_ibat_h, &spr_write_ibatu_h,
810 0x00000000);
811 spr_register(env, SPR_IBAT6L, "IBAT6L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_ibat_h, &spr_write_ibatl_h,
814 0x00000000);
815 spr_register(env, SPR_IBAT7U, "IBAT7U",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_ibat_h, &spr_write_ibatu_h,
818 0x00000000);
819 spr_register(env, SPR_IBAT7L, "IBAT7L",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_ibat_h, &spr_write_ibatl_h,
822 0x00000000);
823 spr_register(env, SPR_DBAT4U, "DBAT4U",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_dbat_h, &spr_write_dbatu_h,
826 0x00000000);
827 spr_register(env, SPR_DBAT4L, "DBAT4L",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_dbat_h, &spr_write_dbatl_h,
830 0x00000000);
831 spr_register(env, SPR_DBAT5U, "DBAT5U",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_dbat_h, &spr_write_dbatu_h,
834 0x00000000);
835 spr_register(env, SPR_DBAT5L, "DBAT5L",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_dbat_h, &spr_write_dbatl_h,
838 0x00000000);
839 spr_register(env, SPR_DBAT6U, "DBAT6U",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_dbat_h, &spr_write_dbatu_h,
842 0x00000000);
843 spr_register(env, SPR_DBAT6L, "DBAT6L",
844 SPR_NOACCESS, SPR_NOACCESS,
845 &spr_read_dbat_h, &spr_write_dbatl_h,
846 0x00000000);
847 spr_register(env, SPR_DBAT7U, "DBAT7U",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_dbat_h, &spr_write_dbatu_h,
850 0x00000000);
851 spr_register(env, SPR_DBAT7L, "DBAT7L",
852 SPR_NOACCESS, SPR_NOACCESS,
853 &spr_read_dbat_h, &spr_write_dbatl_h,
854 0x00000000);
855 env->nb_BATs += 4;
856 #endif
857 }
858
859 /* Generic PowerPC time base */
860 static void gen_tbl (CPUPPCState *env)
861 {
862 spr_register(env, SPR_VTBL, "TBL",
863 &spr_read_tbl, SPR_NOACCESS,
864 &spr_read_tbl, SPR_NOACCESS,
865 0x00000000);
866 spr_register(env, SPR_TBL, "TBL",
867 &spr_read_tbl, SPR_NOACCESS,
868 &spr_read_tbl, &spr_write_tbl,
869 0x00000000);
870 spr_register(env, SPR_VTBU, "TBU",
871 &spr_read_tbu, SPR_NOACCESS,
872 &spr_read_tbu, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_TBU, "TBU",
875 &spr_read_tbu, SPR_NOACCESS,
876 &spr_read_tbu, &spr_write_tbu,
877 0x00000000);
878 }
879
880 /* Softare table search registers */
881 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
882 {
883 #if !defined(CONFIG_USER_ONLY)
884 env->nb_tlb = nb_tlbs;
885 env->nb_ways = nb_ways;
886 env->id_tlbs = 1;
887 env->tlb_type = TLB_6XX;
888 spr_register(env, SPR_DMISS, "DMISS",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, SPR_NOACCESS,
891 0x00000000);
892 spr_register(env, SPR_DCMP, "DCMP",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, SPR_NOACCESS,
895 0x00000000);
896 spr_register(env, SPR_HASH1, "HASH1",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, SPR_NOACCESS,
899 0x00000000);
900 spr_register(env, SPR_HASH2, "HASH2",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, SPR_NOACCESS,
903 0x00000000);
904 spr_register(env, SPR_IMISS, "IMISS",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, SPR_NOACCESS,
907 0x00000000);
908 spr_register(env, SPR_ICMP, "ICMP",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, SPR_NOACCESS,
911 0x00000000);
912 spr_register(env, SPR_RPA, "RPA",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916 #endif
917 }
918
919 /* SPR common to MPC755 and G2 */
920 static void gen_spr_G2_755 (CPUPPCState *env)
921 {
922 /* SGPRs */
923 spr_register(env, SPR_SPRG4, "SPRG4",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
927 spr_register(env, SPR_SPRG5, "SPRG5",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931 spr_register(env, SPR_SPRG6, "SPRG6",
932 SPR_NOACCESS, SPR_NOACCESS,
933 &spr_read_generic, &spr_write_generic,
934 0x00000000);
935 spr_register(env, SPR_SPRG7, "SPRG7",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 }
940
941 /* SPR common to all 7xx PowerPC implementations */
942 static void gen_spr_7xx (CPUPPCState *env)
943 {
944 /* Breakpoints */
945 /* XXX : not implemented */
946 spr_register_kvm(env, SPR_DABR, "DABR",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_generic,
949 KVM_REG_PPC_DABR, 0x00000000);
950 /* XXX : not implemented */
951 spr_register(env, SPR_IABR, "IABR",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955 /* Cache management */
956 /* XXX : not implemented */
957 spr_register(env, SPR_ICTC, "ICTC",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, &spr_write_generic,
960 0x00000000);
961 /* Performance monitors */
962 /* XXX : not implemented */
963 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, &spr_write_generic,
966 0x00000000);
967 /* XXX : not implemented */
968 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
969 SPR_NOACCESS, SPR_NOACCESS,
970 &spr_read_generic, &spr_write_generic,
971 0x00000000);
972 /* XXX : not implemented */
973 spr_register(env, SPR_7XX_PMC1, "PMC1",
974 SPR_NOACCESS, SPR_NOACCESS,
975 &spr_read_generic, &spr_write_generic,
976 0x00000000);
977 /* XXX : not implemented */
978 spr_register(env, SPR_7XX_PMC2, "PMC2",
979 SPR_NOACCESS, SPR_NOACCESS,
980 &spr_read_generic, &spr_write_generic,
981 0x00000000);
982 /* XXX : not implemented */
983 spr_register(env, SPR_7XX_PMC3, "PMC3",
984 SPR_NOACCESS, SPR_NOACCESS,
985 &spr_read_generic, &spr_write_generic,
986 0x00000000);
987 /* XXX : not implemented */
988 spr_register(env, SPR_7XX_PMC4, "PMC4",
989 SPR_NOACCESS, SPR_NOACCESS,
990 &spr_read_generic, &spr_write_generic,
991 0x00000000);
992 /* XXX : not implemented */
993 spr_register(env, SPR_7XX_SIAR, "SIAR",
994 SPR_NOACCESS, SPR_NOACCESS,
995 &spr_read_generic, SPR_NOACCESS,
996 0x00000000);
997 /* XXX : not implemented */
998 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
999 &spr_read_ureg, SPR_NOACCESS,
1000 &spr_read_ureg, SPR_NOACCESS,
1001 0x00000000);
1002 /* XXX : not implemented */
1003 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1004 &spr_read_ureg, SPR_NOACCESS,
1005 &spr_read_ureg, SPR_NOACCESS,
1006 0x00000000);
1007 /* XXX : not implemented */
1008 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1009 &spr_read_ureg, SPR_NOACCESS,
1010 &spr_read_ureg, SPR_NOACCESS,
1011 0x00000000);
1012 /* XXX : not implemented */
1013 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1014 &spr_read_ureg, SPR_NOACCESS,
1015 &spr_read_ureg, SPR_NOACCESS,
1016 0x00000000);
1017 /* XXX : not implemented */
1018 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1019 &spr_read_ureg, SPR_NOACCESS,
1020 &spr_read_ureg, SPR_NOACCESS,
1021 0x00000000);
1022 /* XXX : not implemented */
1023 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1024 &spr_read_ureg, SPR_NOACCESS,
1025 &spr_read_ureg, SPR_NOACCESS,
1026 0x00000000);
1027 /* XXX : not implemented */
1028 spr_register(env, SPR_7XX_USIAR, "USIAR",
1029 &spr_read_ureg, SPR_NOACCESS,
1030 &spr_read_ureg, SPR_NOACCESS,
1031 0x00000000);
1032 /* External access control */
1033 /* XXX : not implemented */
1034 spr_register(env, SPR_EAR, "EAR",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 }
1039
1040 #ifdef TARGET_PPC64
1041 #ifndef CONFIG_USER_ONLY
1042 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1043 {
1044 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1045 spr_load_dump_spr(SPR_AMR);
1046 }
1047
1048 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1049 {
1050 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1051 spr_store_dump_spr(SPR_AMR);
1052 }
1053
1054 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1055 {
1056 TCGv t0 = tcg_temp_new();
1057
1058 gen_load_spr(t0, SPR_UAMOR);
1059 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1060 gen_store_spr(SPR_AMR, t0);
1061 spr_store_dump_spr(SPR_AMR);
1062 }
1063 #endif /* CONFIG_USER_ONLY */
1064
1065 static void gen_spr_amr (CPUPPCState *env)
1066 {
1067 #ifndef CONFIG_USER_ONLY
1068 /* Virtual Page Class Key protection */
1069 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1070 * userspace accessible, 29 is privileged. So we only need to set
1071 * the kvm ONE_REG id on one of them, we use 29 */
1072 spr_register(env, SPR_UAMR, "UAMR",
1073 &spr_read_uamr, &spr_write_uamr_pr,
1074 &spr_read_uamr, &spr_write_uamr,
1075 0);
1076 spr_register_kvm(env, SPR_AMR, "AMR",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, &spr_write_generic,
1079 KVM_REG_PPC_AMR, 0);
1080 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 KVM_REG_PPC_UAMOR, 0);
1084 #endif /* !CONFIG_USER_ONLY */
1085 }
1086 #endif /* TARGET_PPC64 */
1087
1088 static void gen_spr_thrm (CPUPPCState *env)
1089 {
1090 /* Thermal management */
1091 /* XXX : not implemented */
1092 spr_register(env, SPR_THRM1, "THRM1",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, &spr_write_generic,
1095 0x00000000);
1096 /* XXX : not implemented */
1097 spr_register(env, SPR_THRM2, "THRM2",
1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_generic, &spr_write_generic,
1100 0x00000000);
1101 /* XXX : not implemented */
1102 spr_register(env, SPR_THRM3, "THRM3",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_generic, &spr_write_generic,
1105 0x00000000);
1106 }
1107
1108 /* SPR specific to PowerPC 604 implementation */
1109 static void gen_spr_604 (CPUPPCState *env)
1110 {
1111 /* Processor identification */
1112 spr_register(env, SPR_PIR, "PIR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_pir,
1115 0x00000000);
1116 /* Breakpoints */
1117 /* XXX : not implemented */
1118 spr_register(env, SPR_IABR, "IABR",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_generic, &spr_write_generic,
1121 0x00000000);
1122 /* XXX : not implemented */
1123 spr_register_kvm(env, SPR_DABR, "DABR",
1124 SPR_NOACCESS, SPR_NOACCESS,
1125 &spr_read_generic, &spr_write_generic,
1126 KVM_REG_PPC_DABR, 0x00000000);
1127 /* Performance counters */
1128 /* XXX : not implemented */
1129 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_generic, &spr_write_generic,
1132 0x00000000);
1133 /* XXX : not implemented */
1134 spr_register(env, SPR_7XX_PMC1, "PMC1",
1135 SPR_NOACCESS, SPR_NOACCESS,
1136 &spr_read_generic, &spr_write_generic,
1137 0x00000000);
1138 /* XXX : not implemented */
1139 spr_register(env, SPR_7XX_PMC2, "PMC2",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_generic, &spr_write_generic,
1142 0x00000000);
1143 /* XXX : not implemented */
1144 spr_register(env, SPR_7XX_SIAR, "SIAR",
1145 SPR_NOACCESS, SPR_NOACCESS,
1146 &spr_read_generic, SPR_NOACCESS,
1147 0x00000000);
1148 /* XXX : not implemented */
1149 spr_register(env, SPR_SDA, "SDA",
1150 SPR_NOACCESS, SPR_NOACCESS,
1151 &spr_read_generic, SPR_NOACCESS,
1152 0x00000000);
1153 /* External access control */
1154 /* XXX : not implemented */
1155 spr_register(env, SPR_EAR, "EAR",
1156 SPR_NOACCESS, SPR_NOACCESS,
1157 &spr_read_generic, &spr_write_generic,
1158 0x00000000);
1159 }
1160
1161 /* SPR specific to PowerPC 603 implementation */
1162 static void gen_spr_603 (CPUPPCState *env)
1163 {
1164 /* External access control */
1165 /* XXX : not implemented */
1166 spr_register(env, SPR_EAR, "EAR",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 &spr_read_generic, &spr_write_generic,
1169 0x00000000);
1170 /* Breakpoints */
1171 /* XXX : not implemented */
1172 spr_register(env, SPR_IABR, "IABR",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176
1177 }
1178
1179 /* SPR specific to PowerPC G2 implementation */
1180 static void gen_spr_G2 (CPUPPCState *env)
1181 {
1182 /* Memory base address */
1183 /* MBAR */
1184 /* XXX : not implemented */
1185 spr_register(env, SPR_MBAR, "MBAR",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* Exception processing */
1190 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198 /* Breakpoints */
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_DABR, "DABR",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204 /* XXX : not implemented */
1205 spr_register(env, SPR_DABR2, "DABR2",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 /* XXX : not implemented */
1210 spr_register(env, SPR_IABR, "IABR",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_generic,
1213 0x00000000);
1214 /* XXX : not implemented */
1215 spr_register(env, SPR_IABR2, "IABR2",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_generic,
1218 0x00000000);
1219 /* XXX : not implemented */
1220 spr_register(env, SPR_IBCR, "IBCR",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* XXX : not implemented */
1225 spr_register(env, SPR_DBCR, "DBCR",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_generic, &spr_write_generic,
1228 0x00000000);
1229 }
1230
1231 /* SPR specific to PowerPC 602 implementation */
1232 static void gen_spr_602 (CPUPPCState *env)
1233 {
1234 /* ESA registers */
1235 /* XXX : not implemented */
1236 spr_register(env, SPR_SER, "SER",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 /* XXX : not implemented */
1241 spr_register(env, SPR_SEBR, "SEBR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 /* XXX : not implemented */
1246 spr_register(env, SPR_ESASRR, "ESASRR",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_generic, &spr_write_generic,
1249 0x00000000);
1250 /* Floating point status */
1251 /* XXX : not implemented */
1252 spr_register(env, SPR_SP, "SP",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, &spr_write_generic,
1255 0x00000000);
1256 /* XXX : not implemented */
1257 spr_register(env, SPR_LT, "LT",
1258 SPR_NOACCESS, SPR_NOACCESS,
1259 &spr_read_generic, &spr_write_generic,
1260 0x00000000);
1261 /* Watchdog timer */
1262 /* XXX : not implemented */
1263 spr_register(env, SPR_TCR, "TCR",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_generic, &spr_write_generic,
1266 0x00000000);
1267 /* Interrupt base */
1268 spr_register(env, SPR_IBR, "IBR",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1271 0x00000000);
1272 /* XXX : not implemented */
1273 spr_register(env, SPR_IABR, "IABR",
1274 SPR_NOACCESS, SPR_NOACCESS,
1275 &spr_read_generic, &spr_write_generic,
1276 0x00000000);
1277 }
1278
1279 /* SPR specific to PowerPC 601 implementation */
1280 static void gen_spr_601 (CPUPPCState *env)
1281 {
1282 /* Multiplication/division register */
1283 /* MQ */
1284 spr_register(env, SPR_MQ, "MQ",
1285 &spr_read_generic, &spr_write_generic,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 /* RTC registers */
1289 spr_register(env, SPR_601_RTCU, "RTCU",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 SPR_NOACCESS, &spr_write_601_rtcu,
1292 0x00000000);
1293 spr_register(env, SPR_601_VRTCU, "RTCU",
1294 &spr_read_601_rtcu, SPR_NOACCESS,
1295 &spr_read_601_rtcu, SPR_NOACCESS,
1296 0x00000000);
1297 spr_register(env, SPR_601_RTCL, "RTCL",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 SPR_NOACCESS, &spr_write_601_rtcl,
1300 0x00000000);
1301 spr_register(env, SPR_601_VRTCL, "RTCL",
1302 &spr_read_601_rtcl, SPR_NOACCESS,
1303 &spr_read_601_rtcl, SPR_NOACCESS,
1304 0x00000000);
1305 /* Timer */
1306 #if 0 /* ? */
1307 spr_register(env, SPR_601_UDECR, "UDECR",
1308 &spr_read_decr, SPR_NOACCESS,
1309 &spr_read_decr, SPR_NOACCESS,
1310 0x00000000);
1311 #endif
1312 /* External access control */
1313 /* XXX : not implemented */
1314 spr_register(env, SPR_EAR, "EAR",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318 /* Memory management */
1319 #if !defined(CONFIG_USER_ONLY)
1320 spr_register(env, SPR_IBAT0U, "IBAT0U",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_601_ubat, &spr_write_601_ubatu,
1323 0x00000000);
1324 spr_register(env, SPR_IBAT0L, "IBAT0L",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_601_ubat, &spr_write_601_ubatl,
1327 0x00000000);
1328 spr_register(env, SPR_IBAT1U, "IBAT1U",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_601_ubat, &spr_write_601_ubatu,
1331 0x00000000);
1332 spr_register(env, SPR_IBAT1L, "IBAT1L",
1333 SPR_NOACCESS, SPR_NOACCESS,
1334 &spr_read_601_ubat, &spr_write_601_ubatl,
1335 0x00000000);
1336 spr_register(env, SPR_IBAT2U, "IBAT2U",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_601_ubat, &spr_write_601_ubatu,
1339 0x00000000);
1340 spr_register(env, SPR_IBAT2L, "IBAT2L",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_601_ubat, &spr_write_601_ubatl,
1343 0x00000000);
1344 spr_register(env, SPR_IBAT3U, "IBAT3U",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_601_ubat, &spr_write_601_ubatu,
1347 0x00000000);
1348 spr_register(env, SPR_IBAT3L, "IBAT3L",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_601_ubat, &spr_write_601_ubatl,
1351 0x00000000);
1352 env->nb_BATs = 4;
1353 #endif
1354 }
1355
1356 static void gen_spr_74xx (CPUPPCState *env)
1357 {
1358 /* Processor identification */
1359 spr_register(env, SPR_PIR, "PIR",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_pir,
1362 0x00000000);
1363 /* XXX : not implemented */
1364 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368 /* XXX : not implemented */
1369 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1370 &spr_read_ureg, SPR_NOACCESS,
1371 &spr_read_ureg, SPR_NOACCESS,
1372 0x00000000);
1373 /* XXX: not implemented */
1374 spr_register(env, SPR_BAMR, "BAMR",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
1378 /* XXX : not implemented */
1379 spr_register(env, SPR_MSSCR0, "MSSCR0",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383 /* Hardware implementation registers */
1384 /* XXX : not implemented */
1385 spr_register(env, SPR_HID0, "HID0",
1386 SPR_NOACCESS, SPR_NOACCESS,
1387 &spr_read_generic, &spr_write_generic,
1388 0x00000000);
1389 /* XXX : not implemented */
1390 spr_register(env, SPR_HID1, "HID1",
1391 SPR_NOACCESS, SPR_NOACCESS,
1392 &spr_read_generic, &spr_write_generic,
1393 0x00000000);
1394 /* Altivec */
1395 spr_register(env, SPR_VRSAVE, "VRSAVE",
1396 &spr_read_generic, &spr_write_generic,
1397 &spr_read_generic, &spr_write_generic,
1398 0x00000000);
1399 /* XXX : not implemented */
1400 spr_register(env, SPR_L2CR, "L2CR",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, spr_access_nop,
1403 0x00000000);
1404 /* Not strictly an SPR */
1405 vscr_init(env, 0x00010000);
1406 }
1407
1408 static void gen_l3_ctrl (CPUPPCState *env)
1409 {
1410 /* L3CR */
1411 /* XXX : not implemented */
1412 spr_register(env, SPR_L3CR, "L3CR",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_generic,
1415 0x00000000);
1416 /* L3ITCR0 */
1417 /* XXX : not implemented */
1418 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_generic,
1421 0x00000000);
1422 /* L3PM */
1423 /* XXX : not implemented */
1424 spr_register(env, SPR_L3PM, "L3PM",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428 }
1429
1430 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1431 {
1432 #if !defined(CONFIG_USER_ONLY)
1433 env->nb_tlb = nb_tlbs;
1434 env->nb_ways = nb_ways;
1435 env->id_tlbs = 1;
1436 env->tlb_type = TLB_6XX;
1437 /* XXX : not implemented */
1438 spr_register(env, SPR_PTEHI, "PTEHI",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_generic, &spr_write_generic,
1441 0x00000000);
1442 /* XXX : not implemented */
1443 spr_register(env, SPR_PTELO, "PTELO",
1444 SPR_NOACCESS, SPR_NOACCESS,
1445 &spr_read_generic, &spr_write_generic,
1446 0x00000000);
1447 /* XXX : not implemented */
1448 spr_register(env, SPR_TLBMISS, "TLBMISS",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
1452 #endif
1453 }
1454
1455 #if !defined(CONFIG_USER_ONLY)
1456 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1457 {
1458 TCGv t0 = tcg_temp_new();
1459
1460 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1461 gen_store_spr(sprn, t0);
1462 tcg_temp_free(t0);
1463 }
1464
1465 static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn)
1466 {
1467 TCGv t0 = tcg_temp_new();
1468
1469 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1470 gen_store_spr(sprn, t0);
1471 tcg_temp_free(t0);
1472 }
1473
1474 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1475 {
1476 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1477 }
1478
1479 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1480 {
1481 TCGv_i32 t0 = tcg_const_i32(sprn);
1482 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1483 tcg_temp_free_i32(t0);
1484 }
1485 #endif
1486
1487 static void gen_spr_usprgh (CPUPPCState *env)
1488 {
1489 spr_register(env, SPR_USPRG4, "USPRG4",
1490 &spr_read_ureg, SPR_NOACCESS,
1491 &spr_read_ureg, SPR_NOACCESS,
1492 0x00000000);
1493 spr_register(env, SPR_USPRG5, "USPRG5",
1494 &spr_read_ureg, SPR_NOACCESS,
1495 &spr_read_ureg, SPR_NOACCESS,
1496 0x00000000);
1497 spr_register(env, SPR_USPRG6, "USPRG6",
1498 &spr_read_ureg, SPR_NOACCESS,
1499 &spr_read_ureg, SPR_NOACCESS,
1500 0x00000000);
1501 spr_register(env, SPR_USPRG7, "USPRG7",
1502 &spr_read_ureg, SPR_NOACCESS,
1503 &spr_read_ureg, SPR_NOACCESS,
1504 0x00000000);
1505 }
1506
1507 /* PowerPC BookE SPR */
1508 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1509 {
1510 const char *ivor_names[64] = {
1511 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1512 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1513 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1514 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1515 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1516 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1517 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1518 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1519 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1520 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1521 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1522 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1523 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1524 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1525 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1526 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1527 };
1528 #define SPR_BOOKE_IVORxx (-1)
1529 int ivor_sprn[64] = {
1530 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1531 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1532 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1533 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1534 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1535 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1536 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1537 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1538 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1539 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1540 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1541 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1542 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1543 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1544 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1545 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1546 };
1547 int i;
1548
1549 /* Interrupt processing */
1550 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
1558 /* Debug */
1559 /* XXX : not implemented */
1560 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 /* XXX : not implemented */
1565 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 /* XXX : not implemented */
1570 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574 /* XXX : not implemented */
1575 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_generic,
1578 0x00000000);
1579 /* XXX : not implemented */
1580 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_40x_dbcr0,
1583 0x00000000);
1584 /* XXX : not implemented */
1585 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_generic,
1588 0x00000000);
1589 /* XXX : not implemented */
1590 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, &spr_write_generic,
1593 0x00000000);
1594 /* XXX : not implemented */
1595 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_clear,
1598 0x00000000);
1599 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_generic,
1602 0x00000000);
1603 spr_register(env, SPR_BOOKE_ESR, "ESR",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1606 0x00000000);
1607 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1608 SPR_NOACCESS, SPR_NOACCESS,
1609 &spr_read_generic, &spr_write_excp_prefix,
1610 0x00000000);
1611 /* Exception vectors */
1612 for (i = 0; i < 64; i++) {
1613 if (ivor_mask & (1ULL << i)) {
1614 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1615 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1616 exit(1);
1617 }
1618 spr_register(env, ivor_sprn[i], ivor_names[i],
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_generic, &spr_write_excp_vector,
1621 0x00000000);
1622 }
1623 }
1624 spr_register(env, SPR_BOOKE_PID, "PID",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_booke_pid,
1627 0x00000000);
1628 spr_register(env, SPR_BOOKE_TCR, "TCR",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_booke_tcr,
1631 0x00000000);
1632 spr_register(env, SPR_BOOKE_TSR, "TSR",
1633 SPR_NOACCESS, SPR_NOACCESS,
1634 &spr_read_generic, &spr_write_booke_tsr,
1635 0x00000000);
1636 /* Timer */
1637 spr_register(env, SPR_DECR, "DECR",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_decr, &spr_write_decr,
1640 0x00000000);
1641 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1642 SPR_NOACCESS, SPR_NOACCESS,
1643 SPR_NOACCESS, &spr_write_generic,
1644 0x00000000);
1645 /* SPRGs */
1646 spr_register(env, SPR_USPRG0, "USPRG0",
1647 &spr_read_generic, &spr_write_generic,
1648 &spr_read_generic, &spr_write_generic,
1649 0x00000000);
1650 spr_register(env, SPR_SPRG4, "SPRG4",
1651 SPR_NOACCESS, SPR_NOACCESS,
1652 &spr_read_generic, &spr_write_generic,
1653 0x00000000);
1654 spr_register(env, SPR_SPRG5, "SPRG5",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, &spr_write_generic,
1657 0x00000000);
1658 spr_register(env, SPR_SPRG6, "SPRG6",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, &spr_write_generic,
1661 0x00000000);
1662 spr_register(env, SPR_SPRG7, "SPRG7",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic,
1665 0x00000000);
1666 }
1667
1668 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1669 uint32_t maxsize, uint32_t flags,
1670 uint32_t nentries)
1671 {
1672 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1673 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1674 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1675 flags | nentries;
1676 }
1677
1678 /* BookE 2.06 storage control registers */
1679 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1680 uint32_t *tlbncfg)
1681 {
1682 #if !defined(CONFIG_USER_ONLY)
1683 const char *mas_names[8] = {
1684 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1685 };
1686 int mas_sprn[8] = {
1687 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1688 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1689 };
1690 int i;
1691
1692 /* TLB assist registers */
1693 /* XXX : not implemented */
1694 for (i = 0; i < 8; i++) {
1695 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1696 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1697 uea_write = &spr_write_generic;
1698 }
1699 if (mas_mask & (1 << i)) {
1700 spr_register(env, mas_sprn[i], mas_names[i],
1701 SPR_NOACCESS, SPR_NOACCESS,
1702 &spr_read_generic, uea_write,
1703 0x00000000);
1704 }
1705 }
1706 if (env->nb_pids > 1) {
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_BOOKE_PID1, "PID1",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_booke_pid,
1711 0x00000000);
1712 }
1713 if (env->nb_pids > 2) {
1714 /* XXX : not implemented */
1715 spr_register(env, SPR_BOOKE_PID2, "PID2",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, &spr_write_booke_pid,
1718 0x00000000);
1719 }
1720 /* XXX : not implemented */
1721 spr_register(env, SPR_MMUCFG, "MMUCFG",
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, SPR_NOACCESS,
1724 0x00000000); /* TOFIX */
1725 switch (env->nb_ways) {
1726 case 4:
1727 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1728 SPR_NOACCESS, SPR_NOACCESS,
1729 &spr_read_generic, SPR_NOACCESS,
1730 tlbncfg[3]);
1731 /* Fallthru */
1732 case 3:
1733 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, SPR_NOACCESS,
1736 tlbncfg[2]);
1737 /* Fallthru */
1738 case 2:
1739 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, SPR_NOACCESS,
1742 tlbncfg[1]);
1743 /* Fallthru */
1744 case 1:
1745 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, SPR_NOACCESS,
1748 tlbncfg[0]);
1749 /* Fallthru */
1750 case 0:
1751 default:
1752 break;
1753 }
1754 #endif
1755
1756 gen_spr_usprgh(env);
1757 }
1758
1759 /* SPR specific to PowerPC 440 implementation */
1760 static void gen_spr_440 (CPUPPCState *env)
1761 {
1762 /* Cache control */
1763 /* XXX : not implemented */
1764 spr_register(env, SPR_440_DNV0, "DNV0",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, &spr_write_generic,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_440_DNV1, "DNV1",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_440_DNV2, "DNV2",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* XXX : not implemented */
1779 spr_register(env, SPR_440_DNV3, "DNV3",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
1782 0x00000000);
1783 /* XXX : not implemented */
1784 spr_register(env, SPR_440_DTV0, "DTV0",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_generic,
1787 0x00000000);
1788 /* XXX : not implemented */
1789 spr_register(env, SPR_440_DTV1, "DTV1",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_generic,
1792 0x00000000);
1793 /* XXX : not implemented */
1794 spr_register(env, SPR_440_DTV2, "DTV2",
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, &spr_write_generic,
1797 0x00000000);
1798 /* XXX : not implemented */
1799 spr_register(env, SPR_440_DTV3, "DTV3",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* XXX : not implemented */
1804 spr_register(env, SPR_440_DVLIM, "DVLIM",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 /* XXX : not implemented */
1809 spr_register(env, SPR_440_INV0, "INV0",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_generic,
1812 0x00000000);
1813 /* XXX : not implemented */
1814 spr_register(env, SPR_440_INV1, "INV1",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 /* XXX : not implemented */
1819 spr_register(env, SPR_440_INV2, "INV2",
1820 SPR_NOACCESS, SPR_NOACCESS,
1821 &spr_read_generic, &spr_write_generic,
1822 0x00000000);
1823 /* XXX : not implemented */
1824 spr_register(env, SPR_440_INV3, "INV3",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 /* XXX : not implemented */
1829 spr_register(env, SPR_440_ITV0, "ITV0",
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic,
1832 0x00000000);
1833 /* XXX : not implemented */
1834 spr_register(env, SPR_440_ITV1, "ITV1",
1835 SPR_NOACCESS, SPR_NOACCESS,
1836 &spr_read_generic, &spr_write_generic,
1837 0x00000000);
1838 /* XXX : not implemented */
1839 spr_register(env, SPR_440_ITV2, "ITV2",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_generic,
1842 0x00000000);
1843 /* XXX : not implemented */
1844 spr_register(env, SPR_440_ITV3, "ITV3",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_generic,
1847 0x00000000);
1848 /* XXX : not implemented */
1849 spr_register(env, SPR_440_IVLIM, "IVLIM",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
1853 /* Cache debug */
1854 /* XXX : not implemented */
1855 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1856 SPR_NOACCESS, SPR_NOACCESS,
1857 &spr_read_generic, SPR_NOACCESS,
1858 0x00000000);
1859 /* XXX : not implemented */
1860 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1861 SPR_NOACCESS, SPR_NOACCESS,
1862 &spr_read_generic, SPR_NOACCESS,
1863 0x00000000);
1864 /* XXX : not implemented */
1865 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1866 SPR_NOACCESS, SPR_NOACCESS,
1867 &spr_read_generic, SPR_NOACCESS,
1868 0x00000000);
1869 /* XXX : not implemented */
1870 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_generic, SPR_NOACCESS,
1873 0x00000000);
1874 /* XXX : not implemented */
1875 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1876 SPR_NOACCESS, SPR_NOACCESS,
1877 &spr_read_generic, SPR_NOACCESS,
1878 0x00000000);
1879 /* XXX : not implemented */
1880 spr_register(env, SPR_440_DBDR, "DBDR",
1881 SPR_NOACCESS, SPR_NOACCESS,
1882 &spr_read_generic, &spr_write_generic,
1883 0x00000000);
1884 /* Processor control */
1885 spr_register(env, SPR_4xx_CCR0, "CCR0",
1886 SPR_NOACCESS, SPR_NOACCESS,
1887 &spr_read_generic, &spr_write_generic,
1888 0x00000000);
1889 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, SPR_NOACCESS,
1892 0x00000000);
1893 /* Storage control */
1894 spr_register(env, SPR_440_MMUCR, "MMUCR",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 }
1899
1900 /* SPR shared between PowerPC 40x implementations */
1901 static void gen_spr_40x (CPUPPCState *env)
1902 {
1903 /* Cache */
1904 /* not emulated, as QEMU do not emulate caches */
1905 spr_register(env, SPR_40x_DCCR, "DCCR",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 /* not emulated, as QEMU do not emulate caches */
1910 spr_register(env, SPR_40x_ICCR, "ICCR",
1911 SPR_NOACCESS, SPR_NOACCESS,
1912 &spr_read_generic, &spr_write_generic,
1913 0x00000000);
1914 /* not emulated, as QEMU do not emulate caches */
1915 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1916 SPR_NOACCESS, SPR_NOACCESS,
1917 &spr_read_generic, SPR_NOACCESS,
1918 0x00000000);
1919 /* Exception */
1920 spr_register(env, SPR_40x_DEAR, "DEAR",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
1924 spr_register(env, SPR_40x_ESR, "ESR",
1925 SPR_NOACCESS, SPR_NOACCESS,
1926 &spr_read_generic, &spr_write_generic,
1927 0x00000000);
1928 spr_register(env, SPR_40x_EVPR, "EVPR",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_excp_prefix,
1931 0x00000000);
1932 spr_register(env, SPR_40x_SRR2, "SRR2",
1933 &spr_read_generic, &spr_write_generic,
1934 &spr_read_generic, &spr_write_generic,
1935 0x00000000);
1936 spr_register(env, SPR_40x_SRR3, "SRR3",
1937 &spr_read_generic, &spr_write_generic,
1938 &spr_read_generic, &spr_write_generic,
1939 0x00000000);
1940 /* Timers */
1941 spr_register(env, SPR_40x_PIT, "PIT",
1942 SPR_NOACCESS, SPR_NOACCESS,
1943 &spr_read_40x_pit, &spr_write_40x_pit,
1944 0x00000000);
1945 spr_register(env, SPR_40x_TCR, "TCR",
1946 SPR_NOACCESS, SPR_NOACCESS,
1947 &spr_read_generic, &spr_write_booke_tcr,
1948 0x00000000);
1949 spr_register(env, SPR_40x_TSR, "TSR",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, &spr_write_booke_tsr,
1952 0x00000000);
1953 }
1954
1955 /* SPR specific to PowerPC 405 implementation */
1956 static void gen_spr_405 (CPUPPCState *env)
1957 {
1958 /* MMU */
1959 spr_register(env, SPR_40x_PID, "PID",
1960 SPR_NOACCESS, SPR_NOACCESS,
1961 &spr_read_generic, &spr_write_generic,
1962 0x00000000);
1963 spr_register(env, SPR_4xx_CCR0, "CCR0",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 &spr_read_generic, &spr_write_generic,
1966 0x00700000);
1967 /* Debug interface */
1968 /* XXX : not implemented */
1969 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 &spr_read_generic, &spr_write_40x_dbcr0,
1972 0x00000000);
1973 /* XXX : not implemented */
1974 spr_register(env, SPR_405_DBCR1, "DBCR1",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978 /* XXX : not implemented */
1979 spr_register(env, SPR_40x_DBSR, "DBSR",
1980 SPR_NOACCESS, SPR_NOACCESS,
1981 &spr_read_generic, &spr_write_clear,
1982 /* Last reset was system reset */
1983 0x00000300);
1984 /* XXX : not implemented */
1985 spr_register(env, SPR_40x_DAC1, "DAC1",
1986 SPR_NOACCESS, SPR_NOACCESS,
1987 &spr_read_generic, &spr_write_generic,
1988 0x00000000);
1989 spr_register(env, SPR_40x_DAC2, "DAC2",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_generic,
1992 0x00000000);
1993 /* XXX : not implemented */
1994 spr_register(env, SPR_405_DVC1, "DVC1",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_generic,
1997 0x00000000);
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_405_DVC2, "DVC2",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* XXX : not implemented */
2004 spr_register(env, SPR_40x_IAC1, "IAC1",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 spr_register(env, SPR_40x_IAC2, "IAC2",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_generic,
2011 0x00000000);
2012 /* XXX : not implemented */
2013 spr_register(env, SPR_405_IAC3, "IAC3",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0x00000000);
2017 /* XXX : not implemented */
2018 spr_register(env, SPR_405_IAC4, "IAC4",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022 /* Storage control */
2023 /* XXX: TODO: not implemented */
2024 spr_register(env, SPR_405_SLER, "SLER",
2025 SPR_NOACCESS, SPR_NOACCESS,
2026 &spr_read_generic, &spr_write_40x_sler,
2027 0x00000000);
2028 spr_register(env, SPR_40x_ZPR, "ZPR",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_generic,
2031 0x00000000);
2032 /* XXX : not implemented */
2033 spr_register(env, SPR_405_SU0R, "SU0R",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_generic,
2036 0x00000000);
2037 /* SPRG */
2038 spr_register(env, SPR_USPRG0, "USPRG0",
2039 &spr_read_ureg, SPR_NOACCESS,
2040 &spr_read_ureg, SPR_NOACCESS,
2041 0x00000000);
2042 spr_register(env, SPR_SPRG4, "SPRG4",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
2046 spr_register(env, SPR_SPRG5, "SPRG5",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 spr_read_generic, &spr_write_generic,
2049 0x00000000);
2050 spr_register(env, SPR_SPRG6, "SPRG6",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 spr_read_generic, &spr_write_generic,
2053 0x00000000);
2054 spr_register(env, SPR_SPRG7, "SPRG7",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 spr_read_generic, &spr_write_generic,
2057 0x00000000);
2058 gen_spr_usprgh(env);
2059 }
2060
2061 /* SPR shared between PowerPC 401 & 403 implementations */
2062 static void gen_spr_401_403 (CPUPPCState *env)
2063 {
2064 /* Time base */
2065 spr_register(env, SPR_403_VTBL, "TBL",
2066 &spr_read_tbl, SPR_NOACCESS,
2067 &spr_read_tbl, SPR_NOACCESS,
2068 0x00000000);
2069 spr_register(env, SPR_403_TBL, "TBL",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 SPR_NOACCESS, &spr_write_tbl,
2072 0x00000000);
2073 spr_register(env, SPR_403_VTBU, "TBU",
2074 &spr_read_tbu, SPR_NOACCESS,
2075 &spr_read_tbu, SPR_NOACCESS,
2076 0x00000000);
2077 spr_register(env, SPR_403_TBU, "TBU",
2078 SPR_NOACCESS, SPR_NOACCESS,
2079 SPR_NOACCESS, &spr_write_tbu,
2080 0x00000000);
2081 /* Debug */
2082 /* not emulated, as QEMU do not emulate caches */
2083 spr_register(env, SPR_403_CDBCR, "CDBCR",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2087 }
2088
2089 /* SPR specific to PowerPC 401 implementation */
2090 static void gen_spr_401 (CPUPPCState *env)
2091 {
2092 /* Debug interface */
2093 /* XXX : not implemented */
2094 spr_register(env, SPR_40x_DBCR0, "DBCR",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_40x_dbcr0,
2097 0x00000000);
2098 /* XXX : not implemented */
2099 spr_register(env, SPR_40x_DBSR, "DBSR",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_clear,
2102 /* Last reset was system reset */
2103 0x00000300);
2104 /* XXX : not implemented */
2105 spr_register(env, SPR_40x_DAC1, "DAC",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0x00000000);
2109 /* XXX : not implemented */
2110 spr_register(env, SPR_40x_IAC1, "IAC",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
2114 /* Storage control */
2115 /* XXX: TODO: not implemented */
2116 spr_register(env, SPR_405_SLER, "SLER",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_generic, &spr_write_40x_sler,
2119 0x00000000);
2120 /* not emulated, as QEMU never does speculative access */
2121 spr_register(env, SPR_40x_SGR, "SGR",
2122 SPR_NOACCESS, SPR_NOACCESS,
2123 &spr_read_generic, &spr_write_generic,
2124 0xFFFFFFFF);
2125 /* not emulated, as QEMU do not emulate caches */
2126 spr_register(env, SPR_40x_DCWR, "DCWR",
2127 SPR_NOACCESS, SPR_NOACCESS,
2128 &spr_read_generic, &spr_write_generic,
2129 0x00000000);
2130 }
2131
2132 static void gen_spr_401x2 (CPUPPCState *env)
2133 {
2134 gen_spr_401(env);
2135 spr_register(env, SPR_40x_PID, "PID",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, &spr_write_generic,
2138 0x00000000);
2139 spr_register(env, SPR_40x_ZPR, "ZPR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 }
2144
2145 /* SPR specific to PowerPC 403 implementation */
2146 static void gen_spr_403 (CPUPPCState *env)
2147 {
2148 /* Debug interface */
2149 /* XXX : not implemented */
2150 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_40x_dbcr0,
2153 0x00000000);
2154 /* XXX : not implemented */
2155 spr_register(env, SPR_40x_DBSR, "DBSR",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_clear,
2158 /* Last reset was system reset */
2159 0x00000300);
2160 /* XXX : not implemented */
2161 spr_register(env, SPR_40x_DAC1, "DAC1",
2162 SPR_NOACCESS, SPR_NOACCESS,
2163 &spr_read_generic, &spr_write_generic,
2164 0x00000000);
2165 /* XXX : not implemented */
2166 spr_register(env, SPR_40x_DAC2, "DAC2",
2167 SPR_NOACCESS, SPR_NOACCESS,
2168 &spr_read_generic, &spr_write_generic,
2169 0x00000000);
2170 /* XXX : not implemented */
2171 spr_register(env, SPR_40x_IAC1, "IAC1",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 /* XXX : not implemented */
2176 spr_register(env, SPR_40x_IAC2, "IAC2",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_generic, &spr_write_generic,
2179 0x00000000);
2180 }
2181
2182 static void gen_spr_403_real (CPUPPCState *env)
2183 {
2184 spr_register(env, SPR_403_PBL1, "PBL1",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_403_pbr, &spr_write_403_pbr,
2187 0x00000000);
2188 spr_register(env, SPR_403_PBU1, "PBU1",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_403_pbr, &spr_write_403_pbr,
2191 0x00000000);
2192 spr_register(env, SPR_403_PBL2, "PBL2",
2193 SPR_NOACCESS, SPR_NOACCESS,
2194 &spr_read_403_pbr, &spr_write_403_pbr,
2195 0x00000000);
2196 spr_register(env, SPR_403_PBU2, "PBU2",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_403_pbr, &spr_write_403_pbr,
2199 0x00000000);
2200 }
2201
2202 static void gen_spr_403_mmu (CPUPPCState *env)
2203 {
2204 /* MMU */
2205 spr_register(env, SPR_40x_PID, "PID",
2206 SPR_NOACCESS, SPR_NOACCESS,
2207 &spr_read_generic, &spr_write_generic,
2208 0x00000000);
2209 spr_register(env, SPR_40x_ZPR, "ZPR",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_generic,
2212 0x00000000);
2213 }
2214
2215 /* SPR specific to PowerPC compression coprocessor extension */
2216 static void gen_spr_compress (CPUPPCState *env)
2217 {
2218 /* XXX : not implemented */
2219 spr_register(env, SPR_401_SKR, "SKR",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
2223 }
2224
2225 static void gen_spr_5xx_8xx (CPUPPCState *env)
2226 {
2227 /* Exception processing */
2228 spr_register_kvm(env, SPR_DSISR, "DSISR",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 KVM_REG_PPC_DSISR, 0x00000000);
2232 spr_register_kvm(env, SPR_DAR, "DAR",
2233 SPR_NOACCESS, SPR_NOACCESS,
2234 &spr_read_generic, &spr_write_generic,
2235 KVM_REG_PPC_DAR, 0x00000000);
2236 /* Timer */
2237 spr_register(env, SPR_DECR, "DECR",
2238 SPR_NOACCESS, SPR_NOACCESS,
2239 &spr_read_decr, &spr_write_decr,
2240 0x00000000);
2241 /* XXX : not implemented */
2242 spr_register(env, SPR_MPC_EIE, "EIE",
2243 SPR_NOACCESS, SPR_NOACCESS,
2244 &spr_read_generic, &spr_write_generic,
2245 0x00000000);
2246 /* XXX : not implemented */
2247 spr_register(env, SPR_MPC_EID, "EID",
2248 SPR_NOACCESS, SPR_NOACCESS,
2249 &spr_read_generic, &spr_write_generic,
2250 0x00000000);
2251 /* XXX : not implemented */
2252 spr_register(env, SPR_MPC_NRI, "NRI",
2253 SPR_NOACCESS, SPR_NOACCESS,
2254 &spr_read_generic, &spr_write_generic,
2255 0x00000000);
2256 /* XXX : not implemented */
2257 spr_register(env, SPR_MPC_CMPA, "CMPA",
2258 SPR_NOACCESS, SPR_NOACCESS,
2259 &spr_read_generic, &spr_write_generic,
2260 0x00000000);
2261 /* XXX : not implemented */
2262 spr_register(env, SPR_MPC_CMPB, "CMPB",
2263 SPR_NOACCESS, SPR_NOACCESS,
2264 &spr_read_generic, &spr_write_generic,
2265 0x00000000);
2266 /* XXX : not implemented */
2267 spr_register(env, SPR_MPC_CMPC, "CMPC",
2268 SPR_NOACCESS, SPR_NOACCESS,
2269 &spr_read_generic, &spr_write_generic,
2270 0x00000000);
2271 /* XXX : not implemented */
2272 spr_register(env, SPR_MPC_CMPD, "CMPD",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_generic,
2275 0x00000000);
2276 /* XXX : not implemented */
2277 spr_register(env, SPR_MPC_ECR, "ECR",
2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_generic,
2280 0x00000000);
2281 /* XXX : not implemented */
2282 spr_register(env, SPR_MPC_DER, "DER",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2286 /* XXX : not implemented */
2287 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0x00000000);
2291 /* XXX : not implemented */
2292 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2293 SPR_NOACCESS, SPR_NOACCESS,
2294 &spr_read_generic, &spr_write_generic,
2295 0x00000000);
2296 /* XXX : not implemented */
2297 spr_register(env, SPR_MPC_CMPE, "CMPE",
2298 SPR_NOACCESS, SPR_NOACCESS,
2299 &spr_read_generic, &spr_write_generic,
2300 0x00000000);
2301 /* XXX : not implemented */
2302 spr_register(env, SPR_MPC_CMPF, "CMPF",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_generic, &spr_write_generic,
2305 0x00000000);
2306 /* XXX : not implemented */
2307 spr_register(env, SPR_MPC_CMPG, "CMPG",
2308 SPR_NOACCESS, SPR_NOACCESS,
2309 &spr_read_generic, &spr_write_generic,
2310 0x00000000);
2311 /* XXX : not implemented */
2312 spr_register(env, SPR_MPC_CMPH, "CMPH",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 /* XXX : not implemented */
2317 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_generic, &spr_write_generic,
2320 0x00000000);
2321 /* XXX : not implemented */
2322 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 0x00000000);
2326 /* XXX : not implemented */
2327 spr_register(env, SPR_MPC_BAR, "BAR",
2328 SPR_NOACCESS, SPR_NOACCESS,
2329 &spr_read_generic, &spr_write_generic,
2330 0x00000000);
2331 /* XXX : not implemented */
2332 spr_register(env, SPR_MPC_DPDR, "DPDR",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 &spr_read_generic, &spr_write_generic,
2335 0x00000000);
2336 /* XXX : not implemented */
2337 spr_register(env, SPR_MPC_IMMR, "IMMR",
2338 SPR_NOACCESS, SPR_NOACCESS,
2339 &spr_read_generic, &spr_write_generic,
2340 0x00000000);
2341 }
2342
2343 static void gen_spr_5xx (CPUPPCState *env)
2344 {
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* XXX : not implemented */
2351 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355 /* XXX : not implemented */
2356 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360 /* XXX : not implemented */
2361 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2365 /* XXX : not implemented */
2366 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 /* XXX : not implemented */
2371 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 /* XXX : not implemented */
2416 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2417 SPR_NOACCESS, SPR_NOACCESS,
2418 &spr_read_generic, &spr_write_generic,
2419 0x00000000);
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 /* XXX : not implemented */
2436 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440 /* XXX : not implemented */
2441 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445 /* XXX : not implemented */
2446 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450 }
2451
2452 static void gen_spr_8xx (CPUPPCState *env)
2453 {
2454 /* XXX : not implemented */
2455 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 /* XXX : not implemented */
2460 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2461 SPR_NOACCESS, SPR_NOACCESS,
2462 &spr_read_generic, &spr_write_generic,
2463 0x00000000);
2464 /* XXX : not implemented */
2465 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 /* XXX : not implemented */
2470 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_generic, &spr_write_generic,
2473 0x00000000);
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 /* XXX : not implemented */
2525 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2526 SPR_NOACCESS, SPR_NOACCESS,
2527 &spr_read_generic, &spr_write_generic,
2528 0x00000000);
2529 /* XXX : not implemented */
2530 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2531 SPR_NOACCESS, SPR_NOACCESS,
2532 &spr_read_generic, &spr_write_generic,
2533 0x00000000);
2534 /* XXX : not implemented */
2535 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2536 SPR_NOACCESS, SPR_NOACCESS,
2537 &spr_read_generic, &spr_write_generic,
2538 0x00000000);
2539 /* XXX : not implemented */
2540 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2541 SPR_NOACCESS, SPR_NOACCESS,
2542 &spr_read_generic, &spr_write_generic,
2543 0x00000000);
2544 /* XXX : not implemented */
2545 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2546 SPR_NOACCESS, SPR_NOACCESS,
2547 &spr_read_generic, &spr_write_generic,
2548 0x00000000);
2549 /* XXX : not implemented */
2550 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2551 SPR_NOACCESS, SPR_NOACCESS,
2552 &spr_read_generic, &spr_write_generic,
2553 0x00000000);
2554 /* XXX : not implemented */
2555 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2556 SPR_NOACCESS, SPR_NOACCESS,
2557 &spr_read_generic, &spr_write_generic,
2558 0x00000000);
2559 /* XXX : not implemented */
2560 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2561 SPR_NOACCESS, SPR_NOACCESS,
2562 &spr_read_generic, &spr_write_generic,
2563 0x00000000);
2564 /* XXX : not implemented */
2565 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2566 SPR_NOACCESS, SPR_NOACCESS,
2567 &spr_read_generic, &spr_write_generic,
2568 0x00000000);
2569 /* XXX : not implemented */
2570 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2571 SPR_NOACCESS, SPR_NOACCESS,
2572 &spr_read_generic, &spr_write_generic,
2573 0x00000000);
2574 /* XXX : not implemented */
2575 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2576 SPR_NOACCESS, SPR_NOACCESS,
2577 &spr_read_generic, &spr_write_generic,
2578 0x00000000);
2579 }
2580
2581 // XXX: TODO
2582 /*
2583 * AMR => SPR 29 (Power 2.04)
2584 * CTRL => SPR 136 (Power 2.04)
2585 * CTRL => SPR 152 (Power 2.04)
2586 * SCOMC => SPR 276 (64 bits ?)
2587 * SCOMD => SPR 277 (64 bits ?)
2588 * TBU40 => SPR 286 (Power 2.04 hypv)
2589 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2590 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2591 * HDSISR => SPR 306 (Power 2.04 hypv)
2592 * HDAR => SPR 307 (Power 2.04 hypv)
2593 * PURR => SPR 309 (Power 2.04 hypv)
2594 * HDEC => SPR 310 (Power 2.04 hypv)
2595 * HIOR => SPR 311 (hypv)
2596 * RMOR => SPR 312 (970)
2597 * HRMOR => SPR 313 (Power 2.04 hypv)
2598 * HSRR0 => SPR 314 (Power 2.04 hypv)
2599 * HSRR1 => SPR 315 (Power 2.04 hypv)
2600 * LPIDR => SPR 317 (970)
2601 * EPR => SPR 702 (Power 2.04 emb)
2602 * perf => 768-783 (Power 2.04)
2603 * perf => 784-799 (Power 2.04)
2604 * PPR => SPR 896 (Power 2.04)
2605 * EPLC => SPR 947 (Power 2.04 emb)
2606 * EPSC => SPR 948 (Power 2.04 emb)
2607 * DABRX => 1015 (Power 2.04 hypv)
2608 * FPECR => SPR 1022 (?)
2609 * ... and more (thermal management, performance counters, ...)
2610 */
2611
2612 /*****************************************************************************/
2613 /* Exception vectors models */
2614 static void init_excp_4xx_real (CPUPPCState *env)
2615 {
2616 #if !defined(CONFIG_USER_ONLY)
2617 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2618 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2619 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2620 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2621 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2622 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2623 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2624 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2625 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2626 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2627 env->ivor_mask = 0x0000FFF0UL;
2628 env->ivpr_mask = 0xFFFF0000UL;
2629 /* Hardware reset vector */
2630 env->hreset_vector = 0xFFFFFFFCUL;
2631 #endif
2632 }
2633
2634 static void init_excp_4xx_softmmu (CPUPPCState *env)
2635 {
2636 #if !defined(CONFIG_USER_ONLY)
2637 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2638 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2639 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2640 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2641 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2642 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2643 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2644 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2645 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2646 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2647 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2648 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2649 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2650 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2651 env->ivor_mask = 0x0000FFF0UL;
2652 env->ivpr_mask = 0xFFFF0000UL;
2653 /* Hardware reset vector */
2654 env->hreset_vector = 0xFFFFFFFCUL;
2655 #endif
2656 }
2657
2658 static void init_excp_MPC5xx (CPUPPCState *env)
2659 {
2660 #if !defined(CONFIG_USER_ONLY)
2661 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2662 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2663 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2664 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2665 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2666 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2667 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2668 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2669 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2670 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2671 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2672 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2673 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2674 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2675 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2676 env->ivor_mask = 0x0000FFF0UL;
2677 env->ivpr_mask = 0xFFFF0000UL;
2678 /* Hardware reset vector */
2679 env->hreset_vector = 0x00000100UL;
2680 #endif
2681 }
2682
2683 static void init_excp_MPC8xx (CPUPPCState *env)
2684 {
2685 #if !defined(CONFIG_USER_ONLY)
2686 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2687 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2688 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2689 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2690 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2691 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2692 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2693 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2694 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2695 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2696 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2697 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2698 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2699 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2700 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2701 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2702 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2703 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2704 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2705 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2706 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2707 env->ivor_mask = 0x0000FFF0UL;
2708 env->ivpr_mask = 0xFFFF0000UL;
2709 /* Hardware reset vector */
2710 env->hreset_vector = 0x00000100UL;
2711 #endif
2712 }
2713
2714 static void init_excp_G2 (CPUPPCState *env)
2715 {
2716 #if !defined(CONFIG_USER_ONLY)
2717 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2718 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2719 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2720 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2721 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2722 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2723 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2724 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2725 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2726 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2727 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2728 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2729 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2730 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2731 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2732 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2733 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2734 /* Hardware reset vector */
2735 env->hreset_vector = 0x00000100UL;
2736 #endif
2737 }
2738
2739 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2740 {
2741 #if !defined(CONFIG_USER_ONLY)
2742 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2743 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2746 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2762 env->ivor_mask = 0x0000FFF7UL;
2763 env->ivpr_mask = ivpr_mask;
2764 /* Hardware reset vector */
2765 env->hreset_vector = 0xFFFFFFFCUL;
2766 #endif
2767 }
2768
2769 static void init_excp_BookE (CPUPPCState *env)
2770 {
2771 #if !defined(CONFIG_USER_ONLY)
2772 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2773 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2774 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2775 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2776 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2777 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2778 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2779 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2780 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2781 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2782 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2783 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2784 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2785 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2786 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2787 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2788 env->ivor_mask = 0x0000FFE0UL;
2789 env->ivpr_mask = 0xFFFF0000UL;
2790 /* Hardware reset vector */
2791 env->hreset_vector = 0xFFFFFFFCUL;
2792 #endif
2793 }
2794
2795 static void init_excp_601 (CPUPPCState *env)
2796 {
2797 #if !defined(CONFIG_USER_ONLY)
2798 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2799 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2800 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2801 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2802 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2803 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2804 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2805 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2806 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2807 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2808 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2809 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2810 /* Hardware reset vector */
2811 env->hreset_vector = 0x00000100UL;
2812 #endif
2813 }
2814
2815 static void init_excp_602 (CPUPPCState *env)
2816 {
2817 #if !defined(CONFIG_USER_ONLY)
2818 /* XXX: exception prefix has a special behavior on 602 */
2819 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2820 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2821 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2822 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2823 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2824 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2825 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2826 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2827 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2828 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2829 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2830 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2831 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2832 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2833 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2834 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2835 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2836 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2837 /* Hardware reset vector */
2838 env->hreset_vector = 0x00000100UL;
2839 #endif
2840 }
2841
2842 static void init_excp_603 (CPUPPCState *env)
2843 {
2844 #if !defined(CONFIG_USER_ONLY)
2845 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2846 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2847 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2848 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2849 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2850 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2851 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2852 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2853 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2854 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2855 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2856 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2857 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2858 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2859 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2860 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2861 /* Hardware reset vector */
2862 env->hreset_vector = 0x00000100UL;
2863 #endif
2864 }
2865
2866 static void init_excp_604 (CPUPPCState *env)
2867 {
2868 #if !defined(CONFIG_USER_ONLY)
2869 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2870 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2871 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2872 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2873 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2874 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2875 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2876 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2877 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2878 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2879 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2880 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2881 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2882 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2883 /* Hardware reset vector */
2884 env->hreset_vector = 0x00000100UL;
2885 #endif
2886 }
2887
2888 static void init_excp_7x0 (CPUPPCState *env)
2889 {
2890 #if !defined(CONFIG_USER_ONLY)
2891 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2892 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2893 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2894 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2895 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2896 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2897 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2898 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2899 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2900 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2901 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2902 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2903 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2904 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2905 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2906 /* Hardware reset vector */
2907 env->hreset_vector = 0x00000100UL;
2908 #endif
2909 }
2910
2911 static void init_excp_750cl (CPUPPCState *env)
2912 {
2913 #if !defined(CONFIG_USER_ONLY)
2914 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2915 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2916 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2917 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2918 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2919 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2920 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2921 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2922 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2923 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2924 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2925 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2926 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2927 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2928 /* Hardware reset vector */
2929 env->hreset_vector = 0x00000100UL;
2930 #endif
2931 }
2932
2933 static void init_excp_750cx (CPUPPCState *env)
2934 {
2935 #if !defined(CONFIG_USER_ONLY)
2936 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2937 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2938 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2939 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2940 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2941 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2942 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2943 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2944 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2945 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2946 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2947 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2948 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2949 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2950 /* Hardware reset vector */
2951 env->hreset_vector = 0x00000100UL;
2952 #endif
2953 }
2954
2955 /* XXX: Check if this is correct */
2956 static void init_excp_7x5 (CPUPPCState *env)
2957 {
2958 #if !defined(CONFIG_USER_ONLY)
2959 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2960 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2961 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2962 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2963 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2964 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2965 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2966 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2967 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2968 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2969 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2970 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2971 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2972 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2973 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2974 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2975 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2976 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2977 /* Hardware reset vector */
2978 env->hreset_vector = 0x00000100UL;
2979 #endif
2980 }
2981
2982 static void init_excp_7400 (CPUPPCState *env)
2983 {
2984 #if !defined(CONFIG_USER_ONLY)
2985 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2986 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2987 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2988 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2989 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2990 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2991 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2992 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2993 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2994 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2995 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2996 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2997 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2998 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2999 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3000 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3001 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3002 /* Hardware reset vector */
3003 env->hreset_vector = 0x00000100UL;
3004 #endif
3005 }
3006
3007 static void init_excp_7450 (CPUPPCState *env)
3008 {
3009 #if !defined(CONFIG_USER_ONLY)
3010 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3011 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3012 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3013 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3014 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3015 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3016 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3017 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3018 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3019 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3020 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3021 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3022 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3023 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3024 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3025 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3026 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3027 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3028 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3029 /* Hardware reset vector */
3030 env->hreset_vector = 0x00000100UL;
3031 #endif
3032 }
3033
3034 #if defined (TARGET_PPC64)
3035 static void init_excp_970 (CPUPPCState *env)
3036 {
3037 #if !defined(CONFIG_USER_ONLY)
3038 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3039 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3040 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3041 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3042 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3043 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3044 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3045 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3046 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3047 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3048 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3049 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3050 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3051 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3052 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3053 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3054 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3055 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3056 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3057 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3058 /* Hardware reset vector */
3059 env->hreset_vector = 0x0000000000000100ULL;
3060 #endif
3061 }
3062
3063 static void init_excp_POWER7 (CPUPPCState *env)
3064 {
3065 #if !defined(CONFIG_USER_ONLY)
3066 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3067 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3068 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3069 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3070 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3071 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3072 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3073 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3074 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3075 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3076 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3077 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3078 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3079 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3080 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3081 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3082 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3083 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3084 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3085 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3086 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3087 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3088 /* Hardware reset vector */
3089 env->hreset_vector = 0x0000000000000100ULL;
3090 #endif
3091 }
3092 #endif
3093
3094 /*****************************************************************************/
3095 /* Power management enable checks */
3096 static int check_pow_none (CPUPPCState *env)
3097 {
3098 return 0;
3099 }
3100
3101 static int check_pow_nocheck (CPUPPCState *env)
3102 {
3103 return 1;
3104 }
3105
3106 static int check_pow_hid0 (CPUPPCState *env)
3107 {
3108 if (env->spr[SPR_HID0] & 0x00E00000)
3109 return 1;
3110
3111 return 0;
3112 }
3113
3114 static int check_pow_hid0_74xx (CPUPPCState *env)
3115 {
3116 if (env->spr[SPR_HID0] & 0x00600000)
3117 return 1;
3118
3119 return 0;
3120 }
3121
3122 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3123 {
3124 return true;
3125 }
3126
3127 #ifdef TARGET_PPC64
3128 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3129 {
3130 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3131 }
3132 #endif
3133
3134 /*****************************************************************************/
3135 /* PowerPC implementations definitions */
3136
3137 #define POWERPC_FAMILY(_name) \
3138 static void \
3139 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3140 \
3141 static const TypeInfo \
3142 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3143 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3144 .parent = TYPE_POWERPC_CPU, \
3145 .abstract = true, \
3146 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3147 }; \
3148 \
3149 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3150 { \
3151 type_register_static( \
3152 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3153 } \
3154 \
3155 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3156 \
3157 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3158
3159 static void init_proc_401 (CPUPPCState *env)
3160 {
3161 gen_spr_40x(env);
3162 gen_spr_401_403(env);
3163 gen_spr_401(env);
3164 init_excp_4xx_real(env);
3165 env->dcache_line_size = 32;
3166 env->icache_line_size = 32;
3167 /* Allocate hardware IRQ controller */
3168 ppc40x_irq_init(env);
3169
3170 SET_FIT_PERIOD(12, 16, 20, 24);
3171 SET_WDT_PERIOD(16, 20, 24, 28);
3172 }
3173
3174 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3175 {
3176 DeviceClass *dc = DEVICE_CLASS(oc);
3177 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3178
3179 dc->desc = "PowerPC 401";
3180 pcc->init_proc = init_proc_401;
3181 pcc->check_pow = check_pow_nocheck;
3182 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3183 PPC_WRTEE | PPC_DCR |
3184 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3185 PPC_CACHE_DCBZ |
3186 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3187 PPC_4xx_COMMON | PPC_40x_EXCP;
3188 pcc->msr_mask = (1ull << MSR_KEY) |
3189 (1ull << MSR_POW) |
3190 (1ull << MSR_CE) |
3191 (1ull << MSR_ILE) |
3192 (1ull << MSR_EE) |
3193 (1ull << MSR_PR) |
3194 (1ull << MSR_ME) |
3195 (1ull << MSR_DE) |
3196 (1ull << MSR_LE);
3197 pcc->mmu_model = POWERPC_MMU_REAL;
3198 pcc->excp_model = POWERPC_EXCP_40x;
3199 pcc->bus_model = PPC_FLAGS_INPUT_401;
3200 pcc->bfd_mach = bfd_mach_ppc_403;
3201 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3202 POWERPC_FLAG_BUS_CLK;
3203 }
3204
3205 static void init_proc_401x2 (CPUPPCState *env)
3206 {
3207 gen_spr_40x(env);
3208 gen_spr_401_403(env);
3209 gen_spr_401x2(env);
3210 gen_spr_compress(env);
3211 /* Memory management */
3212 #if !defined(CONFIG_USER_ONLY)
3213 env->nb_tlb = 64;
3214 env->nb_ways = 1;
3215 env->id_tlbs = 0;
3216 env->tlb_type = TLB_EMB;
3217 #endif
3218 init_excp_4xx_softmmu(env);
3219 env->dcache_line_size = 32;
3220 env->icache_line_size = 32;
3221 /* Allocate hardware IRQ controller */
3222 ppc40x_irq_init(env);
3223
3224 SET_FIT_PERIOD(12, 16, 20, 24);
3225 SET_WDT_PERIOD(16, 20, 24, 28);
3226 }
3227
3228 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3229 {
3230 DeviceClass *dc = DEVICE_CLASS(oc);
3231 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3232
3233 dc->desc = "PowerPC 401x2";
3234 pcc->init_proc = init_proc_401x2;
3235 pcc->check_pow = check_pow_nocheck;
3236 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3237 PPC_DCR | PPC_WRTEE |
3238 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3239 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3240 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3241 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3242 PPC_4xx_COMMON | PPC_40x_EXCP;
3243 pcc->msr_mask = (1ull << 20) |
3244 (1ull << MSR_KEY) |
3245 (1ull << MSR_POW) |
3246 (1ull << MSR_CE) |
3247 (1ull << MSR_ILE) |
3248 (1ull << MSR_EE) |
3249 (1ull << MSR_PR) |
3250 (1ull << MSR_ME) |
3251 (1ull << MSR_DE) |
3252 (1ull << MSR_IR) |
3253 (1ull << MSR_DR) |
3254 (1ull << MSR_LE);
3255 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3256 pcc->excp_model = POWERPC_EXCP_40x;
3257 pcc->bus_model = PPC_FLAGS_INPUT_401;
3258 pcc->bfd_mach = bfd_mach_ppc_403;
3259 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3260 POWERPC_FLAG_BUS_CLK;
3261 }
3262
3263 static void init_proc_401x3 (CPUPPCState *env)
3264 {
3265 gen_spr_40x(env);
3266 gen_spr_401_403(env);
3267 gen_spr_401(env);
3268 gen_spr_401x2(env);
3269 gen_spr_compress(env);
3270 init_excp_4xx_softmmu(env);
3271 env->dcache_line_size = 32;
3272 env->icache_line_size = 32;
3273 /* Allocate hardware IRQ controller */
3274 ppc40x_irq_init(env);
3275
3276 SET_FIT_PERIOD(12, 16, 20, 24);
3277 SET_WDT_PERIOD(16, 20, 24, 28);
3278 }
3279
3280 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3281 {
3282 DeviceClass *dc = DEVICE_CLASS(oc);
3283 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3284
3285 dc->desc = "PowerPC 401x3";
3286 pcc->init_proc = init_proc_401x3;
3287 pcc->check_pow = check_pow_nocheck;
3288 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3289 PPC_DCR | PPC_WRTEE |
3290 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3291 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3292 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3293 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3294 PPC_4xx_COMMON | PPC_40x_EXCP;
3295 pcc->msr_mask = (1ull << 20) |
3296 (1ull << MSR_KEY) |
3297 (1ull << MSR_POW) |
3298 (1ull << MSR_CE) |
3299 (1ull << MSR_ILE) |
3300 (1ull << MSR_EE) |
3301 (1ull << MSR_PR) |
3302 (1ull << MSR_ME) |
3303 (1ull << MSR_DWE) |
3304 (1ull << MSR_DE) |
3305 (1ull << MSR_IR) |
3306 (1ull << MSR_DR) |
3307 (1ull << MSR_LE);
3308 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3309 pcc->excp_model = POWERPC_EXCP_40x;
3310 pcc->bus_model = PPC_FLAGS_INPUT_401;
3311 pcc->bfd_mach = bfd_mach_ppc_403;
3312 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3313 POWERPC_FLAG_BUS_CLK;
3314 }
3315
3316 static void init_proc_IOP480 (CPUPPCState *env)
3317 {
3318 gen_spr_40x(env);
3319 gen_spr_401_403(env);
3320 gen_spr_401x2(env);
3321 gen_spr_compress(env);
3322 /* Memory management */
3323 #if !defined(CONFIG_USER_ONLY)
3324 env->nb_tlb = 64;
3325 env->nb_ways = 1;
3326 env->id_tlbs = 0;
3327 env->tlb_type = TLB_EMB;
3328 #endif
3329 init_excp_4xx_softmmu(env);
3330 env->dcache_line_size = 32;
3331 env->icache_line_size = 32;
3332 /* Allocate hardware IRQ controller */
3333 ppc40x_irq_init(env);
3334
3335 SET_FIT_PERIOD(8, 12, 16, 20);
3336 SET_WDT_PERIOD(16, 20, 24, 28);
3337 }
3338
3339 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3340 {
3341 DeviceClass *dc = DEVICE_CLASS(oc);
3342 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3343
3344 dc->desc = "IOP480";
3345 pcc->init_proc = init_proc_IOP480;
3346 pcc->check_pow = check_pow_nocheck;
3347 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3348 PPC_DCR | PPC_WRTEE |
3349 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3350 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3351 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3352 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3353 PPC_4xx_COMMON | PPC_40x_EXCP;
3354 pcc->msr_mask = (1ull << 20) |
3355 (1ull << MSR_KEY) |
3356 (1ull << MSR_POW) |
3357 (1ull << MSR_CE) |
3358 (1ull << MSR_ILE) |
3359 (1ull << MSR_EE) |
3360 (1ull << MSR_PR) |
3361 (1ull << MSR_ME) |
3362 (1ull << MSR_DE) |
3363 (1ull << MSR_IR) |
3364 (1ull << MSR_DR) |
3365 (1ull << MSR_LE);
3366 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3367 pcc->excp_model = POWERPC_EXCP_40x;
3368 pcc->bus_model = PPC_FLAGS_INPUT_401;
3369 pcc->bfd_mach = bfd_mach_ppc_403;
3370 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3371 POWERPC_FLAG_BUS_CLK;
3372 }
3373
3374 static void init_proc_403 (CPUPPCState *env)
3375 {
3376 gen_spr_40x(env);
3377 gen_spr_401_403(env);
3378 gen_spr_403(env);
3379 gen_spr_403_real(env);
3380 init_excp_4xx_real(env);
3381 env->dcache_line_size = 32;
3382 env->icache_line_size = 32;
3383 /* Allocate hardware IRQ controller */
3384 ppc40x_irq_init(env);
3385
3386 SET_FIT_PERIOD(8, 12, 16, 20);
3387 SET_WDT_PERIOD(16, 20, 24, 28);
3388 }
3389
3390 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3391 {
3392 DeviceClass *dc = DEVICE_CLASS(oc);
3393 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3394
3395 dc->desc = "PowerPC 403";
3396 pcc->init_proc = init_proc_403;
3397 pcc->check_pow = check_pow_nocheck;
3398 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3399 PPC_DCR | PPC_WRTEE |
3400 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3401 PPC_CACHE_DCBZ |
3402 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3403 PPC_4xx_COMMON | PPC_40x_EXCP;
3404 pcc->msr_mask = (1ull << MSR_POW) |
3405 (1ull << MSR_CE) |
3406 (1ull << MSR_ILE) |
3407 (1ull << MSR_EE) |
3408 (1ull << MSR_PR) |
3409 (1ull << MSR_ME) |
3410 (1ull << MSR_PE) |
3411 (1ull << MSR_PX) |
3412 (1ull << MSR_LE);
3413 pcc->mmu_model = POWERPC_MMU_REAL;
3414 pcc->excp_model = POWERPC_EXCP_40x;
3415 pcc->bus_model = PPC_FLAGS_INPUT_401;
3416 pcc->bfd_mach = bfd_mach_ppc_403;
3417 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3418 POWERPC_FLAG_BUS_CLK;
3419 }
3420
3421 static void init_proc_403GCX (CPUPPCState *env)
3422 {
3423 gen_spr_40x(env);
3424 gen_spr_401_403(env);
3425 gen_spr_403(env);
3426 gen_spr_403_real(env);
3427 gen_spr_403_mmu(env);
3428 /* Bus access control */
3429 /* not emulated, as QEMU never does speculative access */
3430 spr_register(env, SPR_40x_SGR, "SGR",
3431 SPR_NOACCESS, SPR_NOACCESS,
3432 &spr_read_generic, &spr_write_generic,
3433 0xFFFFFFFF);
3434 /* not emulated, as QEMU do not emulate caches */
3435 spr_register(env, SPR_40x_DCWR, "DCWR",
3436 SPR_NOACCESS, SPR_NOACCESS,
3437 &spr_read_generic, &spr_write_generic,
3438 0x00000000);
3439 /* Memory management */
3440 #if !defined(CONFIG_USER_ONLY)
3441 env->nb_tlb = 64;
3442 env->nb_ways = 1;
3443 env->id_tlbs = 0;
3444 env->tlb_type = TLB_EMB;
3445 #endif
3446 init_excp_4xx_softmmu(env);
3447 env->dcache_line_size = 32;
3448 env->icache_line_size = 32;
3449 /* Allocate hardware IRQ controller */
3450 ppc40x_irq_init(env);
3451
3452 SET_FIT_PERIOD(8, 12, 16, 20);
3453 SET_WDT_PERIOD(16, 20, 24, 28);
3454 }
3455
3456 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3457 {
3458 DeviceClass *dc = DEVICE_CLASS(oc);
3459 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3460
3461 dc->desc = "PowerPC 403 GCX";
3462 pcc->init_proc = init_proc_403GCX;
3463 pcc->check_pow = check_pow_nocheck;
3464 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3465 PPC_DCR | PPC_WRTEE |
3466 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3467 PPC_CACHE_DCBZ |
3468 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3469 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3470 PPC_4xx_COMMON | PPC_40x_EXCP;
3471 pcc->msr_mask = (1ull << MSR_POW) |
3472 (1ull << MSR_CE) |
3473 (1ull << MSR_ILE) |
3474 (1ull << MSR_EE) |
3475 (1ull << MSR_PR) |
3476 (1ull << MSR_ME) |
3477 (1ull << MSR_PE) |
3478 (1ull << MSR_PX) |
3479 (1ull << MSR_LE);
3480 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3481 pcc->excp_model = POWERPC_EXCP_40x;
3482 pcc->bus_model = PPC_FLAGS_INPUT_401;
3483 pcc->bfd_mach = bfd_mach_ppc_403;
3484 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3485 POWERPC_FLAG_BUS_CLK;
3486 }
3487
3488 static void init_proc_405 (CPUPPCState *env)
3489 {
3490 /* Time base */
3491 gen_tbl(env);
3492 gen_spr_40x(env);
3493 gen_spr_405(env);
3494 /* Bus access control */
3495 /* not emulated, as QEMU never does speculative access */
3496 spr_register(env, SPR_40x_SGR, "SGR",
3497 SPR_NOACCESS, SPR_NOACCESS,
3498 &spr_read_generic, &spr_write_generic,
3499 0xFFFFFFFF);
3500 /* not emulated, as QEMU do not emulate caches */
3501 spr_register(env, SPR_40x_DCWR, "DCWR",
3502 SPR_NOACCESS, SPR_NOACCESS,
3503 &spr_read_generic, &spr_write_generic,
3504 0x00000000);
3505 /* Memory management */
3506 #if !defined(CONFIG_USER_ONLY)
3507 env->nb_tlb = 64;
3508 env->nb_ways = 1;
3509 env->id_tlbs = 0;
3510 env->tlb_type = TLB_EMB;
3511 #endif
3512 init_excp_4xx_softmmu(env);
3513 env->dcache_line_size = 32;
3514 env->icache_line_size = 32;
3515 /* Allocate hardware IRQ controller */
3516 ppc40x_irq_init(env);
3517
3518 SET_FIT_PERIOD(8, 12, 16, 20);
3519 SET_WDT_PERIOD(16, 20, 24, 28);
3520 }
3521
3522 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3523 {
3524 DeviceClass *dc = DEVICE_CLASS(oc);
3525 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3526
3527 dc->desc = "PowerPC 405";
3528 pcc->init_proc = init_proc_405;
3529 pcc->check_pow = check_pow_nocheck;
3530 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3531 PPC_DCR | PPC_WRTEE |
3532 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3533 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3534 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3535 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3536 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3537 pcc->msr_mask = (1ull << MSR_POW) |
3538 (1ull << MSR_CE) |
3539 (1ull << MSR_EE) |
3540 (1ull << MSR_PR) |
3541 (1ull << MSR_FP) |
3542 (1ull << MSR_DWE) |
3543 (1ull << MSR_DE) |
3544 (1ull << MSR_IR) |
3545 (1ull << MSR_DR);
3546 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3547 pcc->excp_model = POWERPC_EXCP_40x;
3548 pcc->bus_model = PPC_FLAGS_INPUT_405;
3549 pcc->bfd_mach = bfd_mach_ppc_403;
3550 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3551 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3552 }
3553
3554 static void init_proc_440EP (CPUPPCState *env)
3555 {
3556 /* Time base */
3557 gen_tbl(env);
3558 gen_spr_BookE(env, 0x000000000000FFFFULL);
3559 gen_spr_440(env);
3560 gen_spr_usprgh(env);
3561 /* Processor identification */
3562 spr_register(env, SPR_BOOKE_PIR, "PIR",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_pir,
3565 0x00000000);
3566 /* XXX : not implemented */
3567 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
3571 /* XXX : not implemented */
3572 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3573 SPR_NOACCESS, SPR_NOACCESS,
3574 &spr_read_generic, &spr_write_generic,
3575 0x00000000);
3576 /* XXX : not implemented */
3577 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3578 SPR_NOACCESS, SPR_NOACCESS,
3579 &spr_read_generic, &spr_write_generic,
3580 0x00000000);
3581 /* XXX : not implemented */
3582 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3583 SPR_NOACCESS, SPR_NOACCESS,
3584 &spr_read_generic, &spr_write_generic,
3585 0x00000000);
3586 /* XXX : not implemented */
3587 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3588 SPR_NOACCESS, SPR_NOACCESS,
3589 &spr_read_generic, &spr_write_generic,
3590 0x00000000);
3591 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3592 SPR_NOACCESS, SPR_NOACCESS,
3593 &spr_read_generic, &spr_write_generic,
3594 0x00000000);
3595 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3596 SPR_NOACCESS, SPR_NOACCESS,
3597 &spr_read_generic, &spr_write_generic,
3598 0x00000000);
3599 /* XXX : not implemented */
3600 spr_register(env, SPR_440_CCR1, "CCR1",
3601 SPR_NOACCESS, SPR_NOACCESS,
3602 &spr_read_generic, &spr_write_generic,
3603 0x00000000);
3604 /* Memory management */
3605 #if !defined(CONFIG_USER_ONLY)
3606 env->nb_tlb = 64;
3607 env->nb_ways = 1;
3608 env->id_tlbs = 0;
3609 env->tlb_type = TLB_EMB;
3610 #endif
3611 init_excp_BookE(env);
3612 env->dcache_line_size = 32;
3613 env->icache_line_size = 32;
3614 ppc40x_irq_init(env);
3615
3616 SET_FIT_PERIOD(12, 16, 20, 24);
3617 SET_WDT_PERIOD(20, 24, 28, 32);
3618 }
3619
3620 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3621 {
3622 DeviceClass *dc = DEVICE_CLASS(oc);
3623 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3624
3625 dc->desc = "PowerPC 440 EP";
3626 pcc->init_proc = init_proc_440EP;
3627 pcc->check_pow = check_pow_nocheck;
3628 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3629 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3630 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3631 PPC_FLOAT_STFIWX |
3632 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3633 PPC_CACHE | PPC_CACHE_ICBI |
3634 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3635 PPC_MEM_TLBSYNC | PPC_MFTB |
3636 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3637 PPC_440_SPEC;
3638 pcc->msr_mask = (1ull << MSR_POW) |
3639 (1ull << MSR_CE) |
3640 (1ull << MSR_EE) |
3641 (1ull << MSR_PR) |
3642 (1ull << MSR_FP) |
3643 (1ull << MSR_ME) |
3644 (1ull << MSR_FE0) |
3645 (1ull << MSR_DWE) |
3646 (1ull << MSR_DE) |
3647 (1ull << MSR_FE1) |
3648 (1ull << MSR_IR) |
3649 (1ull << MSR_DR);
3650 pcc->mmu_model = POWERPC_MMU_BOOKE;
3651 pcc->excp_model = POWERPC_EXCP_BOOKE;
3652 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3653 pcc->bfd_mach = bfd_mach_ppc_403;
3654 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3655 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3656 }
3657
3658 static void init_proc_440GP (CPUPPCState *env)
3659 {
3660 /* Time base */
3661 gen_tbl(env);
3662 gen_spr_BookE(env, 0x000000000000FFFFULL);
3663 gen_spr_440(env);
3664 gen_spr_usprgh(env);
3665 /* Processor identification */
3666 spr_register(env, SPR_BOOKE_PIR, "PIR",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_pir,
3669 0x00000000);
3670 /* XXX : not implemented */
3671 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
3675 /* XXX : not implemented */
3676 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3677 SPR_NOACCESS, SPR_NOACCESS,
3678 &spr_read_generic, &spr_write_generic,
3679 0x00000000);
3680 /* XXX : not implemented */
3681 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3682 SPR_NOACCESS, SPR_NOACCESS,
3683 &spr_read_generic, &spr_write_generic,
3684 0x00000000);
3685 /* XXX : not implemented */
3686 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3687 SPR_NOACCESS, SPR_NOACCESS,
3688 &spr_read_generic, &spr_write_generic,
3689 0x00000000);
3690 /* Memory management */
3691 #if !defined(CONFIG_USER_ONLY)
3692 env->nb_tlb = 64;
3693 env->nb_ways = 1;
3694 env->id_tlbs = 0;
3695 env->tlb_type = TLB_EMB;
3696 #endif
3697 init_excp_BookE(env);
3698 env->dcache_line_size = 32;
3699 env->icache_line_size = 32;
3700 /* XXX: TODO: allocate internal IRQ controller */
3701
3702 SET_FIT_PERIOD(12, 16, 20, 24);
3703 SET_WDT_PERIOD(20, 24, 28, 32);
3704 }
3705
3706 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3707 {
3708 DeviceClass *dc = DEVICE_CLASS(oc);
3709 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3710
3711 dc->desc = "PowerPC 440 GP";
3712 pcc->init_proc = init_proc_440GP;
3713 pcc->check_pow = check_pow_nocheck;
3714 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3715 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3716 PPC_CACHE | PPC_CACHE_ICBI |
3717 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3718 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3719 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3720 PPC_440_SPEC;
3721 pcc->msr_mask = (1ull << MSR_POW) |
3722 (1ull << MSR_CE) |
3723 (1ull << MSR_EE) |
3724 (1ull << MSR_PR) |
3725 (1ull << MSR_FP) |
3726 (1ull << MSR_ME) |
3727 (1ull << MSR_FE0) |
3728 (1ull << MSR_DWE) |
3729 (1ull << MSR_DE) |
3730 (1ull << MSR_FE1) |
3731 (1ull << MSR_IR) |
3732 (1ull << MSR_DR);
3733 pcc->mmu_model = POWERPC_MMU_BOOKE;
3734 pcc->excp_model = POWERPC_EXCP_BOOKE;
3735 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3736 pcc->bfd_mach = bfd_mach_ppc_403;
3737 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3738 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3739 }
3740
3741 static void init_proc_440x4 (CPUPPCState *env)
3742 {
3743 /* Time base */
3744 gen_tbl(env);
3745 gen_spr_BookE(env, 0x000000000000FFFFULL);
3746 gen_spr_440(env);
3747 gen_spr_usprgh(env);
3748 /* Processor identification */
3749 spr_register(env, SPR_BOOKE_PIR, "PIR",
3750 SPR_NOACCESS, SPR_NOACCESS,
3751 &spr_read_generic, &spr_write_pir,
3752 0x00000000);
3753 /* XXX : not implemented */
3754 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3755 SPR_NOACCESS, SPR_NOACCESS,
3756 &spr_read_generic, &spr_write_generic,
3757 0x00000000);
3758 /* XXX : not implemented */
3759 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3760 SPR_NOACCESS, SPR_NOACCESS,
3761 &spr_read_generic, &spr_write_generic,
3762 0x00000000);
3763 /* XXX : not implemented */
3764 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3765 SPR_NOACCESS, SPR_NOACCESS,
3766 &spr_read_generic, &spr_write_generic,
3767 0x00000000);
3768 /* XXX : not implemented */
3769 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3770 SPR_NOACCESS, SPR_NOACCESS,
3771 &spr_read_generic, &spr_write_generic,
3772 0x00000000);
3773 /* Memory management */
3774 #if !defined(CONFIG_USER_ONLY)
3775 env->nb_tlb = 64;
3776 env->nb_ways = 1;
3777 env->id_tlbs = 0;
3778 env->tlb_type = TLB_EMB;
3779 #endif
3780 init_excp_BookE(env);
3781 env->dcache_line_size = 32;
3782 env->icache_line_size = 32;
3783 /* XXX: TODO: allocate internal IRQ controller */
3784
3785 SET_FIT_PERIOD(12, 16, 20, 24);
3786 SET_WDT_PERIOD(20, 24, 28, 32);
3787 }
3788
3789 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3790 {
3791 DeviceClass *dc = DEVICE_CLASS(oc);
3792 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3793
3794 dc->desc = "PowerPC 440x4";
3795 pcc->init_proc = init_proc_440x4;
3796 pcc->check_pow = check_pow_nocheck;
3797 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3798 PPC_DCR | PPC_WRTEE |
3799 PPC_CACHE | PPC_CACHE_ICBI |
3800 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3801 PPC_MEM_TLBSYNC | PPC_MFTB |
3802 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3803 PPC_440_SPEC;
3804 pcc->msr_mask = (1ull << MSR_POW) |
3805 (1ull << MSR_CE) |
3806 (1ull << MSR_EE) |
3807 (1ull << MSR_PR) |
3808 (1ull << MSR_FP) |
3809 (1ull << MSR_ME) |
3810 (1ull << MSR_FE0) |
3811 (1ull << MSR_DWE) |
3812 (1ull << MSR_DE) |
3813 (1ull << MSR_FE1) |
3814 (1ull << MSR_IR) |
3815 (1ull << MSR_DR);
3816 pcc->mmu_model = POWERPC_MMU_BOOKE;
3817 pcc->excp_model = POWERPC_EXCP_BOOKE;
3818 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3819 pcc->bfd_mach = bfd_mach_ppc_403;
3820 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3821 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3822 }
3823
3824 static void init_proc_440x5 (CPUPPCState *env)
3825 {
3826 /* Time base */
3827 gen_tbl(env);
3828 gen_spr_BookE(env, 0x000000000000FFFFULL);
3829 gen_spr_440(env);
3830 gen_spr_usprgh(env);
3831 /* Processor identification */
3832 spr_register(env, SPR_BOOKE_PIR, "PIR",
3833 SPR_NOACCESS, SPR_NOACCESS,
3834 &spr_read_generic, &spr_write_pir,
3835 0x00000000);
3836 /* XXX : not implemented */
3837 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3838 SPR_NOACCESS, SPR_NOACCESS,
3839 &spr_read_generic, &spr_write_generic,
3840 0x00000000);
3841 /* XXX : not implemented */
3842 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3843 SPR_NOACCESS, SPR_NOACCESS,
3844 &spr_read_generic, &spr_write_generic,
3845 0x00000000);
3846 /* XXX : not implemented */
3847 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3848 SPR_NOACCESS, SPR_NOACCESS,
3849 &spr_read_generic, &spr_write_generic,
3850 0x00000000);
3851 /* XXX : not implemented */
3852 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3853 SPR_NOACCESS, SPR_NOACCESS,
3854 &spr_read_generic, &spr_write_generic,
3855 0x00000000);
3856 /* XXX : not implemented */
3857 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3858 SPR_NOACCESS, SPR_NOACCESS,
3859 &spr_read_generic, &spr_write_generic,
3860 0x00000000);
3861 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3862 SPR_NOACCESS, SPR_NOACCESS,
3863 &spr_read_generic, &spr_write_generic,
3864 0x00000000);
3865 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3866 SPR_NOACCESS, SPR_NOACCESS,
3867 &spr_read_generic, &spr_write_generic,
3868 0x00000000);
3869 /* XXX : not implemented */
3870 spr_register(env, SPR_440_CCR1, "CCR1",
3871 SPR_NOACCESS, SPR_NOACCESS,
3872 &spr_read_generic, &spr_write_generic,
3873 0x00000000);
3874 /* Memory management */
3875 #if !defined(CONFIG_USER_ONLY)
3876 env->nb_tlb = 64;
3877 env->nb_ways = 1;
3878 env->id_tlbs = 0;
3879 env->tlb_type = TLB_EMB;
3880 #endif
3881 init_excp_BookE(env);
3882 env->dcache_line_size = 32;
3883 env->icache_line_size = 32;
3884 ppc40x_irq_init(env);
3885
3886 SET_FIT_PERIOD(12, 16, 20, 24);
3887 SET_WDT_PERIOD(20, 24, 28, 32);
3888 }
3889
3890 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3891 {
3892 DeviceClass *dc = DEVICE_CLASS(oc);
3893 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3894
3895 dc->desc = "PowerPC 440x5";
3896 pcc->init_proc = init_proc_440x5;
3897 pcc->check_pow = check_pow_nocheck;
3898 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3899 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3900 PPC_CACHE | PPC_CACHE_ICBI |
3901 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3902 PPC_MEM_TLBSYNC | PPC_MFTB |
3903 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3904 PPC_440_SPEC;
3905 pcc->msr_mask = (1ull << MSR_POW) |
3906 (1ull << MSR_CE) |
3907 (1ull << MSR_EE) |
3908 (1ull << MSR_PR) |
3909 (1ull << MSR_FP) |
3910 (1ull << MSR_ME) |
3911 (1ull << MSR_FE0) |
3912 (1ull << MSR_DWE) |
3913 (1ull << MSR_DE) |
3914 (1ull << MSR_FE1) |
3915 (1ull << MSR_IR) |
3916 (1ull << MSR_DR);
3917 pcc->mmu_model = POWERPC_MMU_BOOKE;
3918 pcc->excp_model = POWERPC_EXCP_BOOKE;
3919 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3920 pcc->bfd_mach = bfd_mach_ppc_403;
3921 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3922 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3923 }
3924
3925 static void init_proc_460 (CPUPPCState *env)
3926 {
3927 /* Time base */
3928 gen_tbl(env);
3929 gen_spr_BookE(env, 0x000000000000FFFFULL);
3930 gen_spr_440(env);
3931 gen_spr_usprgh(env);
3932 /* Processor identification */
3933 spr_register(env, SPR_BOOKE_PIR, "PIR",
3934 SPR_NOACCESS, SPR_NOACCESS,
3935 &spr_read_generic, &spr_write_pir,
3936 0x00000000);
3937 /* XXX : not implemented */
3938 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3939 SPR_NOACCESS, SPR_NOACCESS,
3940 &spr_read_generic, &spr_write_generic,
3941 0x00000000);
3942 /* XXX : not implemented */
3943 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3944 SPR_NOACCESS, SPR_NOACCESS,
3945 &spr_read_generic, &spr_write_generic,
3946 0x00000000);
3947 /* XXX : not implemented */
3948 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3949 SPR_NOACCESS, SPR_NOACCESS,
3950 &spr_read_generic, &spr_write_generic,
3951 0x00000000);
3952 /* XXX : not implemented */
3953 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3954 SPR_NOACCESS, SPR_NOACCESS,
3955 &spr_read_generic, &spr_write_generic,
3956 0x00000000);
3957 /* XXX : not implemented */
3958 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3959 SPR_NOACCESS, SPR_NOACCESS,
3960 &spr_read_generic, &spr_write_generic,
3961 0x00000000);
3962 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3963 SPR_NOACCESS, SPR_NOACCESS,
3964 &spr_read_generic, &spr_write_generic,
3965 0x00000000);
3966 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3967 SPR_NOACCESS, SPR_NOACCESS,
3968 &spr_read_generic, &spr_write_generic,
3969 0x00000000);
3970 /* XXX : not implemented */
3971 spr_register(env, SPR_440_CCR1, "CCR1",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, &spr_write_generic,
3974 0x00000000);
3975 /* XXX : not implemented */
3976 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3977 &spr_read_generic, &spr_write_generic,
3978 &spr_read_generic, &spr_write_generic,
3979 0x00000000);
3980 /* Memory management */
3981 #if !defined(CONFIG_USER_ONLY)
3982 env->nb_tlb = 64;
3983 env->nb_ways = 1;
3984 env->id_tlbs = 0;
3985 env->tlb_type = TLB_EMB;
3986 #endif
3987 init_excp_BookE(env);
3988 env->dcache_line_size = 32;
3989 env->icache_line_size = 32;
3990 /* XXX: TODO: allocate internal IRQ controller */
3991
3992 SET_FIT_PERIOD(12, 16, 20, 24);
3993 SET_WDT_PERIOD(20, 24, 28, 32);
3994 }
3995
3996 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3997 {
3998 DeviceClass *dc = DEVICE_CLASS(oc);
3999 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4000
4001 dc->desc = "PowerPC 460 (guessed)";
4002 pcc->init_proc = init_proc_460;
4003 pcc->check_pow = check_pow_nocheck;
4004 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4005 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4006 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4007 PPC_CACHE | PPC_CACHE_ICBI |
4008 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4009 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4010 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4011 PPC_440_SPEC;
4012 pcc->msr_mask = (1ull << MSR_POW) |
4013 (1ull << MSR_CE) |
4014 (1ull << MSR_EE) |
4015 (1ull << MSR_PR) |
4016 (1ull << MSR_FP) |
4017 (1ull << MSR_ME) |
4018 (1ull << MSR_FE0) |
4019 (1ull << MSR_DWE) |
4020 (1ull << MSR_DE) |
4021 (1ull << MSR_FE1) |
4022 (1ull << MSR_IR) |
4023 (1ull << MSR_DR);
4024 pcc->mmu_model = POWERPC_MMU_BOOKE;
4025 pcc->excp_model = POWERPC_EXCP_BOOKE;
4026 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4027 pcc->bfd_mach = bfd_mach_ppc_403;
4028 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4029 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4030 }
4031
4032 static void init_proc_460F (CPUPPCState *env)
4033 {
4034 /* Time base */
4035 gen_tbl(env);
4036 gen_spr_BookE(env, 0x000000000000FFFFULL);
4037 gen_spr_440(env);
4038 gen_spr_usprgh(env);
4039 /* Processor identification */
4040 spr_register(env, SPR_BOOKE_PIR, "PIR",
4041 SPR_NOACCESS, SPR_NOACCESS,
4042 &spr_read_generic, &spr_write_pir,
4043 0x00000000);
4044 /* XXX : not implemented */
4045 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4046 SPR_NOACCESS, SPR_NOACCESS,
4047 &spr_read_generic, &spr_write_generic,
4048 0x00000000);
4049 /* XXX : not implemented */
4050 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4051 SPR_NOACCESS, SPR_NOACCESS,
4052 &spr_read_generic, &spr_write_generic,
4053 0x00000000);
4054 /* XXX : not implemented */
4055 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4056 SPR_NOACCESS, SPR_NOACCESS,
4057 &spr_read_generic, &spr_write_generic,
4058 0x00000000);
4059 /* XXX : not implemented */
4060 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4061 SPR_NOACCESS, SPR_NOACCESS,
4062 &spr_read_generic, &spr_write_generic,
4063 0x00000000);
4064 /* XXX : not implemented */
4065 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4066 SPR_NOACCESS, SPR_NOACCESS,
4067 &spr_read_generic, &spr_write_generic,
4068 0x00000000);
4069 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4070 SPR_NOACCESS, SPR_NOACCESS,
4071 &spr_read_generic, &spr_write_generic,
4072 0x00000000);
4073 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
4077 /* XXX : not implemented */
4078 spr_register(env, SPR_440_CCR1, "CCR1",
4079 SPR_NOACCESS, SPR_NOACCESS,
4080 &spr_read_generic, &spr_write_generic,
4081 0x00000000);
4082 /* XXX : not implemented */
4083 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4084 &spr_read_generic, &spr_write_generic,
4085 &spr_read_generic, &spr_write_generic,
4086 0x00000000);
4087 /* Memory management */
4088 #if !defined(CONFIG_USER_ONLY)
4089 env->nb_tlb = 64;
4090 env->nb_ways = 1;
4091 env->id_tlbs = 0;
4092 env->tlb_type = TLB_EMB;
4093 #endif
4094 init_excp_BookE(env);
4095 env->dcache_line_size = 32;
4096 env->icache_line_size = 32;
4097 /* XXX: TODO: allocate internal IRQ controller */
4098
4099 SET_FIT_PERIOD(12, 16, 20, 24);
4100 SET_WDT_PERIOD(20, 24, 28, 32);
4101 }
4102
4103 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4104 {
4105 DeviceClass *dc = DEVICE_CLASS(oc);
4106 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4107
4108 dc->desc = "PowerPC 460F (guessed)";
4109 pcc->init_proc = init_proc_460F;
4110 pcc->check_pow = check_pow_nocheck;
4111 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4112 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4113 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4114 PPC_FLOAT_STFIWX | PPC_MFTB |
4115 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4116 PPC_WRTEE | PPC_MFAPIDI |
4117 PPC_CACHE | PPC_CACHE_ICBI |
4118 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4119 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4120 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4121 PPC_440_SPEC;
4122 pcc->msr_mask = (1ull << MSR_POW) |
4123 (1ull << MSR_CE) |
4124 (1ull << MSR_EE) |
4125 (1ull << MSR_PR) |
4126 (1ull << MSR_FP) |
4127 (1ull << MSR_ME) |
4128 (1ull << MSR_FE0) |
4129 (1ull << MSR_DWE) |
4130 (1ull << MSR_DE) |
4131 (1ull << MSR_FE1) |
4132 (1ull << MSR_IR) |
4133 (1ull << MSR_DR);
4134 pcc->mmu_model = POWERPC_MMU_BOOKE;
4135 pcc->excp_model = POWERPC_EXCP_BOOKE;
4136 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4137 pcc->bfd_mach = bfd_mach_ppc_403;
4138 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4139 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4140 }
4141
4142 static void init_proc_MPC5xx (CPUPPCState *env)
4143 {
4144 /* Time base */
4145 gen_tbl(env);
4146 gen_spr_5xx_8xx(env);
4147 gen_spr_5xx(env);
4148 init_excp_MPC5xx(env);
4149 env->dcache_line_size = 32;
4150 env->icache_line_size = 32;
4151 /* XXX: TODO: allocate internal IRQ controller */
4152 }
4153
4154 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4155 {
4156 DeviceClass *dc = DEVICE_CLASS(oc);
4157 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4158
4159 dc->desc = "Freescale 5xx cores (aka RCPU)";
4160 pcc->init_proc = init_proc_MPC5xx;
4161 pcc->check_pow = check_pow_none;
4162 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4163 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4164 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4165 PPC_MFTB;
4166 pcc->msr_mask = (1ull << MSR_ILE) |
4167 (1ull << MSR_EE) |
4168 (1ull << MSR_PR) |
4169 (1ull << MSR_FP) |
4170 (1ull << MSR_ME) |
4171 (1ull << MSR_FE0) |
4172 (1ull << MSR_SE) |
4173 (1ull << MSR_DE) |
4174 (1ull << MSR_FE1) |
4175 (1ull << MSR_EP) |
4176 (1ull << MSR_RI) |
4177 (1ull << MSR_LE);
4178 pcc->mmu_model = POWERPC_MMU_REAL;
4179 pcc->excp_model = POWERPC_EXCP_603;
4180 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4181 pcc->bfd_mach = bfd_mach_ppc_505;
4182 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4183 POWERPC_FLAG_BUS_CLK;
4184 }
4185
4186 static void init_proc_MPC8xx (CPUPPCState *env)
4187 {
4188 /* Time base */
4189 gen_tbl(env);
4190 gen_spr_5xx_8xx(env);
4191 gen_spr_8xx(env);
4192 init_excp_MPC8xx(env);
4193 env->dcache_line_size = 32;
4194 env->icache_line_size = 32;
4195 /* XXX: TODO: allocate internal IRQ controller */
4196 }
4197
4198 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4199 {
4200 DeviceClass *dc = DEVICE_CLASS(oc);
4201 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4202
4203 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4204 pcc->init_proc = init_proc_MPC8xx;
4205 pcc->check_pow = check_pow_none;
4206 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4207 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4208 PPC_CACHE_ICBI | PPC_MFTB;
4209 pcc->msr_mask = (1ull << MSR_ILE) |
4210 (1ull << MSR_EE) |
4211 (1ull << MSR_PR) |
4212 (1ull << MSR_FP) |
4213 (1ull << MSR_ME) |
4214 (1ull << MSR_SE) |
4215 (1ull << MSR_DE) |
4216 (1ull << MSR_EP) |
4217 (1ull << MSR_IR) |
4218 (1ull << MSR_DR) |
4219 (1ull << MSR_RI) |
4220 (1ull << MSR_LE);
4221 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4222 pcc->excp_model = POWERPC_EXCP_603;
4223 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4224 pcc->bfd_mach = bfd_mach_ppc_860;
4225 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4226 POWERPC_FLAG_BUS_CLK;
4227 }
4228
4229 /* Freescale 82xx cores (aka PowerQUICC-II) */
4230
4231 static void init_proc_G2 (CPUPPCState *env)
4232 {
4233 gen_spr_ne_601(env);
4234 gen_spr_G2_755(env);
4235 gen_spr_G2(env);
4236 /* Time base */
4237 gen_tbl(env);
4238 /* External access control */
4239 /* XXX : not implemented */
4240 spr_register(env, SPR_EAR, "EAR",
4241 SPR_NOACCESS, SPR_NOACCESS,
4242 &spr_read_generic, &spr_write_generic,
4243 0x00000000);
4244 /* Hardware implementation register */
4245 /* XXX : not implemented */
4246 spr_register(env, SPR_HID0, "HID0",
4247 SPR_NOACCESS, SPR_NOACCESS,
4248 &spr_read_generic, &spr_write_generic,
4249 0x00000000);
4250 /* XXX : not implemented */
4251 spr_register(env, SPR_HID1, "HID1",
4252 SPR_NOACCESS, SPR_NOACCESS,
4253 &spr_read_generic, &spr_write_generic,
4254 0x00000000);
4255 /* XXX : not implemented */
4256 spr_register(env, SPR_HID2, "HID2",
4257 SPR_NOACCESS, SPR_NOACCESS,
4258 &spr_read_generic, &spr_write_generic,
4259 0x00000000);
4260 /* Memory management */
4261 gen_low_BATs(env);
4262 gen_high_BATs(env);
4263 gen_6xx_7xx_soft_tlb(env, 64, 2);
4264 init_excp_G2(env);
4265 env->dcache_line_size = 32;
4266 env->icache_line_size = 32;
4267 /* Allocate hardware IRQ controller */
4268 ppc6xx_irq_init(env);
4269 }
4270
4271 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4272 {
4273 DeviceClass *dc = DEVICE_CLASS(oc);
4274 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4275
4276 dc->desc = "PowerPC G2";
4277 pcc->init_proc = init_proc_G2;
4278 pcc->check_pow = check_pow_hid0;
4279 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4280 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4281 PPC_FLOAT_STFIWX |
4282 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4283 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4284 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4285 PPC_SEGMENT | PPC_EXTERN;
4286 pcc->msr_mask = (1ull << MSR_POW) |
4287 (1ull << MSR_TGPR) |
4288 (1ull << MSR_EE) |
4289 (1ull << MSR_PR) |
4290 (1ull << MSR_FP) |
4291 (1ull << MSR_ME) |
4292 (1ull << MSR_FE0) |
4293 (1ull << MSR_SE) |
4294 (1ull << MSR_DE) |
4295 (1ull << MSR_FE1) |
4296 (1ull << MSR_AL) |
4297 (1ull << MSR_EP) |
4298 (1ull << MSR_IR) |
4299 (1ull << MSR_DR) |
4300 (1ull << MSR_RI);
4301 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4302 pcc->excp_model = POWERPC_EXCP_G2;
4303 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4304 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4305 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4306 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4307 }
4308
4309 static void init_proc_G2LE (CPUPPCState *env)
4310 {
4311 gen_spr_ne_601(env);
4312 gen_spr_G2_755(env);
4313 gen_spr_G2(env);
4314 /* Time base */
4315 gen_tbl(env);
4316 /* External access control */
4317 /* XXX : not implemented */
4318 spr_register(env, SPR_EAR, "EAR",
4319 SPR_NOACCESS, SPR_NOACCESS,
4320 &spr_read_generic, &spr_write_generic,
4321 0x00000000);
4322 /* Hardware implementation register */
4323 /* XXX : not implemented */
4324 spr_register(env, SPR_HID0, "HID0",
4325 SPR_NOACCESS, SPR_NOACCESS,
4326 &spr_read_generic, &spr_write_generic,
4327 0x00000000);
4328 /* XXX : not implemented */
4329 spr_register(env, SPR_HID1, "HID1",
4330 SPR_NOACCESS, SPR_NOACCESS,
4331 &spr_read_generic, &spr_write_generic,
4332 0x00000000);
4333 /* XXX : not implemented */
4334 spr_register(env, SPR_HID2, "HID2",
4335 SPR_NOACCESS, SPR_NOACCESS,
4336 &spr_read_generic, &spr_write_generic,
4337 0x00000000);
4338 /* Breakpoints */
4339 /* XXX : not implemented */
4340 spr_register(env, SPR_DABR, "DABR",
4341 SPR_NOACCESS, SPR_NOACCESS,
4342 &spr_read_generic, &spr_write_generic,
4343 0x00000000);
4344 /* XXX : not implemented */
4345 spr_register(env, SPR_DABR2, "DABR2",
4346 SPR_NOACCESS, SPR_NOACCESS,
4347 &spr_read_generic, &spr_write_generic,
4348 0x00000000);
4349 /* XXX : not implemented */
4350 spr_register(env, SPR_IABR2, "IABR2",
4351 SPR_NOACCESS, SPR_NOACCESS,
4352 &spr_read_generic, &spr_write_generic,
4353 0x00000000);
4354 /* XXX : not implemented */
4355 spr_register(env, SPR_IBCR, "IBCR",
4356 SPR_NOACCESS, SPR_NOACCESS,
4357 &spr_read_generic, &spr_write_generic,
4358 0x00000000);
4359 /* XXX : not implemented */
4360 spr_register(env, SPR_DBCR, "DBCR",
4361 SPR_NOACCESS, SPR_NOACCESS,
4362 &spr_read_generic, &spr_write_generic,
4363 0x00000000);
4364
4365 /* Memory management */
4366 gen_low_BATs(env);
4367 gen_high_BATs(env);
4368 gen_6xx_7xx_soft_tlb(env, 64, 2);
4369 init_excp_G2(env);
4370 env->dcache_line_size = 32;
4371 env->icache_line_size = 32;
4372 /* Allocate hardware IRQ controller */
4373 ppc6xx_irq_init(env);
4374 }
4375
4376 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4377 {
4378 DeviceClass *dc = DEVICE_CLASS(oc);
4379 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4380
4381 dc->desc = "PowerPC G2LE";
4382 pcc->init_proc = init_proc_G2LE;
4383 pcc->check_pow = check_pow_hid0;
4384 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4385 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4386 PPC_FLOAT_STFIWX |
4387 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4388 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4389 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4390 PPC_SEGMENT | PPC_EXTERN;
4391 pcc->msr_mask = (1ull << MSR_POW) |
4392 (1ull << MSR_TGPR) |
4393 (1ull << MSR_ILE) |
4394 (1ull << MSR_EE) |
4395 (1ull << MSR_PR) |
4396 (1ull << MSR_FP) |
4397 (1ull << MSR_ME) |
4398 (1ull << MSR_FE0) |
4399 (1ull << MSR_SE) |
4400 (1ull << MSR_DE) |
4401 (1ull << MSR_FE1) |
4402 (1ull << MSR_AL) |
4403 (1ull << MSR_EP) |
4404 (1ull << MSR_IR) |
4405 (1ull << MSR_DR) |
4406 (1ull << MSR_RI) |
4407 (1ull << MSR_LE);
4408 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4409 pcc->excp_model = POWERPC_EXCP_G2;
4410 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4411 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4412 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4413 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4414 }
4415
4416 static void init_proc_e200 (CPUPPCState *env)
4417 {
4418 /* Time base */
4419 gen_tbl(env);
4420 gen_spr_BookE(env, 0x000000070000FFFFULL);
4421 /* XXX : not implemented */
4422 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4423 &spr_read_spefscr, &spr_write_spefscr,
4424 &spr_read_spefscr, &spr_write_spefscr,
4425 0x00000000);
4426 /* Memory management */
4427 gen_spr_BookE206(env, 0x0000005D, NULL);
4428 /* XXX : not implemented */
4429 spr_register(env, SPR_HID0, "HID0",
4430 SPR_NOACCESS, SPR_NOACCESS,
4431 &spr_read_generic, &spr_write_generic,
4432 0x00000000);
4433 /* XXX : not implemented */
4434 spr_register(env, SPR_HID1, "HID1",
4435 SPR_NOACCESS, SPR_NOACCESS,
4436 &spr_read_generic, &spr_write_generic,
4437 0x00000000);
4438 /* XXX : not implemented */
4439 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4440 SPR_NOACCESS, SPR_NOACCESS,
4441 &spr_read_generic, &spr_write_generic,
4442 0x00000000);
4443 /* XXX : not implemented */
4444 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4445 SPR_NOACCESS, SPR_NOACCESS,
4446 &spr_read_generic, &spr_write_generic,
4447 0x00000000);
4448 /* XXX : not implemented */
4449 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4450 SPR_NOACCESS, SPR_NOACCESS,
4451 &spr_read_generic, &spr_write_generic,
4452 0x00000000);
4453 /* XXX : not implemented */
4454 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4455 SPR_NOACCESS, SPR_NOACCESS,
4456 &spr_read_generic, &spr_write_generic,
4457 0x00000000);
4458 /* XXX : not implemented */
4459 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4460 SPR_NOACCESS, SPR_NOACCESS,
4461 &spr_read_generic, &spr_write_generic,
4462 0x00000000);
4463 /* XXX : not implemented */
4464 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4465 &spr_read_generic, SPR_NOACCESS,
4466 &spr_read_generic, SPR_NOACCESS,
4467 0x00000000);
4468 /* XXX : not implemented */
4469 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4470 SPR_NOACCESS, SPR_NOACCESS,
4471 &spr_read_generic, &spr_write_generic,
4472 0x00000000);
4473 /* XXX : not implemented */
4474 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4475 SPR_NOACCESS, SPR_NOACCESS,
4476 &spr_read_generic, &spr_write_generic,
4477 0x00000000);
4478 /* XXX : not implemented */
4479 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4480 SPR_NOACCESS, SPR_NOACCESS,
4481 &spr_read_generic, &spr_write_generic,
4482 0x00000000);
4483 /* XXX : not implemented */
4484 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4485 SPR_NOACCESS, SPR_NOACCESS,
4486 &spr_read_generic, &spr_write_generic,
4487 0x00000000);
4488 /* XXX : not implemented */
4489 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4490 SPR_NOACCESS, SPR_NOACCESS,
4491 &spr_read_generic, &spr_write_generic,
4492 0x00000000);
4493 /* XXX : not implemented */
4494 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4495 SPR_NOACCESS, SPR_NOACCESS,
4496 &spr_read_generic, &spr_write_generic,
4497 0x00000000);
4498 /* XXX : not implemented */
4499 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4500 SPR_NOACCESS, SPR_NOACCESS,
4501 &spr_read_generic, &spr_write_generic,
4502 0x00000000); /* TOFIX */
4503 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4504 SPR_NOACCESS, SPR_NOACCESS,
4505 &spr_read_generic, &spr_write_generic,
4506 0x00000000);
4507 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4508 SPR_NOACCESS, SPR_NOACCESS,
4509 &spr_read_generic, &spr_write_generic,
4510 0x00000000);
4511 #if !defined(CONFIG_USER_ONLY)
4512 env->nb_tlb = 64;
4513 env->nb_ways = 1;
4514 env->id_tlbs = 0;
4515 env->tlb_type = TLB_EMB;
4516 #endif
4517 init_excp_e200(env, 0xFFFF0000UL);
4518 env->dcache_line_size = 32;
4519 env->icache_line_size = 32;
4520 /* XXX: TODO: allocate internal IRQ controller */
4521 }
4522
4523 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4524 {
4525 DeviceClass *dc = DEVICE_CLASS(oc);
4526 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4527
4528 dc->desc = "e200 core";
4529 pcc->init_proc = init_proc_e200;
4530 pcc->check_pow = check_pow_hid0;
4531 /* XXX: unimplemented instructions:
4532 * dcblc
4533 * dcbtlst
4534 * dcbtstls
4535 * icblc
4536 * icbtls
4537 * tlbivax
4538 * all SPE multiply-accumulate instructions
4539 */
4540 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4541 PPC_SPE | PPC_SPE_SINGLE |
4542 PPC_WRTEE | PPC_RFDI |
4543 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4544 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4545 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4546 PPC_BOOKE;
4547 pcc->msr_mask = (1ull << MSR_UCLE) |
4548 (1ull << MSR_SPE) |
4549 (1ull << MSR_POW) |
4550 (1ull << MSR_CE) |
4551 (1ull << MSR_EE) |
4552 (1ull << MSR_PR) |
4553 (1ull << MSR_FP) |
4554 (1ull << MSR_ME) |
4555 (1ull << MSR_FE0) |
4556 (1ull << MSR_DWE) |
4557 (1ull << MSR_DE) |
4558 (1ull << MSR_FE1) |
4559 (1ull << MSR_IR) |
4560 (1ull << MSR_DR);
4561 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4562 pcc->excp_model = POWERPC_EXCP_BOOKE;
4563 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4564 pcc->bfd_mach = bfd_mach_ppc_860;
4565 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4566 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4567 POWERPC_FLAG_BUS_CLK;
4568 }
4569
4570 static void init_proc_e300 (CPUPPCState *env)
4571 {
4572 gen_spr_ne_601(env);
4573 gen_spr_603(env);
4574 /* Time base */
4575 gen_tbl(env);
4576 /* hardware implementation registers */
4577 /* XXX : not implemented */
4578 spr_register(env, SPR_HID0, "HID0",
4579 SPR_NOACCESS, SPR_NOACCESS,
4580 &spr_read_generic, &spr_write_generic,
4581 0x00000000);
4582 /* XXX : not implemented */
4583 spr_register(env, SPR_HID1, "HID1",
4584 SPR_NOACCESS, SPR_NOACCESS,
4585 &spr_read_generic, &spr_write_generic,
4586 0x00000000);
4587 /* XXX : not implemented */
4588 spr_register(env, SPR_HID2, "HID2",
4589 SPR_NOACCESS, SPR_NOACCESS,
4590 &spr_read_generic, &spr_write_generic,
4591 0x00000000);
4592 /* Memory management */
4593 gen_low_BATs(env);
4594 gen_high_BATs(env);
4595 gen_6xx_7xx_soft_tlb(env, 64, 2);
4596 init_excp_603(env);
4597 env->dcache_line_size = 32;
4598 env->icache_line_size = 32;
4599 /* Allocate hardware IRQ controller */
4600 ppc6xx_irq_init(env);
4601 }
4602
4603 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4604 {
4605 DeviceClass *dc = DEVICE_CLASS(oc);
4606 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4607
4608 dc->desc = "e300 core";
4609 pcc->init_proc = init_proc_e300;
4610 pcc->check_pow = check_pow_hid0;
4611 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4612 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4613 PPC_FLOAT_STFIWX |
4614 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4615 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4616 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4617 PPC_SEGMENT | PPC_EXTERN;
4618 pcc->msr_mask = (1ull << MSR_POW) |
4619 (1ull << MSR_TGPR) |
4620 (1ull << MSR_ILE) |
4621 (1ull << MSR_EE) |
4622 (1ull << MSR_PR) |
4623 (1ull << MSR_FP) |
4624 (1ull << MSR_ME) |
4625 (1ull << MSR_FE0) |
4626 (1ull << MSR_SE) |
4627 (1ull << MSR_DE) |
4628 (1ull << MSR_FE1) |
4629 (1ull << MSR_AL) |
4630 (1ull << MSR_EP) |
4631 (1ull << MSR_IR) |
4632 (1ull << MSR_DR) |
4633 (1ull << MSR_RI) |
4634 (1ull << MSR_LE);
4635 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4636 pcc->excp_model = POWERPC_EXCP_603;
4637 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4638 pcc->bfd_mach = bfd_mach_ppc_603;
4639 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4640 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4641 }
4642
4643 #if !defined(CONFIG_USER_ONLY)
4644 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4645 {
4646 TCGv val = tcg_temp_new();
4647 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4648 gen_store_spr(SPR_BOOKE_MAS3, val);
4649 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4650 gen_store_spr(SPR_BOOKE_MAS7, val);
4651 tcg_temp_free(val);
4652 }
4653
4654 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4655 {
4656 TCGv mas7 = tcg_temp_new();
4657 TCGv mas3 = tcg_temp_new();
4658 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4659 tcg_gen_shli_tl(mas7, mas7, 32);
4660 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4661 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4662 tcg_temp_free(mas3);
4663 tcg_temp_free(mas7);
4664 }
4665
4666 #endif
4667
4668 enum fsl_e500_version {
4669 fsl_e500v1,
4670 fsl_e500v2,
4671 fsl_e500mc,
4672 fsl_e5500,
4673 };
4674
4675 static void init_proc_e500 (CPUPPCState *env, int version)
4676 {
4677 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4678 uint32_t tlbncfg[2];
4679 uint64_t ivor_mask;
4680 uint64_t ivpr_mask = 0xFFFF0000ULL;
4681 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4682 | 0x0020; /* 32 kb */
4683 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4684 | 0x0020; /* 32 kb */
4685 #if !defined(CONFIG_USER_ONLY)
4686 int i;
4687 #endif
4688
4689 /* Time base */
4690 gen_tbl(env);
4691 /*
4692 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4693 * complain when accessing them.
4694 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4695 */
4696 switch (version) {
4697 case fsl_e500v1:
4698 case fsl_e500v2:
4699 default:
4700 ivor_mask = 0x0000000F0000FFFFULL;
4701 break;
4702 case fsl_e500mc:
4703 case fsl_e5500:
4704 ivor_mask = 0x000003FE0000FFFFULL;
4705 break;
4706 }
4707 gen_spr_BookE(env, ivor_mask);
4708 /* Processor identification */
4709 spr_register(env, SPR_BOOKE_PIR, "PIR",
4710 SPR_NOACCESS, SPR_NOACCESS,
4711 &spr_read_generic, &spr_write_pir,
4712 0x00000000);
4713 /* XXX : not implemented */
4714 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4715 &spr_read_spefscr, &spr_write_spefscr,
4716 &spr_read_spefscr, &spr_write_spefscr,
4717 0x00000000);
4718 #if !defined(CONFIG_USER_ONLY)
4719 /* Memory management */
4720 env->nb_pids = 3;
4721 env->nb_ways = 2;
4722 env->id_tlbs = 0;
4723 switch (version) {
4724 case fsl_e500v1:
4725 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4726 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4727 break;
4728 case fsl_e500v2:
4729 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4730 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4731 break;
4732 case fsl_e500mc:
4733 case fsl_e5500:
4734 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4735 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4736 break;
4737 default:
4738 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4739 }
4740 #endif
4741 /* Cache sizes */
4742 switch (version) {
4743 case fsl_e500v1:
4744 case fsl_e500v2:
4745 env->dcache_line_size = 32;
4746 env->icache_line_size = 32;
4747 break;
4748 case fsl_e500mc:
4749 case fsl_e5500:
4750 env->dcache_line_size = 64;
4751 env->icache_line_size = 64;
4752 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4753 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4754 break;
4755 default:
4756 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4757 }
4758 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4759 /* XXX : not implemented */
4760 spr_register(env, SPR_HID0, "HID0",
4761 SPR_NOACCESS, SPR_NOACCESS,
4762 &spr_read_generic, &spr_write_generic,
4763 0x00000000);
4764 /* XXX : not implemented */
4765 spr_register(env, SPR_HID1, "HID1",
4766 SPR_NOACCESS, SPR_NOACCESS,
4767 &spr_read_generic, &spr_write_generic,
4768 0x00000000);
4769 /* XXX : not implemented */
4770 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4771 SPR_NOACCESS, SPR_NOACCESS,
4772 &spr_read_generic, &spr_write_generic,
4773 0x00000000);
4774 /* XXX : not implemented */
4775 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4776 SPR_NOACCESS, SPR_NOACCESS,
4777 &spr_read_generic, &spr_write_generic,
4778 0x00000000);
4779 /* XXX : not implemented */
4780 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4781 SPR_NOACCESS, SPR_NOACCESS,
4782 &spr_read_generic, &spr_write_generic,
4783 0x00000000);
4784 /* XXX : not implemented */
4785 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4786 SPR_NOACCESS, SPR_NOACCESS,
4787 &spr_read_generic, &spr_write_generic,
4788 0x00000000);
4789 /* XXX : not implemented */
4790 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4791 SPR_NOACCESS, SPR_NOACCESS,
4792 &spr_read_generic, &spr_write_generic,
4793 0x00000000);
4794 /* XXX : not implemented */
4795 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4796 SPR_NOACCESS, SPR_NOACCESS,
4797 &spr_read_generic, &spr_write_generic,
4798 0x00000000);
4799 /* XXX : not implemented */
4800 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4801 &spr_read_generic, SPR_NOACCESS,
4802 &spr_read_generic, SPR_NOACCESS,
4803 l1cfg0);
4804 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4805 &spr_read_generic, SPR_NOACCESS,
4806 &spr_read_generic, SPR_NOACCESS,
4807 l1cfg1);
4808 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4809 SPR_NOACCESS, SPR_NOACCESS,
4810 &spr_read_generic, &spr_write_e500_l1csr0,
4811 0x00000000);
4812 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4813 SPR_NOACCESS, SPR_NOACCESS,
4814 &spr_read_generic, &spr_write_e500_l1csr1,
4815 0x00000000);
4816 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4817 SPR_NOACCESS, SPR_NOACCESS,
4818 &spr_read_generic, &spr_write_generic,
4819 0x00000000);
4820 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4821 SPR_NOACCESS, SPR_NOACCESS,
4822 &spr_read_generic, &spr_write_generic,
4823 0x00000000);
4824 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4825 SPR_NOACCESS, SPR_NOACCESS,
4826 &spr_read_generic, &spr_write_booke206_mmucsr0,
4827 0x00000000);
4828 spr_register(env, SPR_BOOKE_EPR, "EPR",
4829 SPR_NOACCESS, SPR_NOACCESS,
4830 &spr_read_generic, SPR_NOACCESS,
4831 0x00000000);
4832 /* XXX better abstract into Emb.xxx features */
4833 if (version == fsl_e5500) {
4834 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4835 SPR_NOACCESS, SPR_NOACCESS,
4836 &spr_read_generic, &spr_write_generic,
4837 0x00000000);
4838 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4839 SPR_NOACCESS, SPR_NOACCESS,
4840 &spr_read_mas73, &spr_write_mas73,
4841 0x00000000);
4842 ivpr_mask = (target_ulong)~0xFFFFULL;
4843 }
4844
4845 #if !defined(CONFIG_USER_ONLY)
4846 env->nb_tlb = 0;
4847 env->tlb_type = TLB_MAS;
4848 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4849 env->nb_tlb += booke206_tlb_size(env, i);
4850 }
4851 #endif
4852
4853 init_excp_e200(env, ivpr_mask);
4854 /* Allocate hardware IRQ controller */
4855 ppce500_irq_init(env);
4856 }
4857
4858 static void init_proc_e500v1(CPUPPCState *env)
4859 {
4860 init_proc_e500(env, fsl_e500v1);
4861 }
4862
4863 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4864 {
4865 DeviceClass *dc = DEVICE_CLASS(oc);
4866 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4867
4868 dc->desc = "e500v1 core";
4869 pcc->init_proc = init_proc_e500v1;
4870 pcc->check_pow = check_pow_hid0;
4871 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4872 PPC_SPE | PPC_SPE_SINGLE |
4873 PPC_WRTEE | PPC_RFDI |
4874 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4875 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4876 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4877 pcc->insns_flags2 = PPC2_BOOKE206;
4878 pcc->msr_mask = (1ull << MSR_UCLE) |
4879 (1ull << MSR_SPE) |
4880 (1ull << MSR_POW) |
4881 (1ull << MSR_CE) |
4882 (1ull << MSR_EE) |
4883 (1ull << MSR_PR) |
4884 (1ull << MSR_FP) |
4885 (1ull << MSR_ME) |
4886 (1ull << MSR_FE0) |
4887 (1ull << MSR_DWE) |
4888 (1ull << MSR_DE) |
4889 (1ull << MSR_FE1) |
4890 (1ull << MSR_IR) |
4891 (1ull << MSR_DR);
4892 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4893 pcc->excp_model = POWERPC_EXCP_BOOKE;
4894 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4895 pcc->bfd_mach = bfd_mach_ppc_860;
4896 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4897 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4898 POWERPC_FLAG_BUS_CLK;
4899 }
4900
4901 static void init_proc_e500v2(CPUPPCState *env)
4902 {
4903 init_proc_e500(env, fsl_e500v2);
4904 }
4905
4906 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4907 {
4908 DeviceClass *dc = DEVICE_CLASS(oc);
4909 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4910
4911 dc->desc = "e500v2 core";
4912 pcc->init_proc = init_proc_e500v2;
4913 pcc->check_pow = check_pow_hid0;
4914 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4915 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4916 PPC_WRTEE | PPC_RFDI |
4917 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4918 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4919 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4920 pcc->insns_flags2 = PPC2_BOOKE206;
4921 pcc->msr_mask = (1ull << MSR_UCLE) |
4922 (1ull << MSR_SPE) |
4923 (1ull << MSR_POW) |
4924 (1ull << MSR_CE) |
4925 (1ull << MSR_EE) |
4926 (1ull << MSR_PR) |
4927 (1ull << MSR_FP) |
4928 (1ull << MSR_ME) |
4929 (1ull << MSR_FE0) |
4930 (1ull << MSR_DWE) |
4931 (1ull << MSR_DE) |
4932 (1ull << MSR_FE1) |
4933 (1ull << MSR_IR) |
4934 (1ull << MSR_DR);
4935 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4936 pcc->excp_model = POWERPC_EXCP_BOOKE;
4937 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4938 pcc->bfd_mach = bfd_mach_ppc_860;
4939 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4940 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4941 POWERPC_FLAG_BUS_CLK;
4942 }
4943
4944 static void init_proc_e500mc(CPUPPCState *env)
4945 {
4946 init_proc_e500(env, fsl_e500mc);
4947 }
4948
4949 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4950 {
4951 DeviceClass *dc = DEVICE_CLASS(oc);
4952 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4953
4954 dc->desc = "e500mc core";
4955 pcc->init_proc = init_proc_e500mc;
4956 pcc->check_pow = check_pow_none;
4957 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4958 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4959 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4960 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4961 PPC_FLOAT | PPC_FLOAT_FRES |
4962 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4963 PPC_FLOAT_STFIWX | PPC_WAIT |
4964 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4965 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4966 pcc->msr_mask = (1ull << MSR_GS) |
4967 (1ull << MSR_UCLE) |
4968 (1ull << MSR_CE) |
4969 (1ull << MSR_EE) |
4970 (1ull << MSR_PR) |
4971 (1ull << MSR_FP) |
4972 (1ull << MSR_ME) |
4973 (1ull << MSR_FE0) |
4974 (1ull << MSR_DE) |
4975 (1ull << MSR_FE1) |
4976 (1ull << MSR_IR) |
4977 (1ull << MSR_DR) |
4978 (1ull << MSR_PX) |
4979 (1ull << MSR_RI);
4980 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4981 pcc->excp_model = POWERPC_EXCP_BOOKE;
4982 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4983 /* FIXME: figure out the correct flag for e500mc */
4984 pcc->bfd_mach = bfd_mach_ppc_e500;
4985 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4986 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4987 }
4988
4989 #ifdef TARGET_PPC64
4990 static void init_proc_e5500(CPUPPCState *env)
4991 {
4992 init_proc_e500(env, fsl_e5500);
4993 }
4994
4995 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4996 {
4997 DeviceClass *dc = DEVICE_CLASS(oc);
4998 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4999
5000 dc->desc = "e5500 core";
5001 pcc->init_proc = init_proc_e5500;
5002 pcc->check_pow = check_pow_none;
5003 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5004 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5005 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5006 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5007 PPC_FLOAT | PPC_FLOAT_FRES |
5008 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5009 PPC_FLOAT_STFIWX | PPC_WAIT |
5010 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5011 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5012 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206;
5013 pcc->msr_mask = (1ull << MSR_CM) |
5014 (1ull << MSR_GS) |
5015 (1ull << MSR_UCLE) |
5016 (1ull << MSR_CE) |
5017 (1ull << MSR_EE) |
5018 (1ull << MSR_PR) |
5019 (1ull << MSR_FP) |
5020 (1ull << MSR_ME) |
5021 (1ull << MSR_FE0) |
5022 (1ull << MSR_DE) |
5023 (1ull << MSR_FE1) |
5024 (1ull << MSR_IR) |
5025 (1ull << MSR_DR) |
5026 (1ull << MSR_PX) |
5027 (1ull << MSR_RI);
5028 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5029 pcc->excp_model = POWERPC_EXCP_BOOKE;
5030 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5031 /* FIXME: figure out the correct flag for e5500 */
5032 pcc->bfd_mach = bfd_mach_ppc_e500;
5033 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5034 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5035 }
5036 #endif
5037
5038 /* Non-embedded PowerPC */
5039
5040 /* POWER : same as 601, without mfmsr, mfsr */
5041 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
5042 {
5043 DeviceClass *dc = DEVICE_CLASS(oc);
5044 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5045
5046 dc->desc = "POWER";
5047 /* pcc->insns_flags = XXX_TODO; */
5048 /* POWER RSC (from RAD6000) */
5049 pcc->msr_mask = (1ull << MSR_EE) |
5050 (1ull << MSR_PR) |
5051 (1ull << MSR_FP) |
5052 (1ull << MSR_ME) |
5053 (1ull << MSR_FE0) |
5054 (1ull << MSR_SE) |
5055 (1ull << MSR_DE) |
5056 (1ull << MSR_AL) |
5057 (1ull << MSR_EP) |
5058 (1ull << MSR_IR) |
5059 (1ull << MSR_DR);
5060 }
5061
5062 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5063
5064 static void init_proc_601 (CPUPPCState *env)
5065 {
5066 gen_spr_ne_601(env);
5067 gen_spr_601(env);
5068 /* Hardware implementation registers */
5069 /* XXX : not implemented */
5070 spr_register(env, SPR_HID0, "HID0",
5071 SPR_NOACCESS, SPR_NOACCESS,
5072 &spr_read_generic, &spr_write_hid0_601,
5073 0x80010080);
5074 /* XXX : not implemented */
5075 spr_register(env, SPR_HID1, "HID1",
5076 SPR_NOACCESS, SPR_NOACCESS,
5077 &spr_read_generic, &spr_write_generic,
5078 0x00000000);
5079 /* XXX : not implemented */
5080 spr_register(env, SPR_601_HID2, "HID2",
5081 SPR_NOACCESS, SPR_NOACCESS,
5082 &spr_read_generic, &spr_write_generic,
5083 0x00000000);
5084 /* XXX : not implemented */
5085 spr_register(env, SPR_601_HID5, "HID5",
5086 SPR_NOACCESS, SPR_NOACCESS,
5087 &spr_read_generic, &spr_write_generic,
5088 0x00000000);
5089 /* Memory management */
5090 init_excp_601(env);
5091 /* XXX: beware that dcache line size is 64
5092 * but dcbz uses 32 bytes "sectors"
5093 * XXX: this breaks clcs instruction !
5094 */
5095 env->dcache_line_size = 32;
5096 env->icache_line_size = 64;
5097 /* Allocate hardware IRQ controller */
5098 ppc6xx_irq_init(env);
5099 }
5100
5101 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5102 {
5103 DeviceClass *dc = DEVICE_CLASS(oc);
5104 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5105
5106 dc->desc = "PowerPC 601";
5107 pcc->init_proc = init_proc_601;
5108 pcc->check_pow = check_pow_none;
5109 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5110 PPC_FLOAT |
5111 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5112 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5113 PPC_SEGMENT | PPC_EXTERN;
5114 pcc->msr_mask = (1ull << MSR_EE) |
5115 (1ull << MSR_PR) |
5116 (1ull << MSR_FP) |
5117 (1ull << MSR_ME) |
5118 (1ull << MSR_FE0) |
5119 (1ull << MSR_SE) |
5120 (1ull << MSR_FE1) |
5121 (1ull << MSR_EP) |
5122 (1ull << MSR_IR) |
5123 (1ull << MSR_DR);
5124 pcc->mmu_model = POWERPC_MMU_601;
5125 #if defined(CONFIG_SOFTMMU)
5126 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5127 #endif
5128 pcc->excp_model = POWERPC_EXCP_601;
5129 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5130 pcc->bfd_mach = bfd_mach_ppc_601;
5131 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5132 }
5133
5134 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5135
5136 static void init_proc_601v (CPUPPCState *env)
5137 {
5138 init_proc_601(env);
5139 /* XXX : not implemented */
5140 spr_register(env, SPR_601_HID15, "HID15",
5141 SPR_NOACCESS, SPR_NOACCESS,
5142 &spr_read_generic, &spr_write_generic,
5143 0x00000000);
5144 }
5145
5146 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5147 {
5148 DeviceClass *dc = DEVICE_CLASS(oc);
5149 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5150
5151 dc->desc = "PowerPC 601v";
5152 pcc->init_proc = init_proc_601v;
5153 pcc->check_pow = check_pow_none;
5154 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5155 PPC_FLOAT |
5156 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5157 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5158 PPC_SEGMENT | PPC_EXTERN;
5159 pcc->msr_mask = (1ull << MSR_EE) |
5160 (1ull << MSR_PR) |
5161 (1ull << MSR_FP) |
5162 (1ull << MSR_ME) |
5163 (1ull << MSR_FE0) |
5164 (1ull << MSR_SE) |
5165 (1ull << MSR_FE1) |
5166 (1ull << MSR_EP) |
5167 (1ull << MSR_IR) |
5168 (1ull << MSR_DR);
5169 pcc->mmu_model = POWERPC_MMU_601;
5170 #if defined(CONFIG_SOFTMMU)
5171 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5172 #endif
5173 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5174 pcc->bfd_mach = bfd_mach_ppc_601;
5175 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5176 }
5177
5178 static void init_proc_602 (CPUPPCState *env)
5179 {
5180 gen_spr_ne_601(env);
5181 gen_spr_602(env);
5182 /* Time base */
5183 gen_tbl(env);
5184 /* hardware implementation registers */
5185 /* XXX : not implemented */
5186 spr_register(env, SPR_HID0, "HID0",
5187 SPR_NOACCESS, SPR_NOACCESS,
5188 &spr_read_generic, &spr_write_generic,
5189 0x00000000);
5190 /* XXX : not implemented */
5191 spr_register(env, SPR_HID1, "HID1",
5192 SPR_NOACCESS, SPR_NOACCESS,
5193 &spr_read_generic, &spr_write_generic,
5194 0x00000000);
5195 /* Memory management */
5196 gen_low_BATs(env);
5197 gen_6xx_7xx_soft_tlb(env, 64, 2);
5198 init_excp_602(env);
5199 env->dcache_line_size = 32;
5200 env->icache_line_size = 32;
5201 /* Allocate hardware IRQ controller */
5202 ppc6xx_irq_init(env);
5203 }
5204
5205 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5206 {
5207 DeviceClass *dc = DEVICE_CLASS(oc);
5208 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5209
5210 dc->desc = "PowerPC 602";
5211 pcc->init_proc = init_proc_602;
5212 pcc->check_pow = check_pow_hid0;
5213 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5214 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5215 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5216 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5217 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5218 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5219 PPC_SEGMENT | PPC_602_SPEC;
5220 pcc->msr_mask = (1ull << MSR_VSX) |
5221 (1ull << MSR_SA) |
5222 (1ull << MSR_POW) |
5223 (1ull << MSR_TGPR) |
5224 (1ull << MSR_ILE) |
5225 (1ull << MSR_EE) |
5226 (1ull << MSR_PR) |
5227 (1ull << MSR_FP) |
5228 (1ull << MSR_ME) |
5229 (1ull << MSR_FE0) |
5230 (1ull << MSR_SE) |
5231 (1ull << MSR_DE) |
5232 (1ull << MSR_FE1) |
5233 (1ull << MSR_EP) |
5234 (1ull << MSR_IR) |
5235 (1ull << MSR_DR) |
5236 (1ull << MSR_RI) |
5237 (1ull << MSR_LE);
5238 /* XXX: 602 MMU is quite specific. Should add a special case */
5239 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5240 pcc->excp_model = POWERPC_EXCP_602;
5241 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5242 pcc->bfd_mach = bfd_mach_ppc_602;
5243 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5244 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5245 }
5246
5247 static void init_proc_603 (CPUPPCState *env)
5248 {
5249 gen_spr_ne_601(env);
5250 gen_spr_603(env);
5251 /* Time base */
5252 gen_tbl(env);
5253 /* hardware implementation registers */
5254 /* XXX : not implemented */
5255 spr_register(env, SPR_HID0, "HID0",
5256 SPR_NOACCESS, SPR_NOACCESS,
5257 &spr_read_generic, &spr_write_generic,
5258 0x00000000);
5259 /* XXX : not implemented */
5260 spr_register(env, SPR_HID1, "HID1",
5261 SPR_NOACCESS, SPR_NOACCESS,
5262 &spr_read_generic, &spr_write_generic,
5263 0x00000000);
5264 /* Memory management */
5265 gen_low_BATs(env);
5266 gen_6xx_7xx_soft_tlb(env, 64, 2);
5267 init_excp_603(env);
5268 env->dcache_line_size = 32;
5269 env->icache_line_size = 32;
5270 /* Allocate hardware IRQ controller */
5271 ppc6xx_irq_init(env);
5272 }
5273
5274 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5275 {
5276 DeviceClass *dc = DEVICE_CLASS(oc);
5277 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5278
5279 dc->desc = "PowerPC 603";
5280 pcc->init_proc = init_proc_603;
5281 pcc->check_pow = check_pow_hid0;
5282 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5283 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5284 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5285 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5286 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5287 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5288 PPC_SEGMENT | PPC_EXTERN;
5289 pcc->msr_mask = (1ull << MSR_POW) |
5290 (1ull << MSR_TGPR) |
5291 (1ull << MSR_ILE) |
5292 (1ull << MSR_EE) |
5293 (1ull << MSR_PR) |
5294 (1ull << MSR_FP) |
5295 (1ull << MSR_ME) |
5296 (1ull << MSR_FE0) |
5297 (1ull << MSR_SE) |
5298 (1ull << MSR_DE) |
5299 (1ull << MSR_FE1) |
5300 (1ull << MSR_EP) |
5301 (1ull << MSR_IR) |
5302 (1ull << MSR_DR) |
5303 (1ull << MSR_RI) |
5304 (1ull << MSR_LE);
5305 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5306 pcc->excp_model = POWERPC_EXCP_603;
5307 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5308 pcc->bfd_mach = bfd_mach_ppc_603;
5309 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5310 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5311 }
5312
5313 static void init_proc_603E (CPUPPCState *env)
5314 {
5315 gen_spr_ne_601(env);
5316 gen_spr_603(env);
5317 /* Time base */
5318 gen_tbl(env);
5319 /* hardware implementation registers */
5320 /* XXX : not implemented */
5321 spr_register(env, SPR_HID0, "HID0",
5322 SPR_NOACCESS, SPR_NOACCESS,
5323 &spr_read_generic, &spr_write_generic,
5324 0x00000000);
5325 /* XXX : not implemented */
5326 spr_register(env, SPR_HID1, "HID1",
5327 SPR_NOACCESS, SPR_NOACCESS,
5328 &spr_read_generic, &spr_write_generic,
5329 0x00000000);
5330 /* Memory management */
5331 gen_low_BATs(env);
5332 gen_6xx_7xx_soft_tlb(env, 64, 2);
5333 init_excp_603(env);
5334 env->dcache_line_size = 32;
5335 env->icache_line_size = 32;
5336 /* Allocate hardware IRQ controller */
5337 ppc6xx_irq_init(env);
5338 }
5339
5340 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5341 {
5342 DeviceClass *dc = DEVICE_CLASS(oc);
5343 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5344
5345 dc->desc = "PowerPC 603e";
5346 pcc->init_proc = init_proc_603E;
5347 pcc->check_pow = check_pow_hid0;
5348 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5349 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5350 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5351 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5352 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5353 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5354 PPC_SEGMENT | PPC_EXTERN;
5355 pcc->msr_mask = (1ull << MSR_POW) |
5356 (1ull << MSR_TGPR) |
5357 (1ull << MSR_ILE) |
5358 (1ull << MSR_EE) |
5359 (1ull << MSR_PR) |
5360 (1ull << MSR_FP) |
5361 (1ull << MSR_ME) |
5362 (1ull << MSR_FE0) |
5363 (1ull << MSR_SE) |
5364 (1ull << MSR_DE) |
5365 (1ull << MSR_FE1) |
5366 (1ull << MSR_EP) |
5367 (1ull << MSR_IR) |
5368 (1ull << MSR_DR) |
5369 (1ull << MSR_RI) |
5370 (1ull << MSR_LE);
5371 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5372 pcc->excp_model = POWERPC_EXCP_603E;
5373 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5374 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5375 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5376 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5377 }
5378
5379 static void init_proc_604 (CPUPPCState *env)
5380 {
5381 gen_spr_ne_601(env);
5382 gen_spr_604(env);
5383 /* Time base */
5384 gen_tbl(env);
5385 /* Hardware implementation registers */
5386 /* XXX : not implemented */
5387 spr_register(env, SPR_HID0, "HID0",
5388 SPR_NOACCESS, SPR_NOACCESS,
5389 &spr_read_generic, &spr_write_generic,
5390 0x00000000);
5391 /* Memory management */
5392 gen_low_BATs(env);
5393 init_excp_604(env);
5394 env->dcache_line_size = 32;
5395 env->icache_line_size = 32;
5396 /* Allocate hardware IRQ controller */
5397 ppc6xx_irq_init(env);
5398 }
5399
5400 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5401 {
5402 DeviceClass *dc = DEVICE_CLASS(oc);
5403 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5404
5405 dc->desc = "PowerPC 604";
5406 pcc->init_proc = init_proc_604;
5407 pcc->check_pow = check_pow_nocheck;
5408 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5409 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5410 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5411 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5412 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5413 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5414 PPC_SEGMENT | PPC_EXTERN;
5415 pcc->msr_mask = (1ull << MSR_POW) |
5416 (1ull << MSR_ILE) |
5417 (1ull << MSR_EE) |
5418 (1ull << MSR_PR) |
5419 (1ull << MSR_FP) |
5420 (1ull << MSR_ME) |
5421 (1ull << MSR_FE0) |
5422 (1ull << MSR_SE) |
5423 (1ull << MSR_DE) |
5424 (1ull << MSR_FE1) |
5425 (1ull << MSR_EP) |
5426 (1ull << MSR_IR) |
5427 (1ull << MSR_DR) |
5428 (1ull << MSR_PMM) |
5429 (1ull << MSR_RI) |
5430 (1ull << MSR_LE);
5431 pcc->mmu_model = POWERPC_MMU_32B;
5432 #if defined(CONFIG_SOFTMMU)
5433 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5434 #endif
5435 pcc->excp_model = POWERPC_EXCP_604;
5436 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5437 pcc->bfd_mach = bfd_mach_ppc_604;
5438 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5439 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5440 }
5441
5442 static void init_proc_604E (CPUPPCState *env)
5443 {
5444 gen_spr_ne_601(env);
5445 gen_spr_604(env);
5446 /* XXX : not implemented */
5447 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 /* XXX : not implemented */
5452 spr_register(env, SPR_7XX_PMC3, "PMC3",
5453 SPR_NOACCESS, SPR_NOACCESS,
5454 &spr_read_generic, &spr_write_generic,
5455 0x00000000);
5456 /* XXX : not implemented */
5457 spr_register(env, SPR_7XX_PMC4, "PMC4",
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_write_generic,
5460 0x00000000);
5461 /* Time base */
5462 gen_tbl(env);
5463 /* Hardware implementation registers */
5464 /* XXX : not implemented */
5465 spr_register(env, SPR_HID0, "HID0",
5466 SPR_NOACCESS, SPR_NOACCESS,
5467 &spr_read_generic, &spr_write_generic,
5468 0x00000000);
5469 /* XXX : not implemented */
5470 spr_register(env, SPR_HID1, "HID1",
5471 SPR_NOACCESS, SPR_NOACCESS,
5472 &spr_read_generic, &spr_write_generic,
5473 0x00000000);
5474 /* Memory management */
5475 gen_low_BATs(env);
5476 init_excp_604(env);
5477 env->dcache_line_size = 32;
5478 env->icache_line_size = 32;
5479 /* Allocate hardware IRQ controller */
5480 ppc6xx_irq_init(env);
5481 }
5482
5483 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5484 {
5485 DeviceClass *dc = DEVICE_CLASS(oc);
5486 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5487
5488 dc->desc = "PowerPC 604E";
5489 pcc->init_proc = init_proc_604E;
5490 pcc->check_pow = check_pow_nocheck;
5491 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5492 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5493 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5494 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5495 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5496 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5497 PPC_SEGMENT | PPC_EXTERN;
5498 pcc->msr_mask = (1ull << MSR_POW) |
5499 (1ull << MSR_ILE) |
5500 (1ull << MSR_EE) |
5501 (1ull << MSR_PR) |
5502 (1ull << MSR_FP) |
5503 (1ull << MSR_ME) |
5504 (1ull << MSR_FE0) |
5505 (1ull << MSR_SE) |
5506 (1ull << MSR_DE) |
5507 (1ull << MSR_FE1) |
5508 (1ull << MSR_EP) |
5509 (1ull << MSR_IR) |
5510 (1ull << MSR_DR) |
5511 (1ull << MSR_PMM) |
5512 (1ull << MSR_RI) |
5513 (1ull << MSR_LE);
5514 pcc->mmu_model = POWERPC_MMU_32B;
5515 #if defined(CONFIG_SOFTMMU)
5516 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5517 #endif
5518 pcc->excp_model = POWERPC_EXCP_604;
5519 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5520 pcc->bfd_mach = bfd_mach_ppc_604;
5521 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5522 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5523 }
5524
5525 static void init_proc_740 (CPUPPCState *env)
5526 {
5527 gen_spr_ne_601(env);
5528 gen_spr_7xx(env);
5529 /* Time base */
5530 gen_tbl(env);
5531 /* Thermal management */
5532 gen_spr_thrm(env);
5533 /* Hardware implementation registers */
5534 /* XXX : not implemented */
5535 spr_register(env, SPR_HID0, "HID0",
5536 SPR_NOACCESS, SPR_NOACCESS,
5537 &spr_read_generic, &spr_write_generic,
5538 0x00000000);
5539 /* XXX : not implemented */
5540 spr_register(env, SPR_HID1, "HID1",
5541 SPR_NOACCESS, SPR_NOACCESS,
5542 &spr_read_generic, &spr_write_generic,
5543 0x00000000);
5544 /* Memory management */
5545 gen_low_BATs(env);
5546 init_excp_7x0(env);
5547 env->dcache_line_size = 32;
5548 env->icache_line_size = 32;
5549 /* Allocate hardware IRQ controller */
5550 ppc6xx_irq_init(env);
5551 }
5552
5553 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5554 {
5555 DeviceClass *dc = DEVICE_CLASS(oc);
5556 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5557
5558 dc->desc = "PowerPC 740";
5559 pcc->init_proc = init_proc_740;
5560 pcc->check_pow = check_pow_hid0;
5561 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5562 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5563 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5564 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5565 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5566 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5567 PPC_SEGMENT | PPC_EXTERN;
5568 pcc->msr_mask = (1ull << MSR_POW) |
5569 (1ull << MSR_ILE) |
5570 (1ull << MSR_EE) |
5571 (1ull << MSR_PR) |
5572 (1ull << MSR_FP) |
5573 (1ull << MSR_ME) |
5574 (1ull << MSR_FE0) |
5575 (1ull << MSR_SE) |
5576 (1ull << MSR_DE) |
5577 (1ull << MSR_FE1) |
5578 (1ull << MSR_EP) |
5579 (1ull << MSR_IR) |
5580 (1ull << MSR_DR) |
5581 (1ull << MSR_PMM) |
5582 (1ull << MSR_RI) |
5583 (1ull << MSR_LE);
5584 pcc->mmu_model = POWERPC_MMU_32B;
5585 #if defined(CONFIG_SOFTMMU)
5586 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5587 #endif
5588 pcc->excp_model = POWERPC_EXCP_7x0;
5589 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5590 pcc->bfd_mach = bfd_mach_ppc_750;
5591 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5592 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5593 }
5594
5595 static void init_proc_750 (CPUPPCState *env)
5596 {
5597 gen_spr_ne_601(env);
5598 gen_spr_7xx(env);
5599 /* XXX : not implemented */
5600 spr_register(env, SPR_L2CR, "L2CR",
5601 SPR_NOACCESS, SPR_NOACCESS,
5602 &spr_read_generic, spr_access_nop,
5603 0x00000000);
5604 /* Time base */
5605 gen_tbl(env);
5606 /* Thermal management */
5607 gen_spr_thrm(env);
5608 /* Hardware implementation registers */
5609 /* XXX : not implemented */
5610 spr_register(env, SPR_HID0, "HID0",
5611 SPR_NOACCESS, SPR_NOACCESS,
5612 &spr_read_generic, &spr_write_generic,
5613 0x00000000);
5614 /* XXX : not implemented */
5615 spr_register(env, SPR_HID1, "HID1",
5616 SPR_NOACCESS, SPR_NOACCESS,
5617 &spr_read_generic, &spr_write_generic,
5618 0x00000000);
5619 /* Memory management */
5620 gen_low_BATs(env);
5621 /* XXX: high BATs are also present but are known to be bugged on
5622 * die version 1.x
5623 */
5624 init_excp_7x0(env);
5625 env->dcache_line_size = 32;
5626 env->icache_line_size = 32;
5627 /* Allocate hardware IRQ controller */
5628 ppc6xx_irq_init(env);
5629 }
5630
5631 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5632 {
5633 DeviceClass *dc = DEVICE_CLASS(oc);
5634 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5635
5636 dc->desc = "PowerPC 750";
5637 pcc->init_proc = init_proc_750;
5638 pcc->check_pow = check_pow_hid0;
5639 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5640 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5641 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5642 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5643 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5644 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5645 PPC_SEGMENT | PPC_EXTERN;
5646 pcc->msr_mask = (1ull << MSR_POW) |
5647 (1ull << MSR_ILE) |
5648 (1ull << MSR_EE) |
5649 (1ull << MSR_PR) |
5650 (1ull << MSR_FP) |
5651 (1ull << MSR_ME) |
5652 (1ull << MSR_FE0) |
5653 (1ull << MSR_SE) |
5654 (1ull << MSR_DE) |
5655 (1ull << MSR_FE1) |
5656 (1ull << MSR_EP) |
5657 (1ull << MSR_IR) |
5658 (1ull << MSR_DR) |
5659 (1ull << MSR_PMM) |
5660 (1ull << MSR_RI) |
5661 (1ull << MSR_LE);
5662 pcc->mmu_model = POWERPC_MMU_32B;
5663 #if defined(CONFIG_SOFTMMU)
5664 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5665 #endif
5666 pcc->excp_model = POWERPC_EXCP_7x0;
5667 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5668 pcc->bfd_mach = bfd_mach_ppc_750;
5669 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5670 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5671 }
5672
5673 static void init_proc_750cl (CPUPPCState *env)
5674 {
5675 gen_spr_ne_601(env);
5676 gen_spr_7xx(env);
5677 /* XXX : not implemented */
5678 spr_register(env, SPR_L2CR, "L2CR",
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_generic, spr_access_nop,
5681 0x00000000);
5682 /* Time base */
5683 gen_tbl(env);
5684 /* Thermal management */
5685 /* Those registers are fake on 750CL */
5686 spr_register(env, SPR_THRM1, "THRM1",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic,
5689 0x00000000);
5690 spr_register(env, SPR_THRM2, "THRM2",
5691 SPR_NOACCESS, SPR_NOACCESS,
5692 &spr_read_generic, &spr_write_generic,
5693 0x00000000);
5694 spr_register(env, SPR_THRM3, "THRM3",
5695 SPR_NOACCESS, SPR_NOACCESS,
5696 &spr_read_generic, &spr_write_generic,
5697 0x00000000);
5698 /* XXX: not implemented */
5699 spr_register(env, SPR_750_TDCL, "TDCL",
5700 SPR_NOACCESS, SPR_NOACCESS,
5701 &spr_read_generic, &spr_write_generic,
5702 0x00000000);
5703 spr_register(env, SPR_750_TDCH, "TDCH",
5704 SPR_NOACCESS, SPR_NOACCESS,
5705 &spr_read_generic, &spr_write_generic,
5706 0x00000000);
5707 /* DMA */
5708 /* XXX : not implemented */
5709 spr_register(env, SPR_750_WPAR, "WPAR",
5710 SPR_NOACCESS, SPR_NOACCESS,
5711 &spr_read_generic, &spr_write_generic,
5712 0x00000000);
5713 spr_register(env, SPR_750_DMAL, "DMAL",
5714 SPR_NOACCESS, SPR_NOACCESS,
5715 &spr_read_generic, &spr_write_generic,
5716 0x00000000);
5717 spr_register(env, SPR_750_DMAU, "DMAU",
5718 SPR_NOACCESS, SPR_NOACCESS,
5719 &spr_read_generic, &spr_write_generic,
5720 0x00000000);
5721 /* Hardware implementation registers */
5722 /* XXX : not implemented */
5723 spr_register(env, SPR_HID0, "HID0",
5724 SPR_NOACCESS, SPR_NOACCESS,
5725 &spr_read_generic, &spr_write_generic,
5726 0x00000000);
5727 /* XXX : not implemented */
5728 spr_register(env, SPR_HID1, "HID1",
5729 SPR_NOACCESS, SPR_NOACCESS,
5730 &spr_read_generic, &spr_write_generic,
5731 0x00000000);
5732 /* XXX : not implemented */
5733 spr_register(env, SPR_750CL_HID2, "HID2",
5734 SPR_NOACCESS, SPR_NOACCESS,
5735 &spr_read_generic, &spr_write_generic,
5736 0x00000000);
5737 /* XXX : not implemented */
5738 spr_register(env, SPR_750CL_HID4, "HID4",
5739 SPR_NOACCESS, SPR_NOACCESS,
5740 &spr_read_generic, &spr_write_generic,
5741 0x00000000);
5742 /* Quantization registers */
5743 /* XXX : not implemented */
5744 spr_register(env, SPR_750_GQR0, "GQR0",
5745 SPR_NOACCESS, SPR_NOACCESS,
5746 &spr_read_generic, &spr_write_generic,
5747 0x00000000);
5748 /* XXX : not implemented */
5749 spr_register(env, SPR_750_GQR1, "GQR1",
5750 SPR_NOACCESS, SPR_NOACCESS,
5751 &spr_read_generic, &spr_write_generic,
5752 0x00000000);
5753 /* XXX : not implemented */
5754 spr_register(env, SPR_750_GQR2, "GQR2",
5755 SPR_NOACCESS, SPR_NOACCESS,
5756 &spr_read_generic, &spr_write_generic,
5757 0x00000000);
5758 /* XXX : not implemented */
5759 spr_register(env, SPR_750_GQR3, "GQR3",
5760 SPR_NOACCESS, SPR_NOACCESS,
5761 &spr_read_generic, &spr_write_generic,
5762 0x00000000);
5763 /* XXX : not implemented */
5764 spr_register(env, SPR_750_GQR4, "GQR4",
5765 SPR_NOACCESS, SPR_NOACCESS,
5766 &spr_read_generic, &spr_write_generic,
5767 0x00000000);
5768 /* XXX : not implemented */
5769 spr_register(env, SPR_750_GQR5, "GQR5",
5770 SPR_NOACCESS, SPR_NOACCESS,
5771 &spr_read_generic, &spr_write_generic,
5772 0x00000000);
5773 /* XXX : not implemented */
5774 spr_register(env, SPR_750_GQR6, "GQR6",
5775 SPR_NOACCESS, SPR_NOACCESS,
5776 &spr_read_generic, &spr_write_generic,
5777 0x00000000);
5778 /* XXX : not implemented */
5779 spr_register(env, SPR_750_GQR7, "GQR7",
5780 SPR_NOACCESS, SPR_NOACCESS,
5781 &spr_read_generic, &spr_write_generic,
5782 0x00000000);
5783 /* Memory management */
5784 gen_low_BATs(env);
5785 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5786 gen_high_BATs(env);
5787 init_excp_750cl(env);
5788 env->dcache_line_size = 32;
5789 env->icache_line_size = 32;
5790 /* Allocate hardware IRQ controller */
5791 ppc6xx_irq_init(env);
5792 }
5793
5794 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5795 {
5796 DeviceClass *dc = DEVICE_CLASS(oc);
5797 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5798
5799 dc->desc = "PowerPC 750 CL";
5800 pcc->init_proc = init_proc_750cl;
5801 pcc->check_pow = check_pow_hid0;
5802 /* XXX: not implemented:
5803 * cache lock instructions:
5804 * dcbz_l
5805 * floating point paired instructions
5806 * psq_lux
5807 * psq_lx
5808 * psq_stux
5809 * psq_stx
5810 * ps_abs
5811 * ps_add
5812 * ps_cmpo0
5813 * ps_cmpo1
5814 * ps_cmpu0
5815 * ps_cmpu1
5816 * ps_div
5817 * ps_madd
5818 * ps_madds0
5819 * ps_madds1
5820 * ps_merge00
5821 * ps_merge01
5822 * ps_merge10
5823 * ps_merge11
5824 * ps_mr
5825 * ps_msub
5826 * ps_mul
5827 * ps_muls0
5828 * ps_muls1
5829 * ps_nabs
5830 * ps_neg
5831 * ps_nmadd
5832 * ps_nmsub
5833 * ps_res
5834 * ps_rsqrte
5835 * ps_sel
5836 * ps_sub
5837 * ps_sum0
5838 * ps_sum1
5839 */
5840 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5841 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5842 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5843 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5844 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5845 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5846 PPC_SEGMENT | PPC_EXTERN;
5847 pcc->msr_mask = (1ull << MSR_POW) |
5848 (1ull << MSR_ILE) |
5849 (1ull << MSR_EE) |
5850 (1ull << MSR_PR) |
5851 (1ull << MSR_FP) |
5852 (1ull << MSR_ME) |
5853 (1ull << MSR_FE0) |
5854 (1ull << MSR_SE) |
5855 (1ull << MSR_DE) |
5856 (1ull << MSR_FE1) |
5857 (1ull << MSR_EP) |
5858 (1ull << MSR_IR) |
5859 (1ull << MSR_DR) |
5860 (1ull << MSR_PMM) |
5861 (1ull << MSR_RI) |
5862 (1ull << MSR_LE);
5863 pcc->mmu_model = POWERPC_MMU_32B;
5864 #if defined(CONFIG_SOFTMMU)
5865 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5866 #endif
5867 pcc->excp_model = POWERPC_EXCP_7x0;
5868 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5869 pcc->bfd_mach = bfd_mach_ppc_750;
5870 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5871 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5872 }
5873
5874 static void init_proc_750cx (CPUPPCState *env)
5875 {
5876 gen_spr_ne_601(env);
5877 gen_spr_7xx(env);
5878 /* XXX : not implemented */
5879 spr_register(env, SPR_L2CR, "L2CR",
5880 SPR_NOACCESS, SPR_NOACCESS,
5881 &spr_read_generic, spr_access_nop,
5882 0x00000000);
5883 /* Time base */
5884 gen_tbl(env);
5885 /* Thermal management */
5886 gen_spr_thrm(env);
5887 /* This register is not implemented but is present for compatibility */
5888 spr_register(env, SPR_SDA, "SDA",
5889 SPR_NOACCESS, SPR_NOACCESS,
5890 &spr_read_generic, &spr_write_generic,
5891 0x00000000);
5892 /* Hardware implementation registers */
5893 /* XXX : not implemented */
5894 spr_register(env, SPR_HID0, "HID0",
5895 SPR_NOACCESS, SPR_NOACCESS,
5896 &spr_read_generic, &spr_write_generic,
5897 0x00000000);
5898 /* XXX : not implemented */
5899 spr_register(env, SPR_HID1, "HID1",
5900 SPR_NOACCESS, SPR_NOACCESS,
5901 &spr_read_generic, &spr_write_generic,
5902 0x00000000);
5903 /* Memory management */
5904 gen_low_BATs(env);
5905 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5906 gen_high_BATs(env);
5907 init_excp_750cx(env);
5908 env->dcache_line_size = 32;
5909 env->icache_line_size = 32;
5910 /* Allocate hardware IRQ controller */
5911 ppc6xx_irq_init(env);
5912 }
5913
5914 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5915 {
5916 DeviceClass *dc = DEVICE_CLASS(oc);
5917 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5918
5919 dc->desc = "PowerPC 750CX";
5920 pcc->init_proc = init_proc_750cx;
5921 pcc->check_pow = check_pow_hid0;
5922 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5923 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5924 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5925 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5926 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5927 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5928 PPC_SEGMENT | PPC_EXTERN;
5929 pcc->msr_mask = (1ull << MSR_POW) |
5930 (1ull << MSR_ILE) |
5931 (1ull << MSR_EE) |
5932 (1ull << MSR_PR) |
5933 (1ull << MSR_FP) |
5934 (1ull << MSR_ME) |
5935 (1ull << MSR_FE0) |
5936 (1ull << MSR_SE) |
5937 (1ull << MSR_DE) |
5938 (1ull << MSR_FE1) |
5939 (1ull << MSR_EP) |
5940 (1ull << MSR_IR) |
5941 (1ull << MSR_DR) |
5942 (1ull << MSR_PMM) |
5943 (1ull << MSR_RI) |
5944 (1ull << MSR_LE);
5945 pcc->mmu_model = POWERPC_MMU_32B;
5946 #if defined(CONFIG_SOFTMMU)
5947 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5948 #endif
5949 pcc->excp_model = POWERPC_EXCP_7x0;
5950 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5951 pcc->bfd_mach = bfd_mach_ppc_750;
5952 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5953 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5954 }
5955
5956 static void init_proc_750fx (CPUPPCState *env)
5957 {
5958 gen_spr_ne_601(env);
5959 gen_spr_7xx(env);
5960 /* XXX : not implemented */
5961 spr_register(env, SPR_L2CR, "L2CR",
5962 SPR_NOACCESS, SPR_NOACCESS,
5963 &spr_read_generic, spr_access_nop,
5964 0x00000000);
5965 /* Time base */
5966 gen_tbl(env);
5967 /* Thermal management */
5968 gen_spr_thrm(env);
5969 /* XXX : not implemented */
5970 spr_register(env, SPR_750_THRM4, "THRM4",
5971 SPR_NOACCESS, SPR_NOACCESS,
5972 &spr_read_generic, &spr_write_generic,
5973 0x00000000);
5974 /* Hardware implementation registers */
5975 /* XXX : not implemented */
5976 spr_register(env, SPR_HID0, "HID0",
5977 SPR_NOACCESS, SPR_NOACCESS,
5978 &spr_read_generic, &spr_write_generic,
5979 0x00000000);
5980 /* XXX : not implemented */
5981 spr_register(env, SPR_HID1, "HID1",
5982 SPR_NOACCESS, SPR_NOACCESS,
5983 &spr_read_generic, &spr_write_generic,
5984 0x00000000);
5985 /* XXX : not implemented */
5986 spr_register(env, SPR_750FX_HID2, "HID2",
5987 SPR_NOACCESS, SPR_NOACCESS,
5988 &spr_read_generic, &spr_write_generic,
5989 0x00000000);
5990 /* Memory management */
5991 gen_low_BATs(env);
5992 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5993 gen_high_BATs(env);
5994 init_excp_7x0(env);
5995 env->dcache_line_size = 32;
5996 env->icache_line_size = 32;
5997 /* Allocate hardware IRQ controller */
5998 ppc6xx_irq_init(env);
5999 }
6000
6001 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6002 {
6003 DeviceClass *dc = DEVICE_CLASS(oc);
6004 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6005
6006 dc->desc = "PowerPC 750FX";
6007 pcc->init_proc = init_proc_750fx;
6008 pcc->check_pow = check_pow_hid0;
6009 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6010 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6011 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6012 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6013 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6014 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6015 PPC_SEGMENT | PPC_EXTERN;
6016 pcc->msr_mask = (1ull << MSR_POW) |
6017 (1ull << MSR_ILE) |
6018 (1ull << MSR_EE) |
6019 (1ull << MSR_PR) |
6020 (1ull << MSR_FP) |
6021 (1ull << MSR_ME) |
6022 (1ull << MSR_FE0) |
6023 (1ull << MSR_SE) |
6024 (1ull << MSR_DE) |
6025 (1ull << MSR_FE1) |
6026 (1ull << MSR_EP) |
6027 (1ull << MSR_IR) |
6028 (1ull << MSR_DR) |
6029 (1ull << MSR_PMM) |
6030 (1ull << MSR_RI) |
6031 (1ull << MSR_LE);
6032 pcc->mmu_model = POWERPC_MMU_32B;
6033 #if defined(CONFIG_SOFTMMU)
6034 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6035 #endif
6036 pcc->excp_model = POWERPC_EXCP_7x0;
6037 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6038 pcc->bfd_mach = bfd_mach_ppc_750;
6039 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6040 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6041 }
6042
6043 static void init_proc_750gx (CPUPPCState *env)
6044 {
6045 gen_spr_ne_601(env);
6046 gen_spr_7xx(env);
6047 /* XXX : not implemented (XXX: different from 750fx) */
6048 spr_register(env, SPR_L2CR, "L2CR",
6049 SPR_NOACCESS, SPR_NOACCESS,
6050 &spr_read_generic, spr_access_nop,
6051 0x00000000);
6052 /* Time base */
6053 gen_tbl(env);
6054 /* Thermal management */
6055 gen_spr_thrm(env);
6056 /* XXX : not implemented */
6057 spr_register(env, SPR_750_THRM4, "THRM4",
6058 SPR_NOACCESS, SPR_NOACCESS,
6059 &spr_read_generic, &spr_write_generic,
6060 0x00000000);
6061 /* Hardware implementation registers */
6062 /* XXX : not implemented (XXX: different from 750fx) */
6063 spr_register(env, SPR_HID0, "HID0",
6064 SPR_NOACCESS, SPR_NOACCESS,
6065 &spr_read_generic, &spr_write_generic,
6066 0x00000000);
6067 /* XXX : not implemented */
6068 spr_register(env, SPR_HID1, "HID1",
6069 SPR_NOACCESS, SPR_NOACCESS,
6070 &spr_read_generic, &spr_write_generic,
6071 0x00000000);
6072 /* XXX : not implemented (XXX: different from 750fx) */
6073 spr_register(env, SPR_750FX_HID2, "HID2",
6074 SPR_NOACCESS, SPR_NOACCESS,
6075 &spr_read_generic, &spr_write_generic,
6076 0x00000000);
6077 /* Memory management */
6078 gen_low_BATs(env);
6079 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6080 gen_high_BATs(env);
6081 init_excp_7x0(env);
6082 env->dcache_line_size = 32;
6083 env->icache_line_size = 32;
6084 /* Allocate hardware IRQ controller */
6085 ppc6xx_irq_init(env);
6086 }
6087
6088 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6089 {
6090 DeviceClass *dc = DEVICE_CLASS(oc);
6091 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6092
6093 dc->desc = "PowerPC 750GX";
6094 pcc->init_proc = init_proc_750gx;
6095 pcc->check_pow = check_pow_hid0;
6096 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6097 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6098 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6099 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6100 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6101 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6102 PPC_SEGMENT | PPC_EXTERN;
6103 pcc->msr_mask = (1ull << MSR_POW) |
6104 (1ull << MSR_ILE) |
6105 (1ull << MSR_EE) |
6106 (1ull << MSR_PR) |
6107 (1ull << MSR_FP) |
6108 (1ull << MSR_ME) |
6109 (1ull << MSR_FE0) |
6110 (1ull << MSR_SE) |
6111 (1ull << MSR_DE) |
6112 (1ull << MSR_FE1) |
6113 (1ull << MSR_EP) |
6114 (1ull << MSR_IR) |
6115 (1ull << MSR_DR) |
6116 (1ull << MSR_PMM) |
6117 (1ull << MSR_RI) |
6118 (1ull << MSR_LE);
6119 pcc->mmu_model = POWERPC_MMU_32B;
6120 #if defined(CONFIG_SOFTMMU)
6121 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6122 #endif
6123 pcc->excp_model = POWERPC_EXCP_7x0;
6124 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6125 pcc->bfd_mach = bfd_mach_ppc_750;
6126 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6127 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6128 }
6129
6130 static void init_proc_745 (CPUPPCState *env)
6131 {
6132 gen_spr_ne_601(env);
6133 gen_spr_7xx(env);
6134 gen_spr_G2_755(env);
6135 /* Time base */
6136 gen_tbl(env);
6137 /* Thermal management */
6138 gen_spr_thrm(env);
6139 /* Hardware implementation registers */
6140 /* XXX : not implemented */
6141 spr_register(env, SPR_HID0, "HID0",
6142 SPR_NOACCESS, SPR_NOACCESS,
6143 &spr_read_generic, &spr_write_generic,
6144 0x00000000);
6145 /* XXX : not implemented */
6146 spr_register(env, SPR_HID1, "HID1",
6147 SPR_NOACCESS, SPR_NOACCESS,
6148 &spr_read_generic, &spr_write_generic,
6149 0x00000000);
6150 /* XXX : not implemented */
6151 spr_register(env, SPR_HID2, "HID2",
6152 SPR_NOACCESS, SPR_NOACCESS,
6153 &spr_read_generic, &spr_write_generic,
6154 0x00000000);
6155 /* Memory management */
6156 gen_low_BATs(env);
6157 gen_high_BATs(env);
6158 gen_6xx_7xx_soft_tlb(env, 64, 2);
6159 init_excp_7x5(env);
6160 env->dcache_line_size = 32;
6161 env->icache_line_size = 32;
6162 /* Allocate hardware IRQ controller */
6163 ppc6xx_irq_init(env);
6164 }
6165
6166 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6167 {
6168 DeviceClass *dc = DEVICE_CLASS(oc);
6169 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6170
6171 dc->desc = "PowerPC 745";
6172 pcc->init_proc = init_proc_745;
6173 pcc->check_pow = check_pow_hid0;
6174 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6175 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6176 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6177 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6178 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6179 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6180 PPC_SEGMENT | PPC_EXTERN;
6181 pcc->msr_mask = (1ull << MSR_POW) |
6182 (1ull << MSR_ILE) |
6183 (1ull << MSR_EE) |
6184 (1ull << MSR_PR) |
6185 (1ull << MSR_FP) |
6186 (1ull << MSR_ME) |
6187 (1ull << MSR_FE0) |
6188 (1ull << MSR_SE) |
6189 (1ull << MSR_DE) |
6190 (1ull << MSR_FE1) |
6191 (1ull << MSR_EP) |
6192 (1ull << MSR_IR) |
6193 (1ull << MSR_DR) |
6194 (1ull << MSR_PMM) |
6195 (1ull << MSR_RI) |
6196 (1ull << MSR_LE);
6197 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6198 pcc->excp_model = POWERPC_EXCP_7x5;
6199 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6200 pcc->bfd_mach = bfd_mach_ppc_750;
6201 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6202 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6203 }
6204
6205 static void init_proc_755 (CPUPPCState *env)
6206 {
6207 gen_spr_ne_601(env);
6208 gen_spr_7xx(env);
6209 gen_spr_G2_755(env);
6210 /* Time base */
6211 gen_tbl(env);
6212 /* L2 cache control */
6213 /* XXX : not implemented */
6214 spr_register(env, SPR_L2CR, "L2CR",
6215 SPR_NOACCESS, SPR_NOACCESS,
6216 &spr_read_generic, spr_access_nop,
6217 0x00000000);
6218 /* XXX : not implemented */
6219 spr_register(env, SPR_L2PMCR, "L2PMCR",
6220 SPR_NOACCESS, SPR_NOACCESS,
6221 &spr_read_generic, &spr_write_generic,
6222 0x00000000);
6223 /* Thermal management */
6224 gen_spr_thrm(env);
6225 /* Hardware implementation registers */
6226 /* XXX : not implemented */
6227 spr_register(env, SPR_HID0, "HID0",
6228 SPR_NOACCESS, SPR_NOACCESS,
6229 &spr_read_generic, &spr_write_generic,
6230 0x00000000);
6231 /* XXX : not implemented */
6232 spr_register(env, SPR_HID1, "HID1",
6233 SPR_NOACCESS, SPR_NOACCESS,
6234 &spr_read_generic, &spr_write_generic,
6235 0x00000000);
6236 /* XXX : not implemented */
6237 spr_register(env, SPR_HID2, "HID2",
6238 SPR_NOACCESS, SPR_NOACCESS,
6239 &spr_read_generic, &spr_write_generic,
6240 0x00000000);
6241 /* Memory management */
6242 gen_low_BATs(env);
6243 gen_high_BATs(env);
6244 gen_6xx_7xx_soft_tlb(env, 64, 2);
6245 init_excp_7x5(env);
6246 env->dcache_line_size = 32;
6247 env->icache_line_size = 32;
6248 /* Allocate hardware IRQ controller */
6249 ppc6xx_irq_init(env);
6250 }
6251
6252 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6253 {
6254 DeviceClass *dc = DEVICE_CLASS(oc);
6255 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6256
6257 dc->desc = "PowerPC 755";
6258 pcc->init_proc = init_proc_755;
6259 pcc->check_pow = check_pow_hid0;
6260 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6261 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6262 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6263 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6264 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6265 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6266 PPC_SEGMENT | PPC_EXTERN;
6267 pcc->msr_mask = (1ull << MSR_POW) |
6268 (1ull << MSR_ILE) |
6269 (1ull << MSR_EE) |
6270 (1ull << MSR_PR) |
6271 (1ull << MSR_FP) |
6272 (1ull << MSR_ME) |
6273 (1ull << MSR_FE0) |
6274 (1ull << MSR_SE) |
6275 (1ull << MSR_DE) |
6276 (1ull << MSR_FE1) |
6277 (1ull << MSR_EP) |
6278 (1ull << MSR_IR) |
6279 (1ull << MSR_DR) |
6280 (1ull << MSR_PMM) |
6281 (1ull << MSR_RI) |
6282 (1ull << MSR_LE);
6283 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6284 pcc->excp_model = POWERPC_EXCP_7x5;
6285 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6286 pcc->bfd_mach = bfd_mach_ppc_750;
6287 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6288 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6289 }
6290
6291 static void init_proc_7400 (CPUPPCState *env)
6292 {
6293 gen_spr_ne_601(env);
6294 gen_spr_7xx(env);
6295 /* Time base */
6296 gen_tbl(env);
6297 /* 74xx specific SPR */
6298 gen_spr_74xx(env);
6299 /* XXX : not implemented */
6300 spr_register(env, SPR_UBAMR, "UBAMR",
6301 &spr_read_ureg, SPR_NOACCESS,
6302 &spr_read_ureg, SPR_NOACCESS,
6303 0x00000000);
6304 /* XXX: this seems not implemented on all revisions. */
6305 /* XXX : not implemented */
6306 spr_register(env, SPR_MSSCR1, "MSSCR1",
6307 SPR_NOACCESS, SPR_NOACCESS,
6308 &spr_read_generic, &spr_write_generic,
6309 0x00000000);
6310 /* Thermal management */
6311 gen_spr_thrm(env);
6312 /* Memory management */
6313 gen_low_BATs(env);
6314 init_excp_7400(env);
6315 env->dcache_line_size = 32;
6316 env->icache_line_size = 32;
6317 /* Allocate hardware IRQ controller */
6318 ppc6xx_irq_init(env);
6319 }
6320
6321 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6322 {
6323 DeviceClass *dc = DEVICE_CLASS(oc);
6324 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6325
6326 dc->desc = "PowerPC 7400 (aka G4)";
6327 pcc->init_proc = init_proc_7400;
6328 pcc->check_pow = check_pow_hid0;
6329 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6330 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6331 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6332 PPC_FLOAT_STFIWX |
6333 PPC_CACHE | PPC_CACHE_ICBI |
6334 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6335 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6336 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6337 PPC_MEM_TLBIA |
6338 PPC_SEGMENT | PPC_EXTERN |
6339 PPC_ALTIVEC;
6340 pcc->msr_mask = (1ull << MSR_VR) |
6341 (1ull << MSR_POW) |
6342 (1ull << MSR_ILE) |
6343 (1ull << MSR_EE) |
6344 (1ull << MSR_PR) |
6345 (1ull << MSR_FP) |
6346 (1ull << MSR_ME) |
6347 (1ull << MSR_FE0) |
6348 (1ull << MSR_SE) |
6349 (1ull << MSR_DE) |
6350 (1ull << MSR_FE1) |
6351 (1ull << MSR_EP) |
6352 (1ull << MSR_IR) |
6353 (1ull << MSR_DR) |
6354 (1ull << MSR_PMM) |
6355 (1ull << MSR_RI) |
6356 (1ull << MSR_LE);
6357 pcc->mmu_model = POWERPC_MMU_32B;
6358 #if defined(CONFIG_SOFTMMU)
6359 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6360 #endif
6361 pcc->excp_model = POWERPC_EXCP_74xx;
6362 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6363 pcc->bfd_mach = bfd_mach_ppc_7400;
6364 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6365 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6366 POWERPC_FLAG_BUS_CLK;
6367 }
6368
6369 static void init_proc_7410 (CPUPPCState *env)
6370 {
6371 gen_spr_ne_601(env);
6372 gen_spr_7xx(env);
6373 /* Time base */
6374 gen_tbl(env);
6375 /* 74xx specific SPR */
6376 gen_spr_74xx(env);
6377 /* XXX : not implemented */
6378 spr_register(env, SPR_UBAMR, "UBAMR",
6379 &spr_read_ureg, SPR_NOACCESS,
6380 &spr_read_ureg, SPR_NOACCESS,
6381 0x00000000);
6382 /* Thermal management */
6383 gen_spr_thrm(env);
6384 /* L2PMCR */
6385 /* XXX : not implemented */
6386 spr_register(env, SPR_L2PMCR, "L2PMCR",
6387 SPR_NOACCESS, SPR_NOACCESS,
6388 &spr_read_generic, &spr_write_generic,
6389 0x00000000);
6390 /* LDSTDB */
6391 /* XXX : not implemented */
6392 spr_register(env, SPR_LDSTDB, "LDSTDB",
6393 SPR_NOACCESS, SPR_NOACCESS,
6394 &spr_read_generic, &spr_write_generic,
6395 0x00000000);
6396 /* Memory management */
6397 gen_low_BATs(env);
6398 init_excp_7400(env);
6399 env->dcache_line_size = 32;
6400 env->icache_line_size = 32;
6401 /* Allocate hardware IRQ controller */
6402 ppc6xx_irq_init(env);
6403 }
6404
6405 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6406 {
6407 DeviceClass *dc = DEVICE_CLASS(oc);
6408 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6409
6410 dc->desc = "PowerPC 7410 (aka G4)";
6411 pcc->init_proc = init_proc_7410;
6412 pcc->check_pow = check_pow_hid0;
6413 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6414 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6415 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6416 PPC_FLOAT_STFIWX |
6417 PPC_CACHE | PPC_CACHE_ICBI |
6418 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6419 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6420 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6421 PPC_MEM_TLBIA |
6422 PPC_SEGMENT | PPC_EXTERN |
6423 PPC_ALTIVEC;
6424 pcc->msr_mask = (1ull << MSR_VR) |
6425 (1ull << MSR_POW) |
6426 (1ull << MSR_ILE) |
6427 (1ull << MSR_EE) |
6428 (1ull << MSR_PR) |
6429 (1ull << MSR_FP) |
6430 (1ull << MSR_ME) |
6431 (1ull << MSR_FE0) |
6432 (1ull << MSR_SE) |
6433 (1ull << MSR_DE) |
6434 (1ull << MSR_FE1) |
6435 (1ull << MSR_EP) |
6436 (1ull << MSR_IR) |
6437 (1ull << MSR_DR) |
6438 (1ull << MSR_PMM) |
6439 (1ull << MSR_RI) |
6440 (1ull << MSR_LE);
6441 pcc->mmu_model = POWERPC_MMU_32B;
6442 #if defined(CONFIG_SOFTMMU)
6443 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6444 #endif
6445 pcc->excp_model = POWERPC_EXCP_74xx;
6446 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6447 pcc->bfd_mach = bfd_mach_ppc_7400;
6448 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6449 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6450 POWERPC_FLAG_BUS_CLK;
6451 }
6452
6453 static void init_proc_7440 (CPUPPCState *env)
6454 {
6455 gen_spr_ne_601(env);
6456 gen_spr_7xx(env);
6457 /* Time base */
6458 gen_tbl(env);
6459 /* 74xx specific SPR */
6460 gen_spr_74xx(env);
6461 /* XXX : not implemented */
6462 spr_register(env, SPR_UBAMR, "UBAMR",
6463 &spr_read_ureg, SPR_NOACCESS,
6464 &spr_read_ureg, SPR_NOACCESS,
6465 0x00000000);
6466 /* LDSTCR */
6467 /* XXX : not implemented */
6468 spr_register(env, SPR_LDSTCR, "LDSTCR",
6469 SPR_NOACCESS, SPR_NOACCESS,
6470 &spr_read_generic, &spr_write_generic,
6471 0x00000000);
6472 /* ICTRL */
6473 /* XXX : not implemented */
6474 spr_register(env, SPR_ICTRL, "ICTRL",
6475 SPR_NOACCESS, SPR_NOACCESS,
6476 &spr_read_generic, &spr_write_generic,
6477 0x00000000);
6478 /* MSSSR0 */
6479 /* XXX : not implemented */
6480 spr_register(env, SPR_MSSSR0, "MSSSR0",
6481 SPR_NOACCESS, SPR_NOACCESS,
6482 &spr_read_generic, &spr_write_generic,
6483 0x00000000);
6484 /* PMC */
6485 /* XXX : not implemented */
6486 spr_register(env, SPR_7XX_PMC5, "PMC5",
6487 SPR_NOACCESS, SPR_NOACCESS,
6488 &spr_read_generic, &spr_write_generic,
6489 0x00000000);
6490 /* XXX : not implemented */
6491 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6492 &spr_read_ureg, SPR_NOACCESS,
6493 &spr_read_ureg, SPR_NOACCESS,
6494 0x00000000);
6495 /* XXX : not implemented */
6496 spr_register(env, SPR_7XX_PMC6, "PMC6",
6497 SPR_NOACCESS, SPR_NOACCESS,
6498 &spr_read_generic, &spr_write_generic,
6499 0x00000000);
6500 /* XXX : not implemented */
6501 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6502 &spr_read_ureg, SPR_NOACCESS,
6503 &spr_read_ureg, SPR_NOACCESS,
6504 0x00000000);
6505 /* Memory management */
6506 gen_low_BATs(env);
6507 gen_74xx_soft_tlb(env, 128, 2);
6508 init_excp_7450(env);
6509 env->dcache_line_size = 32;
6510 env->icache_line_size = 32;
6511 /* Allocate hardware IRQ controller */
6512 ppc6xx_irq_init(env);
6513 }
6514
6515 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6516 {
6517 DeviceClass *dc = DEVICE_CLASS(oc);
6518 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6519
6520 dc->desc = "PowerPC 7440 (aka G4)";
6521 pcc->init_proc = init_proc_7440;
6522 pcc->check_pow = check_pow_hid0_74xx;
6523 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6524 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6525 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6526 PPC_FLOAT_STFIWX |
6527 PPC_CACHE | PPC_CACHE_ICBI |
6528 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6529 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6530 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6531 PPC_MEM_TLBIA | PPC_74xx_TLB |
6532 PPC_SEGMENT | PPC_EXTERN |
6533 PPC_ALTIVEC;
6534 pcc->msr_mask = (1ull << MSR_VR) |
6535 (1ull << MSR_POW) |
6536 (1ull << MSR_ILE) |
6537 (1ull << MSR_EE) |
6538 (1ull << MSR_PR) |
6539 (1ull << MSR_FP) |
6540 (1ull << MSR_ME) |
6541 (1ull << MSR_FE0) |
6542 (1ull << MSR_SE) |
6543 (1ull << MSR_DE) |
6544 (1ull << MSR_FE1) |
6545 (1ull << MSR_EP) |
6546 (1ull << MSR_IR) |
6547 (1ull << MSR_DR) |
6548 (1ull << MSR_PMM) |
6549 (1ull << MSR_RI) |
6550 (1ull << MSR_LE);
6551 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6552 pcc->excp_model = POWERPC_EXCP_74xx;
6553 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6554 pcc->bfd_mach = bfd_mach_ppc_7400;
6555 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6556 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6557 POWERPC_FLAG_BUS_CLK;
6558 }
6559
6560 static void init_proc_7450 (CPUPPCState *env)
6561 {
6562 gen_spr_ne_601(env);
6563 gen_spr_7xx(env);
6564 /* Time base */
6565 gen_tbl(env);
6566 /* 74xx specific SPR */
6567 gen_spr_74xx(env);
6568 /* Level 3 cache control */
6569 gen_l3_ctrl(env);
6570 /* L3ITCR1 */
6571 /* XXX : not implemented */
6572 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6573 SPR_NOACCESS, SPR_NOACCESS,
6574 &spr_read_generic, &spr_write_generic,
6575 0x00000000);
6576 /* L3ITCR2 */
6577 /* XXX : not implemented */
6578 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6579 SPR_NOACCESS, SPR_NOACCESS,
6580 &spr_read_generic, &spr_write_generic,
6581 0x00000000);
6582 /* L3ITCR3 */
6583 /* XXX : not implemented */
6584 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6585 SPR_NOACCESS, SPR_NOACCESS,
6586 &spr_read_generic, &spr_write_generic,
6587 0x00000000);
6588 /* L3OHCR */
6589 /* XXX : not implemented */
6590 spr_register(env, SPR_L3OHCR, "L3OHCR",
6591 SPR_NOACCESS, SPR_NOACCESS,
6592 &spr_read_generic, &spr_write_generic,
6593 0x00000000);
6594 /* XXX : not implemented */
6595 spr_register(env, SPR_UBAMR, "UBAMR",
6596 &spr_read_ureg, SPR_NOACCESS,
6597 &spr_read_ureg, SPR_NOACCESS,
6598 0x00000000);
6599 /* LDSTCR */
6600 /* XXX : not implemented */
6601 spr_register(env, SPR_LDSTCR, "LDSTCR",
6602 SPR_NOACCESS, SPR_NOACCESS,
6603 &spr_read_generic, &spr_write_generic,
6604 0x00000000);
6605 /* ICTRL */
6606 /* XXX : not implemented */
6607 spr_register(env, SPR_ICTRL, "ICTRL",
6608 SPR_NOACCESS, SPR_NOACCESS,
6609 &spr_read_generic, &spr_write_generic,
6610 0x00000000);
6611 /* MSSSR0 */
6612 /* XXX : not implemented */
6613 spr_register(env, SPR_MSSSR0, "MSSSR0",
6614 SPR_NOACCESS, SPR_NOACCESS,
6615 &spr_read_generic, &spr_write_generic,
6616 0x00000000);
6617 /* PMC */
6618 /* XXX : not implemented */
6619 spr_register(env, SPR_7XX_PMC5, "PMC5",
6620 SPR_NOACCESS, SPR_NOACCESS,
6621 &spr_read_generic, &spr_write_generic,
6622 0x00000000);
6623 /* XXX : not implemented */
6624 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6625 &spr_read_ureg, SPR_NOACCESS,
6626 &spr_read_ureg, SPR_NOACCESS,
6627 0x00000000);
6628 /* XXX : not implemented */
6629 spr_register(env, SPR_7XX_PMC6, "PMC6",
6630 SPR_NOACCESS, SPR_NOACCESS,
6631 &spr_read_generic, &spr_write_generic,
6632 0x00000000);
6633 /* XXX : not implemented */
6634 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6635 &spr_read_ureg, SPR_NOACCESS,
6636 &spr_read_ureg, SPR_NOACCESS,
6637 0x00000000);
6638 /* Memory management */
6639 gen_low_BATs(env);
6640 gen_74xx_soft_tlb(env, 128, 2);
6641 init_excp_7450(env);
6642 env->dcache_line_size = 32;
6643 env->icache_line_size = 32;
6644 /* Allocate hardware IRQ controller */
6645 ppc6xx_irq_init(env);
6646 }
6647
6648 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6649 {
6650 DeviceClass *dc = DEVICE_CLASS(oc);
6651 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6652
6653 dc->desc = "PowerPC 7450 (aka G4)";
6654 pcc->init_proc = init_proc_7450;
6655 pcc->check_pow = check_pow_hid0_74xx;
6656 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6657 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6658 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6659 PPC_FLOAT_STFIWX |
6660 PPC_CACHE | PPC_CACHE_ICBI |
6661 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6662 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6663 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6664 PPC_MEM_TLBIA | PPC_74xx_TLB |
6665 PPC_SEGMENT | PPC_EXTERN |
6666 PPC_ALTIVEC;
6667 pcc->msr_mask = (1ull << MSR_VR) |
6668 (1ull << MSR_POW) |
6669 (1ull << MSR_ILE) |
6670 (1ull << MSR_EE) |
6671 (1ull << MSR_PR) |
6672 (1ull << MSR_FP) |
6673 (1ull << MSR_ME) |
6674 (1ull << MSR_FE0) |
6675 (1ull << MSR_SE) |
6676 (1ull << MSR_DE) |
6677 (1ull << MSR_FE1) |
6678 (1ull << MSR_EP) |
6679 (1ull << MSR_IR) |
6680 (1ull << MSR_DR) |
6681 (1ull << MSR_PMM) |
6682 (1ull << MSR_RI) |
6683 (1ull << MSR_LE);
6684 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6685 pcc->excp_model = POWERPC_EXCP_74xx;
6686 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6687 pcc->bfd_mach = bfd_mach_ppc_7400;
6688 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6689 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6690 POWERPC_FLAG_BUS_CLK;
6691 }
6692
6693 static void init_proc_7445 (CPUPPCState *env)
6694 {
6695 gen_spr_ne_601(env);
6696 gen_spr_7xx(env);
6697 /* Time base */
6698 gen_tbl(env);
6699 /* 74xx specific SPR */
6700 gen_spr_74xx(env);
6701 /* LDSTCR */
6702 /* XXX : not implemented */
6703 spr_register(env, SPR_LDSTCR, "LDSTCR",
6704 SPR_NOACCESS, SPR_NOACCESS,
6705 &spr_read_generic, &spr_write_generic,
6706 0x00000000);
6707 /* ICTRL */
6708 /* XXX : not implemented */
6709 spr_register(env, SPR_ICTRL, "ICTRL",
6710 SPR_NOACCESS, SPR_NOACCESS,
6711 &spr_read_generic, &spr_write_generic,
6712 0x00000000);
6713 /* MSSSR0 */
6714 /* XXX : not implemented */
6715 spr_register(env, SPR_MSSSR0, "MSSSR0",
6716 SPR_NOACCESS, SPR_NOACCESS,
6717 &spr_read_generic, &spr_write_generic,
6718 0x00000000);
6719 /* PMC */
6720 /* XXX : not implemented */
6721 spr_register(env, SPR_7XX_PMC5, "PMC5",
6722 SPR_NOACCESS, SPR_NOACCESS,
6723 &spr_read_generic, &spr_write_generic,
6724 0x00000000);
6725 /* XXX : not implemented */
6726 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6727 &spr_read_ureg, SPR_NOACCESS,
6728 &spr_read_ureg, SPR_NOACCESS,
6729 0x00000000);
6730 /* XXX : not implemented */
6731 spr_register(env, SPR_7XX_PMC6, "PMC6",
6732 SPR_NOACCESS, SPR_NOACCESS,
6733 &spr_read_generic, &spr_write_generic,
6734 0x00000000);
6735 /* XXX : not implemented */
6736 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6737 &spr_read_ureg, SPR_NOACCESS,
6738 &spr_read_ureg, SPR_NOACCESS,
6739 0x00000000);
6740 /* SPRGs */
6741 spr_register(env, SPR_SPRG4, "SPRG4",
6742 SPR_NOACCESS, SPR_NOACCESS,
6743 &spr_read_generic, &spr_write_generic,
6744 0x00000000);
6745 spr_register(env, SPR_USPRG4, "USPRG4",
6746 &spr_read_ureg, SPR_NOACCESS,
6747 &spr_read_ureg, SPR_NOACCESS,
6748 0x00000000);
6749 spr_register(env, SPR_SPRG5, "SPRG5",
6750 SPR_NOACCESS, SPR_NOACCESS,
6751 &spr_read_generic, &spr_write_generic,
6752 0x00000000);
6753 spr_register(env, SPR_USPRG5, "USPRG5",
6754 &spr_read_ureg, SPR_NOACCESS,
6755 &spr_read_ureg, SPR_NOACCESS,
6756 0x00000000);
6757 spr_register(env, SPR_SPRG6, "SPRG6",
6758 SPR_NOACCESS, SPR_NOACCESS,
6759 &spr_read_generic, &spr_write_generic,
6760 0x00000000);
6761 spr_register(env, SPR_USPRG6, "USPRG6",
6762 &spr_read_ureg, SPR_NOACCESS,
6763 &spr_read_ureg, SPR_NOACCESS,
6764 0x00000000);
6765 spr_register(env, SPR_SPRG7, "SPRG7",
6766 SPR_NOACCESS, SPR_NOACCESS,
6767 &spr_read_generic, &spr_write_generic,
6768 0x00000000);
6769 spr_register(env, SPR_USPRG7, "USPRG7",
6770 &spr_read_ureg, SPR_NOACCESS,
6771 &spr_read_ureg, SPR_NOACCESS,
6772 0x00000000);
6773 /* Memory management */
6774 gen_low_BATs(env);
6775 gen_high_BATs(env);
6776 gen_74xx_soft_tlb(env, 128, 2);
6777 init_excp_7450(env);
6778 env->dcache_line_size = 32;
6779 env->icache_line_size = 32;
6780 /* Allocate hardware IRQ controller */
6781 ppc6xx_irq_init(env);
6782 }
6783
6784 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6785 {
6786 DeviceClass *dc = DEVICE_CLASS(oc);
6787 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6788
6789 dc->desc = "PowerPC 7445 (aka G4)";
6790 pcc->init_proc = init_proc_7445;
6791 pcc->check_pow = check_pow_hid0_74xx;
6792 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6793 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6794 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6795 PPC_FLOAT_STFIWX |
6796 PPC_CACHE | PPC_CACHE_ICBI |
6797 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6798 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6799 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6800 PPC_MEM_TLBIA | PPC_74xx_TLB |
6801 PPC_SEGMENT | PPC_EXTERN |
6802 PPC_ALTIVEC;
6803 pcc->msr_mask = (1ull << MSR_VR) |
6804 (1ull << MSR_POW) |
6805 (1ull << MSR_ILE) |
6806 (1ull << MSR_EE) |
6807 (1ull << MSR_PR) |
6808 (1ull << MSR_FP) |
6809 (1ull << MSR_ME) |
6810 (1ull << MSR_FE0) |
6811 (1ull << MSR_SE) |
6812 (1ull << MSR_DE) |
6813 (1ull << MSR_FE1) |
6814 (1ull << MSR_EP) |
6815 (1ull << MSR_IR) |
6816 (1ull << MSR_DR) |
6817 (1ull << MSR_PMM) |
6818 (1ull << MSR_RI) |
6819 (1ull << MSR_LE);
6820 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6821 pcc->excp_model = POWERPC_EXCP_74xx;
6822 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6823 pcc->bfd_mach = bfd_mach_ppc_7400;
6824 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6825 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6826 POWERPC_FLAG_BUS_CLK;
6827 }
6828
6829 static void init_proc_7455 (CPUPPCState *env)
6830 {
6831 gen_spr_ne_601(env);
6832 gen_spr_7xx(env);
6833 /* Time base */
6834 gen_tbl(env);
6835 /* 74xx specific SPR */
6836 gen_spr_74xx(env);
6837 /* Level 3 cache control */
6838 gen_l3_ctrl(env);
6839 /* LDSTCR */
6840 /* XXX : not implemented */
6841 spr_register(env, SPR_LDSTCR, "LDSTCR",
6842 SPR_NOACCESS, SPR_NOACCESS,
6843 &spr_read_generic, &spr_write_generic,
6844 0x00000000);
6845 /* ICTRL */
6846 /* XXX : not implemented */
6847 spr_register(env, SPR_ICTRL, "ICTRL",
6848 SPR_NOACCESS, SPR_NOACCESS,
6849 &spr_read_generic, &spr_write_generic,
6850 0x00000000);
6851 /* MSSSR0 */
6852 /* XXX : not implemented */
6853 spr_register(env, SPR_MSSSR0, "MSSSR0",
6854 SPR_NOACCESS, SPR_NOACCESS,
6855 &spr_read_generic, &spr_write_generic,
6856 0x00000000);
6857 /* PMC */
6858 /* XXX : not implemented */
6859 spr_register(env, SPR_7XX_PMC5, "PMC5",
6860 SPR_NOACCESS, SPR_NOACCESS,
6861 &spr_read_generic, &spr_write_generic,
6862 0x00000000);
6863 /* XXX : not implemented */
6864 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6865 &spr_read_ureg, SPR_NOACCESS,
6866 &spr_read_ureg, SPR_NOACCESS,
6867 0x00000000);
6868 /* XXX : not implemented */
6869 spr_register(env, SPR_7XX_PMC6, "PMC6",
6870 SPR_NOACCESS, SPR_NOACCESS,
6871 &spr_read_generic, &spr_write_generic,
6872 0x00000000);
6873 /* XXX : not implemented */
6874 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6875 &spr_read_ureg, SPR_NOACCESS,
6876 &spr_read_ureg, SPR_NOACCESS,
6877 0x00000000);
6878 /* SPRGs */
6879 spr_register(env, SPR_SPRG4, "SPRG4",
6880 SPR_NOACCESS, SPR_NOACCESS,
6881 &spr_read_generic, &spr_write_generic,
6882 0x00000000);
6883 spr_register(env, SPR_USPRG4, "USPRG4",
6884 &spr_read_ureg, SPR_NOACCESS,
6885 &spr_read_ureg, SPR_NOACCESS,
6886 0x00000000);
6887 spr_register(env, SPR_SPRG5, "SPRG5",
6888 SPR_NOACCESS, SPR_NOACCESS,
6889 &spr_read_generic, &spr_write_generic,
6890 0x00000000);
6891 spr_register(env, SPR_USPRG5, "USPRG5",
6892 &spr_read_ureg, SPR_NOACCESS,
6893 &spr_read_ureg, SPR_NOACCESS,
6894 0x00000000);
6895 spr_register(env, SPR_SPRG6, "SPRG6",
6896 SPR_NOACCESS, SPR_NOACCESS,
6897 &spr_read_generic, &spr_write_generic,
6898 0x00000000);
6899 spr_register(env, SPR_USPRG6, "USPRG6",
6900 &spr_read_ureg, SPR_NOACCESS,
6901 &spr_read_ureg, SPR_NOACCESS,
6902 0x00000000);
6903 spr_register(env, SPR_SPRG7, "SPRG7",
6904 SPR_NOACCESS, SPR_NOACCESS,
6905 &spr_read_generic, &spr_write_generic,
6906 0x00000000);
6907 spr_register(env, SPR_USPRG7, "USPRG7",
6908 &spr_read_ureg, SPR_NOACCESS,
6909 &spr_read_ureg, SPR_NOACCESS,
6910 0x00000000);
6911 /* Memory management */
6912 gen_low_BATs(env);
6913 gen_high_BATs(env);
6914 gen_74xx_soft_tlb(env, 128, 2);
6915 init_excp_7450(env);
6916 env->dcache_line_size = 32;
6917 env->icache_line_size = 32;
6918 /* Allocate hardware IRQ controller */
6919 ppc6xx_irq_init(env);
6920 }
6921
6922 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6923 {
6924 DeviceClass *dc = DEVICE_CLASS(oc);
6925 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6926
6927 dc->desc = "PowerPC 7455 (aka G4)";
6928 pcc->init_proc = init_proc_7455;
6929 pcc->check_pow = check_pow_hid0_74xx;
6930 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6931 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6932 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6933 PPC_FLOAT_STFIWX |
6934 PPC_CACHE | PPC_CACHE_ICBI |
6935 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6936 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6937 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6938 PPC_MEM_TLBIA | PPC_74xx_TLB |
6939 PPC_SEGMENT | PPC_EXTERN |
6940 PPC_ALTIVEC;
6941 pcc->msr_mask = (1ull << MSR_VR) |
6942 (1ull << MSR_POW) |
6943 (1ull << MSR_ILE) |
6944 (1ull << MSR_EE) |
6945 (1ull << MSR_PR) |
6946 (1ull << MSR_FP) |
6947 (1ull << MSR_ME) |
6948 (1ull << MSR_FE0) |
6949 (1ull << MSR_SE) |
6950 (1ull << MSR_DE) |
6951 (1ull << MSR_FE1) |
6952 (1ull << MSR_EP) |
6953 (1ull << MSR_IR) |
6954 (1ull << MSR_DR) |
6955 (1ull << MSR_PMM) |
6956 (1ull << MSR_RI) |
6957 (1ull << MSR_LE);
6958 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6959 pcc->excp_model = POWERPC_EXCP_74xx;
6960 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6961 pcc->bfd_mach = bfd_mach_ppc_7400;
6962 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6963 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6964 POWERPC_FLAG_BUS_CLK;
6965 }
6966
6967 static void init_proc_7457 (CPUPPCState *env)
6968 {
6969 gen_spr_ne_601(env);
6970 gen_spr_7xx(env);
6971 /* Time base */
6972 gen_tbl(env);
6973 /* 74xx specific SPR */
6974 gen_spr_74xx(env);
6975 /* Level 3 cache control */
6976 gen_l3_ctrl(env);
6977 /* L3ITCR1 */
6978 /* XXX : not implemented */
6979 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6980 SPR_NOACCESS, SPR_NOACCESS,
6981 &spr_read_generic, &spr_write_generic,
6982 0x00000000);
6983 /* L3ITCR2 */
6984 /* XXX : not implemented */
6985 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6986 SPR_NOACCESS, SPR_NOACCESS,
6987 &spr_read_generic, &spr_write_generic,
6988 0x00000000);
6989 /* L3ITCR3 */
6990 /* XXX : not implemented */
6991 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6992 SPR_NOACCESS, SPR_NOACCESS,
6993 &spr_read_generic, &spr_write_generic,
6994 0x00000000);
6995 /* L3OHCR */
6996 /* XXX : not implemented */
6997 spr_register(env, SPR_L3OHCR, "L3OHCR",
6998 SPR_NOACCESS, SPR_NOACCESS,
6999 &spr_read_generic, &spr_write_generic,
7000 0x00000000);
7001 /* LDSTCR */
7002 /* XXX : not implemented */
7003 spr_register(env, SPR_LDSTCR, "LDSTCR",
7004 SPR_NOACCESS, SPR_NOACCESS,
7005 &spr_read_generic, &spr_write_generic,
7006 0x00000000);
7007 /* ICTRL */
7008 /* XXX : not implemented */
7009 spr_register(env, SPR_ICTRL, "ICTRL",
7010 SPR_NOACCESS, SPR_NOACCESS,
7011 &spr_read_generic, &spr_write_generic,
7012 0x00000000);
7013 /* MSSSR0 */
7014 /* XXX : not implemented */
7015 spr_register(env, SPR_MSSSR0, "MSSSR0",
7016 SPR_NOACCESS, SPR_NOACCESS,
7017 &spr_read_generic, &spr_write_generic,
7018 0x00000000);
7019 /* PMC */
7020 /* XXX : not implemented */
7021 spr_register(env, SPR_7XX_PMC5, "PMC5",
7022 SPR_NOACCESS, SPR_NOACCESS,
7023 &spr_read_generic, &spr_write_generic,
7024 0x00000000);
7025 /* XXX : not implemented */
7026 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7027 &spr_read_ureg, SPR_NOACCESS,
7028 &spr_read_ureg, SPR_NOACCESS,
7029 0x00000000);
7030 /* XXX : not implemented */
7031 spr_register(env, SPR_7XX_PMC6, "PMC6",
7032 SPR_NOACCESS, SPR_NOACCESS,
7033 &spr_read_generic, &spr_write_generic,
7034 0x00000000);
7035 /* XXX : not implemented */
7036 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7037 &spr_read_ureg, SPR_NOACCESS,
7038 &spr_read_ureg, SPR_NOACCESS,
7039 0x00000000);
7040 /* SPRGs */
7041 spr_register(env, SPR_SPRG4, "SPRG4",
7042 SPR_NOACCESS, SPR_NOACCESS,
7043 &spr_read_generic, &spr_write_generic,
7044 0x00000000);
7045 spr_register(env, SPR_USPRG4, "USPRG4",
7046 &spr_read_ureg, SPR_NOACCESS,
7047 &spr_read_ureg, SPR_NOACCESS,
7048 0x00000000);
7049 spr_register(env, SPR_SPRG5, "SPRG5",
7050 SPR_NOACCESS, SPR_NOACCESS,
7051 &spr_read_generic, &spr_write_generic,
7052 0x00000000);
7053 spr_register(env, SPR_USPRG5, "USPRG5",
7054 &spr_read_ureg, SPR_NOACCESS,
7055 &spr_read_ureg, SPR_NOACCESS,
7056 0x00000000);
7057 spr_register(env, SPR_SPRG6, "SPRG6",
7058 SPR_NOACCESS, SPR_NOACCESS,
7059 &spr_read_generic, &spr_write_generic,
7060 0x00000000);
7061 spr_register(env, SPR_USPRG6, "USPRG6",
7062 &spr_read_ureg, SPR_NOACCESS,
7063 &spr_read_ureg, SPR_NOACCESS,
7064 0x00000000);
7065 spr_register(env, SPR_SPRG7, "SPRG7",
7066 SPR_NOACCESS, SPR_NOACCESS,
7067 &spr_read_generic, &spr_write_generic,
7068 0x00000000);
7069 spr_register(env, SPR_USPRG7, "USPRG7",
7070 &spr_read_ureg, SPR_NOACCESS,
7071 &spr_read_ureg, SPR_NOACCESS,
7072 0x00000000);
7073 /* Memory management */
7074 gen_low_BATs(env);
7075 gen_high_BATs(env);
7076 gen_74xx_soft_tlb(env, 128, 2);
7077 init_excp_7450(env);
7078 env->dcache_line_size = 32;
7079 env->icache_line_size = 32;
7080 /* Allocate hardware IRQ controller */
7081 ppc6xx_irq_init(env);
7082 }
7083
7084 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7085 {
7086 DeviceClass *dc = DEVICE_CLASS(oc);
7087 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7088
7089 dc->desc = "PowerPC 7457 (aka G4)";
7090 pcc->init_proc = init_proc_7457;
7091 pcc->check_pow = check_pow_hid0_74xx;
7092 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7093 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7094 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7095 PPC_FLOAT_STFIWX |
7096 PPC_CACHE | PPC_CACHE_ICBI |
7097 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7098 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7099 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7100 PPC_MEM_TLBIA | PPC_74xx_TLB |
7101 PPC_SEGMENT | PPC_EXTERN |
7102 PPC_ALTIVEC;
7103 pcc->msr_mask = (1ull << MSR_VR) |
7104 (1ull << MSR_POW) |
7105 (1ull << MSR_ILE) |
7106 (1ull << MSR_EE) |
7107 (1ull << MSR_PR) |
7108 (1ull << MSR_FP) |
7109 (1ull << MSR_ME) |
7110 (1ull << MSR_FE0) |
7111 (1ull << MSR_SE) |
7112 (1ull << MSR_DE) |
7113 (1ull << MSR_FE1) |
7114 (1ull << MSR_EP) |
7115 (1ull << MSR_IR) |
7116 (1ull << MSR_DR) |
7117 (1ull << MSR_PMM) |
7118 (1ull << MSR_RI) |
7119 (1ull << MSR_LE);
7120 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7121 pcc->excp_model = POWERPC_EXCP_74xx;
7122 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7123 pcc->bfd_mach = bfd_mach_ppc_7400;
7124 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7125 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7126 POWERPC_FLAG_BUS_CLK;
7127 }
7128
7129 static void init_proc_e600 (CPUPPCState *env)
7130 {
7131 gen_spr_ne_601(env);
7132 gen_spr_7xx(env);
7133 /* Time base */
7134 gen_tbl(env);
7135 /* 74xx specific SPR */
7136 gen_spr_74xx(env);
7137 /* XXX : not implemented */
7138 spr_register(env, SPR_UBAMR, "UBAMR",
7139 &spr_read_ureg, SPR_NOACCESS,
7140 &spr_read_ureg, SPR_NOACCESS,
7141 0x00000000);
7142 /* XXX : not implemented */
7143 spr_register(env, SPR_LDSTCR, "LDSTCR",
7144 SPR_NOACCESS, SPR_NOACCESS,
7145 &spr_read_generic, &spr_write_generic,
7146 0x00000000);
7147 /* XXX : not implemented */
7148 spr_register(env, SPR_ICTRL, "ICTRL",
7149 SPR_NOACCESS, SPR_NOACCESS,
7150 &spr_read_generic, &spr_write_generic,
7151 0x00000000);
7152 /* XXX : not implemented */
7153 spr_register(env, SPR_MSSSR0, "MSSSR0",
7154 SPR_NOACCESS, SPR_NOACCESS,
7155 &spr_read_generic, &spr_write_generic,
7156 0x00000000);
7157 /* XXX : not implemented */
7158 spr_register(env, SPR_7XX_PMC5, "PMC5",
7159 SPR_NOACCESS, SPR_NOACCESS,
7160 &spr_read_generic, &spr_write_generic,
7161 0x00000000);
7162 /* XXX : not implemented */
7163 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7164 &spr_read_ureg, SPR_NOACCESS,
7165 &spr_read_ureg, SPR_NOACCESS,
7166 0x00000000);
7167 /* XXX : not implemented */
7168 spr_register(env, SPR_7XX_PMC6, "PMC6",
7169 SPR_NOACCESS, SPR_NOACCESS,
7170 &spr_read_generic, &spr_write_generic,
7171 0x00000000);
7172 /* XXX : not implemented */
7173 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7174 &spr_read_ureg, SPR_NOACCESS,
7175 &spr_read_ureg, SPR_NOACCESS,
7176 0x00000000);
7177 /* SPRGs */
7178 spr_register(env, SPR_SPRG4, "SPRG4",
7179 SPR_NOACCESS, SPR_NOACCESS,
7180 &spr_read_generic, &spr_write_generic,
7181 0x00000000);
7182 spr_register(env, SPR_USPRG4, "USPRG4",
7183 &spr_read_ureg, SPR_NOACCESS,
7184 &spr_read_ureg, SPR_NOACCESS,
7185 0x00000000);
7186 spr_register(env, SPR_SPRG5, "SPRG5",
7187 SPR_NOACCESS, SPR_NOACCESS,
7188 &spr_read_generic, &spr_write_generic,
7189 0x00000000);
7190 spr_register(env, SPR_USPRG5, "USPRG5",
7191 &spr_read_ureg, SPR_NOACCESS,
7192 &spr_read_ureg, SPR_NOACCESS,
7193 0x00000000);
7194 spr_register(env, SPR_SPRG6, "SPRG6",
7195 SPR_NOACCESS, SPR_NOACCESS,
7196 &spr_read_generic, &spr_write_generic,
7197 0x00000000);
7198 spr_register(env, SPR_USPRG6, "USPRG6",
7199 &spr_read_ureg, SPR_NOACCESS,
7200 &spr_read_ureg, SPR_NOACCESS,
7201 0x00000000);
7202 spr_register(env, SPR_SPRG7, "SPRG7",
7203 SPR_NOACCESS, SPR_NOACCESS,
7204 &spr_read_generic, &spr_write_generic,
7205 0x00000000);
7206 spr_register(env, SPR_USPRG7, "USPRG7",
7207 &spr_read_ureg, SPR_NOACCESS,
7208 &spr_read_ureg, SPR_NOACCESS,
7209 0x00000000);
7210 /* Memory management */
7211 gen_low_BATs(env);
7212 gen_high_BATs(env);
7213 gen_74xx_soft_tlb(env, 128, 2);
7214 init_excp_7450(env);
7215 env->dcache_line_size = 32;
7216 env->icache_line_size = 32;
7217 /* Allocate hardware IRQ controller */
7218 ppc6xx_irq_init(env);
7219 }
7220
7221 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7222 {
7223 DeviceClass *dc = DEVICE_CLASS(oc);
7224 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7225
7226 dc->desc = "PowerPC e600";
7227 pcc->init_proc = init_proc_e600;
7228 pcc->check_pow = check_pow_hid0_74xx;
7229 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7230 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7231 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7232 PPC_FLOAT_STFIWX |
7233 PPC_CACHE | PPC_CACHE_ICBI |
7234 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7235 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7236 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7237 PPC_MEM_TLBIA | PPC_74xx_TLB |
7238 PPC_SEGMENT | PPC_EXTERN |
7239 PPC_ALTIVEC;
7240 pcc->insns_flags2 = PPC_NONE;
7241 pcc->msr_mask = (1ull << MSR_VR) |
7242 (1ull << MSR_POW) |
7243 (1ull << MSR_ILE) |
7244 (1ull << MSR_EE) |
7245 (1ull << MSR_PR) |
7246 (1ull << MSR_FP) |
7247 (1ull << MSR_ME) |
7248 (1ull << MSR_FE0) |
7249 (1ull << MSR_SE) |
7250 (1ull << MSR_DE) |
7251 (1ull << MSR_FE1) |
7252 (1ull << MSR_EP) |
7253 (1ull << MSR_IR) |
7254 (1ull << MSR_DR) |
7255 (1ull << MSR_PMM) |
7256 (1ull << MSR_RI) |
7257 (1ull << MSR_LE);
7258 pcc->mmu_model = POWERPC_MMU_32B;
7259 #if defined(CONFIG_SOFTMMU)
7260 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7261 #endif
7262 pcc->excp_model = POWERPC_EXCP_74xx;
7263 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7264 pcc->bfd_mach = bfd_mach_ppc_7400;
7265 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7266 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7267 POWERPC_FLAG_BUS_CLK;
7268 }
7269
7270 #if defined (TARGET_PPC64)
7271 #if defined(CONFIG_USER_ONLY)
7272 #define POWERPC970_HID5_INIT 0x00000080
7273 #else
7274 #define POWERPC970_HID5_INIT 0x00000000
7275 #endif
7276
7277 enum BOOK3S_CPU_TYPE {
7278 BOOK3S_CPU_970,
7279 BOOK3S_CPU_POWER5PLUS,
7280 BOOK3S_CPU_POWER6,
7281 BOOK3S_CPU_POWER7,
7282 BOOK3S_CPU_POWER8
7283 };
7284
7285 static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
7286 int sprn, int cause)
7287 {
7288 TCGv_i32 t1 = tcg_const_i32(bit);
7289 TCGv_i32 t2 = tcg_const_i32(sprn);
7290 TCGv_i32 t3 = tcg_const_i32(cause);
7291
7292 gen_update_current_nip(opaque);
7293 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7294
7295 tcg_temp_free_i32(t3);
7296 tcg_temp_free_i32(t2);
7297 tcg_temp_free_i32(t1);
7298 }
7299
7300 static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit,
7301 int sprn, int cause)
7302 {
7303 TCGv_i32 t1 = tcg_const_i32(bit);
7304 TCGv_i32 t2 = tcg_const_i32(sprn);
7305 TCGv_i32 t3 = tcg_const_i32(cause);
7306
7307 gen_update_current_nip(opaque);
7308 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7309
7310 tcg_temp_free_i32(t3);
7311 tcg_temp_free_i32(t2);
7312 tcg_temp_free_i32(t1);
7313 }
7314
7315 static void spr_read_prev_upper32(void *opaque, int gprn, int sprn)
7316 {
7317 TCGv spr_up = tcg_temp_new();
7318 TCGv spr = tcg_temp_new();
7319
7320 gen_load_spr(spr, sprn - 1);
7321 tcg_gen_shri_tl(spr_up, spr, 32);
7322 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7323
7324 tcg_temp_free(spr);
7325 tcg_temp_free(spr_up);
7326 }
7327
7328 static void spr_write_prev_upper32(void *opaque, int sprn, int gprn)
7329 {
7330 TCGv spr = tcg_temp_new();
7331
7332 gen_load_spr(spr, sprn - 1);
7333 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7334 gen_store_spr(sprn - 1, spr);
7335
7336 tcg_temp_free(spr);
7337 }
7338
7339 static int check_pow_970 (CPUPPCState *env)
7340 {
7341 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7342 return 1;
7343 }
7344
7345 return 0;
7346 }
7347
7348 static void gen_spr_970_hid(CPUPPCState *env)
7349 {
7350 /* Hardware implementation registers */
7351 /* XXX : not implemented */
7352 spr_register(env, SPR_HID0, "HID0",
7353 SPR_NOACCESS, SPR_NOACCESS,
7354 &spr_read_generic, &spr_write_clear,
7355 0x60000000);
7356 spr_register(env, SPR_HID1, "HID1",
7357 SPR_NOACCESS, SPR_NOACCESS,
7358 &spr_read_generic, &spr_write_generic,
7359 0x00000000);
7360 spr_register(env, SPR_970_HID5, "HID5",
7361 SPR_NOACCESS, SPR_NOACCESS,
7362 &spr_read_generic, &spr_write_generic,
7363 POWERPC970_HID5_INIT);
7364 }
7365
7366 static void gen_spr_970_hior(CPUPPCState *env)
7367 {
7368 spr_register(env, SPR_HIOR, "SPR_HIOR",
7369 SPR_NOACCESS, SPR_NOACCESS,
7370 &spr_read_hior, &spr_write_hior,
7371 0x00000000);
7372 }
7373
7374 static void gen_spr_970_lpar(CPUPPCState *env)
7375 {
7376 /* Logical partitionning */
7377 /* PPC970: HID4 is effectively the LPCR */
7378 spr_register(env, SPR_970_HID4, "HID4",
7379 SPR_NOACCESS, SPR_NOACCESS,
7380 &spr_read_generic, &spr_write_generic,
7381 0x00000000);
7382 }
7383
7384 static void gen_spr_book3s_common(CPUPPCState *env)
7385 {
7386 spr_register(env, SPR_CTRL, "SPR_CTRL",
7387 SPR_NOACCESS, SPR_NOACCESS,
7388 SPR_NOACCESS, &spr_write_generic,
7389 0x00000000);
7390 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7391 &spr_read_ureg, SPR_NOACCESS,
7392 &spr_read_ureg, SPR_NOACCESS,
7393 0x00000000);
7394 }
7395
7396 static void gen_spr_book3s_altivec(CPUPPCState *env)
7397 {
7398 if (!(env->insns_flags & PPC_ALTIVEC)) {
7399 return;
7400 }
7401
7402 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7403 &spr_read_generic, &spr_write_generic,
7404 &spr_read_generic, &spr_write_generic,
7405 KVM_REG_PPC_VRSAVE, 0x00000000);
7406
7407 /* Can't find information on what this should be on reset. This
7408 * value is the one used by 74xx processors. */
7409 vscr_init(env, 0x00010000);
7410 }
7411
7412 static void gen_spr_book3s_dbg(CPUPPCState *env)
7413 {
7414 /*
7415 * TODO: different specs define different scopes for these,
7416 * will have to address this:
7417 * 970: super/write and super/read
7418 * powerisa 2.03..2.04: hypv/write and super/read.
7419 * powerisa 2.05 and newer: hypv/write and hypv/read.
7420 */
7421 spr_register_kvm(env, SPR_DABR, "DABR",
7422 SPR_NOACCESS, SPR_NOACCESS,
7423 &spr_read_generic, &spr_write_generic,
7424 KVM_REG_PPC_DABR, 0x00000000);
7425 spr_register_kvm(env, SPR_DABRX, "DABRX",
7426 SPR_NOACCESS, SPR_NOACCESS,
7427 &spr_read_generic, &spr_write_generic,
7428 KVM_REG_PPC_DABRX, 0x00000000);
7429 }
7430
7431 static void gen_spr_970_dbg(CPUPPCState *env)
7432 {
7433 /* Breakpoints */
7434 spr_register(env, SPR_IABR, "IABR",
7435 SPR_NOACCESS, SPR_NOACCESS,
7436 &spr_read_generic, &spr_write_generic,
7437 0x00000000);
7438 }
7439
7440 static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7441 {
7442 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7443 SPR_NOACCESS, SPR_NOACCESS,
7444 &spr_read_generic, &spr_write_generic,
7445 KVM_REG_PPC_MMCR0, 0x00000000);
7446 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7447 SPR_NOACCESS, SPR_NOACCESS,
7448 &spr_read_generic, &spr_write_generic,
7449 KVM_REG_PPC_MMCR1, 0x00000000);
7450 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7451 SPR_NOACCESS, SPR_NOACCESS,
7452 &spr_read_generic, &spr_write_generic,
7453 KVM_REG_PPC_MMCRA, 0x00000000);
7454 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7455 SPR_NOACCESS, SPR_NOACCESS,
7456 &spr_read_generic, &spr_write_generic,
7457 KVM_REG_PPC_PMC1, 0x00000000);
7458 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7459 SPR_NOACCESS, SPR_NOACCESS,
7460 &spr_read_generic, &spr_write_generic,
7461 KVM_REG_PPC_PMC2, 0x00000000);
7462 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7463 SPR_NOACCESS, SPR_NOACCESS,
7464 &spr_read_generic, &spr_write_generic,
7465 KVM_REG_PPC_PMC3, 0x00000000);
7466 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7467 SPR_NOACCESS, SPR_NOACCESS,
7468 &spr_read_generic, &spr_write_generic,
7469 KVM_REG_PPC_PMC4, 0x00000000);
7470 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7471 SPR_NOACCESS, SPR_NOACCESS,
7472 &spr_read_generic, &spr_write_generic,
7473 KVM_REG_PPC_PMC5, 0x00000000);
7474 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7475 SPR_NOACCESS, SPR_NOACCESS,
7476 &spr_read_generic, &spr_write_generic,
7477 KVM_REG_PPC_PMC6, 0x00000000);
7478 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7479 SPR_NOACCESS, SPR_NOACCESS,
7480 &spr_read_generic, &spr_write_generic,
7481 KVM_REG_PPC_SIAR, 0x00000000);
7482 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7483 SPR_NOACCESS, SPR_NOACCESS,
7484 &spr_read_generic, &spr_write_generic,
7485 KVM_REG_PPC_SDAR, 0x00000000);
7486 }
7487
7488 static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7489 {
7490 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7491 &spr_read_ureg, SPR_NOACCESS,
7492 &spr_read_ureg, &spr_write_ureg,
7493 0x00000000);
7494 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7495 &spr_read_ureg, SPR_NOACCESS,
7496 &spr_read_ureg, &spr_write_ureg,
7497 0x00000000);
7498 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7499 &spr_read_ureg, SPR_NOACCESS,
7500 &spr_read_ureg, &spr_write_ureg,
7501 0x00000000);
7502 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7503 &spr_read_ureg, SPR_NOACCESS,
7504 &spr_read_ureg, &spr_write_ureg,
7505 0x00000000);
7506 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7507 &spr_read_ureg, SPR_NOACCESS,
7508 &spr_read_ureg, &spr_write_ureg,
7509 0x00000000);
7510 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7511 &spr_read_ureg, SPR_NOACCESS,
7512 &spr_read_ureg, &spr_write_ureg,
7513 0x00000000);
7514 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7515 &spr_read_ureg, SPR_NOACCESS,
7516 &spr_read_ureg, &spr_write_ureg,
7517 0x00000000);
7518 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7519 &spr_read_ureg, SPR_NOACCESS,
7520 &spr_read_ureg, &spr_write_ureg,
7521 0x00000000);
7522 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7523 &spr_read_ureg, SPR_NOACCESS,
7524 &spr_read_ureg, &spr_write_ureg,
7525 0x00000000);
7526 spr_register(env, SPR_POWER_USIAR, "USIAR",
7527 &spr_read_ureg, SPR_NOACCESS,
7528 &spr_read_ureg, &spr_write_ureg,
7529 0x00000000);
7530 spr_register(env, SPR_POWER_USDAR, "USDAR",
7531 &spr_read_ureg, SPR_NOACCESS,
7532 &spr_read_ureg, &spr_write_ureg,
7533 0x00000000);
7534 }
7535
7536 static void gen_spr_970_pmu_sup(CPUPPCState *env)
7537 {
7538 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7539 SPR_NOACCESS, SPR_NOACCESS,
7540 &spr_read_generic, &spr_write_generic,
7541 KVM_REG_PPC_PMC7, 0x00000000);
7542 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7543 SPR_NOACCESS, SPR_NOACCESS,
7544 &spr_read_generic, &spr_write_generic,
7545 KVM_REG_PPC_PMC8, 0x00000000);
7546 }
7547
7548 static void gen_spr_970_pmu_user(CPUPPCState *env)
7549 {
7550 spr_register(env, SPR_970_UPMC7, "UPMC7",
7551 &spr_read_ureg, SPR_NOACCESS,
7552 &spr_read_ureg, &spr_write_ureg,
7553 0x00000000);
7554 spr_register(env, SPR_970_UPMC8, "UPMC8",
7555 &spr_read_ureg, SPR_NOACCESS,
7556 &spr_read_ureg, &spr_write_ureg,
7557 0x00000000);
7558 }
7559
7560 static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7561 {
7562 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7563 SPR_NOACCESS, SPR_NOACCESS,
7564 &spr_read_generic, &spr_write_generic,
7565 KVM_REG_PPC_MMCR2, 0x00000000);
7566 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7567 SPR_NOACCESS, SPR_NOACCESS,
7568 &spr_read_generic, &spr_write_generic,
7569 KVM_REG_PPC_MMCRS, 0x00000000);
7570 }
7571
7572 static void gen_spr_power8_pmu_user(CPUPPCState *env)
7573 {
7574 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7575 &spr_read_ureg, SPR_NOACCESS,
7576 &spr_read_ureg, &spr_write_ureg,
7577 0x00000000);
7578 }
7579
7580 static void gen_spr_power5p_ear(CPUPPCState *env)
7581 {
7582 /* External access control */
7583 spr_register(env, SPR_EAR, "EAR",
7584 SPR_NOACCESS, SPR_NOACCESS,
7585 &spr_read_generic, &spr_write_generic,
7586 0x00000000);
7587 }
7588
7589 static void gen_spr_power5p_lpar(CPUPPCState *env)
7590 {
7591 /* Logical partitionning */
7592 spr_register_kvm(env, SPR_LPCR, "LPCR",
7593 SPR_NOACCESS, SPR_NOACCESS,
7594 &spr_read_generic, &spr_write_generic,
7595 KVM_REG_PPC_LPCR, 0x00000000);
7596 }
7597
7598 static void gen_spr_book3s_ids(CPUPPCState *env)
7599 {
7600 /* Processor identification */
7601 spr_register(env, SPR_PIR, "PIR",
7602 SPR_NOACCESS, SPR_NOACCESS,
7603 &spr_read_generic, &spr_write_pir,
7604 0x00000000);
7605 }
7606
7607 static void gen_spr_power8_ids(CPUPPCState *env)
7608 {
7609 /* Thread identification */
7610 spr_register(env, SPR_TIR, "TIR",
7611 SPR_NOACCESS, SPR_NOACCESS,
7612 &spr_read_generic, SPR_NOACCESS,
7613 0x00000000);
7614 }
7615
7616 static void gen_spr_book3s_purr(CPUPPCState *env)
7617 {
7618 #if !defined(CONFIG_USER_ONLY)
7619 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7620 spr_register_kvm(env, SPR_PURR, "PURR",
7621 &spr_read_purr, SPR_NOACCESS,
7622 &spr_read_purr, SPR_NOACCESS,
7623 KVM_REG_PPC_PURR, 0x00000000);
7624 spr_register_kvm(env, SPR_SPURR, "SPURR",
7625 &spr_read_purr, SPR_NOACCESS,
7626 &spr_read_purr, SPR_NOACCESS,
7627 KVM_REG_PPC_SPURR, 0x00000000);
7628 #endif
7629 }
7630
7631 static void gen_spr_power6_dbg(CPUPPCState *env)
7632 {
7633 #if !defined(CONFIG_USER_ONLY)
7634 spr_register(env, SPR_CFAR, "SPR_CFAR",
7635 SPR_NOACCESS, SPR_NOACCESS,
7636 &spr_read_cfar, &spr_write_cfar,
7637 0x00000000);
7638 #endif
7639 }
7640
7641 static void gen_spr_power5p_common(CPUPPCState *env)
7642 {
7643 spr_register_kvm(env, SPR_PPR, "PPR",
7644 &spr_read_generic, &spr_write_generic,
7645 &spr_read_generic, &spr_write_generic,
7646 KVM_REG_PPC_PPR, 0x00000000);
7647 }
7648
7649 static void gen_spr_power6_common(CPUPPCState *env)
7650 {
7651 #if !defined(CONFIG_USER_ONLY)
7652 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7653 SPR_NOACCESS, SPR_NOACCESS,
7654 &spr_read_generic, &spr_write_generic,
7655 KVM_REG_PPC_DSCR, 0x00000000);
7656 #endif
7657 /*
7658 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7659 * POWERPC_EXCP_INVAL_SPR.
7660 */
7661 spr_register(env, SPR_PCR, "PCR",
7662 SPR_NOACCESS, SPR_NOACCESS,
7663 SPR_NOACCESS, SPR_NOACCESS,
7664 0x00000000);
7665 }
7666
7667 static void spr_read_tar(void *opaque, int gprn, int sprn)
7668 {
7669 gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7670 spr_read_generic(opaque, gprn, sprn);
7671 }
7672
7673 static void spr_write_tar(void *opaque, int sprn, int gprn)
7674 {
7675 gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7676 spr_write_generic(opaque, sprn, gprn);
7677 }
7678
7679 static void gen_spr_power8_tce_address_control(CPUPPCState *env)
7680 {
7681 spr_register(env, SPR_TAR, "TAR",
7682 &spr_read_tar, &spr_write_tar,
7683 &spr_read_generic, &spr_write_generic,
7684 0x00000000);
7685 }
7686
7687 static void spr_read_tm(void *opaque, int gprn, int sprn)
7688 {
7689 gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7690 spr_read_generic(opaque, gprn, sprn);
7691 }
7692
7693 static void spr_write_tm(void *opaque, int sprn, int gprn)
7694 {
7695 gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7696 spr_write_generic(opaque, sprn, gprn);
7697 }
7698
7699 static void spr_read_tm_upper32(void *opaque, int gprn, int sprn)
7700 {
7701 gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7702 spr_read_prev_upper32(opaque, gprn, sprn);
7703 }
7704
7705 static void spr_write_tm_upper32(void *opaque, int sprn, int gprn)
7706 {
7707 gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7708 spr_write_prev_upper32(opaque, sprn, gprn);
7709 }
7710
7711 static void gen_spr_power8_tm(CPUPPCState *env)
7712 {
7713 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
7714 &spr_read_tm, &spr_write_tm,
7715 &spr_read_tm, &spr_write_tm,
7716 KVM_REG_PPC_TFHAR, 0x00000000);
7717 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
7718 &spr_read_tm, &spr_write_tm,
7719 &spr_read_tm, &spr_write_tm,
7720 KVM_REG_PPC_TFIAR, 0x00000000);
7721 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
7722 &spr_read_tm, &spr_write_tm,
7723 &spr_read_tm, &spr_write_tm,
7724 KVM_REG_PPC_TEXASR, 0x00000000);
7725 spr_register(env, SPR_TEXASRU, "TEXASRU",
7726 &spr_read_tm_upper32, &spr_write_tm_upper32,
7727 &spr_read_tm_upper32, &spr_write_tm_upper32,
7728 0x00000000);
7729 }
7730
7731 static void spr_read_ebb(void *opaque, int gprn, int sprn)
7732 {
7733 gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7734 spr_read_generic(opaque, gprn, sprn);
7735 }
7736
7737 static void spr_write_ebb(void *opaque, int sprn, int gprn)
7738 {
7739 gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7740 spr_write_generic(opaque, sprn, gprn);
7741 }
7742
7743 static void spr_read_ebb_upper32(void *opaque, int gprn, int sprn)
7744 {
7745 gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7746 spr_read_prev_upper32(opaque, gprn, sprn);
7747 }
7748
7749 static void spr_write_ebb_upper32(void *opaque, int sprn, int gprn)
7750 {
7751 gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7752 spr_write_prev_upper32(opaque, sprn, gprn);
7753 }
7754
7755 static void gen_spr_power8_ebb(CPUPPCState *env)
7756 {
7757 spr_register(env, SPR_BESCRS, "BESCRS",
7758 &spr_read_ebb, &spr_write_ebb,
7759 &spr_read_generic, &spr_write_generic,
7760 0x00000000);
7761 spr_register(env, SPR_BESCRSU, "BESCRSU",
7762 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7763 &spr_read_prev_upper32, &spr_write_prev_upper32,
7764 0x00000000);
7765 spr_register(env, SPR_BESCRR, "BESCRR",
7766 &spr_read_ebb, &spr_write_ebb,
7767 &spr_read_generic, &spr_write_generic,
7768 0x00000000);
7769 spr_register(env, SPR_BESCRRU, "BESCRRU",
7770 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7771 &spr_read_prev_upper32, &spr_write_prev_upper32,
7772 0x00000000);
7773 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
7774 &spr_read_ebb, &spr_write_ebb,
7775 &spr_read_generic, &spr_write_generic,
7776 KVM_REG_PPC_EBBHR, 0x00000000);
7777 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
7778 &spr_read_ebb, &spr_write_ebb,
7779 &spr_read_generic, &spr_write_generic,
7780 KVM_REG_PPC_EBBRR, 0x00000000);
7781 spr_register_kvm(env, SPR_BESCR, "BESCR",
7782 &spr_read_ebb, &spr_write_ebb,
7783 &spr_read_generic, &spr_write_generic,
7784 KVM_REG_PPC_BESCR, 0x00000000);
7785 }
7786
7787 static void gen_spr_power8_fscr(CPUPPCState *env)
7788 {
7789 #if defined(CONFIG_USER_ONLY)
7790 target_ulong initval = 1ULL << FSCR_TAR;
7791 #else
7792 target_ulong initval = 0;
7793 #endif
7794 spr_register_kvm(env, SPR_FSCR, "FSCR",
7795 SPR_NOACCESS, SPR_NOACCESS,
7796 &spr_read_generic, &spr_write_generic,
7797 KVM_REG_PPC_FSCR, initval);
7798 }
7799
7800 static void init_proc_book3s_64(CPUPPCState *env, int version)
7801 {
7802 gen_spr_ne_601(env);
7803 gen_tbl(env);
7804 gen_spr_book3s_altivec(env);
7805 gen_spr_book3s_pmu_sup(env);
7806 gen_spr_book3s_pmu_user(env);
7807 gen_spr_book3s_common(env);
7808
7809 switch (version) {
7810 case BOOK3S_CPU_970:
7811 case BOOK3S_CPU_POWER5PLUS:
7812 gen_spr_970_hid(env);
7813 gen_spr_970_hior(env);
7814 gen_low_BATs(env);
7815 gen_spr_970_pmu_sup(env);
7816 gen_spr_970_pmu_user(env);
7817 break;
7818 case BOOK3S_CPU_POWER7:
7819 case BOOK3S_CPU_POWER8:
7820 gen_spr_book3s_ids(env);
7821 gen_spr_amr(env);
7822 gen_spr_book3s_purr(env);
7823 break;
7824 default:
7825 g_assert_not_reached();
7826 }
7827 if (version >= BOOK3S_CPU_POWER5PLUS) {
7828 gen_spr_power5p_common(env);
7829 gen_spr_power5p_lpar(env);
7830 gen_spr_power5p_ear(env);
7831 } else {
7832 gen_spr_970_lpar(env);
7833 }
7834 if (version == BOOK3S_CPU_970) {
7835 gen_spr_970_dbg(env);
7836 }
7837 if (version >= BOOK3S_CPU_POWER6) {
7838 gen_spr_power6_common(env);
7839 gen_spr_power6_dbg(env);
7840 }
7841 if (version >= BOOK3S_CPU_POWER8) {
7842 gen_spr_power8_tce_address_control(env);
7843 gen_spr_power8_ids(env);
7844 gen_spr_power8_ebb(env);
7845 gen_spr_power8_fscr(env);
7846 gen_spr_power8_pmu_sup(env);
7847 gen_spr_power8_pmu_user(env);
7848 gen_spr_power8_tm(env);
7849 }
7850 if (version < BOOK3S_CPU_POWER8) {
7851 gen_spr_book3s_dbg(env);
7852 }
7853 #if !defined(CONFIG_USER_ONLY)
7854 switch (version) {
7855 case BOOK3S_CPU_970:
7856 case BOOK3S_CPU_POWER5PLUS:
7857 env->slb_nr = 64;
7858 break;
7859 case BOOK3S_CPU_POWER7:
7860 case BOOK3S_CPU_POWER8:
7861 default:
7862 env->slb_nr = 32;
7863 break;
7864 }
7865 #endif
7866 /* Allocate hardware IRQ controller */
7867 switch (version) {
7868 case BOOK3S_CPU_970:
7869 case BOOK3S_CPU_POWER5PLUS:
7870 init_excp_970(env);
7871 ppc970_irq_init(env);
7872 break;
7873 case BOOK3S_CPU_POWER7:
7874 case BOOK3S_CPU_POWER8:
7875 init_excp_POWER7(env);
7876 ppcPOWER7_irq_init(env);
7877 break;
7878 default:
7879 g_assert_not_reached();
7880 }
7881
7882 env->dcache_line_size = 128;
7883 env->icache_line_size = 128;
7884 }
7885
7886 static void init_proc_970(CPUPPCState *env)
7887 {
7888 init_proc_book3s_64(env, BOOK3S_CPU_970);
7889 }
7890
7891 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7892 {
7893 DeviceClass *dc = DEVICE_CLASS(oc);
7894 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7895
7896 dc->desc = "PowerPC 970";
7897 pcc->init_proc = init_proc_970;
7898 pcc->check_pow = check_pow_970;
7899 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7900 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7901 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7902 PPC_FLOAT_STFIWX |
7903 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7904 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7905 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7906 PPC_64B | PPC_ALTIVEC |
7907 PPC_SEGMENT_64B | PPC_SLBI;
7908 pcc->msr_mask = (1ull << MSR_SF) |
7909 (1ull << MSR_VR) |
7910 (1ull << MSR_POW) |
7911 (1ull << MSR_EE) |
7912 (1ull << MSR_PR) |
7913 (1ull << MSR_FP) |
7914 (1ull << MSR_ME) |
7915 (1ull << MSR_FE0) |
7916 (1ull << MSR_SE) |
7917 (1ull << MSR_DE) |
7918 (1ull << MSR_FE1) |
7919 (1ull << MSR_IR) |
7920 (1ull << MSR_DR) |
7921 (1ull << MSR_PMM) |
7922 (1ull << MSR_RI);
7923 pcc->mmu_model = POWERPC_MMU_64B;
7924 #if defined(CONFIG_SOFTMMU)
7925 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7926 #endif
7927 pcc->excp_model = POWERPC_EXCP_970;
7928 pcc->bus_model = PPC_FLAGS_INPUT_970;
7929 pcc->bfd_mach = bfd_mach_ppc64;
7930 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7931 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7932 POWERPC_FLAG_BUS_CLK;
7933 pcc->l1_dcache_size = 0x8000;
7934 pcc->l1_icache_size = 0x10000;
7935 }
7936
7937 static void init_proc_power5plus(CPUPPCState *env)
7938 {
7939 init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
7940 }
7941
7942 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
7943 {
7944 DeviceClass *dc = DEVICE_CLASS(oc);
7945 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7946
7947 dc->fw_name = "PowerPC,POWER5";
7948 dc->desc = "POWER5+";
7949 pcc->init_proc = init_proc_power5plus;
7950 pcc->check_pow = check_pow_970;
7951 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7952 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7953 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7954 PPC_FLOAT_STFIWX |
7955 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7956 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7957 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7958 PPC_64B |
7959 PPC_SEGMENT_64B | PPC_SLBI;
7960 pcc->msr_mask = (1ull << MSR_SF) |
7961 (1ull << MSR_VR) |
7962 (1ull << MSR_POW) |
7963 (1ull << MSR_EE) |
7964 (1ull << MSR_PR) |
7965 (1ull << MSR_FP) |
7966 (1ull << MSR_ME) |
7967 (1ull << MSR_FE0) |
7968 (1ull << MSR_SE) |
7969 (1ull << MSR_DE) |
7970 (1ull << MSR_FE1) |
7971 (1ull << MSR_IR) |
7972 (1ull << MSR_DR) |
7973 (1ull << MSR_PMM) |
7974 (1ull << MSR_RI);
7975 pcc->mmu_model = POWERPC_MMU_64B;
7976 #if defined(CONFIG_SOFTMMU)
7977 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7978 #endif
7979 pcc->excp_model = POWERPC_EXCP_970;
7980 pcc->bus_model = PPC_FLAGS_INPUT_970;
7981 pcc->bfd_mach = bfd_mach_ppc64;
7982 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7983 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7984 POWERPC_FLAG_BUS_CLK;
7985 pcc->l1_dcache_size = 0x8000;
7986 pcc->l1_icache_size = 0x10000;
7987 }
7988
7989 static void powerpc_get_compat(Object *obj, Visitor *v,
7990 void *opaque, const char *name, Error **errp)
7991 {
7992 char *value = (char *)"";
7993 Property *prop = opaque;
7994 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
7995
7996 switch (*max_compat) {
7997 case CPU_POWERPC_LOGICAL_2_05:
7998 value = (char *)"power6";
7999 break;
8000 case CPU_POWERPC_LOGICAL_2_06:
8001 value = (char *)"power7";
8002 break;
8003 case CPU_POWERPC_LOGICAL_2_07:
8004 value = (char *)"power8";
8005 break;
8006 case 0:
8007 break;
8008 default:
8009 error_setg(errp, "Internal error: compat is set to %x",
8010 max_compat ? *max_compat : -1);
8011 break;
8012 }
8013
8014 visit_type_str(v, &value, name, errp);
8015 }
8016
8017 static void powerpc_set_compat(Object *obj, Visitor *v,
8018 void *opaque, const char *name, Error **errp)
8019 {
8020 Error *error = NULL;
8021 char *value = NULL;
8022 Property *prop = opaque;
8023 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8024
8025 visit_type_str(v, &value, name, &error);
8026 if (error) {
8027 error_propagate(errp, error);
8028 return;
8029 }
8030
8031 if (strcmp(value, "power6") == 0) {
8032 *max_compat = CPU_POWERPC_LOGICAL_2_05;
8033 } else if (strcmp(value, "power7") == 0) {
8034 *max_compat = CPU_POWERPC_LOGICAL_2_06;
8035 } else if (strcmp(value, "power8") == 0) {
8036 *max_compat = CPU_POWERPC_LOGICAL_2_07;
8037 } else {
8038 error_setg(errp, "Invalid compatibility mode \"%s\"", value);
8039 }
8040
8041 g_free(value);
8042 }
8043
8044 static PropertyInfo powerpc_compat_propinfo = {
8045 .name = "str",
8046 .legacy_name = "powerpc-server-compat",
8047 .get = powerpc_get_compat,
8048 .set = powerpc_set_compat,
8049 };
8050
8051 #define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \
8052 DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t)
8053
8054 static Property powerpc_servercpu_properties[] = {
8055 DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU, max_compat),
8056 DEFINE_PROP_END_OF_LIST(),
8057 };
8058
8059 static void init_proc_POWER7 (CPUPPCState *env)
8060 {
8061 init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
8062 }
8063
8064 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8065 {
8066 DeviceClass *dc = DEVICE_CLASS(oc);
8067 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8068
8069 dc->fw_name = "PowerPC,POWER7";
8070 dc->desc = "POWER7";
8071 dc->props = powerpc_servercpu_properties;
8072 pcc->pvr = CPU_POWERPC_POWER7_BASE;
8073 pcc->pvr_mask = CPU_POWERPC_POWER7_MASK;
8074 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
8075 pcc->init_proc = init_proc_POWER7;
8076 pcc->check_pow = check_pow_nocheck;
8077 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8078 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8079 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8080 PPC_FLOAT_FRSQRTES |
8081 PPC_FLOAT_STFIWX |
8082 PPC_FLOAT_EXT |
8083 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8084 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8085 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8086 PPC_64B | PPC_ALTIVEC |
8087 PPC_SEGMENT_64B | PPC_SLBI |
8088 PPC_POPCNTB | PPC_POPCNTWD;
8089 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8090 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8091 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8092 PPC2_FP_TST_ISA206;
8093 pcc->msr_mask = (1ull << MSR_SF) |
8094 (1ull << MSR_VR) |
8095 (1ull << MSR_VSX) |
8096 (1ull << MSR_EE) |
8097 (1ull << MSR_PR) |
8098 (1ull << MSR_FP) |
8099 (1ull << MSR_ME) |
8100 (1ull << MSR_FE0) |
8101 (1ull << MSR_SE) |
8102 (1ull << MSR_DE) |
8103 (1ull << MSR_FE1) |
8104 (1ull << MSR_IR) |
8105 (1ull << MSR_DR) |
8106 (1ull << MSR_PMM) |
8107 (1ull << MSR_RI) |
8108 (1ull << MSR_LE);
8109 pcc->mmu_model = POWERPC_MMU_2_06;
8110 #if defined(CONFIG_SOFTMMU)
8111 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8112 #endif
8113 pcc->excp_model = POWERPC_EXCP_POWER7;
8114 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8115 pcc->bfd_mach = bfd_mach_ppc64;
8116 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8117 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8118 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8119 POWERPC_FLAG_VSX;
8120 pcc->l1_dcache_size = 0x8000;
8121 pcc->l1_icache_size = 0x8000;
8122 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8123 }
8124
8125 POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
8126 {
8127 DeviceClass *dc = DEVICE_CLASS(oc);
8128 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8129
8130 dc->fw_name = "PowerPC,POWER7+";
8131 dc->desc = "POWER7+";
8132 dc->props = powerpc_servercpu_properties;
8133 pcc->pvr = CPU_POWERPC_POWER7P_BASE;
8134 pcc->pvr_mask = CPU_POWERPC_POWER7P_MASK;
8135 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
8136 pcc->init_proc = init_proc_POWER7;
8137 pcc->check_pow = check_pow_nocheck;
8138 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8139 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8140 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8141 PPC_FLOAT_FRSQRTES |
8142 PPC_FLOAT_STFIWX |
8143 PPC_FLOAT_EXT |
8144 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8145 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8146 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8147 PPC_64B | PPC_ALTIVEC |
8148 PPC_SEGMENT_64B | PPC_SLBI |
8149 PPC_POPCNTB | PPC_POPCNTWD;
8150 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8151 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8152 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8153 PPC2_FP_TST_ISA206;
8154 pcc->msr_mask = (1ull << MSR_SF) |
8155 (1ull << MSR_VR) |
8156 (1ull << MSR_VSX) |
8157 (1ull << MSR_EE) |
8158 (1ull << MSR_PR) |
8159 (1ull << MSR_FP) |
8160 (1ull << MSR_ME) |
8161 (1ull << MSR_FE0) |
8162 (1ull << MSR_SE) |
8163 (1ull << MSR_DE) |
8164 (1ull << MSR_FE1) |
8165 (1ull << MSR_IR) |
8166 (1ull << MSR_DR) |
8167 (1ull << MSR_PMM) |
8168 (1ull << MSR_RI) |
8169 (1ull << MSR_LE);
8170 pcc->mmu_model = POWERPC_MMU_2_06;
8171 #if defined(CONFIG_SOFTMMU)
8172 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8173 #endif
8174 pcc->excp_model = POWERPC_EXCP_POWER7;
8175 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8176 pcc->bfd_mach = bfd_mach_ppc64;
8177 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8178 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8179 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8180 POWERPC_FLAG_VSX;
8181 pcc->l1_dcache_size = 0x8000;
8182 pcc->l1_icache_size = 0x8000;
8183 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8184 }
8185
8186 static void init_proc_POWER8(CPUPPCState *env)
8187 {
8188 init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
8189 }
8190
8191 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8192 {
8193 DeviceClass *dc = DEVICE_CLASS(oc);
8194 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8195
8196 dc->fw_name = "PowerPC,POWER8";
8197 dc->desc = "POWER8";
8198 dc->props = powerpc_servercpu_properties;
8199 pcc->pvr = CPU_POWERPC_POWER8_BASE;
8200 pcc->pvr_mask = CPU_POWERPC_POWER8_MASK;
8201 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
8202 pcc->init_proc = init_proc_POWER8;
8203 pcc->check_pow = check_pow_nocheck;
8204 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8205 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8206 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8207 PPC_FLOAT_FRSQRTES |
8208 PPC_FLOAT_STFIWX |
8209 PPC_FLOAT_EXT |
8210 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8211 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8212 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8213 PPC_64B | PPC_64BX | PPC_ALTIVEC |
8214 PPC_SEGMENT_64B | PPC_SLBI |
8215 PPC_POPCNTB | PPC_POPCNTWD;
8216 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8217 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8218 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8219 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8220 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8221 PPC2_ISA205 | PPC2_ISA207S;
8222 pcc->msr_mask = (1ull << MSR_SF) |
8223 (1ull << MSR_TM) |
8224 (1ull << MSR_VR) |
8225 (1ull << MSR_VSX) |
8226 (1ull << MSR_EE) |
8227 (1ull << MSR_PR) |
8228 (1ull << MSR_FP) |
8229 (1ull << MSR_ME) |
8230 (1ull << MSR_FE0) |
8231 (1ull << MSR_SE) |
8232 (1ull << MSR_DE) |
8233 (1ull << MSR_FE1) |
8234 (1ull << MSR_IR) |
8235 (1ull << MSR_DR) |
8236 (1ull << MSR_PMM) |
8237 (1ull << MSR_RI) |
8238 (1ull << MSR_LE);
8239 pcc->mmu_model = POWERPC_MMU_2_06;
8240 #if defined(CONFIG_SOFTMMU)
8241 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8242 #endif
8243 pcc->excp_model = POWERPC_EXCP_POWER7;
8244 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8245 pcc->bfd_mach = bfd_mach_ppc64;
8246 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8247 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8248 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8249 POWERPC_FLAG_VSX;
8250 pcc->l1_dcache_size = 0x8000;
8251 pcc->l1_icache_size = 0x8000;
8252 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8253 }
8254 #endif /* defined (TARGET_PPC64) */
8255
8256
8257 /*****************************************************************************/
8258 /* Generic CPU instantiation routine */
8259 static void init_ppc_proc(PowerPCCPU *cpu)
8260 {
8261 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8262 CPUPPCState *env = &cpu->env;
8263 #if !defined(CONFIG_USER_ONLY)
8264 int i;
8265
8266 env->irq_inputs = NULL;
8267 /* Set all exception vectors to an invalid address */
8268 for (i = 0; i < POWERPC_EXCP_NB; i++)
8269 env->excp_vectors[i] = (target_ulong)(-1ULL);
8270 env->ivor_mask = 0x00000000;
8271 env->ivpr_mask = 0x00000000;
8272 /* Default MMU definitions */
8273 env->nb_BATs = 0;
8274 env->nb_tlb = 0;
8275 env->nb_ways = 0;
8276 env->tlb_type = TLB_NONE;
8277 #endif
8278 /* Register SPR common to all PowerPC implementations */
8279 gen_spr_generic(env);
8280 spr_register(env, SPR_PVR, "PVR",
8281 /* Linux permits userspace to read PVR */
8282 #if defined(CONFIG_LINUX_USER)
8283 &spr_read_generic,
8284 #else
8285 SPR_NOACCESS,
8286 #endif
8287 SPR_NOACCESS,
8288 &spr_read_generic, SPR_NOACCESS,
8289 pcc->pvr);
8290 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8291 if (pcc->svr != POWERPC_SVR_NONE) {
8292 if (pcc->svr & POWERPC_SVR_E500) {
8293 spr_register(env, SPR_E500_SVR, "SVR",
8294 SPR_NOACCESS, SPR_NOACCESS,
8295 &spr_read_generic, SPR_NOACCESS,
8296 pcc->svr & ~POWERPC_SVR_E500);
8297 } else {
8298 spr_register(env, SPR_SVR, "SVR",
8299 SPR_NOACCESS, SPR_NOACCESS,
8300 &spr_read_generic, SPR_NOACCESS,
8301 pcc->svr);
8302 }
8303 }
8304 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8305 (*pcc->init_proc)(env);
8306
8307 /* MSR bits & flags consistency checks */
8308 if (env->msr_mask & (1 << 25)) {
8309 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8310 case POWERPC_FLAG_SPE:
8311 case POWERPC_FLAG_VRE:
8312 break;
8313 default:
8314 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8315 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8316 exit(1);
8317 }
8318 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8319 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8320 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8321 exit(1);
8322 }
8323 if (env->msr_mask & (1 << 17)) {
8324 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8325 case POWERPC_FLAG_TGPR:
8326 case POWERPC_FLAG_CE:
8327 break;
8328 default:
8329 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8330 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8331 exit(1);
8332 }
8333 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8334 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8335 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8336 exit(1);
8337 }
8338 if (env->msr_mask & (1 << 10)) {
8339 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8340 POWERPC_FLAG_UBLE)) {
8341 case POWERPC_FLAG_SE:
8342 case POWERPC_FLAG_DWE:
8343 case POWERPC_FLAG_UBLE:
8344 break;
8345 default:
8346 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8347 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8348 "POWERPC_FLAG_UBLE\n");
8349 exit(1);
8350 }
8351 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8352 POWERPC_FLAG_UBLE)) {
8353 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8354 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8355 "POWERPC_FLAG_UBLE\n");
8356 exit(1);
8357 }
8358 if (env->msr_mask & (1 << 9)) {
8359 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8360 case POWERPC_FLAG_BE:
8361 case POWERPC_FLAG_DE:
8362 break;
8363 default:
8364 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8365 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8366 exit(1);
8367 }
8368 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8369 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8370 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8371 exit(1);
8372 }
8373 if (env->msr_mask & (1 << 2)) {
8374 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8375 case POWERPC_FLAG_PX:
8376 case POWERPC_FLAG_PMM:
8377 break;
8378 default:
8379 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8380 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8381 exit(1);
8382 }
8383 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8384 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8385 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8386 exit(1);
8387 }
8388 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8389 fprintf(stderr, "PowerPC flags inconsistency\n"
8390 "Should define the time-base and decrementer clock source\n");
8391 exit(1);
8392 }
8393 /* Allocate TLBs buffer when needed */
8394 #if !defined(CONFIG_USER_ONLY)
8395 if (env->nb_tlb != 0) {
8396 int nb_tlb = env->nb_tlb;
8397 if (env->id_tlbs != 0)
8398 nb_tlb *= 2;
8399 switch (env->tlb_type) {
8400 case TLB_6XX:
8401 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
8402 break;
8403 case TLB_EMB:
8404 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
8405 break;
8406 case TLB_MAS:
8407 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
8408 break;
8409 }
8410 /* Pre-compute some useful values */
8411 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8412 }
8413 if (env->irq_inputs == NULL) {
8414 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8415 " Attempt QEMU to crash very soon !\n");
8416 }
8417 #endif
8418 if (env->check_pow == NULL) {
8419 fprintf(stderr, "WARNING: no power management check handler "
8420 "registered.\n"
8421 " Attempt QEMU to crash very soon !\n");
8422 }
8423 }
8424
8425 #if defined(PPC_DUMP_CPU)
8426 static void dump_ppc_sprs (CPUPPCState *env)
8427 {
8428 ppc_spr_t *spr;
8429 #if !defined(CONFIG_USER_ONLY)
8430 uint32_t sr, sw;
8431 #endif
8432 uint32_t ur, uw;
8433 int i, j, n;
8434
8435 printf("Special purpose registers:\n");
8436 for (i = 0; i < 32; i++) {
8437 for (j = 0; j < 32; j++) {
8438 n = (i << 5) | j;
8439 spr = &env->spr_cb[n];
8440 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8441 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8442 #if !defined(CONFIG_USER_ONLY)
8443 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8444 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8445 if (sw || sr || uw || ur) {
8446 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8447 (i << 5) | j, (i << 5) | j, spr->name,
8448 sw ? 'w' : '-', sr ? 'r' : '-',
8449 uw ? 'w' : '-', ur ? 'r' : '-');
8450 }
8451 #else
8452 if (uw || ur) {
8453 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8454 (i << 5) | j, (i << 5) | j, spr->name,
8455 uw ? 'w' : '-', ur ? 'r' : '-');
8456 }
8457 #endif
8458 }
8459 }
8460 fflush(stdout);
8461 fflush(stderr);
8462 }
8463 #endif
8464
8465 /*****************************************************************************/
8466 #include <stdlib.h>
8467 #include <string.h>
8468
8469 /* Opcode types */
8470 enum {
8471 PPC_DIRECT = 0, /* Opcode routine */
8472 PPC_INDIRECT = 1, /* Indirect opcode table */
8473 };
8474
8475 static inline int is_indirect_opcode (void *handler)
8476 {
8477 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
8478 }
8479
8480 static inline opc_handler_t **ind_table(void *handler)
8481 {
8482 return (opc_handler_t **)((uintptr_t)handler & ~3);
8483 }
8484
8485 /* Instruction table creation */
8486 /* Opcodes tables creation */
8487 static void fill_new_table (opc_handler_t **table, int len)
8488 {
8489 int i;
8490
8491 for (i = 0; i < len; i++)
8492 table[i] = &invalid_handler;
8493 }
8494
8495 static int create_new_table (opc_handler_t **table, unsigned char idx)
8496 {
8497 opc_handler_t **tmp;
8498
8499 tmp = g_new(opc_handler_t *, 0x20);
8500 fill_new_table(tmp, 0x20);
8501 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8502
8503 return 0;
8504 }
8505
8506 static int insert_in_table (opc_handler_t **table, unsigned char idx,
8507 opc_handler_t *handler)
8508 {
8509 if (table[idx] != &invalid_handler)
8510 return -1;
8511 table[idx] = handler;
8512
8513 return 0;
8514 }
8515
8516 static int register_direct_insn (opc_handler_t **ppc_opcodes,
8517 unsigned char idx, opc_handler_t *handler)
8518 {
8519 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8520 printf("*** ERROR: opcode %02x already assigned in main "
8521 "opcode table\n", idx);
8522 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8523 printf(" Registered handler '%s' - new handler '%s'\n",
8524 ppc_opcodes[idx]->oname, handler->oname);
8525 #endif
8526 return -1;
8527 }
8528
8529 return 0;
8530 }
8531
8532 static int register_ind_in_table (opc_handler_t **table,
8533 unsigned char idx1, unsigned char idx2,
8534 opc_handler_t *handler)
8535 {
8536 if (table[idx1] == &invalid_handler) {
8537 if (create_new_table(table, idx1) < 0) {
8538 printf("*** ERROR: unable to create indirect table "
8539 "idx=%02x\n", idx1);
8540 return -1;
8541 }
8542 } else {
8543 if (!is_indirect_opcode(table[idx1])) {
8544 printf("*** ERROR: idx %02x already assigned to a direct "
8545 "opcode\n", idx1);
8546 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8547 printf(" Registered handler '%s' - new handler '%s'\n",
8548 ind_table(table[idx1])[idx2]->oname, handler->oname);
8549 #endif
8550 return -1;
8551 }
8552 }
8553 if (handler != NULL &&
8554 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8555 printf("*** ERROR: opcode %02x already assigned in "
8556 "opcode table %02x\n", idx2, idx1);
8557 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8558 printf(" Registered handler '%s' - new handler '%s'\n",
8559 ind_table(table[idx1])[idx2]->oname, handler->oname);
8560 #endif
8561 return -1;
8562 }
8563
8564 return 0;
8565 }
8566
8567 static int register_ind_insn (opc_handler_t **ppc_opcodes,
8568 unsigned char idx1, unsigned char idx2,
8569 opc_handler_t *handler)
8570 {
8571 int ret;
8572
8573 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8574
8575 return ret;
8576 }
8577
8578 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8579 unsigned char idx1, unsigned char idx2,
8580 unsigned char idx3, opc_handler_t *handler)
8581 {
8582 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8583 printf("*** ERROR: unable to join indirect table idx "
8584 "[%02x-%02x]\n", idx1, idx2);
8585 return -1;
8586 }
8587 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8588 handler) < 0) {
8589 printf("*** ERROR: unable to insert opcode "
8590 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8591 return -1;
8592 }
8593
8594 return 0;
8595 }
8596
8597 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8598 {
8599 if (insn->opc2 != 0xFF) {
8600 if (insn->opc3 != 0xFF) {
8601 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8602 insn->opc3, &insn->handler) < 0)
8603 return -1;
8604 } else {
8605 if (register_ind_insn(ppc_opcodes, insn->opc1,
8606 insn->opc2, &insn->handler) < 0)
8607 return -1;
8608 }
8609 } else {
8610 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8611 return -1;
8612 }
8613
8614 return 0;
8615 }
8616
8617 static int test_opcode_table (opc_handler_t **table, int len)
8618 {
8619 int i, count, tmp;
8620
8621 for (i = 0, count = 0; i < len; i++) {
8622 /* Consistency fixup */
8623 if (table[i] == NULL)
8624 table[i] = &invalid_handler;
8625 if (table[i] != &invalid_handler) {
8626 if (is_indirect_opcode(table[i])) {
8627 tmp = test_opcode_table(ind_table(table[i]), 0x20);
8628 if (tmp == 0) {
8629 free(table[i]);
8630 table[i] = &invalid_handler;
8631 } else {
8632 count++;
8633 }
8634 } else {
8635 count++;
8636 }
8637 }
8638 }
8639
8640 return count;
8641 }
8642
8643 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8644 {
8645 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
8646 printf("*** WARNING: no opcode defined !\n");
8647 }
8648
8649 /*****************************************************************************/
8650 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8651 {
8652 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8653 CPUPPCState *env = &cpu->env;
8654 opcode_t *opc;
8655
8656 fill_new_table(env->opcodes, 0x40);
8657 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8658 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8659 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8660 if (register_insn(env->opcodes, opc) < 0) {
8661 error_setg(errp, "ERROR initializing PowerPC instruction "
8662 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8663 opc->opc3);
8664 return;
8665 }
8666 }
8667 }
8668 fix_opcode_tables(env->opcodes);
8669 fflush(stdout);
8670 fflush(stderr);
8671 }
8672
8673 #if defined(PPC_DUMP_CPU)
8674 static void dump_ppc_insns (CPUPPCState *env)
8675 {
8676 opc_handler_t **table, *handler;
8677 const char *p, *q;
8678 uint8_t opc1, opc2, opc3;
8679
8680 printf("Instructions set:\n");
8681 /* opc1 is 6 bits long */
8682 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
8683 table = env->opcodes;
8684 handler = table[opc1];
8685 if (is_indirect_opcode(handler)) {
8686 /* opc2 is 5 bits long */
8687 for (opc2 = 0; opc2 < 0x20; opc2++) {
8688 table = env->opcodes;
8689 handler = env->opcodes[opc1];
8690 table = ind_table(handler);
8691 handler = table[opc2];
8692 if (is_indirect_opcode(handler)) {
8693 table = ind_table(handler);
8694 /* opc3 is 5 bits long */
8695 for (opc3 = 0; opc3 < 0x20; opc3++) {
8696 handler = table[opc3];
8697 if (handler->handler != &gen_invalid) {
8698 /* Special hack to properly dump SPE insns */
8699 p = strchr(handler->oname, '_');
8700 if (p == NULL) {
8701 printf("INSN: %02x %02x %02x (%02d %04d) : "
8702 "%s\n",
8703 opc1, opc2, opc3, opc1,
8704 (opc3 << 5) | opc2,
8705 handler->oname);
8706 } else {
8707 q = "speundef";
8708 if ((p - handler->oname) != strlen(q) ||
8709 memcmp(handler->oname, q, strlen(q)) != 0) {
8710 /* First instruction */
8711 printf("INSN: %02x %02x %02x (%02d %04d) : "
8712 "%.*s\n",
8713 opc1, opc2 << 1, opc3, opc1,
8714 (opc3 << 6) | (opc2 << 1),
8715 (int)(p - handler->oname),
8716 handler->oname);
8717 }
8718 if (strcmp(p + 1, q) != 0) {
8719 /* Second instruction */
8720 printf("INSN: %02x %02x %02x (%02d %04d) : "
8721 "%s\n",
8722 opc1, (opc2 << 1) | 1, opc3, opc1,
8723 (opc3 << 6) | (opc2 << 1) | 1,
8724 p + 1);
8725 }
8726 }
8727 }
8728 }
8729 } else {
8730 if (handler->handler != &gen_invalid) {
8731 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8732 opc1, opc2, opc1, opc2, handler->oname);
8733 }
8734 }
8735 }
8736 } else {
8737 if (handler->handler != &gen_invalid) {
8738 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8739 opc1, opc1, handler->oname);
8740 }
8741 }
8742 }
8743 }
8744 #endif
8745
8746 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8747 {
8748 if (n < 32) {
8749 stfq_p(mem_buf, env->fpr[n]);
8750 return 8;
8751 }
8752 if (n == 32) {
8753 stl_p(mem_buf, env->fpscr);
8754 return 4;
8755 }
8756 return 0;
8757 }
8758
8759 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8760 {
8761 if (n < 32) {
8762 env->fpr[n] = ldfq_p(mem_buf);
8763 return 8;
8764 }
8765 if (n == 32) {
8766 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
8767 return 4;
8768 }
8769 return 0;
8770 }
8771
8772 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8773 {
8774 if (n < 32) {
8775 #ifdef HOST_WORDS_BIGENDIAN
8776 stq_p(mem_buf, env->avr[n].u64[0]);
8777 stq_p(mem_buf+8, env->avr[n].u64[1]);
8778 #else
8779 stq_p(mem_buf, env->avr[n].u64[1]);
8780 stq_p(mem_buf+8, env->avr[n].u64[0]);
8781 #endif
8782 return 16;
8783 }
8784 if (n == 32) {
8785 stl_p(mem_buf, env->vscr);
8786 return 4;
8787 }
8788 if (n == 33) {
8789 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
8790 return 4;
8791 }
8792 return 0;
8793 }
8794
8795 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8796 {
8797 if (n < 32) {
8798 #ifdef HOST_WORDS_BIGENDIAN
8799 env->avr[n].u64[0] = ldq_p(mem_buf);
8800 env->avr[n].u64[1] = ldq_p(mem_buf+8);
8801 #else
8802 env->avr[n].u64[1] = ldq_p(mem_buf);
8803 env->avr[n].u64[0] = ldq_p(mem_buf+8);
8804 #endif
8805 return 16;
8806 }
8807 if (n == 32) {
8808 env->vscr = ldl_p(mem_buf);
8809 return 4;
8810 }
8811 if (n == 33) {
8812 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
8813 return 4;
8814 }
8815 return 0;
8816 }
8817
8818 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8819 {
8820 if (n < 32) {
8821 #if defined(TARGET_PPC64)
8822 stl_p(mem_buf, env->gpr[n] >> 32);
8823 #else
8824 stl_p(mem_buf, env->gprh[n]);
8825 #endif
8826 return 4;
8827 }
8828 if (n == 32) {
8829 stq_p(mem_buf, env->spe_acc);
8830 return 8;
8831 }
8832 if (n == 33) {
8833 stl_p(mem_buf, env->spe_fscr);
8834 return 4;
8835 }
8836 return 0;
8837 }
8838
8839 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8840 {
8841 if (n < 32) {
8842 #if defined(TARGET_PPC64)
8843 target_ulong lo = (uint32_t)env->gpr[n];
8844 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
8845 env->gpr[n] = lo | hi;
8846 #else
8847 env->gprh[n] = ldl_p(mem_buf);
8848 #endif
8849 return 4;
8850 }
8851 if (n == 32) {
8852 env->spe_acc = ldq_p(mem_buf);
8853 return 8;
8854 }
8855 if (n == 33) {
8856 env->spe_fscr = ldl_p(mem_buf);
8857 return 4;
8858 }
8859 return 0;
8860 }
8861
8862 static int ppc_fixup_cpu(PowerPCCPU *cpu)
8863 {
8864 CPUPPCState *env = &cpu->env;
8865
8866 /* TCG doesn't (yet) emulate some groups of instructions that
8867 * are implemented on some otherwise supported CPUs (e.g. VSX
8868 * and decimal floating point instructions on POWER7). We
8869 * remove unsupported instruction groups from the cpu state's
8870 * instruction masks and hope the guest can cope. For at
8871 * least the pseries machine, the unavailability of these
8872 * instructions can be advertised to the guest via the device
8873 * tree. */
8874 if ((env->insns_flags & ~PPC_TCG_INSNS)
8875 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
8876 fprintf(stderr, "Warning: Disabling some instructions which are not "
8877 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
8878 env->insns_flags & ~PPC_TCG_INSNS,
8879 env->insns_flags2 & ~PPC_TCG_INSNS2);
8880 }
8881 env->insns_flags &= PPC_TCG_INSNS;
8882 env->insns_flags2 &= PPC_TCG_INSNS2;
8883 return 0;
8884 }
8885
8886 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
8887 {
8888 #ifdef TARGET_PPCEMB
8889 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
8890 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
8891 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
8892 #else
8893 return true;
8894 #endif
8895 }
8896
8897 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
8898 {
8899 CPUState *cs = CPU(dev);
8900 PowerPCCPU *cpu = POWERPC_CPU(dev);
8901 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8902 Error *local_err = NULL;
8903 #if !defined(CONFIG_USER_ONLY)
8904 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
8905 #endif
8906
8907 #if !defined(CONFIG_USER_ONLY)
8908 if (smp_threads > max_smt) {
8909 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
8910 max_smt, kvm_enabled() ? "KVM" : "TCG");
8911 return;
8912 }
8913 if (!is_power_of_2(smp_threads)) {
8914 error_setg(errp, "Cannot support %d threads on PPC with %s, "
8915 "threads count must be a power of 2.",
8916 smp_threads, kvm_enabled() ? "KVM" : "TCG");
8917 return;
8918 }
8919
8920 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
8921 + (cs->cpu_index % smp_threads);
8922 #endif
8923
8924 if (tcg_enabled()) {
8925 if (ppc_fixup_cpu(cpu) != 0) {
8926 error_setg(errp, "Unable to emulate selected CPU with TCG");
8927 return;
8928 }
8929 }
8930
8931 #if defined(TARGET_PPCEMB)
8932 if (!ppc_cpu_is_valid(pcc)) {
8933 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
8934 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
8935 "or choose another CPU model.");
8936 return;
8937 }
8938 #endif
8939
8940 create_ppc_opcodes(cpu, &local_err);
8941 if (local_err != NULL) {
8942 error_propagate(errp, local_err);
8943 return;
8944 }
8945 init_ppc_proc(cpu);
8946
8947 if (pcc->insns_flags & PPC_FLOAT) {
8948 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
8949 33, "power-fpu.xml", 0);
8950 }
8951 if (pcc->insns_flags & PPC_ALTIVEC) {
8952 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
8953 34, "power-altivec.xml", 0);
8954 }
8955 if (pcc->insns_flags & PPC_SPE) {
8956 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
8957 34, "power-spe.xml", 0);
8958 }
8959
8960 qemu_init_vcpu(cs);
8961
8962 pcc->parent_realize(dev, errp);
8963
8964 #if defined(PPC_DUMP_CPU)
8965 {
8966 CPUPPCState *env = &cpu->env;
8967 const char *mmu_model, *excp_model, *bus_model;
8968 switch (env->mmu_model) {
8969 case POWERPC_MMU_32B:
8970 mmu_model = "PowerPC 32";
8971 break;
8972 case POWERPC_MMU_SOFT_6xx:
8973 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8974 break;
8975 case POWERPC_MMU_SOFT_74xx:
8976 mmu_model = "PowerPC 74xx with software driven TLBs";
8977 break;
8978 case POWERPC_MMU_SOFT_4xx:
8979 mmu_model = "PowerPC 4xx with software driven TLBs";
8980 break;
8981 case POWERPC_MMU_SOFT_4xx_Z:
8982 mmu_model = "PowerPC 4xx with software driven TLBs "
8983 "and zones protections";
8984 break;
8985 case POWERPC_MMU_REAL:
8986 mmu_model = "PowerPC real mode only";
8987 break;
8988 case POWERPC_MMU_MPC8xx:
8989 mmu_model = "PowerPC MPC8xx";
8990 break;
8991 case POWERPC_MMU_BOOKE:
8992 mmu_model = "PowerPC BookE";
8993 break;
8994 case POWERPC_MMU_BOOKE206:
8995 mmu_model = "PowerPC BookE 2.06";
8996 break;
8997 case POWERPC_MMU_601:
8998 mmu_model = "PowerPC 601";
8999 break;
9000 #if defined (TARGET_PPC64)
9001 case POWERPC_MMU_64B:
9002 mmu_model = "PowerPC 64";
9003 break;
9004 #endif
9005 default:
9006 mmu_model = "Unknown or invalid";
9007 break;
9008 }
9009 switch (env->excp_model) {
9010 case POWERPC_EXCP_STD:
9011 excp_model = "PowerPC";
9012 break;
9013 case POWERPC_EXCP_40x:
9014 excp_model = "PowerPC 40x";
9015 break;
9016 case POWERPC_EXCP_601:
9017 excp_model = "PowerPC 601";
9018 break;
9019 case POWERPC_EXCP_602:
9020 excp_model = "PowerPC 602";
9021 break;
9022 case POWERPC_EXCP_603:
9023 excp_model = "PowerPC 603";
9024 break;
9025 case POWERPC_EXCP_603E:
9026 excp_model = "PowerPC 603e";
9027 break;
9028 case POWERPC_EXCP_604:
9029 excp_model = "PowerPC 604";
9030 break;
9031 case POWERPC_EXCP_7x0:
9032 excp_model = "PowerPC 740/750";
9033 break;
9034 case POWERPC_EXCP_7x5:
9035 excp_model = "PowerPC 745/755";
9036 break;
9037 case POWERPC_EXCP_74xx:
9038 excp_model = "PowerPC 74xx";
9039 break;
9040 case POWERPC_EXCP_BOOKE:
9041 excp_model = "PowerPC BookE";
9042 break;
9043 #if defined (TARGET_PPC64)
9044 case POWERPC_EXCP_970:
9045 excp_model = "PowerPC 970";
9046 break;
9047 #endif
9048 default:
9049 excp_model = "Unknown or invalid";
9050 break;
9051 }
9052 switch (env->bus_model) {
9053 case PPC_FLAGS_INPUT_6xx:
9054 bus_model = "PowerPC 6xx";
9055 break;
9056 case PPC_FLAGS_INPUT_BookE:
9057 bus_model = "PowerPC BookE";
9058 break;
9059 case PPC_FLAGS_INPUT_405:
9060 bus_model = "PowerPC 405";
9061 break;
9062 case PPC_FLAGS_INPUT_401:
9063 bus_model = "PowerPC 401/403";
9064 break;
9065 case PPC_FLAGS_INPUT_RCPU:
9066 bus_model = "RCPU / MPC8xx";
9067 break;
9068 #if defined (TARGET_PPC64)
9069 case PPC_FLAGS_INPUT_970:
9070 bus_model = "PowerPC 970";
9071 break;
9072 #endif
9073 default:
9074 bus_model = "Unknown or invalid";
9075 break;
9076 }
9077 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9078 " MMU model : %s\n",
9079 object_class_get_name(OBJECT_CLASS(pcc)),
9080 pcc->pvr, pcc->msr_mask, mmu_model);
9081 #if !defined(CONFIG_USER_ONLY)
9082 if (env->tlb.tlb6) {
9083 printf(" %d %s TLB in %d ways\n",
9084 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9085 env->nb_ways);
9086 }
9087 #endif
9088 printf(" Exceptions model : %s\n"
9089 " Bus model : %s\n",
9090 excp_model, bus_model);
9091 printf(" MSR features :\n");
9092 if (env->flags & POWERPC_FLAG_SPE)
9093 printf(" signal processing engine enable"
9094 "\n");
9095 else if (env->flags & POWERPC_FLAG_VRE)
9096 printf(" vector processor enable\n");
9097 if (env->flags & POWERPC_FLAG_TGPR)
9098 printf(" temporary GPRs\n");
9099 else if (env->flags & POWERPC_FLAG_CE)
9100 printf(" critical input enable\n");
9101 if (env->flags & POWERPC_FLAG_SE)
9102 printf(" single-step trace mode\n");
9103 else if (env->flags & POWERPC_FLAG_DWE)
9104 printf(" debug wait enable\n");
9105 else if (env->flags & POWERPC_FLAG_UBLE)
9106 printf(" user BTB lock enable\n");
9107 if (env->flags & POWERPC_FLAG_BE)
9108 printf(" branch-step trace mode\n");
9109 else if (env->flags & POWERPC_FLAG_DE)
9110 printf(" debug interrupt enable\n");
9111 if (env->flags & POWERPC_FLAG_PX)
9112 printf(" inclusive protection\n");
9113 else if (env->flags & POWERPC_FLAG_PMM)
9114 printf(" performance monitor mark\n");
9115 if (env->flags == POWERPC_FLAG_NONE)
9116 printf(" none\n");
9117 printf(" Time-base/decrementer clock source: %s\n",
9118 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9119 dump_ppc_insns(env);
9120 dump_ppc_sprs(env);
9121 fflush(stdout);
9122 }
9123 #endif
9124 }
9125
9126 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
9127 {
9128 PowerPCCPU *cpu = POWERPC_CPU(dev);
9129 CPUPPCState *env = &cpu->env;
9130 int i;
9131
9132 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
9133 if (env->opcodes[i] != &invalid_handler) {
9134 g_free(env->opcodes[i]);
9135 }
9136 }
9137 }
9138
9139 int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
9140 {
9141 int ret = smp_threads;
9142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9143
9144 switch (cpu->cpu_version) {
9145 case CPU_POWERPC_LOGICAL_2_05:
9146 ret = 2;
9147 break;
9148 case CPU_POWERPC_LOGICAL_2_06:
9149 ret = 4;
9150 break;
9151 case CPU_POWERPC_LOGICAL_2_07:
9152 ret = 8;
9153 break;
9154 default:
9155 if (pcc->pcr_mask & PCR_COMPAT_2_06) {
9156 ret = 4;
9157 } else if (pcc->pcr_mask & PCR_COMPAT_2_05) {
9158 ret = 2;
9159 }
9160 break;
9161 }
9162
9163 return MIN(ret, smp_threads);
9164 }
9165
9166 int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version)
9167 {
9168 int ret = 0;
9169 CPUPPCState *env = &cpu->env;
9170
9171 cpu->cpu_version = cpu_version;
9172
9173 switch (cpu_version) {
9174 case CPU_POWERPC_LOGICAL_2_05:
9175 env->spr[SPR_PCR] = PCR_COMPAT_2_05;
9176 break;
9177 case CPU_POWERPC_LOGICAL_2_06:
9178 env->spr[SPR_PCR] = PCR_COMPAT_2_06;
9179 break;
9180 case CPU_POWERPC_LOGICAL_2_06_PLUS:
9181 env->spr[SPR_PCR] = PCR_COMPAT_2_06;
9182 break;
9183 default:
9184 env->spr[SPR_PCR] = 0;
9185 break;
9186 }
9187
9188 if (kvm_enabled() && kvmppc_set_compat(cpu, cpu->max_compat) < 0) {
9189 error_report("Unable to set compatibility mode in KVM");
9190 ret = -1;
9191 }
9192
9193 return ret;
9194 }
9195
9196 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
9197 {
9198 ObjectClass *oc = (ObjectClass *)a;
9199 uint32_t pvr = *(uint32_t *)b;
9200 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9201
9202 /* -cpu host does a PVR lookup during construction */
9203 if (unlikely(strcmp(object_class_get_name(oc),
9204 TYPE_HOST_POWERPC_CPU) == 0)) {
9205 return -1;
9206 }
9207
9208 if (!ppc_cpu_is_valid(pcc)) {
9209 return -1;
9210 }
9211
9212 return pcc->pvr == pvr ? 0 : -1;
9213 }
9214
9215 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
9216 {
9217 GSList *list, *item;
9218 PowerPCCPUClass *pcc = NULL;
9219
9220 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9221 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
9222 if (item != NULL) {
9223 pcc = POWERPC_CPU_CLASS(item->data);
9224 }
9225 g_slist_free(list);
9226
9227 return pcc;
9228 }
9229
9230 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
9231 {
9232 ObjectClass *oc = (ObjectClass *)a;
9233 uint32_t pvr = *(uint32_t *)b;
9234 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9235 gint ret;
9236
9237 /* -cpu host does a PVR lookup during construction */
9238 if (unlikely(strcmp(object_class_get_name(oc),
9239 TYPE_HOST_POWERPC_CPU) == 0)) {
9240 return -1;
9241 }
9242
9243 if (!ppc_cpu_is_valid(pcc)) {
9244 return -1;
9245 }
9246
9247 ret = (((pcc->pvr & pcc->pvr_mask) == (pvr & pcc->pvr_mask)) ? 0 : -1);
9248
9249 return ret;
9250 }
9251
9252 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
9253 {
9254 GSList *list, *item;
9255 PowerPCCPUClass *pcc = NULL;
9256
9257 list = object_class_get_list(TYPE_POWERPC_CPU, true);
9258 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
9259 if (item != NULL) {
9260 pcc = POWERPC_CPU_CLASS(item->data);
9261 }
9262 g_slist_free(list);
9263
9264 return pcc;
9265 }
9266
9267 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
9268 {
9269 ObjectClass *oc = (ObjectClass *)a;
9270 const char *name = b;
9271 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9272
9273 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
9274 ppc_cpu_is_valid(pcc) &&
9275 strcmp(object_class_get_name(oc) + strlen(name),
9276 "-" TYPE_POWERPC_CPU) == 0) {
9277 return 0;
9278 }
9279 return -1;
9280 }
9281
9282 #include <ctype.h>
9283
9284 static ObjectClass *ppc_cpu_class_by_name(const char *name);
9285
9286 static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
9287 {
9288 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
9289
9290 /* Cache target class lookups in the alias table */
9291 if (!alias->oc) {
9292 alias->oc = ppc_cpu_class_by_name(alias->model);
9293 if (!alias->oc) {
9294 /* Fast check for non-existing aliases */
9295 alias->oc = invalid_class;
9296 }
9297 }
9298
9299 if (alias->oc == invalid_class) {
9300 return NULL;
9301 } else {
9302 return alias->oc;
9303 }
9304 }
9305
9306 static ObjectClass *ppc_cpu_class_by_name(const char *name)
9307 {
9308 GSList *list, *item;
9309 ObjectClass *ret = NULL;
9310 const char *p;
9311 int i, len;
9312
9313 /* Check if the given name is a PVR */
9314 len = strlen(name);
9315 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9316 p = name + 2;
9317 goto check_pvr;
9318 } else if (len == 8) {
9319 p = name;
9320 check_pvr:
9321 for (i = 0; i < 8; i++) {
9322 if (!qemu_isxdigit(*p++))
9323 break;
9324 }
9325 if (i == 8) {
9326 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
9327 return ret;
9328 }
9329 }
9330
9331 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9332 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
9333 if (item != NULL) {
9334 ret = OBJECT_CLASS(item->data);
9335 }
9336 g_slist_free(list);
9337
9338 if (ret) {
9339 return ret;
9340 }
9341
9342 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9343 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
9344 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
9345 }
9346 }
9347
9348 return NULL;
9349 }
9350
9351 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
9352 {
9353 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
9354 }
9355
9356 /* Sort by PVR, ordering special case "host" last. */
9357 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
9358 {
9359 ObjectClass *oc_a = (ObjectClass *)a;
9360 ObjectClass *oc_b = (ObjectClass *)b;
9361 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
9362 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
9363 const char *name_a = object_class_get_name(oc_a);
9364 const char *name_b = object_class_get_name(oc_b);
9365
9366 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
9367 return 1;
9368 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
9369 return -1;
9370 } else {
9371 /* Avoid an integer overflow during subtraction */
9372 if (pcc_a->pvr < pcc_b->pvr) {
9373 return -1;
9374 } else if (pcc_a->pvr > pcc_b->pvr) {
9375 return 1;
9376 } else {
9377 return 0;
9378 }
9379 }
9380 }
9381
9382 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
9383 {
9384 ObjectClass *oc = data;
9385 CPUListState *s = user_data;
9386 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9387 const char *typename = object_class_get_name(oc);
9388 char *name;
9389 int i;
9390
9391 if (!ppc_cpu_is_valid(pcc)) {
9392 return;
9393 }
9394 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
9395 return;
9396 }
9397
9398 name = g_strndup(typename,
9399 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9400 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
9401 name, pcc->pvr);
9402 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9403 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9404 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
9405
9406 if (alias_oc != oc) {
9407 continue;
9408 }
9409 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
9410 alias->alias, name);
9411 }
9412 g_free(name);
9413 }
9414
9415 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
9416 {
9417 CPUListState s = {
9418 .file = f,
9419 .cpu_fprintf = cpu_fprintf,
9420 };
9421 GSList *list;
9422
9423 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9424 list = g_slist_sort(list, ppc_cpu_list_compare);
9425 g_slist_foreach(list, ppc_cpu_list_entry, &s);
9426 g_slist_free(list);
9427
9428 #ifdef CONFIG_KVM
9429 cpu_fprintf(f, "\n");
9430 cpu_fprintf(f, "PowerPC %-16s\n", "host");
9431 #endif
9432 }
9433
9434 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9435 {
9436 ObjectClass *oc = data;
9437 CpuDefinitionInfoList **first = user_data;
9438 const char *typename;
9439 CpuDefinitionInfoList *entry;
9440 CpuDefinitionInfo *info;
9441 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9442
9443 if (!ppc_cpu_is_valid(pcc)) {
9444 return;
9445 }
9446
9447 typename = object_class_get_name(oc);
9448 info = g_malloc0(sizeof(*info));
9449 info->name = g_strndup(typename,
9450 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9451
9452 entry = g_malloc0(sizeof(*entry));
9453 entry->value = info;
9454 entry->next = *first;
9455 *first = entry;
9456 }
9457
9458 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
9459 {
9460 CpuDefinitionInfoList *cpu_list = NULL;
9461 GSList *list;
9462 int i;
9463
9464 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9465 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9466 g_slist_free(list);
9467
9468 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9469 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9470 ObjectClass *oc;
9471 CpuDefinitionInfoList *entry;
9472 CpuDefinitionInfo *info;
9473
9474 oc = ppc_cpu_class_by_alias(alias);
9475 if (oc == NULL) {
9476 continue;
9477 }
9478
9479 info = g_malloc0(sizeof(*info));
9480 info->name = g_strdup(alias->alias);
9481
9482 entry = g_malloc0(sizeof(*entry));
9483 entry->value = info;
9484 entry->next = cpu_list;
9485 cpu_list = entry;
9486 }
9487
9488 return cpu_list;
9489 }
9490
9491 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9492 {
9493 PowerPCCPU *cpu = POWERPC_CPU(cs);
9494
9495 cpu->env.nip = value;
9496 }
9497
9498 static bool ppc_cpu_has_work(CPUState *cs)
9499 {
9500 PowerPCCPU *cpu = POWERPC_CPU(cs);
9501 CPUPPCState *env = &cpu->env;
9502
9503 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9504 }
9505
9506 /* CPUClass::reset() */
9507 static void ppc_cpu_reset(CPUState *s)
9508 {
9509 PowerPCCPU *cpu = POWERPC_CPU(s);
9510 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9511 CPUPPCState *env = &cpu->env;
9512 target_ulong msr;
9513 int i;
9514
9515 pcc->parent_reset(s);
9516
9517 msr = (target_ulong)0;
9518 if (0) {
9519 /* XXX: find a suitable condition to enable the hypervisor mode */
9520 msr |= (target_ulong)MSR_HVB;
9521 }
9522 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9523 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9524 msr |= (target_ulong)1 << MSR_EP;
9525 #if defined(DO_SINGLE_STEP) && 0
9526 /* Single step trace mode */
9527 msr |= (target_ulong)1 << MSR_SE;
9528 msr |= (target_ulong)1 << MSR_BE;
9529 #endif
9530 #if defined(CONFIG_USER_ONLY)
9531 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9532 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9533 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
9534 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9535 msr |= (target_ulong)1 << MSR_PR;
9536 #if defined(TARGET_PPC64)
9537 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
9538 #endif
9539 #if !defined(TARGET_WORDS_BIGENDIAN)
9540 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
9541 #endif
9542 #endif
9543
9544 #if defined(TARGET_PPC64)
9545 if (env->mmu_model & POWERPC_MMU_64) {
9546 env->msr |= (1ULL << MSR_SF);
9547 }
9548 #endif
9549
9550 hreg_store_msr(env, msr, 1);
9551
9552 #if !defined(CONFIG_USER_ONLY)
9553 env->nip = env->hreset_vector | env->excp_prefix;
9554 if (env->mmu_model != POWERPC_MMU_REAL) {
9555 ppc_tlb_invalidate_all(env);
9556 }
9557 #endif
9558
9559 hreg_compute_hflags(env);
9560 env->reserve_addr = (target_ulong)-1ULL;
9561 /* Be sure no exception or interrupt is pending */
9562 env->pending_interrupts = 0;
9563 s->exception_index = POWERPC_EXCP_NONE;
9564 env->error_code = 0;
9565
9566 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
9567 env->vpa_addr = 0;
9568 env->slb_shadow_addr = 0;
9569 env->slb_shadow_size = 0;
9570 env->dtl_addr = 0;
9571 env->dtl_size = 0;
9572 #endif /* TARGET_PPC64 */
9573
9574 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9575 ppc_spr_t *spr = &env->spr_cb[i];
9576
9577 if (!spr->name) {
9578 continue;
9579 }
9580 env->spr[i] = spr->default_value;
9581 }
9582
9583 /* Flush all TLBs */
9584 tlb_flush(s, 1);
9585 }
9586
9587 static void ppc_cpu_initfn(Object *obj)
9588 {
9589 CPUState *cs = CPU(obj);
9590 PowerPCCPU *cpu = POWERPC_CPU(obj);
9591 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9592 CPUPPCState *env = &cpu->env;
9593
9594 cs->env_ptr = env;
9595 cpu_exec_init(env);
9596 cpu->cpu_dt_id = cs->cpu_index;
9597
9598 env->msr_mask = pcc->msr_mask;
9599 env->mmu_model = pcc->mmu_model;
9600 env->excp_model = pcc->excp_model;
9601 env->bus_model = pcc->bus_model;
9602 env->insns_flags = pcc->insns_flags;
9603 env->insns_flags2 = pcc->insns_flags2;
9604 env->flags = pcc->flags;
9605 env->bfd_mach = pcc->bfd_mach;
9606 env->check_pow = pcc->check_pow;
9607
9608 #if defined(TARGET_PPC64)
9609 if (pcc->sps) {
9610 env->sps = *pcc->sps;
9611 } else if (env->mmu_model & POWERPC_MMU_64) {
9612 /* Use default sets of page sizes */
9613 static const struct ppc_segment_page_sizes defsps = {
9614 .sps = {
9615 { .page_shift = 12, /* 4K */
9616 .slb_enc = 0,
9617 .enc = { { .page_shift = 12, .pte_enc = 0 } }
9618 },
9619 { .page_shift = 24, /* 16M */
9620 .slb_enc = 0x100,
9621 .enc = { { .page_shift = 24, .pte_enc = 0 } }
9622 },
9623 },
9624 };
9625 env->sps = defsps;
9626 }
9627 #endif /* defined(TARGET_PPC64) */
9628
9629 if (tcg_enabled()) {
9630 ppc_translate_init();
9631 }
9632 }
9633
9634 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
9635 {
9636 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9637 CPUClass *cc = CPU_CLASS(oc);
9638 DeviceClass *dc = DEVICE_CLASS(oc);
9639
9640 pcc->parent_realize = dc->realize;
9641 pcc->pvr = CPU_POWERPC_DEFAULT_MASK;
9642 pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK;
9643 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
9644 dc->realize = ppc_cpu_realizefn;
9645 dc->unrealize = ppc_cpu_unrealizefn;
9646
9647 pcc->parent_reset = cc->reset;
9648 cc->reset = ppc_cpu_reset;
9649
9650 cc->class_by_name = ppc_cpu_class_by_name;
9651 cc->has_work = ppc_cpu_has_work;
9652 cc->do_interrupt = ppc_cpu_do_interrupt;
9653 cc->dump_state = ppc_cpu_dump_state;
9654 cc->dump_statistics = ppc_cpu_dump_statistics;
9655 cc->set_pc = ppc_cpu_set_pc;
9656 cc->gdb_read_register = ppc_cpu_gdb_read_register;
9657 cc->gdb_write_register = ppc_cpu_gdb_write_register;
9658 #ifdef CONFIG_USER_ONLY
9659 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
9660 #else
9661 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
9662 cc->vmsd = &vmstate_ppc_cpu;
9663 #if defined(TARGET_PPC64)
9664 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
9665 cc->write_elf64_qemunote = ppc64_cpu_write_elf64_qemunote;
9666 #endif
9667 #endif
9668
9669 cc->gdb_num_core_regs = 71;
9670 #if defined(TARGET_PPC64)
9671 cc->gdb_core_xml_file = "power64-core.xml";
9672 #else
9673 cc->gdb_core_xml_file = "power-core.xml";
9674 #endif
9675
9676 dc->fw_name = "PowerPC,UNKNOWN";
9677 }
9678
9679 static const TypeInfo ppc_cpu_type_info = {
9680 .name = TYPE_POWERPC_CPU,
9681 .parent = TYPE_CPU,
9682 .instance_size = sizeof(PowerPCCPU),
9683 .instance_init = ppc_cpu_initfn,
9684 .abstract = true,
9685 .class_size = sizeof(PowerPCCPUClass),
9686 .class_init = ppc_cpu_class_init,
9687 };
9688
9689 static void ppc_cpu_register_types(void)
9690 {
9691 type_register_static(&ppc_cpu_type_info);
9692 }
9693
9694 type_init(ppc_cpu_register_types)
CRIS target port of Qemu