hw/arm/virt-acpi-build.c

   1 /* Support for generating ACPI tables and passing them to Guests
   2  *
   3  * ARM virt ACPI generation
   4  *
   5  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
   6  * Copyright (C) 2006 Fabrice Bellard
   7  * Copyright (C) 2013 Red Hat Inc
   8  *
   9  * Author: Michael S. Tsirkin <mst@redhat.com>
  10  *
  11  * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
  12  *
  13  * Author: Shannon Zhao <zhaoshenglong@huawei.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24
  25  * You should have received a copy of the GNU General Public License along
  26  * with this program; if not, see <http://www.gnu.org/licenses/>.
  27  */
  28
  29 #include "qemu-common.h"
  30 #include "hw/arm/virt-acpi-build.h"
  31 #include "qemu/bitmap.h"
  32 #include "trace.h"
  33 #include "qom/cpu.h"
  34 #include "target-arm/cpu.h"
  35 #include "hw/acpi/acpi-defs.h"
  36 #include "hw/acpi/acpi.h"
  37 #include "hw/nvram/fw_cfg.h"
  38 #include "hw/acpi/bios-linker-loader.h"
  39 #include "hw/loader.h"
  40 #include "hw/hw.h"
  41 #include "hw/acpi/aml-build.h"
  42 #include "hw/pci/pcie_host.h"
  43 #include "hw/pci/pci.h"
  44
  45 #define ARM_SPI_BASE 32
  46
  47 typedef struct VirtAcpiCpuInfo {
  48     DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
  49 } VirtAcpiCpuInfo;
  50
  51 static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
  52 {
  53     CPUState *cpu;
  54
  55     memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
  56     CPU_FOREACH(cpu) {
  57         set_bit(cpu->cpu_index, cpuinfo->found_cpus);
  58     }
  59 }
  60
  61 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
  62 {
  63     uint16_t i;
  64
  65     for (i = 0; i < smp_cpus; i++) {
  66         Aml *dev = aml_device("C%03x", i);
  67         aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
  68         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
  69         aml_append(scope, dev);
  70     }
  71 }
  72
  73 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
  74                                            int uart_irq)
  75 {
  76     Aml *dev = aml_device("COM0");
  77     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
  78     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
  79
  80     Aml *crs = aml_resource_template();
  81     aml_append(crs, aml_memory32_fixed(uart_memmap->base,
  82                                        uart_memmap->size, AML_READ_WRITE));
  83     aml_append(crs,
  84                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  85                              AML_EXCLUSIVE, uart_irq));
  86     aml_append(dev, aml_name_decl("_CRS", crs));
  87
  88     /* The _ADR entry is used to link this device to the UART described
  89      * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
  90      */
  91     aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
  92
  93     aml_append(scope, dev);
  94 }
  95
  96 static void acpi_dsdt_add_rtc(Aml *scope, const MemMapEntry *rtc_memmap,
  97                                           int rtc_irq)
  98 {
  99     Aml *dev = aml_device("RTC0");
 100     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
 101     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 102
 103     Aml *crs = aml_resource_template();
 104     aml_append(crs, aml_memory32_fixed(rtc_memmap->base,
 105                                        rtc_memmap->size, AML_READ_WRITE));
 106     aml_append(crs,
 107                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 108                              AML_EXCLUSIVE, rtc_irq));
 109     aml_append(dev, aml_name_decl("_CRS", crs));
 110     aml_append(scope, dev);
 111 }
 112
 113 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
 114 {
 115     Aml *dev, *crs;
 116     hwaddr base = flash_memmap->base;
 117     hwaddr size = flash_memmap->size;
 118
 119     dev = aml_device("FLS0");
 120     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 121     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 122
 123     crs = aml_resource_template();
 124     aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 125     aml_append(dev, aml_name_decl("_CRS", crs));
 126     aml_append(scope, dev);
 127
 128     dev = aml_device("FLS1");
 129     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 130     aml_append(dev, aml_name_decl("_UID", aml_int(1)));
 131     crs = aml_resource_template();
 132     aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
 133     aml_append(dev, aml_name_decl("_CRS", crs));
 134     aml_append(scope, dev);
 135 }
 136
 137 static void acpi_dsdt_add_virtio(Aml *scope,
 138                                  const MemMapEntry *virtio_mmio_memmap,
 139                                  int mmio_irq, int num)
 140 {
 141     hwaddr base = virtio_mmio_memmap->base;
 142     hwaddr size = virtio_mmio_memmap->size;
 143     int irq = mmio_irq;
 144     int i;
 145
 146     for (i = 0; i < num; i++) {
 147         Aml *dev = aml_device("VR%02u", i);
 148         aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
 149         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
 150
 151         Aml *crs = aml_resource_template();
 152         aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 153         aml_append(crs,
 154                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 155                                  AML_EXCLUSIVE, irq + i));
 156         aml_append(dev, aml_name_decl("_CRS", crs));
 157         aml_append(scope, dev);
 158         base += size;
 159     }
 160 }
 161
 162 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq)
 163 {
 164     Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
 165     int i, bus_no;
 166     hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
 167     hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
 168     hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
 169     hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
 170     hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
 171     hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
 172     int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
 173
 174     Aml *dev = aml_device("%s", "PCI0");
 175     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 176     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 177     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
 178     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
 179     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 180     aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
 181     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
 182
 183     /* Declare the PCI Routing Table. */
 184     Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
 185     for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
 186         for (i = 0; i < PCI_NUM_PINS; i++) {
 187             int gsi = (i + bus_no) % PCI_NUM_PINS;
 188             Aml *pkg = aml_package(4);
 189             aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
 190             aml_append(pkg, aml_int(i));
 191             aml_append(pkg, aml_name("GSI%d", gsi));
 192             aml_append(pkg, aml_int(0));
 193             aml_append(rt_pkg, pkg);
 194         }
 195     }
 196     aml_append(dev, aml_name_decl("_PRT", rt_pkg));
 197
 198     /* Create GSI link device */
 199     for (i = 0; i < PCI_NUM_PINS; i++) {
 200         Aml *dev_gsi = aml_device("GSI%d", i);
 201         aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
 202         aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
 203         crs = aml_resource_template();
 204         aml_append(crs,
 205                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 206                                  AML_EXCLUSIVE, irq + i));
 207         aml_append(dev_gsi, aml_name_decl("_PRS", crs));
 208         crs = aml_resource_template();
 209         aml_append(crs,
 210                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 211                                  AML_EXCLUSIVE, irq + i));
 212         aml_append(dev_gsi, aml_name_decl("_CRS", crs));
 213         method = aml_method("_SRS", 1);
 214         aml_append(dev_gsi, method);
 215         aml_append(dev, dev_gsi);
 216     }
 217
 218     method = aml_method("_CBA", 0);
 219     aml_append(method, aml_return(aml_int(base_ecam)));
 220     aml_append(dev, method);
 221
 222     method = aml_method("_CRS", 0);
 223     Aml *rbuf = aml_resource_template();
 224     aml_append(rbuf,
 225         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 226                             0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
 227                             nr_pcie_buses));
 228     aml_append(rbuf,
 229         aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 230                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
 231                          base_mmio + size_mmio - 1, 0x0000, size_mmio));
 232     aml_append(rbuf,
 233         aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 234                      AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
 235                      size_pio));
 236
 237     aml_append(method, aml_name_decl("RBUF", rbuf));
 238     aml_append(method, aml_return(rbuf));
 239     aml_append(dev, method);
 240
 241     /* Declare an _OSC (OS Control Handoff) method */
 242     aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
 243     aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
 244     method = aml_method("_OSC", 4);
 245     aml_append(method,
 246         aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
 247
 248     /* PCI Firmware Specification 3.0
 249      * 4.5.1. _OSC Interface for PCI Host Bridge Devices
 250      * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
 251      * identified by the Universal Unique IDentifier (UUID)
 252      * 33DB4D5B-1FF7-401C-9657-7441C03DD766
 253      */
 254     UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
 255     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 256     aml_append(ifctx,
 257         aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
 258     aml_append(ifctx,
 259         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
 260     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
 261     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
 262     aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
 263                                 aml_name("CTRL")));
 264
 265     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
 266     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
 267                                  aml_name("CDW1")));
 268     aml_append(ifctx, ifctx1);
 269
 270     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
 271     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
 272                                  aml_name("CDW1")));
 273     aml_append(ifctx, ifctx1);
 274
 275     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
 276     aml_append(ifctx, aml_return(aml_arg(3)));
 277     aml_append(method, ifctx);
 278
 279     elsectx = aml_else();
 280     aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
 281                                   aml_name("CDW1")));
 282     aml_append(elsectx, aml_return(aml_arg(3)));
 283     aml_append(method, elsectx);
 284     aml_append(dev, method);
 285
 286     method = aml_method("_DSM", 4);
 287
 288     /* PCI Firmware Specification 3.0
 289      * 4.6.1. _DSM for PCI Express Slot Information
 290      * The UUID in _DSM in this context is
 291      * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
 292      */
 293     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
 294     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 295     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
 296     uint8_t byte_list[1] = {1};
 297     buf = aml_buffer(1, byte_list);
 298     aml_append(ifctx1, aml_return(buf));
 299     aml_append(ifctx, ifctx1);
 300     aml_append(method, ifctx);
 301
 302     byte_list[0] = 0;
 303     buf = aml_buffer(1, byte_list);
 304     aml_append(method, aml_return(buf));
 305     aml_append(dev, method);
 306
 307     Aml *dev_rp0 = aml_device("%s", "RP0");
 308     aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
 309     aml_append(dev, dev_rp0);
 310     aml_append(scope, dev);
 311 }
 312
 313 /* RSDP */
 314 static GArray *
 315 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
 316 {
 317     AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
 318
 319     bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
 320                              true /* fseg memory */);
 321
 322     memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
 323     memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
 324     rsdp->length = cpu_to_le32(sizeof(*rsdp));
 325     rsdp->revision = 0x02;
 326
 327     /* Point to RSDT */
 328     rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
 329     /* Address to be filled by Guest linker */
 330     bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
 331                                    ACPI_BUILD_TABLE_FILE,
 332                                    rsdp_table, &rsdp->rsdt_physical_address,
 333                                    sizeof rsdp->rsdt_physical_address);
 334     rsdp->checksum = 0;
 335     /* Checksum to be filled by Guest linker */
 336     bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
 337                                     rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
 338
 339     return rsdp_table;
 340 }
 341
 342 static void
 343 build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
 344 {
 345     AcpiSerialPortConsoleRedirection *spcr;
 346     const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART];
 347     int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE;
 348
 349     spcr = acpi_data_push(table_data, sizeof(*spcr));
 350
 351     spcr->interface_type = 0x3;    /* ARM PL011 UART */
 352
 353     spcr->base_address.space_id = AML_SYSTEM_MEMORY;
 354     spcr->base_address.bit_width = 8;
 355     spcr->base_address.bit_offset = 0;
 356     spcr->base_address.access_width = 1;
 357     spcr->base_address.address = cpu_to_le64(uart_memmap->base);
 358
 359     spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
 360     spcr->gsi = cpu_to_le32(irq);  /* Global System Interrupt */
 361
 362     spcr->baud = 3;                /* Baud Rate: 3 = 9600 */
 363     spcr->parity = 0;              /* No Parity */
 364     spcr->stopbits = 1;            /* 1 Stop bit */
 365     spcr->flowctrl = (1 << 1);     /* Bit[1] = RTS/CTS hardware flow control */
 366     spcr->term_type = 0;           /* Terminal Type: 0 = VT100 */
 367
 368     spcr->pci_device_id = 0xffff;  /* PCI Device ID: not a PCI device */
 369     spcr->pci_vendor_id = 0xffff;  /* PCI Vendor ID: not a PCI device */
 370
 371     build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2);
 372 }
 373
 374 static void
 375 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
 376 {
 377     AcpiTableMcfg *mcfg;
 378     const MemMapEntry *memmap = guest_info->memmap;
 379     int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
 380
 381     mcfg = acpi_data_push(table_data, len);
 382     mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
 383
 384     /* Only a single allocation so no need to play with segments */
 385     mcfg->allocation[0].pci_segment = cpu_to_le16(0);
 386     mcfg->allocation[0].start_bus_number = 0;
 387     mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
 388                                           / PCIE_MMCFG_SIZE_MIN) - 1;
 389
 390     build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1);
 391 }
 392
 393 /* GTDT */
 394 static void
 395 build_gtdt(GArray *table_data, GArray *linker)
 396 {
 397     int gtdt_start = table_data->len;
 398     AcpiGenericTimerTable *gtdt;
 399
 400     gtdt = acpi_data_push(table_data, sizeof *gtdt);
 401     /* The interrupt values are the same with the device tree when adding 16 */
 402     gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16;
 403     gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
 404
 405     gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16;
 406     gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE;
 407
 408     gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16;
 409     gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
 410
 411     gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16;
 412     gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
 413
 414     build_header(linker, table_data,
 415                  (void *)(table_data->data + gtdt_start), "GTDT",
 416                  table_data->len - gtdt_start, 2);
 417 }
 418
 419 /* MADT */
 420 static void
 421 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
 422            VirtAcpiCpuInfo *cpuinfo)
 423 {
 424     int madt_start = table_data->len;
 425     const MemMapEntry *memmap = guest_info->memmap;
 426     const int *irqmap = guest_info->irqmap;
 427     AcpiMultipleApicTable *madt;
 428     AcpiMadtGenericDistributor *gicd;
 429     AcpiMadtGenericMsiFrame *gic_msi;
 430     int i;
 431
 432     madt = acpi_data_push(table_data, sizeof *madt);
 433
 434     for (i = 0; i < guest_info->smp_cpus; i++) {
 435         AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
 436                                                      sizeof *gicc);
 437         gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
 438         gicc->length = sizeof(*gicc);
 439         gicc->base_address = memmap[VIRT_GIC_CPU].base;
 440         gicc->cpu_interface_number = i;
 441         gicc->arm_mpidr = i;
 442         gicc->uid = i;
 443         if (test_bit(i, cpuinfo->found_cpus)) {
 444             gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
 445         }
 446     }
 447
 448     gicd = acpi_data_push(table_data, sizeof *gicd);
 449     gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
 450     gicd->length = sizeof(*gicd);
 451     gicd->base_address = memmap[VIRT_GIC_DIST].base;
 452
 453     gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
 454     gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
 455     gic_msi->length = sizeof(*gic_msi);
 456     gic_msi->gic_msi_frame_id = 0;
 457     gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
 458     gic_msi->flags = cpu_to_le32(1);
 459     gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
 460     gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
 461
 462     build_header(linker, table_data,
 463                  (void *)(table_data->data + madt_start), "APIC",
 464                  table_data->len - madt_start, 3);
 465 }
 466
 467 /* FADT */
 468 static void
 469 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
 470 {
 471     AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
 472
 473     /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
 474     fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
 475     fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
 476                                        (1 << ACPI_FADT_ARM_PSCI_USE_HVC));
 477
 478     /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
 479     fadt->minor_revision = 0x1;
 480
 481     fadt->dsdt = cpu_to_le32(dsdt);
 482     /* DSDT address to be filled by Guest linker */
 483     bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
 484                                    ACPI_BUILD_TABLE_FILE,
 485                                    table_data, &fadt->dsdt,
 486                                    sizeof fadt->dsdt);
 487
 488     build_header(linker, table_data,
 489                  (void *)fadt, "FACP", sizeof(*fadt), 5);
 490 }
 491
 492 /* DSDT */
 493 static void
 494 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
 495 {
 496     Aml *scope, *dsdt;
 497     const MemMapEntry *memmap = guest_info->memmap;
 498     const int *irqmap = guest_info->irqmap;
 499
 500     dsdt = init_aml_allocator();
 501     /* Reserve space for header */
 502     acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
 503
 504     scope = aml_scope("\\_SB");
 505     acpi_dsdt_add_cpus(scope, guest_info->smp_cpus);
 506     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
 507                        (irqmap[VIRT_UART] + ARM_SPI_BASE));
 508     acpi_dsdt_add_rtc(scope, &memmap[VIRT_RTC],
 509                       (irqmap[VIRT_RTC] + ARM_SPI_BASE));
 510     acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
 511     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
 512                     (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
 513     acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE));
 514
 515     aml_append(dsdt, scope);
 516
 517     /* copy AML table into ACPI tables blob and patch header there */
 518     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
 519     build_header(linker, table_data,
 520         (void *)(table_data->data + table_data->len - dsdt->buf->len),
 521         "DSDT", dsdt->buf->len, 2);
 522     free_aml_allocator();
 523 }
 524
 525 typedef
 526 struct AcpiBuildState {
 527     /* Copy of table in RAM (for patching). */
 528     MemoryRegion *table_mr;
 529     MemoryRegion *rsdp_mr;
 530     MemoryRegion *linker_mr;
 531     /* Is table patched? */
 532     bool patched;
 533     VirtGuestInfo *guest_info;
 534 } AcpiBuildState;
 535
 536 static
 537 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
 538 {
 539     GArray *table_offsets;
 540     unsigned dsdt, rsdt;
 541     VirtAcpiCpuInfo cpuinfo;
 542     GArray *tables_blob = tables->table_data;
 543
 544     virt_acpi_get_cpu_info(&cpuinfo);
 545
 546     table_offsets = g_array_new(false, true /* clear */,
 547                                         sizeof(uint32_t));
 548
 549     bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
 550                              64, false /* high memory */);
 551
 552     /*
 553      * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
 554      * RSDP
 555      * RSDT
 556      * FADT
 557      * GTDT
 558      * MADT
 559      * MCFG
 560      * DSDT
 561      */
 562
 563     /* DSDT is pointed to by FADT */
 564     dsdt = tables_blob->len;
 565     build_dsdt(tables_blob, tables->linker, guest_info);
 566
 567     /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
 568     acpi_add_table(table_offsets, tables_blob);
 569     build_fadt(tables_blob, tables->linker, dsdt);
 570
 571     acpi_add_table(table_offsets, tables_blob);
 572     build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
 573
 574     acpi_add_table(table_offsets, tables_blob);
 575     build_gtdt(tables_blob, tables->linker);
 576
 577     acpi_add_table(table_offsets, tables_blob);
 578     build_mcfg(tables_blob, tables->linker, guest_info);
 579
 580     acpi_add_table(table_offsets, tables_blob);
 581     build_spcr(tables_blob, tables->linker, guest_info);
 582
 583     /* RSDT is pointed to by RSDP */
 584     rsdt = tables_blob->len;
 585     build_rsdt(tables_blob, tables->linker, table_offsets);
 586
 587     /* RSDP is in FSEG memory, so allocate it separately */
 588     build_rsdp(tables->rsdp, tables->linker, rsdt);
 589
 590     /* Cleanup memory that's no longer used. */
 591     g_array_free(table_offsets, true);
 592 }
 593
 594 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
 595 {
 596     uint32_t size = acpi_data_len(data);
 597
 598     /* Make sure RAM size is correct - in case it got changed
 599      * e.g. by migration */
 600     memory_region_ram_resize(mr, size, &error_abort);
 601
 602     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
 603     memory_region_set_dirty(mr, 0, size);
 604 }
 605
 606 static void virt_acpi_build_update(void *build_opaque, uint32_t offset)
 607 {
 608     AcpiBuildState *build_state = build_opaque;
 609     AcpiBuildTables tables;
 610
 611     /* No state to update or already patched? Nothing to do. */
 612     if (!build_state || build_state->patched) {
 613         return;
 614     }
 615     build_state->patched = true;
 616
 617     acpi_build_tables_init(&tables);
 618
 619     virt_acpi_build(build_state->guest_info, &tables);
 620
 621     acpi_ram_update(build_state->table_mr, tables.table_data);
 622     acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
 623     acpi_ram_update(build_state->linker_mr, tables.linker);
 624
 625
 626     acpi_build_tables_cleanup(&tables, true);
 627 }
 628
 629 static void virt_acpi_build_reset(void *build_opaque)
 630 {
 631     AcpiBuildState *build_state = build_opaque;
 632     build_state->patched = false;
 633 }
 634
 635 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
 636                                        GArray *blob, const char *name,
 637                                        uint64_t max_size)
 638 {
 639     return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
 640                         name, virt_acpi_build_update, build_state);
 641 }
 642
 643 static const VMStateDescription vmstate_virt_acpi_build = {
 644     .name = "virt_acpi_build",
 645     .version_id = 1,
 646     .minimum_version_id = 1,
 647     .fields = (VMStateField[]) {
 648         VMSTATE_BOOL(patched, AcpiBuildState),
 649         VMSTATE_END_OF_LIST()
 650     },
 651 };
 652
 653 void virt_acpi_setup(VirtGuestInfo *guest_info)
 654 {
 655     AcpiBuildTables tables;
 656     AcpiBuildState *build_state;
 657
 658     if (!guest_info->fw_cfg) {
 659         trace_virt_acpi_setup();
 660         return;
 661     }
 662
 663     if (!acpi_enabled) {
 664         trace_virt_acpi_setup();
 665         return;
 666     }
 667
 668     build_state = g_malloc0(sizeof *build_state);
 669     build_state->guest_info = guest_info;
 670
 671     acpi_build_tables_init(&tables);
 672     virt_acpi_build(build_state->guest_info, &tables);
 673
 674     /* Now expose it all to Guest */
 675     build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
 676                                                ACPI_BUILD_TABLE_FILE,
 677                                                ACPI_BUILD_TABLE_MAX_SIZE);
 678     assert(build_state->table_mr != NULL);
 679
 680     build_state->linker_mr =
 681         acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
 682
 683     fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
 684                     tables.tcpalog->data, acpi_data_len(tables.tcpalog));
 685
 686     build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
 687                                               ACPI_BUILD_RSDP_FILE, 0);
 688
 689     qemu_register_reset(virt_acpi_build_reset, build_state);
 690     virt_acpi_build_reset(build_state);
 691     vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
 692
 693     /* Cleanup tables but don't free the memory: we track it
 694      * in build_state.
 695      */
 696     acpi_build_tables_cleanup(&tables, false);
 697 }