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acpi: extend aml_or() to accept target argument
[qemu/cris-port.git] / hw / i386 / acpi-build.c
blob374644f630ffcc9344198dc8c092a4fe4be1f540
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "hw/mem/nvdimm.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46
47 /* Supported chipsets: */
48 #include "hw/acpi/piix4.h"
49 #include "hw/acpi/pcihp.h"
50 #include "hw/i386/ich9.h"
51 #include "hw/pci/pci_bus.h"
52 #include "hw/pci-host/q35.h"
53 #include "hw/i386/intel_iommu.h"
54
55 #include "hw/i386/q35-acpi-dsdt.hex"
56 #include "hw/i386/acpi-dsdt.hex"
57
58 #include "hw/acpi/aml-build.h"
59
60 #include "qapi/qmp/qint.h"
61 #include "qom/qom-qobject.h"
62
63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
65 * a little bit, there should be plenty of free space since the DSDT
66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
67 */
68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
69 #define ACPI_BUILD_ALIGN_SIZE 0x1000
70
71 #define ACPI_BUILD_TABLE_SIZE 0x20000
72
73 /* #define DEBUG_ACPI_BUILD */
74 #ifdef DEBUG_ACPI_BUILD
75 #define ACPI_BUILD_DPRINTF(fmt, ...) \
76 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
77 #else
78 #define ACPI_BUILD_DPRINTF(fmt, ...)
79 #endif
80
81 typedef struct AcpiCpuInfo {
82 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
83 } AcpiCpuInfo;
84
85 typedef struct AcpiMcfgInfo {
86 uint64_t mcfg_base;
87 uint32_t mcfg_size;
88 } AcpiMcfgInfo;
89
90 typedef struct AcpiPmInfo {
91 bool s3_disabled;
92 bool s4_disabled;
93 bool pcihp_bridge_en;
94 uint8_t s4_val;
95 uint16_t sci_int;
96 uint8_t acpi_enable_cmd;
97 uint8_t acpi_disable_cmd;
98 uint32_t gpe0_blk;
99 uint32_t gpe0_blk_len;
100 uint32_t io_base;
101 uint16_t cpu_hp_io_base;
102 uint16_t cpu_hp_io_len;
103 uint16_t mem_hp_io_base;
104 uint16_t mem_hp_io_len;
105 uint16_t pcihp_io_base;
106 uint16_t pcihp_io_len;
107 } AcpiPmInfo;
108
109 typedef struct AcpiMiscInfo {
110 bool has_hpet;
111 TPMVersion tpm_version;
112 const unsigned char *dsdt_code;
113 unsigned dsdt_size;
114 uint16_t pvpanic_port;
115 uint16_t applesmc_io_base;
116 } AcpiMiscInfo;
117
118 typedef struct AcpiBuildPciBusHotplugState {
119 GArray *device_table;
120 GArray *notify_table;
121 struct AcpiBuildPciBusHotplugState *parent;
122 bool pcihp_bridge_en;
123 } AcpiBuildPciBusHotplugState;
124
125 static void acpi_get_dsdt(AcpiMiscInfo *info)
126 {
127 Object *piix = piix4_pm_find();
128 Object *lpc = ich9_lpc_find();
129 assert(!!piix != !!lpc);
130
131 if (piix) {
132 info->dsdt_code = AcpiDsdtAmlCode;
133 info->dsdt_size = sizeof AcpiDsdtAmlCode;
134 }
135 if (lpc) {
136 info->dsdt_code = Q35AcpiDsdtAmlCode;
137 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
138 }
139 }
140
141 static
142 int acpi_add_cpu_info(Object *o, void *opaque)
143 {
144 AcpiCpuInfo *cpu = opaque;
145 uint64_t apic_id;
146
147 if (object_dynamic_cast(o, TYPE_CPU)) {
148 apic_id = object_property_get_int(o, "apic-id", NULL);
149 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
150
151 set_bit(apic_id, cpu->found_cpus);
152 }
153
154 object_child_foreach(o, acpi_add_cpu_info, opaque);
155 return 0;
156 }
157
158 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
159 {
160 Object *root = object_get_root();
161
162 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
163 object_child_foreach(root, acpi_add_cpu_info, cpu);
164 }
165
166 static void acpi_get_pm_info(AcpiPmInfo *pm)
167 {
168 Object *piix = piix4_pm_find();
169 Object *lpc = ich9_lpc_find();
170 Object *obj = NULL;
171 QObject *o;
172
173 pm->cpu_hp_io_base = 0;
174 pm->pcihp_io_base = 0;
175 pm->pcihp_io_len = 0;
176 if (piix) {
177 obj = piix;
178 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
179 pm->pcihp_io_base =
180 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
181 pm->pcihp_io_len =
182 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
183 }
184 if (lpc) {
185 obj = lpc;
186 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
187 }
188 assert(obj);
189
190 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
191 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
192 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
193
194 /* Fill in optional s3/s4 related properties */
195 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
196 if (o) {
197 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
198 } else {
199 pm->s3_disabled = false;
200 }
201 qobject_decref(o);
202 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
203 if (o) {
204 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
205 } else {
206 pm->s4_disabled = false;
207 }
208 qobject_decref(o);
209 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
210 if (o) {
211 pm->s4_val = qint_get_int(qobject_to_qint(o));
212 } else {
213 pm->s4_val = false;
214 }
215 qobject_decref(o);
216
217 /* Fill in mandatory properties */
218 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
219
220 pm->acpi_enable_cmd = object_property_get_int(obj,
221 ACPI_PM_PROP_ACPI_ENABLE_CMD,
222 NULL);
223 pm->acpi_disable_cmd = object_property_get_int(obj,
224 ACPI_PM_PROP_ACPI_DISABLE_CMD,
225 NULL);
226 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
227 NULL);
228 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
229 NULL);
230 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
231 NULL);
232 pm->pcihp_bridge_en =
233 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
234 NULL);
235 }
236
237 static void acpi_get_misc_info(AcpiMiscInfo *info)
238 {
239 info->has_hpet = hpet_find();
240 info->tpm_version = tpm_get_version();
241 info->pvpanic_port = pvpanic_port();
242 info->applesmc_io_base = applesmc_port();
243 }
244
245 /*
246 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
247 * On i386 arch we only have two pci hosts, so we can look only for them.
248 */
249 static Object *acpi_get_i386_pci_host(void)
250 {
251 PCIHostState *host;
252
253 host = OBJECT_CHECK(PCIHostState,
254 object_resolve_path("/machine/i440fx", NULL),
255 TYPE_PCI_HOST_BRIDGE);
256 if (!host) {
257 host = OBJECT_CHECK(PCIHostState,
258 object_resolve_path("/machine/q35", NULL),
259 TYPE_PCI_HOST_BRIDGE);
260 }
261
262 return OBJECT(host);
263 }
264
265 static void acpi_get_pci_info(PcPciInfo *info)
266 {
267 Object *pci_host;
268
269
270 pci_host = acpi_get_i386_pci_host();
271 g_assert(pci_host);
272
273 info->w32.begin = object_property_get_int(pci_host,
274 PCI_HOST_PROP_PCI_HOLE_START,
275 NULL);
276 info->w32.end = object_property_get_int(pci_host,
277 PCI_HOST_PROP_PCI_HOLE_END,
278 NULL);
279 info->w64.begin = object_property_get_int(pci_host,
280 PCI_HOST_PROP_PCI_HOLE64_START,
281 NULL);
282 info->w64.end = object_property_get_int(pci_host,
283 PCI_HOST_PROP_PCI_HOLE64_END,
284 NULL);
285 }
286
287 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
288
289 static void acpi_align_size(GArray *blob, unsigned align)
290 {
291 /* Align size to multiple of given size. This reduces the chance
292 * we need to change size in the future (breaking cross version migration).
293 */
294 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
295 }
296
297 /* FACS */
298 static void
299 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
300 {
301 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
302 memcpy(&facs->signature, "FACS", 4);
303 facs->length = cpu_to_le32(sizeof(*facs));
304 }
305
306 /* Load chipset information in FADT */
307 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
308 {
309 fadt->model = 1;
310 fadt->reserved1 = 0;
311 fadt->sci_int = cpu_to_le16(pm->sci_int);
312 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
313 fadt->acpi_enable = pm->acpi_enable_cmd;
314 fadt->acpi_disable = pm->acpi_disable_cmd;
315 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
316 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
317 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
318 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
319 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
320 /* EVT, CNT, TMR length matches hw/acpi/core.c */
321 fadt->pm1_evt_len = 4;
322 fadt->pm1_cnt_len = 2;
323 fadt->pm_tmr_len = 4;
324 fadt->gpe0_blk_len = pm->gpe0_blk_len;
325 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
326 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
327 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
328 (1 << ACPI_FADT_F_PROC_C1) |
329 (1 << ACPI_FADT_F_SLP_BUTTON) |
330 (1 << ACPI_FADT_F_RTC_S4));
331 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
332 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
333 * For more than 8 CPUs, "Clustered Logical" mode has to be used
334 */
335 if (max_cpus > 8) {
336 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
337 }
338 }
339
340
341 /* FADT */
342 static void
343 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
344 unsigned facs, unsigned dsdt)
345 {
346 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
347
348 fadt->firmware_ctrl = cpu_to_le32(facs);
349 /* FACS address to be filled by Guest linker */
350 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
351 ACPI_BUILD_TABLE_FILE,
352 table_data, &fadt->firmware_ctrl,
353 sizeof fadt->firmware_ctrl);
354
355 fadt->dsdt = cpu_to_le32(dsdt);
356 /* DSDT address to be filled by Guest linker */
357 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
358 ACPI_BUILD_TABLE_FILE,
359 table_data, &fadt->dsdt,
360 sizeof fadt->dsdt);
361
362 fadt_setup(fadt, pm);
363
364 build_header(linker, table_data,
365 (void *)fadt, "FACP", sizeof(*fadt), 1, NULL);
366 }
367
368 static void
369 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
370 PcGuestInfo *guest_info)
371 {
372 int madt_start = table_data->len;
373
374 AcpiMultipleApicTable *madt;
375 AcpiMadtIoApic *io_apic;
376 AcpiMadtIntsrcovr *intsrcovr;
377 AcpiMadtLocalNmi *local_nmi;
378 int i;
379
380 madt = acpi_data_push(table_data, sizeof *madt);
381 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
382 madt->flags = cpu_to_le32(1);
383
384 for (i = 0; i < guest_info->apic_id_limit; i++) {
385 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
386 apic->type = ACPI_APIC_PROCESSOR;
387 apic->length = sizeof(*apic);
388 apic->processor_id = i;
389 apic->local_apic_id = i;
390 if (test_bit(i, cpu->found_cpus)) {
391 apic->flags = cpu_to_le32(1);
392 } else {
393 apic->flags = cpu_to_le32(0);
394 }
395 }
396 io_apic = acpi_data_push(table_data, sizeof *io_apic);
397 io_apic->type = ACPI_APIC_IO;
398 io_apic->length = sizeof(*io_apic);
399 #define ACPI_BUILD_IOAPIC_ID 0x0
400 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
401 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
402 io_apic->interrupt = cpu_to_le32(0);
403
404 if (guest_info->apic_xrupt_override) {
405 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
406 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
407 intsrcovr->length = sizeof(*intsrcovr);
408 intsrcovr->source = 0;
409 intsrcovr->gsi = cpu_to_le32(2);
410 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
411 }
412 for (i = 1; i < 16; i++) {
413 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
414 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
415 /* No need for a INT source override structure. */
416 continue;
417 }
418 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
419 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
420 intsrcovr->length = sizeof(*intsrcovr);
421 intsrcovr->source = i;
422 intsrcovr->gsi = cpu_to_le32(i);
423 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
424 }
425
426 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
427 local_nmi->type = ACPI_APIC_LOCAL_NMI;
428 local_nmi->length = sizeof(*local_nmi);
429 local_nmi->processor_id = 0xff; /* all processors */
430 local_nmi->flags = cpu_to_le16(0);
431 local_nmi->lint = 1; /* ACPI_LINT1 */
432
433 build_header(linker, table_data,
434 (void *)(table_data->data + madt_start), "APIC",
435 table_data->len - madt_start, 1, NULL);
436 }
437
438 /* Assign BSEL property to all buses. In the future, this can be changed
439 * to only assign to buses that support hotplug.
440 */
441 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
442 {
443 unsigned *bsel_alloc = opaque;
444 unsigned *bus_bsel;
445
446 if (qbus_is_hotpluggable(BUS(bus))) {
447 bus_bsel = g_malloc(sizeof *bus_bsel);
448
449 *bus_bsel = (*bsel_alloc)++;
450 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
451 bus_bsel, NULL);
452 }
453
454 return bsel_alloc;
455 }
456
457 static void acpi_set_pci_info(void)
458 {
459 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
460 unsigned bsel_alloc = 0;
461
462 if (bus) {
463 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
464 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
465 }
466 }
467
468 static void build_append_pcihp_notify_entry(Aml *method, int slot)
469 {
470 Aml *if_ctx;
471 int32_t devfn = PCI_DEVFN(slot, 0);
472
473 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot)));
474 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
475 aml_append(method, if_ctx);
476 }
477
478 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
479 bool pcihp_bridge_en)
480 {
481 Aml *dev, *notify_method, *method;
482 QObject *bsel;
483 PCIBus *sec;
484 int i;
485
486 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
487 if (bsel) {
488 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
489
490 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
491 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
492 }
493
494 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
495 DeviceClass *dc;
496 PCIDeviceClass *pc;
497 PCIDevice *pdev = bus->devices[i];
498 int slot = PCI_SLOT(i);
499 bool hotplug_enabled_dev;
500 bool bridge_in_acpi;
501
502 if (!pdev) {
503 if (bsel) { /* add hotplug slots for non present devices */
504 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
505 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
506 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
507 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
508 aml_append(method,
509 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
510 );
511 aml_append(dev, method);
512 aml_append(parent_scope, dev);
513
514 build_append_pcihp_notify_entry(notify_method, slot);
515 }
516 continue;
517 }
518
519 pc = PCI_DEVICE_GET_CLASS(pdev);
520 dc = DEVICE_GET_CLASS(pdev);
521
522 /* When hotplug for bridges is enabled, bridges are
523 * described in ACPI separately (see build_pci_bus_end).
524 * In this case they aren't themselves hot-pluggable.
525 * Hotplugged bridges *are* hot-pluggable.
526 */
527 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
528 !DEVICE(pdev)->hotplugged;
529
530 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
531
532 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
533 continue;
534 }
535
536 /* start to compose PCI slot descriptor */
537 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
538 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
539
540 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
541 /* add VGA specific AML methods */
542 int s3d;
543
544 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
545 s3d = 3;
546 } else {
547 s3d = 0;
548 }
549
550 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
551 aml_append(method, aml_return(aml_int(0)));
552 aml_append(dev, method);
553
554 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
555 aml_append(method, aml_return(aml_int(0)));
556 aml_append(dev, method);
557
558 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
559 aml_append(method, aml_return(aml_int(s3d)));
560 aml_append(dev, method);
561 } else if (hotplug_enabled_dev) {
562 /* add _SUN/_EJ0 to make slot hotpluggable */
563 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
564
565 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
566 aml_append(method,
567 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
568 );
569 aml_append(dev, method);
570
571 if (bsel) {
572 build_append_pcihp_notify_entry(notify_method, slot);
573 }
574 } else if (bridge_in_acpi) {
575 /*
576 * device is coldplugged bridge,
577 * add child device descriptions into its scope
578 */
579 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
580
581 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
582 }
583 /* slot descriptor has been composed, add it into parent context */
584 aml_append(parent_scope, dev);
585 }
586
587 if (bsel) {
588 aml_append(parent_scope, notify_method);
589 }
590
591 /* Append PCNT method to notify about events on local and child buses.
592 * Add unconditionally for root since DSDT expects it.
593 */
594 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
595
596 /* If bus supports hotplug select it and notify about local events */
597 if (bsel) {
598 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
599 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
600 aml_append(method,
601 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
602 );
603 aml_append(method,
604 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
605 );
606 }
607
608 /* Notify about child bus events in any case */
609 if (pcihp_bridge_en) {
610 QLIST_FOREACH(sec, &bus->child, sibling) {
611 int32_t devfn = sec->parent_dev->devfn;
612
613 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
614 }
615 }
616 aml_append(parent_scope, method);
617 qobject_decref(bsel);
618 }
619
620 /*
621 * initialize_route - Initialize the interrupt routing rule
622 * through a specific LINK:
623 * if (lnk_idx == idx)
624 * route using link 'link_name'
625 */
626 static Aml *initialize_route(Aml *route, const char *link_name,
627 Aml *lnk_idx, int idx)
628 {
629 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
630 Aml *pkg = aml_package(4);
631
632 aml_append(pkg, aml_int(0));
633 aml_append(pkg, aml_int(0));
634 aml_append(pkg, aml_name("%s", link_name));
635 aml_append(pkg, aml_int(0));
636 aml_append(if_ctx, aml_store(pkg, route));
637
638 return if_ctx;
639 }
640
641 /*
642 * build_prt - Define interrupt rounting rules
643 *
644 * Returns an array of 128 routes, one for each device,
645 * based on device location.
646 * The main goal is to equaly distribute the interrupts
647 * over the 4 existing ACPI links (works only for i440fx).
648 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
649 *
650 */
651 static Aml *build_prt(void)
652 {
653 Aml *method, *while_ctx, *pin, *res;
654
655 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
656 res = aml_local(0);
657 pin = aml_local(1);
658 aml_append(method, aml_store(aml_package(128), res));
659 aml_append(method, aml_store(aml_int(0), pin));
660
661 /* while (pin < 128) */
662 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
663 {
664 Aml *slot = aml_local(2);
665 Aml *lnk_idx = aml_local(3);
666 Aml *route = aml_local(4);
667
668 /* slot = pin >> 2 */
669 aml_append(while_ctx,
670 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
671 /* lnk_idx = (slot + pin) & 3 */
672 aml_append(while_ctx,
673 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3)), lnk_idx));
674
675 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
676 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
677 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
678 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
679 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
680
681 /* route[0] = 0x[slot]FFFF */
682 aml_append(while_ctx,
683 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
684 NULL),
685 aml_index(route, aml_int(0))));
686 /* route[1] = pin & 3 */
687 aml_append(while_ctx,
688 aml_store(aml_and(pin, aml_int(3)), aml_index(route, aml_int(1))));
689 /* res[pin] = route */
690 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
691 /* pin++ */
692 aml_append(while_ctx, aml_increment(pin));
693 }
694 aml_append(method, while_ctx);
695 /* return res*/
696 aml_append(method, aml_return(res));
697
698 return method;
699 }
700
701 typedef struct CrsRangeEntry {
702 uint64_t base;
703 uint64_t limit;
704 } CrsRangeEntry;
705
706 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
707 {
708 CrsRangeEntry *entry;
709
710 entry = g_malloc(sizeof(*entry));
711 entry->base = base;
712 entry->limit = limit;
713
714 g_ptr_array_add(ranges, entry);
715 }
716
717 static void crs_range_free(gpointer data)
718 {
719 CrsRangeEntry *entry = (CrsRangeEntry *)data;
720 g_free(entry);
721 }
722
723 static gint crs_range_compare(gconstpointer a, gconstpointer b)
724 {
725 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
726 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
727
728 return (int64_t)entry_a->base - (int64_t)entry_b->base;
729 }
730
731 /*
732 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
733 * interval, computes the 'free' ranges from the same interval.
734 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
735 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
736 */
737 static void crs_replace_with_free_ranges(GPtrArray *ranges,
738 uint64_t start, uint64_t end)
739 {
740 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
741 uint64_t free_base = start;
742 int i;
743
744 g_ptr_array_sort(ranges, crs_range_compare);
745 for (i = 0; i < ranges->len; i++) {
746 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
747
748 if (free_base < used->base) {
749 crs_range_insert(free_ranges, free_base, used->base - 1);
750 }
751
752 free_base = used->limit + 1;
753 }
754
755 if (free_base < end) {
756 crs_range_insert(free_ranges, free_base, end);
757 }
758
759 g_ptr_array_set_size(ranges, 0);
760 for (i = 0; i < free_ranges->len; i++) {
761 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
762 }
763
764 g_ptr_array_free(free_ranges, false);
765 }
766
767 /*
768 * crs_range_merge - merges adjacent ranges in the given array.
769 * Array elements are deleted and replaced with the merged ranges.
770 */
771 static void crs_range_merge(GPtrArray *range)
772 {
773 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
774 CrsRangeEntry *entry;
775 uint64_t range_base, range_limit;
776 int i;
777
778 if (!range->len) {
779 return;
780 }
781
782 g_ptr_array_sort(range, crs_range_compare);
783
784 entry = g_ptr_array_index(range, 0);
785 range_base = entry->base;
786 range_limit = entry->limit;
787 for (i = 1; i < range->len; i++) {
788 entry = g_ptr_array_index(range, i);
789 if (entry->base - 1 == range_limit) {
790 range_limit = entry->limit;
791 } else {
792 crs_range_insert(tmp, range_base, range_limit);
793 range_base = entry->base;
794 range_limit = entry->limit;
795 }
796 }
797 crs_range_insert(tmp, range_base, range_limit);
798
799 g_ptr_array_set_size(range, 0);
800 for (i = 0; i < tmp->len; i++) {
801 entry = g_ptr_array_index(tmp, i);
802 crs_range_insert(range, entry->base, entry->limit);
803 }
804 g_ptr_array_free(tmp, true);
805 }
806
807 static Aml *build_crs(PCIHostState *host,
808 GPtrArray *io_ranges, GPtrArray *mem_ranges)
809 {
810 Aml *crs = aml_resource_template();
811 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
812 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
813 CrsRangeEntry *entry;
814 uint8_t max_bus = pci_bus_num(host->bus);
815 uint8_t type;
816 int devfn;
817 int i;
818
819 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
820 uint64_t range_base, range_limit;
821 PCIDevice *dev = host->bus->devices[devfn];
822
823 if (!dev) {
824 continue;
825 }
826
827 for (i = 0; i < PCI_NUM_REGIONS; i++) {
828 PCIIORegion *r = &dev->io_regions[i];
829
830 range_base = r->addr;
831 range_limit = r->addr + r->size - 1;
832
833 /*
834 * Work-around for old bioses
835 * that do not support multiple root buses
836 */
837 if (!range_base || range_base > range_limit) {
838 continue;
839 }
840
841 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
842 crs_range_insert(host_io_ranges, range_base, range_limit);
843 } else { /* "memory" */
844 crs_range_insert(host_mem_ranges, range_base, range_limit);
845 }
846 }
847
848 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
849 if (type == PCI_HEADER_TYPE_BRIDGE) {
850 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
851 if (subordinate > max_bus) {
852 max_bus = subordinate;
853 }
854
855 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
856 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
857
858 /*
859 * Work-around for old bioses
860 * that do not support multiple root buses
861 */
862 if (range_base && range_base <= range_limit) {
863 crs_range_insert(host_io_ranges, range_base, range_limit);
864 }
865
866 range_base =
867 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
868 range_limit =
869 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
870
871 /*
872 * Work-around for old bioses
873 * that do not support multiple root buses
874 */
875 if (range_base && range_base <= range_limit) {
876 crs_range_insert(host_mem_ranges, range_base, range_limit);
877 }
878
879 range_base =
880 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
881 range_limit =
882 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
883
884 /*
885 * Work-around for old bioses
886 * that do not support multiple root buses
887 */
888 if (range_base && range_base <= range_limit) {
889 crs_range_insert(host_mem_ranges, range_base, range_limit);
890 }
891 }
892 }
893
894 crs_range_merge(host_io_ranges);
895 for (i = 0; i < host_io_ranges->len; i++) {
896 entry = g_ptr_array_index(host_io_ranges, i);
897 aml_append(crs,
898 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
899 AML_POS_DECODE, AML_ENTIRE_RANGE,
900 0, entry->base, entry->limit, 0,
901 entry->limit - entry->base + 1));
902 crs_range_insert(io_ranges, entry->base, entry->limit);
903 }
904 g_ptr_array_free(host_io_ranges, true);
905
906 crs_range_merge(host_mem_ranges);
907 for (i = 0; i < host_mem_ranges->len; i++) {
908 entry = g_ptr_array_index(host_mem_ranges, i);
909 aml_append(crs,
910 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
911 AML_MAX_FIXED, AML_NON_CACHEABLE,
912 AML_READ_WRITE,
913 0, entry->base, entry->limit, 0,
914 entry->limit - entry->base + 1));
915 crs_range_insert(mem_ranges, entry->base, entry->limit);
916 }
917 g_ptr_array_free(host_mem_ranges, true);
918
919 aml_append(crs,
920 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
921 0,
922 pci_bus_num(host->bus),
923 max_bus,
924 0,
925 max_bus - pci_bus_num(host->bus) + 1));
926
927 return crs;
928 }
929
930 static void
931 build_ssdt(GArray *table_data, GArray *linker,
932 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
933 PcPciInfo *pci, PcGuestInfo *guest_info)
934 {
935 MachineState *machine = MACHINE(qdev_get_machine());
936 uint32_t nr_mem = machine->ram_slots;
937 unsigned acpi_cpus = guest_info->apic_id_limit;
938 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
939 PCIBus *bus = NULL;
940 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
941 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
942 CrsRangeEntry *entry;
943 int root_bus_limit = 0xFF;
944 int i;
945
946 ssdt = init_aml_allocator();
947 /* The current AML generator can cover the APIC ID range [0..255],
948 * inclusive, for VCPU hotplug. */
949 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
950 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
951
952 /* Reserve space for header */
953 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
954
955 bus = PC_MACHINE(machine)->bus;
956 if (bus) {
957 QLIST_FOREACH(bus, &bus->child, sibling) {
958 uint8_t bus_num = pci_bus_num(bus);
959 uint8_t numa_node = pci_bus_numa_node(bus);
960
961 /* look only for expander root buses */
962 if (!pci_bus_is_root(bus)) {
963 continue;
964 }
965
966 if (bus_num < root_bus_limit) {
967 root_bus_limit = bus_num - 1;
968 }
969
970 scope = aml_scope("\\_SB");
971 dev = aml_device("PC%.02X", bus_num);
972 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
973 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
974 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
975
976 if (numa_node != NUMA_NODE_UNASSIGNED) {
977 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
978 }
979
980 aml_append(dev, build_prt());
981 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
982 io_ranges, mem_ranges);
983 aml_append(dev, aml_name_decl("_CRS", crs));
984 aml_append(scope, dev);
985 aml_append(ssdt, scope);
986 }
987 }
988
989 scope = aml_scope("\\_SB.PCI0");
990 /* build PCI0._CRS */
991 crs = aml_resource_template();
992 aml_append(crs,
993 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
994 0x0000, 0x0, root_bus_limit,
995 0x0000, root_bus_limit + 1));
996 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
997
998 aml_append(crs,
999 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1000 AML_POS_DECODE, AML_ENTIRE_RANGE,
1001 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1002
1003 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
1004 for (i = 0; i < io_ranges->len; i++) {
1005 entry = g_ptr_array_index(io_ranges, i);
1006 aml_append(crs,
1007 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1008 AML_POS_DECODE, AML_ENTIRE_RANGE,
1009 0x0000, entry->base, entry->limit,
1010 0x0000, entry->limit - entry->base + 1));
1011 }
1012
1013 aml_append(crs,
1014 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1015 AML_CACHEABLE, AML_READ_WRITE,
1016 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1017
1018 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
1019 for (i = 0; i < mem_ranges->len; i++) {
1020 entry = g_ptr_array_index(mem_ranges, i);
1021 aml_append(crs,
1022 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1023 AML_NON_CACHEABLE, AML_READ_WRITE,
1024 0, entry->base, entry->limit,
1025 0, entry->limit - entry->base + 1));
1026 }
1027
1028 if (pci->w64.begin) {
1029 aml_append(crs,
1030 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1031 AML_CACHEABLE, AML_READ_WRITE,
1032 0, pci->w64.begin, pci->w64.end - 1, 0,
1033 pci->w64.end - pci->w64.begin));
1034 }
1035 aml_append(scope, aml_name_decl("_CRS", crs));
1036
1037 /* reserve GPE0 block resources */
1038 dev = aml_device("GPE0");
1039 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1040 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1041 /* device present, functioning, decoding, not shown in UI */
1042 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1043 crs = aml_resource_template();
1044 aml_append(crs,
1045 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
1046 );
1047 aml_append(dev, aml_name_decl("_CRS", crs));
1048 aml_append(scope, dev);
1049
1050 g_ptr_array_free(io_ranges, true);
1051 g_ptr_array_free(mem_ranges, true);
1052
1053 /* reserve PCIHP resources */
1054 if (pm->pcihp_io_len) {
1055 dev = aml_device("PHPR");
1056 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1057 aml_append(dev,
1058 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1059 /* device present, functioning, decoding, not shown in UI */
1060 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1061 crs = aml_resource_template();
1062 aml_append(crs,
1063 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1064 pm->pcihp_io_len)
1065 );
1066 aml_append(dev, aml_name_decl("_CRS", crs));
1067 aml_append(scope, dev);
1068 }
1069 aml_append(ssdt, scope);
1070
1071 /* create S3_ / S4_ / S5_ packages if necessary */
1072 scope = aml_scope("\\");
1073 if (!pm->s3_disabled) {
1074 pkg = aml_package(4);
1075 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1076 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1077 aml_append(pkg, aml_int(0)); /* reserved */
1078 aml_append(pkg, aml_int(0)); /* reserved */
1079 aml_append(scope, aml_name_decl("_S3", pkg));
1080 }
1081
1082 if (!pm->s4_disabled) {
1083 pkg = aml_package(4);
1084 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1085 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1086 aml_append(pkg, aml_int(pm->s4_val));
1087 aml_append(pkg, aml_int(0)); /* reserved */
1088 aml_append(pkg, aml_int(0)); /* reserved */
1089 aml_append(scope, aml_name_decl("_S4", pkg));
1090 }
1091
1092 pkg = aml_package(4);
1093 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1094 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1095 aml_append(pkg, aml_int(0)); /* reserved */
1096 aml_append(pkg, aml_int(0)); /* reserved */
1097 aml_append(scope, aml_name_decl("_S5", pkg));
1098 aml_append(ssdt, scope);
1099
1100 if (misc->applesmc_io_base) {
1101 scope = aml_scope("\\_SB.PCI0.ISA");
1102 dev = aml_device("SMC");
1103
1104 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1105 /* device present, functioning, decoding, not shown in UI */
1106 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1107
1108 crs = aml_resource_template();
1109 aml_append(crs,
1110 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1111 0x01, APPLESMC_MAX_DATA_LENGTH)
1112 );
1113 aml_append(crs, aml_irq_no_flags(6));
1114 aml_append(dev, aml_name_decl("_CRS", crs));
1115
1116 aml_append(scope, dev);
1117 aml_append(ssdt, scope);
1118 }
1119
1120 if (misc->pvpanic_port) {
1121 scope = aml_scope("\\_SB.PCI0.ISA");
1122
1123 dev = aml_device("PEVT");
1124 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1125
1126 crs = aml_resource_template();
1127 aml_append(crs,
1128 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1129 );
1130 aml_append(dev, aml_name_decl("_CRS", crs));
1131
1132 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1133 misc->pvpanic_port, 1));
1134 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1135 aml_append(field, aml_named_field("PEPT", 8));
1136 aml_append(dev, field);
1137
1138 /* device present, functioning, decoding, shown in UI */
1139 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1140
1141 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1142 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1143 aml_append(method, aml_return(aml_local(0)));
1144 aml_append(dev, method);
1145
1146 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1147 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1148 aml_append(dev, method);
1149
1150 aml_append(scope, dev);
1151 aml_append(ssdt, scope);
1152 }
1153
1154 sb_scope = aml_scope("\\_SB");
1155 {
1156 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
1157 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
1158 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1159 aml_append(dev,
1160 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
1161 );
1162 /* device present, functioning, decoding, not shown in UI */
1163 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1164 crs = aml_resource_template();
1165 aml_append(crs,
1166 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
1167 pm->cpu_hp_io_len)
1168 );
1169 aml_append(dev, aml_name_decl("_CRS", crs));
1170 aml_append(sb_scope, dev);
1171 /* declare CPU hotplug MMIO region and PRS field to access it */
1172 aml_append(sb_scope, aml_operation_region(
1173 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
1174 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1175 aml_append(field, aml_named_field("PRS", 256));
1176 aml_append(sb_scope, field);
1177
1178 /* build Processor object for each processor */
1179 for (i = 0; i < acpi_cpus; i++) {
1180 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1181
1182 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
1183 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i))));
1184 aml_append(dev, method);
1185
1186 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1187 aml_append(method, aml_return(aml_call1("CPST", aml_int(i))));
1188 aml_append(dev, method);
1189
1190 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1191 aml_append(method,
1192 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
1193 );
1194 aml_append(dev, method);
1195
1196 aml_append(sb_scope, dev);
1197 }
1198
1199 /* build this code:
1200 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1201 */
1202 /* Arg0 = Processor ID = APIC ID */
1203 method = aml_method("NTFY", 2, AML_NOTSERIALIZED);
1204 for (i = 0; i < acpi_cpus; i++) {
1205 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1206 aml_append(ifctx,
1207 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1208 );
1209 aml_append(method, ifctx);
1210 }
1211 aml_append(sb_scope, method);
1212
1213 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1214 *
1215 * Note: The ability to create variable-sized packages was first
1216 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1217 * ith up to 255 elements. Windows guests up to win2k8 fail when
1218 * VarPackageOp is used.
1219 */
1220 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1221 aml_varpackage(acpi_cpus);
1222
1223 for (i = 0; i < acpi_cpus; i++) {
1224 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1225 aml_append(pkg, aml_int(b));
1226 }
1227 aml_append(sb_scope, aml_name_decl("CPON", pkg));
1228
1229 /* build memory devices */
1230 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1231 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE));
1232 aml_append(scope,
1233 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem))
1234 );
1235
1236 crs = aml_resource_template();
1237 aml_append(crs,
1238 aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
1239 pm->mem_hp_io_len)
1240 );
1241 aml_append(scope, aml_name_decl("_CRS", crs));
1242
1243 aml_append(scope, aml_operation_region(
1244 stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO,
1245 pm->mem_hp_io_base, pm->mem_hp_io_len)
1246 );
1247
1248 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
1249 AML_NOLOCK, AML_PRESERVE);
1250 aml_append(field, /* read only */
1251 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
1252 aml_append(field, /* read only */
1253 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32));
1254 aml_append(field, /* read only */
1255 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32));
1256 aml_append(field, /* read only */
1257 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32));
1258 aml_append(field, /* read only */
1259 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
1260 aml_append(scope, field);
1261
1262 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC,
1263 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1264 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1265 aml_append(field, /* 1 if enabled, read only */
1266 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
1267 aml_append(field,
1268 /*(read) 1 if has a insert event. (write) 1 to clear event */
1269 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1));
1270 aml_append(field,
1271 /* (read) 1 if has a remove event. (write) 1 to clear event */
1272 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1));
1273 aml_append(field,
1274 /* initiates device eject, write only */
1275 aml_named_field(stringify(MEMORY_SLOT_EJECT), 1));
1276 aml_append(scope, field);
1277
1278 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
1279 AML_NOLOCK, AML_PRESERVE);
1280 aml_append(field, /* DIMM selector, write only */
1281 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
1282 aml_append(field, /* _OST event code, write only */
1283 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32));
1284 aml_append(field, /* _OST status code, write only */
1285 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32));
1286 aml_append(scope, field);
1287
1288 aml_append(sb_scope, scope);
1289
1290 for (i = 0; i < nr_mem; i++) {
1291 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1292 const char *s;
1293
1294 dev = aml_device("MP%02X", i);
1295 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1296 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1297
1298 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1299 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD);
1300 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1301 aml_append(dev, method);
1302
1303 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1304 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD);
1305 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1306 aml_append(dev, method);
1307
1308 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1309 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD);
1310 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1311 aml_append(dev, method);
1312
1313 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1314 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD);
1315 aml_append(method, aml_return(aml_call4(
1316 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1317 )));
1318 aml_append(dev, method);
1319
1320 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1321 s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD);
1322 aml_append(method, aml_return(aml_call2(
1323 s, aml_name("_UID"), aml_arg(0))));
1324 aml_append(dev, method);
1325
1326 aml_append(sb_scope, dev);
1327 }
1328
1329 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1330 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1331 */
1332 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2,
1333 AML_NOTSERIALIZED);
1334 for (i = 0; i < nr_mem; i++) {
1335 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1336 aml_append(ifctx,
1337 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1338 );
1339 aml_append(method, ifctx);
1340 }
1341 aml_append(sb_scope, method);
1342
1343 {
1344 Object *pci_host;
1345 PCIBus *bus = NULL;
1346
1347 pci_host = acpi_get_i386_pci_host();
1348 if (pci_host) {
1349 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1350 }
1351
1352 if (bus) {
1353 Aml *scope = aml_scope("PCI0");
1354 /* Scan all PCI buses. Generate tables to support hotplug. */
1355 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1356
1357 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
1358 dev = aml_device("ISA.TPM");
1359 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
1360 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1361 crs = aml_resource_template();
1362 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1363 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1364 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
1365 aml_append(dev, aml_name_decl("_CRS", crs));
1366 aml_append(scope, dev);
1367 }
1368
1369 aml_append(sb_scope, scope);
1370 }
1371 }
1372 aml_append(ssdt, sb_scope);
1373 }
1374
1375 /* copy AML table into ACPI tables blob and patch header there */
1376 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1377 build_header(linker, table_data,
1378 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1379 "SSDT", ssdt->buf->len, 1, NULL);
1380 free_aml_allocator();
1381 }
1382
1383 static void
1384 build_hpet(GArray *table_data, GArray *linker)
1385 {
1386 Acpi20Hpet *hpet;
1387
1388 hpet = acpi_data_push(table_data, sizeof(*hpet));
1389 /* Note timer_block_id value must be kept in sync with value advertised by
1390 * emulated hpet
1391 */
1392 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1393 hpet->addr.address = cpu_to_le64(HPET_BASE);
1394 build_header(linker, table_data,
1395 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL);
1396 }
1397
1398 static void
1399 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1400 {
1401 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1402 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1403
1404 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1405 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1406 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1407
1408 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1409 false /* high memory */);
1410
1411 /* log area start address to be filled by Guest linker */
1412 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1413 ACPI_BUILD_TPMLOG_FILE,
1414 table_data, &tcpa->log_area_start_address,
1415 sizeof(tcpa->log_area_start_address));
1416
1417 build_header(linker, table_data,
1418 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL);
1419
1420 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1421 }
1422
1423 static void
1424 build_tpm2(GArray *table_data, GArray *linker)
1425 {
1426 Acpi20TPM2 *tpm2_ptr;
1427
1428 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
1429
1430 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
1431 tpm2_ptr->control_area_address = cpu_to_le64(0);
1432 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
1433
1434 build_header(linker, table_data,
1435 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL);
1436 }
1437
1438 typedef enum {
1439 MEM_AFFINITY_NOFLAGS = 0,
1440 MEM_AFFINITY_ENABLED = (1 << 0),
1441 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1442 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1443 } MemoryAffinityFlags;
1444
1445 static void
1446 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1447 uint64_t len, int node, MemoryAffinityFlags flags)
1448 {
1449 numamem->type = ACPI_SRAT_MEMORY;
1450 numamem->length = sizeof(*numamem);
1451 memset(numamem->proximity, 0, 4);
1452 numamem->proximity[0] = node;
1453 numamem->flags = cpu_to_le32(flags);
1454 numamem->base_addr = cpu_to_le64(base);
1455 numamem->range_length = cpu_to_le64(len);
1456 }
1457
1458 static void
1459 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1460 {
1461 AcpiSystemResourceAffinityTable *srat;
1462 AcpiSratProcessorAffinity *core;
1463 AcpiSratMemoryAffinity *numamem;
1464
1465 int i;
1466 uint64_t curnode;
1467 int srat_start, numa_start, slots;
1468 uint64_t mem_len, mem_base, next_base;
1469 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1470 ram_addr_t hotplugabble_address_space_size =
1471 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1472 NULL);
1473
1474 srat_start = table_data->len;
1475
1476 srat = acpi_data_push(table_data, sizeof *srat);
1477 srat->reserved1 = cpu_to_le32(1);
1478 core = (void *)(srat + 1);
1479
1480 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1481 core = acpi_data_push(table_data, sizeof *core);
1482 core->type = ACPI_SRAT_PROCESSOR;
1483 core->length = sizeof(*core);
1484 core->local_apic_id = i;
1485 curnode = guest_info->node_cpu[i];
1486 core->proximity_lo = curnode;
1487 memset(core->proximity_hi, 0, 3);
1488 core->local_sapic_eid = 0;
1489 core->flags = cpu_to_le32(1);
1490 }
1491
1492
1493 /* the memory map is a bit tricky, it contains at least one hole
1494 * from 640k-1M and possibly another one from 3.5G-4G.
1495 */
1496 next_base = 0;
1497 numa_start = table_data->len;
1498
1499 numamem = acpi_data_push(table_data, sizeof *numamem);
1500 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1501 next_base = 1024 * 1024;
1502 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1503 mem_base = next_base;
1504 mem_len = guest_info->node_mem[i - 1];
1505 if (i == 1) {
1506 mem_len -= 1024 * 1024;
1507 }
1508 next_base = mem_base + mem_len;
1509
1510 /* Cut out the ACPI_PCI hole */
1511 if (mem_base <= guest_info->ram_size_below_4g &&
1512 next_base > guest_info->ram_size_below_4g) {
1513 mem_len -= next_base - guest_info->ram_size_below_4g;
1514 if (mem_len > 0) {
1515 numamem = acpi_data_push(table_data, sizeof *numamem);
1516 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1517 MEM_AFFINITY_ENABLED);
1518 }
1519 mem_base = 1ULL << 32;
1520 mem_len = next_base - guest_info->ram_size_below_4g;
1521 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1522 }
1523 numamem = acpi_data_push(table_data, sizeof *numamem);
1524 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1525 MEM_AFFINITY_ENABLED);
1526 }
1527 slots = (table_data->len - numa_start) / sizeof *numamem;
1528 for (; slots < guest_info->numa_nodes + 2; slots++) {
1529 numamem = acpi_data_push(table_data, sizeof *numamem);
1530 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1531 }
1532
1533 /*
1534 * Entry is required for Windows to enable memory hotplug in OS.
1535 * Memory devices may override proximity set by this entry,
1536 * providing _PXM method if necessary.
1537 */
1538 if (hotplugabble_address_space_size) {
1539 numamem = acpi_data_push(table_data, sizeof *numamem);
1540 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
1541 hotplugabble_address_space_size, 0,
1542 MEM_AFFINITY_HOTPLUGGABLE |
1543 MEM_AFFINITY_ENABLED);
1544 }
1545
1546 build_header(linker, table_data,
1547 (void *)(table_data->data + srat_start),
1548 "SRAT",
1549 table_data->len - srat_start, 1, NULL);
1550 }
1551
1552 static void
1553 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1554 {
1555 AcpiTableMcfg *mcfg;
1556 const char *sig;
1557 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1558
1559 mcfg = acpi_data_push(table_data, len);
1560 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1561 /* Only a single allocation so no need to play with segments */
1562 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1563 mcfg->allocation[0].start_bus_number = 0;
1564 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1565
1566 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1567 * To avoid table size changes (which create migration issues),
1568 * always create the table even if there are no allocations,
1569 * but set the signature to a reserved value in this case.
1570 * ACPI spec requires OSPMs to ignore such tables.
1571 */
1572 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1573 /* Reserved signature: ignored by OSPM */
1574 sig = "QEMU";
1575 } else {
1576 sig = "MCFG";
1577 }
1578 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL);
1579 }
1580
1581 static void
1582 build_dmar_q35(GArray *table_data, GArray *linker)
1583 {
1584 int dmar_start = table_data->len;
1585
1586 AcpiTableDmar *dmar;
1587 AcpiDmarHardwareUnit *drhd;
1588
1589 dmar = acpi_data_push(table_data, sizeof(*dmar));
1590 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1591 dmar->flags = 0; /* No intr_remap for now */
1592
1593 /* DMAR Remapping Hardware Unit Definition structure */
1594 drhd = acpi_data_push(table_data, sizeof(*drhd));
1595 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1596 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1597 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1598 drhd->pci_segment = cpu_to_le16(0);
1599 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1600
1601 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1602 "DMAR", table_data->len - dmar_start, 1, NULL);
1603 }
1604
1605 static void
1606 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1607 {
1608 AcpiTableHeader *dsdt;
1609
1610 assert(misc->dsdt_code && misc->dsdt_size);
1611
1612 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1613 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1614
1615 memset(dsdt, 0, sizeof *dsdt);
1616 build_header(linker, table_data, dsdt, "DSDT",
1617 misc->dsdt_size, 1, NULL);
1618 }
1619
1620 static GArray *
1621 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1622 {
1623 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1624
1625 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1626 true /* fseg memory */);
1627
1628 memcpy(&rsdp->signature, "RSD PTR ", 8);
1629 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1630 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1631 /* Address to be filled by Guest linker */
1632 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1633 ACPI_BUILD_TABLE_FILE,
1634 rsdp_table, &rsdp->rsdt_physical_address,
1635 sizeof rsdp->rsdt_physical_address);
1636 rsdp->checksum = 0;
1637 /* Checksum to be filled by Guest linker */
1638 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1639 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1640
1641 return rsdp_table;
1642 }
1643
1644 typedef
1645 struct AcpiBuildState {
1646 /* Copy of table in RAM (for patching). */
1647 MemoryRegion *table_mr;
1648 /* Is table patched? */
1649 uint8_t patched;
1650 PcGuestInfo *guest_info;
1651 void *rsdp;
1652 MemoryRegion *rsdp_mr;
1653 MemoryRegion *linker_mr;
1654 } AcpiBuildState;
1655
1656 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1657 {
1658 Object *pci_host;
1659 QObject *o;
1660
1661 pci_host = acpi_get_i386_pci_host();
1662 g_assert(pci_host);
1663
1664 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1665 if (!o) {
1666 return false;
1667 }
1668 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
1669 qobject_decref(o);
1670
1671 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1672 assert(o);
1673 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
1674 qobject_decref(o);
1675 return true;
1676 }
1677
1678 static bool acpi_has_iommu(void)
1679 {
1680 bool ambiguous;
1681 Object *intel_iommu;
1682
1683 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
1684 &ambiguous);
1685 return intel_iommu && !ambiguous;
1686 }
1687
1688 static bool acpi_has_nvdimm(void)
1689 {
1690 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1691
1692 return pcms->nvdimm;
1693 }
1694
1695 static
1696 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
1697 {
1698 GArray *table_offsets;
1699 unsigned facs, ssdt, dsdt, rsdt;
1700 AcpiCpuInfo cpu;
1701 AcpiPmInfo pm;
1702 AcpiMiscInfo misc;
1703 AcpiMcfgInfo mcfg;
1704 PcPciInfo pci;
1705 uint8_t *u;
1706 size_t aml_len = 0;
1707 GArray *tables_blob = tables->table_data;
1708
1709 acpi_get_cpu_info(&cpu);
1710 acpi_get_pm_info(&pm);
1711 acpi_get_dsdt(&misc);
1712 acpi_get_misc_info(&misc);
1713 acpi_get_pci_info(&pci);
1714
1715 table_offsets = g_array_new(false, true /* clear */,
1716 sizeof(uint32_t));
1717 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1718
1719 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
1720 64 /* Ensure FACS is aligned */,
1721 false /* high memory */);
1722
1723 /*
1724 * FACS is pointed to by FADT.
1725 * We place it first since it's the only table that has alignment
1726 * requirements.
1727 */
1728 facs = tables_blob->len;
1729 build_facs(tables_blob, tables->linker, guest_info);
1730
1731 /* DSDT is pointed to by FADT */
1732 dsdt = tables_blob->len;
1733 build_dsdt(tables_blob, tables->linker, &misc);
1734
1735 /* Count the size of the DSDT and SSDT, we will need it for legacy
1736 * sizing of ACPI tables.
1737 */
1738 aml_len += tables_blob->len - dsdt;
1739
1740 /* ACPI tables pointed to by RSDT */
1741 acpi_add_table(table_offsets, tables_blob);
1742 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
1743
1744 ssdt = tables_blob->len;
1745 acpi_add_table(table_offsets, tables_blob);
1746 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
1747 guest_info);
1748 aml_len += tables_blob->len - ssdt;
1749
1750 acpi_add_table(table_offsets, tables_blob);
1751 build_madt(tables_blob, tables->linker, &cpu, guest_info);
1752
1753 if (misc.has_hpet) {
1754 acpi_add_table(table_offsets, tables_blob);
1755 build_hpet(tables_blob, tables->linker);
1756 }
1757 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
1758 acpi_add_table(table_offsets, tables_blob);
1759 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
1760
1761 if (misc.tpm_version == TPM_VERSION_2_0) {
1762 acpi_add_table(table_offsets, tables_blob);
1763 build_tpm2(tables_blob, tables->linker);
1764 }
1765 }
1766 if (guest_info->numa_nodes) {
1767 acpi_add_table(table_offsets, tables_blob);
1768 build_srat(tables_blob, tables->linker, guest_info);
1769 }
1770 if (acpi_get_mcfg(&mcfg)) {
1771 acpi_add_table(table_offsets, tables_blob);
1772 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
1773 }
1774 if (acpi_has_iommu()) {
1775 acpi_add_table(table_offsets, tables_blob);
1776 build_dmar_q35(tables_blob, tables->linker);
1777 }
1778
1779 if (acpi_has_nvdimm()) {
1780 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
1781 }
1782
1783 /* Add tables supplied by user (if any) */
1784 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
1785 unsigned len = acpi_table_len(u);
1786
1787 acpi_add_table(table_offsets, tables_blob);
1788 g_array_append_vals(tables_blob, u, len);
1789 }
1790
1791 /* RSDT is pointed to by RSDP */
1792 rsdt = tables_blob->len;
1793 build_rsdt(tables_blob, tables->linker, table_offsets);
1794
1795 /* RSDP is in FSEG memory, so allocate it separately */
1796 build_rsdp(tables->rsdp, tables->linker, rsdt);
1797
1798 /* We'll expose it all to Guest so we want to reduce
1799 * chance of size changes.
1800 *
1801 * We used to align the tables to 4k, but of course this would
1802 * too simple to be enough. 4k turned out to be too small an
1803 * alignment very soon, and in fact it is almost impossible to
1804 * keep the table size stable for all (max_cpus, max_memory_slots)
1805 * combinations. So the table size is always 64k for pc-i440fx-2.1
1806 * and we give an error if the table grows beyond that limit.
1807 *
1808 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1809 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1810 * than 2.0 and we can always pad the smaller tables with zeros. We can
1811 * then use the exact size of the 2.0 tables.
1812 *
1813 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1814 */
1815 if (guest_info->legacy_acpi_table_size) {
1816 /* Subtracting aml_len gives the size of fixed tables. Then add the
1817 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1818 */
1819 int legacy_aml_len =
1820 guest_info->legacy_acpi_table_size +
1821 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
1822 int legacy_table_size =
1823 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
1824 ACPI_BUILD_ALIGN_SIZE);
1825 if (tables_blob->len > legacy_table_size) {
1826 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1827 error_report("Warning: migration may not work.");
1828 }
1829 g_array_set_size(tables_blob, legacy_table_size);
1830 } else {
1831 /* Make sure we have a buffer in case we need to resize the tables. */
1832 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1833 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1834 error_report("Warning: ACPI tables are larger than 64k.");
1835 error_report("Warning: migration may not work.");
1836 error_report("Warning: please remove CPUs, NUMA nodes, "
1837 "memory slots or PCI bridges.");
1838 }
1839 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1840 }
1841
1842 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
1843
1844 /* Cleanup memory that's no longer used. */
1845 g_array_free(table_offsets, true);
1846 }
1847
1848 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1849 {
1850 uint32_t size = acpi_data_len(data);
1851
1852 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1853 memory_region_ram_resize(mr, size, &error_abort);
1854
1855 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1856 memory_region_set_dirty(mr, 0, size);
1857 }
1858
1859 static void acpi_build_update(void *build_opaque)
1860 {
1861 AcpiBuildState *build_state = build_opaque;
1862 AcpiBuildTables tables;
1863
1864 /* No state to update or already patched? Nothing to do. */
1865 if (!build_state || build_state->patched) {
1866 return;
1867 }
1868 build_state->patched = 1;
1869
1870 acpi_build_tables_init(&tables);
1871
1872 acpi_build(build_state->guest_info, &tables);
1873
1874 acpi_ram_update(build_state->table_mr, tables.table_data);
1875
1876 if (build_state->rsdp) {
1877 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
1878 } else {
1879 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1880 }
1881
1882 acpi_ram_update(build_state->linker_mr, tables.linker);
1883 acpi_build_tables_cleanup(&tables, true);
1884 }
1885
1886 static void acpi_build_reset(void *build_opaque)
1887 {
1888 AcpiBuildState *build_state = build_opaque;
1889 build_state->patched = 0;
1890 }
1891
1892 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
1893 GArray *blob, const char *name,
1894 uint64_t max_size)
1895 {
1896 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
1897 name, acpi_build_update, build_state);
1898 }
1899
1900 static const VMStateDescription vmstate_acpi_build = {
1901 .name = "acpi_build",
1902 .version_id = 1,
1903 .minimum_version_id = 1,
1904 .fields = (VMStateField[]) {
1905 VMSTATE_UINT8(patched, AcpiBuildState),
1906 VMSTATE_END_OF_LIST()
1907 },
1908 };
1909
1910 void acpi_setup(PcGuestInfo *guest_info)
1911 {
1912 AcpiBuildTables tables;
1913 AcpiBuildState *build_state;
1914
1915 if (!guest_info->fw_cfg) {
1916 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1917 return;
1918 }
1919
1920 if (!guest_info->has_acpi_build) {
1921 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1922 return;
1923 }
1924
1925 if (!acpi_enabled) {
1926 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1927 return;
1928 }
1929
1930 build_state = g_malloc0(sizeof *build_state);
1931
1932 build_state->guest_info = guest_info;
1933
1934 acpi_set_pci_info();
1935
1936 acpi_build_tables_init(&tables);
1937 acpi_build(build_state->guest_info, &tables);
1938
1939 /* Now expose it all to Guest */
1940 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
1941 ACPI_BUILD_TABLE_FILE,
1942 ACPI_BUILD_TABLE_MAX_SIZE);
1943 assert(build_state->table_mr != NULL);
1944
1945 build_state->linker_mr =
1946 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
1947
1948 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
1949 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
1950
1951 if (!guest_info->rsdp_in_ram) {
1952 /*
1953 * Keep for compatibility with old machine types.
1954 * Though RSDP is small, its contents isn't immutable, so
1955 * we'll update it along with the rest of tables on guest access.
1956 */
1957 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
1958
1959 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
1960 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
1961 acpi_build_update, build_state,
1962 build_state->rsdp, rsdp_size);
1963 build_state->rsdp_mr = NULL;
1964 } else {
1965 build_state->rsdp = NULL;
1966 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
1967 ACPI_BUILD_RSDP_FILE, 0);
1968 }
1969
1970 qemu_register_reset(acpi_build_reset, build_state);
1971 acpi_build_reset(build_state);
1972 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
1973
1974 /* Cleanup tables but don't free the memory: we track it
1975 * in build_state.
1976 */
1977 acpi_build_tables_cleanup(&tables, false);
1978 }
CRIS target port of Qemu