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pc: acpi: memhp: move MHPD.MCRS method into SSDT
[qemu/cris-port.git] / target-xtensa / translate.c
blobfbcec945a1aaa1a3565acd841648fd97619fc792
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <stdio.h>
32
33 #include "cpu.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg-op.h"
37 #include "qemu/log.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/cpu_ldst.h"
40 #include "exec/semihost.h"
41
42 #include "exec/helper-proto.h"
43 #include "exec/helper-gen.h"
44
45 #include "trace-tcg.h"
46
47
48 typedef struct DisasContext {
49 const XtensaConfig *config;
50 TranslationBlock *tb;
51 uint32_t pc;
52 uint32_t next_pc;
53 int cring;
54 int ring;
55 uint32_t lbeg;
56 uint32_t lend;
57 TCGv_i32 litbase;
58 int is_jmp;
59 int singlestep_enabled;
60
61 bool sar_5bit;
62 bool sar_m32_5bit;
63 bool sar_m32_allocated;
64 TCGv_i32 sar_m32;
65
66 uint32_t ccount_delta;
67 unsigned window;
68
69 bool debug;
70 bool icount;
71 TCGv_i32 next_icount;
72
73 unsigned cpenable;
74 } DisasContext;
75
76 static TCGv_ptr cpu_env;
77 static TCGv_i32 cpu_pc;
78 static TCGv_i32 cpu_R[16];
79 static TCGv_i32 cpu_FR[16];
80 static TCGv_i32 cpu_SR[256];
81 static TCGv_i32 cpu_UR[256];
82
83 #include "exec/gen-icount.h"
84
85 typedef struct XtensaReg {
86 const char *name;
87 uint64_t opt_bits;
88 enum {
89 SR_R = 1,
90 SR_W = 2,
91 SR_X = 4,
92 SR_RW = 3,
93 SR_RWX = 7,
94 } access;
95 } XtensaReg;
96
97 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
98 .name = (regname), \
99 .opt_bits = XTENSA_OPTION_BIT(opt), \
100 .access = (acc), \
101 }
102
103 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
104
105 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
106 .name = (regname), \
107 .opt_bits = (opt), \
108 .access = (acc), \
109 }
110
111 #define XTENSA_REG_BITS(regname, opt) \
112 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
113
114 static const XtensaReg sregnames[256] = {
115 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
116 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
117 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
118 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
119 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
120 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
121 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
122 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
123 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
124 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
125 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
126 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
127 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
128 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
129 [WINDOW_START] = XTENSA_REG("WINDOW_START",
130 XTENSA_OPTION_WINDOWED_REGISTER),
131 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
132 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
133 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
134 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
135 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
136 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
137 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
138 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
139 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
140 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
141 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
142 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
143 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
144 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
145 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
146 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
147 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
148 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
152 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
153 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
154 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
155 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
157 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
159 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
160 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
161 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
162 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
163 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
164 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
165 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
166 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
167 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
168 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
169 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
170 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
171 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
172 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
173 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
174 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
175 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
176 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
177 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
178 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
179 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
180 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
181 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
182 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
183 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
184 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
185 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
186 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
187 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
188 XTENSA_OPTION_TIMER_INTERRUPT),
189 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
190 XTENSA_OPTION_TIMER_INTERRUPT),
191 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
192 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
193 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
194 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
195 };
196
197 static const XtensaReg uregnames[256] = {
198 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
199 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
200 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
201 };
202
203 void xtensa_translate_init(void)
204 {
205 static const char * const regnames[] = {
206 "ar0", "ar1", "ar2", "ar3",
207 "ar4", "ar5", "ar6", "ar7",
208 "ar8", "ar9", "ar10", "ar11",
209 "ar12", "ar13", "ar14", "ar15",
210 };
211 static const char * const fregnames[] = {
212 "f0", "f1", "f2", "f3",
213 "f4", "f5", "f6", "f7",
214 "f8", "f9", "f10", "f11",
215 "f12", "f13", "f14", "f15",
216 };
217 int i;
218
219 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
220 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
221 offsetof(CPUXtensaState, pc), "pc");
222
223 for (i = 0; i < 16; i++) {
224 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
225 offsetof(CPUXtensaState, regs[i]),
226 regnames[i]);
227 }
228
229 for (i = 0; i < 16; i++) {
230 cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
231 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
232 fregnames[i]);
233 }
234
235 for (i = 0; i < 256; ++i) {
236 if (sregnames[i].name) {
237 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
238 offsetof(CPUXtensaState, sregs[i]),
239 sregnames[i].name);
240 }
241 }
242
243 for (i = 0; i < 256; ++i) {
244 if (uregnames[i].name) {
245 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
246 offsetof(CPUXtensaState, uregs[i]),
247 uregnames[i].name);
248 }
249 }
250 }
251
252 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
253 {
254 return xtensa_option_bits_enabled(dc->config, opt);
255 }
256
257 static inline bool option_enabled(DisasContext *dc, int opt)
258 {
259 return xtensa_option_enabled(dc->config, opt);
260 }
261
262 static void init_litbase(DisasContext *dc)
263 {
264 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
265 dc->litbase = tcg_temp_local_new_i32();
266 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
267 }
268 }
269
270 static void reset_litbase(DisasContext *dc)
271 {
272 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
273 tcg_temp_free(dc->litbase);
274 }
275 }
276
277 static void init_sar_tracker(DisasContext *dc)
278 {
279 dc->sar_5bit = false;
280 dc->sar_m32_5bit = false;
281 dc->sar_m32_allocated = false;
282 }
283
284 static void reset_sar_tracker(DisasContext *dc)
285 {
286 if (dc->sar_m32_allocated) {
287 tcg_temp_free(dc->sar_m32);
288 }
289 }
290
291 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
292 {
293 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
294 if (dc->sar_m32_5bit) {
295 tcg_gen_discard_i32(dc->sar_m32);
296 }
297 dc->sar_5bit = true;
298 dc->sar_m32_5bit = false;
299 }
300
301 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
302 {
303 TCGv_i32 tmp = tcg_const_i32(32);
304 if (!dc->sar_m32_allocated) {
305 dc->sar_m32 = tcg_temp_local_new_i32();
306 dc->sar_m32_allocated = true;
307 }
308 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
309 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
310 dc->sar_5bit = false;
311 dc->sar_m32_5bit = true;
312 tcg_temp_free(tmp);
313 }
314
315 static void gen_advance_ccount(DisasContext *dc)
316 {
317 if (dc->ccount_delta > 0) {
318 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
319 gen_helper_advance_ccount(cpu_env, tmp);
320 tcg_temp_free(tmp);
321 }
322 dc->ccount_delta = 0;
323 }
324
325 static void gen_exception(DisasContext *dc, int excp)
326 {
327 TCGv_i32 tmp = tcg_const_i32(excp);
328 gen_advance_ccount(dc);
329 gen_helper_exception(cpu_env, tmp);
330 tcg_temp_free(tmp);
331 }
332
333 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
334 {
335 TCGv_i32 tpc = tcg_const_i32(dc->pc);
336 TCGv_i32 tcause = tcg_const_i32(cause);
337 gen_advance_ccount(dc);
338 gen_helper_exception_cause(cpu_env, tpc, tcause);
339 tcg_temp_free(tpc);
340 tcg_temp_free(tcause);
341 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
342 cause == SYSCALL_CAUSE) {
343 dc->is_jmp = DISAS_UPDATE;
344 }
345 }
346
347 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
348 TCGv_i32 vaddr)
349 {
350 TCGv_i32 tpc = tcg_const_i32(dc->pc);
351 TCGv_i32 tcause = tcg_const_i32(cause);
352 gen_advance_ccount(dc);
353 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
354 tcg_temp_free(tpc);
355 tcg_temp_free(tcause);
356 }
357
358 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
359 {
360 TCGv_i32 tpc = tcg_const_i32(dc->pc);
361 TCGv_i32 tcause = tcg_const_i32(cause);
362 gen_advance_ccount(dc);
363 gen_helper_debug_exception(cpu_env, tpc, tcause);
364 tcg_temp_free(tpc);
365 tcg_temp_free(tcause);
366 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
367 dc->is_jmp = DISAS_UPDATE;
368 }
369 }
370
371 static bool gen_check_privilege(DisasContext *dc)
372 {
373 if (dc->cring) {
374 gen_exception_cause(dc, PRIVILEGED_CAUSE);
375 dc->is_jmp = DISAS_UPDATE;
376 return false;
377 }
378 return true;
379 }
380
381 static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
382 {
383 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
384 !(dc->cpenable & (1 << cp))) {
385 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
386 dc->is_jmp = DISAS_UPDATE;
387 return false;
388 }
389 return true;
390 }
391
392 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
393 {
394 tcg_gen_mov_i32(cpu_pc, dest);
395 gen_advance_ccount(dc);
396 if (dc->icount) {
397 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
398 }
399 if (dc->singlestep_enabled) {
400 gen_exception(dc, EXCP_DEBUG);
401 } else {
402 if (slot >= 0) {
403 tcg_gen_goto_tb(slot);
404 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
405 } else {
406 tcg_gen_exit_tb(0);
407 }
408 }
409 dc->is_jmp = DISAS_UPDATE;
410 }
411
412 static void gen_jump(DisasContext *dc, TCGv dest)
413 {
414 gen_jump_slot(dc, dest, -1);
415 }
416
417 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
418 {
419 TCGv_i32 tmp = tcg_const_i32(dest);
420 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
421 slot = -1;
422 }
423 gen_jump_slot(dc, tmp, slot);
424 tcg_temp_free(tmp);
425 }
426
427 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
428 int slot)
429 {
430 TCGv_i32 tcallinc = tcg_const_i32(callinc);
431
432 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
433 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
434 tcg_temp_free(tcallinc);
435 tcg_gen_movi_i32(cpu_R[callinc << 2],
436 (callinc << 30) | (dc->next_pc & 0x3fffffff));
437 gen_jump_slot(dc, dest, slot);
438 }
439
440 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
441 {
442 gen_callw_slot(dc, callinc, dest, -1);
443 }
444
445 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
446 {
447 TCGv_i32 tmp = tcg_const_i32(dest);
448 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
449 slot = -1;
450 }
451 gen_callw_slot(dc, callinc, tmp, slot);
452 tcg_temp_free(tmp);
453 }
454
455 static bool gen_check_loop_end(DisasContext *dc, int slot)
456 {
457 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
458 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
459 dc->next_pc == dc->lend) {
460 TCGLabel *label = gen_new_label();
461
462 gen_advance_ccount(dc);
463 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
464 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
465 gen_jumpi(dc, dc->lbeg, slot);
466 gen_set_label(label);
467 gen_jumpi(dc, dc->next_pc, -1);
468 return true;
469 }
470 return false;
471 }
472
473 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
474 {
475 if (!gen_check_loop_end(dc, slot)) {
476 gen_jumpi(dc, dc->next_pc, slot);
477 }
478 }
479
480 static void gen_brcond(DisasContext *dc, TCGCond cond,
481 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
482 {
483 TCGLabel *label = gen_new_label();
484
485 gen_advance_ccount(dc);
486 tcg_gen_brcond_i32(cond, t0, t1, label);
487 gen_jumpi_check_loop_end(dc, 0);
488 gen_set_label(label);
489 gen_jumpi(dc, dc->pc + offset, 1);
490 }
491
492 static void gen_brcondi(DisasContext *dc, TCGCond cond,
493 TCGv_i32 t0, uint32_t t1, uint32_t offset)
494 {
495 TCGv_i32 tmp = tcg_const_i32(t1);
496 gen_brcond(dc, cond, t0, tmp, offset);
497 tcg_temp_free(tmp);
498 }
499
500 static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
501 {
502 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
503 if (sregnames[sr].name) {
504 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name);
505 } else {
506 qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
507 }
508 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
509 return false;
510 } else if (!(sregnames[sr].access & access)) {
511 static const char * const access_text[] = {
512 [SR_R] = "rsr",
513 [SR_W] = "wsr",
514 [SR_X] = "xsr",
515 };
516 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
517 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
518 access_text[access]);
519 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
520 return false;
521 }
522 return true;
523 }
524
525 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
526 {
527 gen_advance_ccount(dc);
528 tcg_gen_mov_i32(d, cpu_SR[sr]);
529 }
530
531 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
532 {
533 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
534 tcg_gen_or_i32(d, d, cpu_SR[sr]);
535 tcg_gen_andi_i32(d, d, 0xfffffffc);
536 }
537
538 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
539 {
540 static void (* const rsr_handler[256])(DisasContext *dc,
541 TCGv_i32 d, uint32_t sr) = {
542 [CCOUNT] = gen_rsr_ccount,
543 [PTEVADDR] = gen_rsr_ptevaddr,
544 };
545
546 if (rsr_handler[sr]) {
547 rsr_handler[sr](dc, d, sr);
548 } else {
549 tcg_gen_mov_i32(d, cpu_SR[sr]);
550 }
551 }
552
553 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
554 {
555 gen_helper_wsr_lbeg(cpu_env, s);
556 gen_jumpi_check_loop_end(dc, 0);
557 }
558
559 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
560 {
561 gen_helper_wsr_lend(cpu_env, s);
562 gen_jumpi_check_loop_end(dc, 0);
563 }
564
565 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
566 {
567 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
568 if (dc->sar_m32_5bit) {
569 tcg_gen_discard_i32(dc->sar_m32);
570 }
571 dc->sar_5bit = false;
572 dc->sar_m32_5bit = false;
573 }
574
575 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
576 {
577 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
578 }
579
580 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
581 {
582 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
583 /* This can change tb->flags, so exit tb */
584 gen_jumpi_check_loop_end(dc, -1);
585 }
586
587 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
588 {
589 tcg_gen_ext8s_i32(cpu_SR[sr], s);
590 }
591
592 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
593 {
594 gen_helper_wsr_windowbase(cpu_env, v);
595 /* This can change tb->flags, so exit tb */
596 gen_jumpi_check_loop_end(dc, -1);
597 }
598
599 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
600 {
601 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
602 /* This can change tb->flags, so exit tb */
603 gen_jumpi_check_loop_end(dc, -1);
604 }
605
606 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
607 {
608 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
609 }
610
611 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
612 {
613 gen_helper_wsr_rasid(cpu_env, v);
614 /* This can change tb->flags, so exit tb */
615 gen_jumpi_check_loop_end(dc, -1);
616 }
617
618 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
619 {
620 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
621 }
622
623 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
624 {
625 gen_helper_wsr_ibreakenable(cpu_env, v);
626 gen_jumpi_check_loop_end(dc, 0);
627 }
628
629 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
630 {
631 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
632 }
633
634 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
635 {
636 unsigned id = sr - IBREAKA;
637
638 if (id < dc->config->nibreak) {
639 TCGv_i32 tmp = tcg_const_i32(id);
640 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
641 tcg_temp_free(tmp);
642 gen_jumpi_check_loop_end(dc, 0);
643 }
644 }
645
646 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
647 {
648 unsigned id = sr - DBREAKA;
649
650 if (id < dc->config->ndbreak) {
651 TCGv_i32 tmp = tcg_const_i32(id);
652 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
653 tcg_temp_free(tmp);
654 }
655 }
656
657 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
658 {
659 unsigned id = sr - DBREAKC;
660
661 if (id < dc->config->ndbreak) {
662 TCGv_i32 tmp = tcg_const_i32(id);
663 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
664 tcg_temp_free(tmp);
665 }
666 }
667
668 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
669 {
670 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
671 /* This can change tb->flags, so exit tb */
672 gen_jumpi_check_loop_end(dc, -1);
673 }
674
675 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
676 {
677 tcg_gen_andi_i32(cpu_SR[sr], v,
678 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
679 gen_helper_check_interrupts(cpu_env);
680 gen_jumpi_check_loop_end(dc, 0);
681 }
682
683 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
684 {
685 TCGv_i32 tmp = tcg_temp_new_i32();
686
687 tcg_gen_andi_i32(tmp, v,
688 dc->config->inttype_mask[INTTYPE_EDGE] |
689 dc->config->inttype_mask[INTTYPE_NMI] |
690 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
691 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
692 tcg_temp_free(tmp);
693 gen_helper_check_interrupts(cpu_env);
694 }
695
696 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
697 {
698 tcg_gen_mov_i32(cpu_SR[sr], v);
699 gen_helper_check_interrupts(cpu_env);
700 gen_jumpi_check_loop_end(dc, 0);
701 }
702
703 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
704 {
705 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
706 PS_UM | PS_EXCM | PS_INTLEVEL;
707
708 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
709 mask |= PS_RING;
710 }
711 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
712 gen_helper_check_interrupts(cpu_env);
713 /* This can change mmu index and tb->flags, so exit tb */
714 gen_jumpi_check_loop_end(dc, -1);
715 }
716
717 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
718 {
719 if (dc->icount) {
720 tcg_gen_mov_i32(dc->next_icount, v);
721 } else {
722 tcg_gen_mov_i32(cpu_SR[sr], v);
723 }
724 }
725
726 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
727 {
728 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
729 /* This can change tb->flags, so exit tb */
730 gen_jumpi_check_loop_end(dc, -1);
731 }
732
733 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
734 {
735 uint32_t id = sr - CCOMPARE;
736 if (id < dc->config->nccompare) {
737 uint32_t int_bit = 1 << dc->config->timerint[id];
738 gen_advance_ccount(dc);
739 tcg_gen_mov_i32(cpu_SR[sr], v);
740 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
741 gen_helper_check_interrupts(cpu_env);
742 }
743 }
744
745 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
746 {
747 static void (* const wsr_handler[256])(DisasContext *dc,
748 uint32_t sr, TCGv_i32 v) = {
749 [LBEG] = gen_wsr_lbeg,
750 [LEND] = gen_wsr_lend,
751 [SAR] = gen_wsr_sar,
752 [BR] = gen_wsr_br,
753 [LITBASE] = gen_wsr_litbase,
754 [ACCHI] = gen_wsr_acchi,
755 [WINDOW_BASE] = gen_wsr_windowbase,
756 [WINDOW_START] = gen_wsr_windowstart,
757 [PTEVADDR] = gen_wsr_ptevaddr,
758 [RASID] = gen_wsr_rasid,
759 [ITLBCFG] = gen_wsr_tlbcfg,
760 [DTLBCFG] = gen_wsr_tlbcfg,
761 [IBREAKENABLE] = gen_wsr_ibreakenable,
762 [ATOMCTL] = gen_wsr_atomctl,
763 [IBREAKA] = gen_wsr_ibreaka,
764 [IBREAKA + 1] = gen_wsr_ibreaka,
765 [DBREAKA] = gen_wsr_dbreaka,
766 [DBREAKA + 1] = gen_wsr_dbreaka,
767 [DBREAKC] = gen_wsr_dbreakc,
768 [DBREAKC + 1] = gen_wsr_dbreakc,
769 [CPENABLE] = gen_wsr_cpenable,
770 [INTSET] = gen_wsr_intset,
771 [INTCLEAR] = gen_wsr_intclear,
772 [INTENABLE] = gen_wsr_intenable,
773 [PS] = gen_wsr_ps,
774 [ICOUNT] = gen_wsr_icount,
775 [ICOUNTLEVEL] = gen_wsr_icountlevel,
776 [CCOMPARE] = gen_wsr_ccompare,
777 [CCOMPARE + 1] = gen_wsr_ccompare,
778 [CCOMPARE + 2] = gen_wsr_ccompare,
779 };
780
781 if (wsr_handler[sr]) {
782 wsr_handler[sr](dc, sr, s);
783 } else {
784 tcg_gen_mov_i32(cpu_SR[sr], s);
785 }
786 }
787
788 static void gen_wur(uint32_t ur, TCGv_i32 s)
789 {
790 switch (ur) {
791 case FCR:
792 gen_helper_wur_fcr(cpu_env, s);
793 break;
794
795 case FSR:
796 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
797 break;
798
799 default:
800 tcg_gen_mov_i32(cpu_UR[ur], s);
801 break;
802 }
803 }
804
805 static void gen_load_store_alignment(DisasContext *dc, int shift,
806 TCGv_i32 addr, bool no_hw_alignment)
807 {
808 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
809 tcg_gen_andi_i32(addr, addr, ~0 << shift);
810 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
811 no_hw_alignment) {
812 TCGLabel *label = gen_new_label();
813 TCGv_i32 tmp = tcg_temp_new_i32();
814 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
815 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
816 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
817 gen_set_label(label);
818 tcg_temp_free(tmp);
819 }
820 }
821
822 static void gen_waiti(DisasContext *dc, uint32_t imm4)
823 {
824 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
825 TCGv_i32 intlevel = tcg_const_i32(imm4);
826 gen_advance_ccount(dc);
827 gen_helper_waiti(cpu_env, pc, intlevel);
828 tcg_temp_free(pc);
829 tcg_temp_free(intlevel);
830 }
831
832 static bool gen_window_check1(DisasContext *dc, unsigned r1)
833 {
834 if (r1 / 4 > dc->window) {
835 TCGv_i32 pc = tcg_const_i32(dc->pc);
836 TCGv_i32 w = tcg_const_i32(r1 / 4);
837
838 gen_advance_ccount(dc);
839 gen_helper_window_check(cpu_env, pc, w);
840 dc->is_jmp = DISAS_UPDATE;
841 return false;
842 }
843 return true;
844 }
845
846 static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
847 {
848 return gen_window_check1(dc, r1 > r2 ? r1 : r2);
849 }
850
851 static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
852 unsigned r3)
853 {
854 return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
855 }
856
857 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
858 {
859 TCGv_i32 m = tcg_temp_new_i32();
860
861 if (hi) {
862 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
863 } else {
864 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
865 }
866 return m;
867 }
868
869 static inline unsigned xtensa_op0_insn_len(unsigned op0)
870 {
871 return op0 >= 8 ? 2 : 3;
872 }
873
874 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
875 {
876 #define HAS_OPTION_BITS(opt) do { \
877 if (!option_bits_enabled(dc, opt)) { \
878 qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \
879 __FILE__, __LINE__); \
880 goto invalid_opcode; \
881 } \
882 } while (0)
883
884 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
885
886 #define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
887 #define RESERVED() do { \
888 qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
889 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
890 goto invalid_opcode; \
891 } while (0)
892
893
894 #ifdef TARGET_WORDS_BIGENDIAN
895 #define OP0 (((b0) & 0xf0) >> 4)
896 #define OP1 (((b2) & 0xf0) >> 4)
897 #define OP2 ((b2) & 0xf)
898 #define RRR_R ((b1) & 0xf)
899 #define RRR_S (((b1) & 0xf0) >> 4)
900 #define RRR_T ((b0) & 0xf)
901 #else
902 #define OP0 (((b0) & 0xf))
903 #define OP1 (((b2) & 0xf))
904 #define OP2 (((b2) & 0xf0) >> 4)
905 #define RRR_R (((b1) & 0xf0) >> 4)
906 #define RRR_S (((b1) & 0xf))
907 #define RRR_T (((b0) & 0xf0) >> 4)
908 #endif
909 #define RRR_X ((RRR_R & 0x4) >> 2)
910 #define RRR_Y ((RRR_T & 0x4) >> 2)
911 #define RRR_W (RRR_R & 0x3)
912
913 #define RRRN_R RRR_R
914 #define RRRN_S RRR_S
915 #define RRRN_T RRR_T
916
917 #define RRI4_R RRR_R
918 #define RRI4_S RRR_S
919 #define RRI4_T RRR_T
920 #ifdef TARGET_WORDS_BIGENDIAN
921 #define RRI4_IMM4 ((b2) & 0xf)
922 #else
923 #define RRI4_IMM4 (((b2) & 0xf0) >> 4)
924 #endif
925
926 #define RRI8_R RRR_R
927 #define RRI8_S RRR_S
928 #define RRI8_T RRR_T
929 #define RRI8_IMM8 (b2)
930 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
931
932 #ifdef TARGET_WORDS_BIGENDIAN
933 #define RI16_IMM16 (((b1) << 8) | (b2))
934 #else
935 #define RI16_IMM16 (((b2) << 8) | (b1))
936 #endif
937
938 #ifdef TARGET_WORDS_BIGENDIAN
939 #define CALL_N (((b0) & 0xc) >> 2)
940 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
941 #else
942 #define CALL_N (((b0) & 0x30) >> 4)
943 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
944 #endif
945 #define CALL_OFFSET_SE \
946 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
947
948 #define CALLX_N CALL_N
949 #ifdef TARGET_WORDS_BIGENDIAN
950 #define CALLX_M ((b0) & 0x3)
951 #else
952 #define CALLX_M (((b0) & 0xc0) >> 6)
953 #endif
954 #define CALLX_S RRR_S
955
956 #define BRI12_M CALLX_M
957 #define BRI12_S RRR_S
958 #ifdef TARGET_WORDS_BIGENDIAN
959 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
960 #else
961 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
962 #endif
963 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
964
965 #define BRI8_M BRI12_M
966 #define BRI8_R RRI8_R
967 #define BRI8_S RRI8_S
968 #define BRI8_IMM8 RRI8_IMM8
969 #define BRI8_IMM8_SE RRI8_IMM8_SE
970
971 #define RSR_SR (b1)
972
973 uint8_t b0 = cpu_ldub_code(env, dc->pc);
974 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
975 uint8_t b2 = 0;
976 unsigned len = xtensa_op0_insn_len(OP0);
977
978 static const uint32_t B4CONST[] = {
979 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
980 };
981
982 static const uint32_t B4CONSTU[] = {
983 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
984 };
985
986 switch (len) {
987 case 2:
988 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
989 break;
990
991 case 3:
992 b2 = cpu_ldub_code(env, dc->pc + 2);
993 break;
994
995 default:
996 RESERVED();
997 }
998 dc->next_pc = dc->pc + len;
999
1000 switch (OP0) {
1001 case 0: /*QRST*/
1002 switch (OP1) {
1003 case 0: /*RST0*/
1004 switch (OP2) {
1005 case 0: /*ST0*/
1006 if ((RRR_R & 0xc) == 0x8) {
1007 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1008 }
1009
1010 switch (RRR_R) {
1011 case 0: /*SNM0*/
1012 switch (CALLX_M) {
1013 case 0: /*ILL*/
1014 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1015 break;
1016
1017 case 1: /*reserved*/
1018 RESERVED();
1019 break;
1020
1021 case 2: /*JR*/
1022 switch (CALLX_N) {
1023 case 0: /*RET*/
1024 case 2: /*JX*/
1025 if (gen_window_check1(dc, CALLX_S)) {
1026 gen_jump(dc, cpu_R[CALLX_S]);
1027 }
1028 break;
1029
1030 case 1: /*RETWw*/
1031 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1032 {
1033 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1034 gen_advance_ccount(dc);
1035 gen_helper_retw(tmp, cpu_env, tmp);
1036 gen_jump(dc, tmp);
1037 tcg_temp_free(tmp);
1038 }
1039 break;
1040
1041 case 3: /*reserved*/
1042 RESERVED();
1043 break;
1044 }
1045 break;
1046
1047 case 3: /*CALLX*/
1048 if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) {
1049 break;
1050 }
1051 switch (CALLX_N) {
1052 case 0: /*CALLX0*/
1053 {
1054 TCGv_i32 tmp = tcg_temp_new_i32();
1055 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1056 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1057 gen_jump(dc, tmp);
1058 tcg_temp_free(tmp);
1059 }
1060 break;
1061
1062 case 1: /*CALLX4w*/
1063 case 2: /*CALLX8w*/
1064 case 3: /*CALLX12w*/
1065 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1066 {
1067 TCGv_i32 tmp = tcg_temp_new_i32();
1068
1069 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1070 gen_callw(dc, CALLX_N, tmp);
1071 tcg_temp_free(tmp);
1072 }
1073 break;
1074 }
1075 break;
1076 }
1077 break;
1078
1079 case 1: /*MOVSPw*/
1080 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1081 if (gen_window_check2(dc, RRR_T, RRR_S)) {
1082 TCGv_i32 pc = tcg_const_i32(dc->pc);
1083 gen_advance_ccount(dc);
1084 gen_helper_movsp(cpu_env, pc);
1085 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1086 tcg_temp_free(pc);
1087 }
1088 break;
1089
1090 case 2: /*SYNC*/
1091 switch (RRR_T) {
1092 case 0: /*ISYNC*/
1093 break;
1094
1095 case 1: /*RSYNC*/
1096 break;
1097
1098 case 2: /*ESYNC*/
1099 break;
1100
1101 case 3: /*DSYNC*/
1102 break;
1103
1104 case 8: /*EXCW*/
1105 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1106 break;
1107
1108 case 12: /*MEMW*/
1109 break;
1110
1111 case 13: /*EXTW*/
1112 break;
1113
1114 case 15: /*NOP*/
1115 break;
1116
1117 default: /*reserved*/
1118 RESERVED();
1119 break;
1120 }
1121 break;
1122
1123 case 3: /*RFEIx*/
1124 switch (RRR_T) {
1125 case 0: /*RFETx*/
1126 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1127 switch (RRR_S) {
1128 case 0: /*RFEx*/
1129 if (gen_check_privilege(dc)) {
1130 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1131 gen_helper_check_interrupts(cpu_env);
1132 gen_jump(dc, cpu_SR[EPC1]);
1133 }
1134 break;
1135
1136 case 1: /*RFUEx*/
1137 RESERVED();
1138 break;
1139
1140 case 2: /*RFDEx*/
1141 if (gen_check_privilege(dc)) {
1142 gen_jump(dc, cpu_SR[
1143 dc->config->ndepc ? DEPC : EPC1]);
1144 }
1145 break;
1146
1147 case 4: /*RFWOw*/
1148 case 5: /*RFWUw*/
1149 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1150 if (gen_check_privilege(dc)) {
1151 TCGv_i32 tmp = tcg_const_i32(1);
1152
1153 tcg_gen_andi_i32(
1154 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1155 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1156
1157 if (RRR_S == 4) {
1158 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1159 cpu_SR[WINDOW_START], tmp);
1160 } else {
1161 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1162 cpu_SR[WINDOW_START], tmp);
1163 }
1164
1165 gen_helper_restore_owb(cpu_env);
1166 gen_helper_check_interrupts(cpu_env);
1167 gen_jump(dc, cpu_SR[EPC1]);
1168
1169 tcg_temp_free(tmp);
1170 }
1171 break;
1172
1173 default: /*reserved*/
1174 RESERVED();
1175 break;
1176 }
1177 break;
1178
1179 case 1: /*RFIx*/
1180 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1181 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1182 if (gen_check_privilege(dc)) {
1183 tcg_gen_mov_i32(cpu_SR[PS],
1184 cpu_SR[EPS2 + RRR_S - 2]);
1185 gen_helper_check_interrupts(cpu_env);
1186 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1187 }
1188 } else {
1189 qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S);
1190 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1191 }
1192 break;
1193
1194 case 2: /*RFME*/
1195 TBD();
1196 break;
1197
1198 default: /*reserved*/
1199 RESERVED();
1200 break;
1201
1202 }
1203 break;
1204
1205 case 4: /*BREAKx*/
1206 HAS_OPTION(XTENSA_OPTION_DEBUG);
1207 if (dc->debug) {
1208 gen_debug_exception(dc, DEBUGCAUSE_BI);
1209 }
1210 break;
1211
1212 case 5: /*SYSCALLx*/
1213 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1214 switch (RRR_S) {
1215 case 0: /*SYSCALLx*/
1216 gen_exception_cause(dc, SYSCALL_CAUSE);
1217 break;
1218
1219 case 1: /*SIMCALL*/
1220 if (semihosting_enabled()) {
1221 if (gen_check_privilege(dc)) {
1222 gen_helper_simcall(cpu_env);
1223 }
1224 } else {
1225 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
1226 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1227 }
1228 break;
1229
1230 default:
1231 RESERVED();
1232 break;
1233 }
1234 break;
1235
1236 case 6: /*RSILx*/
1237 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1238 if (gen_check_privilege(dc) &&
1239 gen_window_check1(dc, RRR_T)) {
1240 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1241 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1242 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1243 gen_helper_check_interrupts(cpu_env);
1244 gen_jumpi_check_loop_end(dc, 0);
1245 }
1246 break;
1247
1248 case 7: /*WAITIx*/
1249 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1250 if (gen_check_privilege(dc)) {
1251 gen_waiti(dc, RRR_S);
1252 }
1253 break;
1254
1255 case 8: /*ANY4p*/
1256 case 9: /*ALL4p*/
1257 case 10: /*ANY8p*/
1258 case 11: /*ALL8p*/
1259 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1260 {
1261 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1262 TCGv_i32 mask = tcg_const_i32(
1263 ((1 << shift) - 1) << RRR_S);
1264 TCGv_i32 tmp = tcg_temp_new_i32();
1265
1266 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1267 if (RRR_R & 1) { /*ALL*/
1268 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1269 } else { /*ANY*/
1270 tcg_gen_add_i32(tmp, tmp, mask);
1271 }
1272 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1273 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1274 tmp, RRR_T, 1);
1275 tcg_temp_free(mask);
1276 tcg_temp_free(tmp);
1277 }
1278 break;
1279
1280 default: /*reserved*/
1281 RESERVED();
1282 break;
1283
1284 }
1285 break;
1286
1287 case 1: /*AND*/
1288 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1289 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1290 }
1291 break;
1292
1293 case 2: /*OR*/
1294 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1295 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1296 }
1297 break;
1298
1299 case 3: /*XOR*/
1300 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1301 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1302 }
1303 break;
1304
1305 case 4: /*ST1*/
1306 switch (RRR_R) {
1307 case 0: /*SSR*/
1308 if (gen_window_check1(dc, RRR_S)) {
1309 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1310 }
1311 break;
1312
1313 case 1: /*SSL*/
1314 if (gen_window_check1(dc, RRR_S)) {
1315 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1316 }
1317 break;
1318
1319 case 2: /*SSA8L*/
1320 if (gen_window_check1(dc, RRR_S)) {
1321 TCGv_i32 tmp = tcg_temp_new_i32();
1322 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1323 gen_right_shift_sar(dc, tmp);
1324 tcg_temp_free(tmp);
1325 }
1326 break;
1327
1328 case 3: /*SSA8B*/
1329 if (gen_window_check1(dc, RRR_S)) {
1330 TCGv_i32 tmp = tcg_temp_new_i32();
1331 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1332 gen_left_shift_sar(dc, tmp);
1333 tcg_temp_free(tmp);
1334 }
1335 break;
1336
1337 case 4: /*SSAI*/
1338 {
1339 TCGv_i32 tmp = tcg_const_i32(
1340 RRR_S | ((RRR_T & 1) << 4));
1341 gen_right_shift_sar(dc, tmp);
1342 tcg_temp_free(tmp);
1343 }
1344 break;
1345
1346 case 6: /*RER*/
1347 TBD();
1348 break;
1349
1350 case 7: /*WER*/
1351 TBD();
1352 break;
1353
1354 case 8: /*ROTWw*/
1355 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1356 if (gen_check_privilege(dc)) {
1357 TCGv_i32 tmp = tcg_const_i32(
1358 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1359 gen_helper_rotw(cpu_env, tmp);
1360 tcg_temp_free(tmp);
1361 /* This can change tb->flags, so exit tb */
1362 gen_jumpi_check_loop_end(dc, -1);
1363 }
1364 break;
1365
1366 case 14: /*NSAu*/
1367 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1368 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1369 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1370 }
1371 break;
1372
1373 case 15: /*NSAUu*/
1374 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1375 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1376 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1377 }
1378 break;
1379
1380 default: /*reserved*/
1381 RESERVED();
1382 break;
1383 }
1384 break;
1385
1386 case 5: /*TLB*/
1387 HAS_OPTION_BITS(
1388 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1389 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1390 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1391 if (gen_check_privilege(dc) &&
1392 gen_window_check2(dc, RRR_S, RRR_T)) {
1393 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1394
1395 switch (RRR_R & 7) {
1396 case 3: /*RITLB0*/ /*RDTLB0*/
1397 gen_helper_rtlb0(cpu_R[RRR_T],
1398 cpu_env, cpu_R[RRR_S], dtlb);
1399 break;
1400
1401 case 4: /*IITLB*/ /*IDTLB*/
1402 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1403 /* This could change memory mapping, so exit tb */
1404 gen_jumpi_check_loop_end(dc, -1);
1405 break;
1406
1407 case 5: /*PITLB*/ /*PDTLB*/
1408 tcg_gen_movi_i32(cpu_pc, dc->pc);
1409 gen_helper_ptlb(cpu_R[RRR_T],
1410 cpu_env, cpu_R[RRR_S], dtlb);
1411 break;
1412
1413 case 6: /*WITLB*/ /*WDTLB*/
1414 gen_helper_wtlb(
1415 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1416 /* This could change memory mapping, so exit tb */
1417 gen_jumpi_check_loop_end(dc, -1);
1418 break;
1419
1420 case 7: /*RITLB1*/ /*RDTLB1*/
1421 gen_helper_rtlb1(cpu_R[RRR_T],
1422 cpu_env, cpu_R[RRR_S], dtlb);
1423 break;
1424
1425 default:
1426 tcg_temp_free(dtlb);
1427 RESERVED();
1428 break;
1429 }
1430 tcg_temp_free(dtlb);
1431 }
1432 break;
1433
1434 case 6: /*RT0*/
1435 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1436 break;
1437 }
1438 switch (RRR_S) {
1439 case 0: /*NEG*/
1440 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1441 break;
1442
1443 case 1: /*ABS*/
1444 {
1445 TCGv_i32 zero = tcg_const_i32(0);
1446 TCGv_i32 neg = tcg_temp_new_i32();
1447
1448 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1449 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1450 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1451 tcg_temp_free(neg);
1452 tcg_temp_free(zero);
1453 }
1454 break;
1455
1456 default: /*reserved*/
1457 RESERVED();
1458 break;
1459 }
1460 break;
1461
1462 case 7: /*reserved*/
1463 RESERVED();
1464 break;
1465
1466 case 8: /*ADD*/
1467 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1468 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1469 }
1470 break;
1471
1472 case 9: /*ADD**/
1473 case 10:
1474 case 11:
1475 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1476 TCGv_i32 tmp = tcg_temp_new_i32();
1477 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1478 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1479 tcg_temp_free(tmp);
1480 }
1481 break;
1482
1483 case 12: /*SUB*/
1484 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1485 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1486 }
1487 break;
1488
1489 case 13: /*SUB**/
1490 case 14:
1491 case 15:
1492 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1493 TCGv_i32 tmp = tcg_temp_new_i32();
1494 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1495 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1496 tcg_temp_free(tmp);
1497 }
1498 break;
1499 }
1500 break;
1501
1502 case 1: /*RST1*/
1503 switch (OP2) {
1504 case 0: /*SLLI*/
1505 case 1:
1506 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1507 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1508 32 - (RRR_T | ((OP2 & 1) << 4)));
1509 }
1510 break;
1511
1512 case 2: /*SRAI*/
1513 case 3:
1514 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1515 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1516 RRR_S | ((OP2 & 1) << 4));
1517 }
1518 break;
1519
1520 case 4: /*SRLI*/
1521 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1522 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1523 }
1524 break;
1525
1526 case 6: /*XSR*/
1527 if (gen_check_sr(dc, RSR_SR, SR_X) &&
1528 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1529 gen_window_check1(dc, RRR_T)) {
1530 TCGv_i32 tmp = tcg_temp_new_i32();
1531
1532 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1533 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1534 gen_wsr(dc, RSR_SR, tmp);
1535 tcg_temp_free(tmp);
1536 }
1537 break;
1538
1539 /*
1540 * Note: 64 bit ops are used here solely because SAR values
1541 * have range 0..63
1542 */
1543 #define gen_shift_reg(cmd, reg) do { \
1544 TCGv_i64 tmp = tcg_temp_new_i64(); \
1545 tcg_gen_extu_i32_i64(tmp, reg); \
1546 tcg_gen_##cmd##_i64(v, v, tmp); \
1547 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \
1548 tcg_temp_free_i64(v); \
1549 tcg_temp_free_i64(tmp); \
1550 } while (0)
1551
1552 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1553
1554 case 8: /*SRC*/
1555 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1556 TCGv_i64 v = tcg_temp_new_i64();
1557 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1558 gen_shift(shr);
1559 }
1560 break;
1561
1562 case 9: /*SRL*/
1563 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1564 break;
1565 }
1566 if (dc->sar_5bit) {
1567 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1568 } else {
1569 TCGv_i64 v = tcg_temp_new_i64();
1570 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1571 gen_shift(shr);
1572 }
1573 break;
1574
1575 case 10: /*SLL*/
1576 if (!gen_window_check2(dc, RRR_R, RRR_S)) {
1577 break;
1578 }
1579 if (dc->sar_m32_5bit) {
1580 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1581 } else {
1582 TCGv_i64 v = tcg_temp_new_i64();
1583 TCGv_i32 s = tcg_const_i32(32);
1584 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1585 tcg_gen_andi_i32(s, s, 0x3f);
1586 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1587 gen_shift_reg(shl, s);
1588 tcg_temp_free(s);
1589 }
1590 break;
1591
1592 case 11: /*SRA*/
1593 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1594 break;
1595 }
1596 if (dc->sar_5bit) {
1597 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1598 } else {
1599 TCGv_i64 v = tcg_temp_new_i64();
1600 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1601 gen_shift(sar);
1602 }
1603 break;
1604 #undef gen_shift
1605 #undef gen_shift_reg
1606
1607 case 12: /*MUL16U*/
1608 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1609 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1610 TCGv_i32 v1 = tcg_temp_new_i32();
1611 TCGv_i32 v2 = tcg_temp_new_i32();
1612 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1613 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1614 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1615 tcg_temp_free(v2);
1616 tcg_temp_free(v1);
1617 }
1618 break;
1619
1620 case 13: /*MUL16S*/
1621 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1622 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1623 TCGv_i32 v1 = tcg_temp_new_i32();
1624 TCGv_i32 v2 = tcg_temp_new_i32();
1625 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1626 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1627 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1628 tcg_temp_free(v2);
1629 tcg_temp_free(v1);
1630 }
1631 break;
1632
1633 default: /*reserved*/
1634 RESERVED();
1635 break;
1636 }
1637 break;
1638
1639 case 2: /*RST2*/
1640 if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1641 break;
1642 }
1643
1644 if (OP2 >= 12) {
1645 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1646 TCGLabel *label = gen_new_label();
1647 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1648 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1649 gen_set_label(label);
1650 }
1651
1652 switch (OP2) {
1653 #define BOOLEAN_LOGIC(fn, r, s, t) \
1654 do { \
1655 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1656 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1657 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1658 \
1659 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1660 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1661 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1662 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1663 tcg_temp_free(tmp1); \
1664 tcg_temp_free(tmp2); \
1665 } while (0)
1666
1667 case 0: /*ANDBp*/
1668 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1669 break;
1670
1671 case 1: /*ANDBCp*/
1672 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1673 break;
1674
1675 case 2: /*ORBp*/
1676 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1677 break;
1678
1679 case 3: /*ORBCp*/
1680 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1681 break;
1682
1683 case 4: /*XORBp*/
1684 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1685 break;
1686
1687 #undef BOOLEAN_LOGIC
1688
1689 case 8: /*MULLi*/
1690 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1691 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1692 break;
1693
1694 case 10: /*MULUHi*/
1695 case 11: /*MULSHi*/
1696 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1697 {
1698 TCGv lo = tcg_temp_new();
1699
1700 if (OP2 == 10) {
1701 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1702 cpu_R[RRR_S], cpu_R[RRR_T]);
1703 } else {
1704 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1705 cpu_R[RRR_S], cpu_R[RRR_T]);
1706 }
1707 tcg_temp_free(lo);
1708 }
1709 break;
1710
1711 case 12: /*QUOUi*/
1712 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1713 break;
1714
1715 case 13: /*QUOSi*/
1716 case 15: /*REMSi*/
1717 {
1718 TCGLabel *label1 = gen_new_label();
1719 TCGLabel *label2 = gen_new_label();
1720
1721 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1722 label1);
1723 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1724 label1);
1725 tcg_gen_movi_i32(cpu_R[RRR_R],
1726 OP2 == 13 ? 0x80000000 : 0);
1727 tcg_gen_br(label2);
1728 gen_set_label(label1);
1729 if (OP2 == 13) {
1730 tcg_gen_div_i32(cpu_R[RRR_R],
1731 cpu_R[RRR_S], cpu_R[RRR_T]);
1732 } else {
1733 tcg_gen_rem_i32(cpu_R[RRR_R],
1734 cpu_R[RRR_S], cpu_R[RRR_T]);
1735 }
1736 gen_set_label(label2);
1737 }
1738 break;
1739
1740 case 14: /*REMUi*/
1741 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1742 break;
1743
1744 default: /*reserved*/
1745 RESERVED();
1746 break;
1747 }
1748 break;
1749
1750 case 3: /*RST3*/
1751 switch (OP2) {
1752 case 0: /*RSR*/
1753 if (gen_check_sr(dc, RSR_SR, SR_R) &&
1754 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1755 gen_window_check1(dc, RRR_T)) {
1756 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1757 }
1758 break;
1759
1760 case 1: /*WSR*/
1761 if (gen_check_sr(dc, RSR_SR, SR_W) &&
1762 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1763 gen_window_check1(dc, RRR_T)) {
1764 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1765 }
1766 break;
1767
1768 case 2: /*SEXTu*/
1769 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1770 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1771 int shift = 24 - RRR_T;
1772
1773 if (shift == 24) {
1774 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1775 } else if (shift == 16) {
1776 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1777 } else {
1778 TCGv_i32 tmp = tcg_temp_new_i32();
1779 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1780 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1781 tcg_temp_free(tmp);
1782 }
1783 }
1784 break;
1785
1786 case 3: /*CLAMPSu*/
1787 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1788 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1789 TCGv_i32 tmp1 = tcg_temp_new_i32();
1790 TCGv_i32 tmp2 = tcg_temp_new_i32();
1791 TCGv_i32 zero = tcg_const_i32(0);
1792
1793 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1794 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1795 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1796
1797 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1798 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
1799
1800 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1801 cpu_R[RRR_S], tmp1);
1802 tcg_temp_free(tmp1);
1803 tcg_temp_free(tmp2);
1804 tcg_temp_free(zero);
1805 }
1806 break;
1807
1808 case 4: /*MINu*/
1809 case 5: /*MAXu*/
1810 case 6: /*MINUu*/
1811 case 7: /*MAXUu*/
1812 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1813 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1814 static const TCGCond cond[] = {
1815 TCG_COND_LE,
1816 TCG_COND_GE,
1817 TCG_COND_LEU,
1818 TCG_COND_GEU
1819 };
1820 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1821 cpu_R[RRR_S], cpu_R[RRR_T],
1822 cpu_R[RRR_S], cpu_R[RRR_T]);
1823 }
1824 break;
1825
1826 case 8: /*MOVEQZ*/
1827 case 9: /*MOVNEZ*/
1828 case 10: /*MOVLTZ*/
1829 case 11: /*MOVGEZ*/
1830 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1831 static const TCGCond cond[] = {
1832 TCG_COND_EQ,
1833 TCG_COND_NE,
1834 TCG_COND_LT,
1835 TCG_COND_GE,
1836 };
1837 TCGv_i32 zero = tcg_const_i32(0);
1838
1839 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1840 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1841 tcg_temp_free(zero);
1842 }
1843 break;
1844
1845 case 12: /*MOVFp*/
1846 case 13: /*MOVTp*/
1847 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1848 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1849 TCGv_i32 zero = tcg_const_i32(0);
1850 TCGv_i32 tmp = tcg_temp_new_i32();
1851
1852 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1853 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1854 cpu_R[RRR_R], tmp, zero,
1855 cpu_R[RRR_S], cpu_R[RRR_R]);
1856
1857 tcg_temp_free(tmp);
1858 tcg_temp_free(zero);
1859 }
1860 break;
1861
1862 case 14: /*RUR*/
1863 if (gen_window_check1(dc, RRR_R)) {
1864 int st = (RRR_S << 4) + RRR_T;
1865 if (uregnames[st].name) {
1866 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1867 } else {
1868 qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st);
1869 TBD();
1870 }
1871 }
1872 break;
1873
1874 case 15: /*WUR*/
1875 if (gen_window_check1(dc, RRR_T)) {
1876 if (uregnames[RSR_SR].name) {
1877 gen_wur(RSR_SR, cpu_R[RRR_T]);
1878 } else {
1879 qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR);
1880 TBD();
1881 }
1882 }
1883 break;
1884
1885 }
1886 break;
1887
1888 case 4: /*EXTUI*/
1889 case 5:
1890 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1891 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1892 int maskimm = (1 << (OP2 + 1)) - 1;
1893
1894 TCGv_i32 tmp = tcg_temp_new_i32();
1895 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1896 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1897 tcg_temp_free(tmp);
1898 }
1899 break;
1900
1901 case 6: /*CUST0*/
1902 RESERVED();
1903 break;
1904
1905 case 7: /*CUST1*/
1906 RESERVED();
1907 break;
1908
1909 case 8: /*LSCXp*/
1910 switch (OP2) {
1911 case 0: /*LSXf*/
1912 case 1: /*LSXUf*/
1913 case 4: /*SSXf*/
1914 case 5: /*SSXUf*/
1915 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1916 if (gen_window_check2(dc, RRR_S, RRR_T) &&
1917 gen_check_cpenable(dc, 0)) {
1918 TCGv_i32 addr = tcg_temp_new_i32();
1919 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1920 gen_load_store_alignment(dc, 2, addr, false);
1921 if (OP2 & 0x4) {
1922 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1923 } else {
1924 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1925 }
1926 if (OP2 & 0x1) {
1927 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1928 }
1929 tcg_temp_free(addr);
1930 }
1931 break;
1932
1933 default: /*reserved*/
1934 RESERVED();
1935 break;
1936 }
1937 break;
1938
1939 case 9: /*LSC4*/
1940 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1941 break;
1942 }
1943 switch (OP2) {
1944 case 0: /*L32E*/
1945 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1946 if (gen_check_privilege(dc) &&
1947 gen_window_check2(dc, RRR_S, RRR_T)) {
1948 TCGv_i32 addr = tcg_temp_new_i32();
1949 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1950 (0xffffffc0 | (RRR_R << 2)));
1951 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1952 tcg_temp_free(addr);
1953 }
1954 break;
1955
1956 case 4: /*S32E*/
1957 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1958 if (gen_check_privilege(dc) &&
1959 gen_window_check2(dc, RRR_S, RRR_T)) {
1960 TCGv_i32 addr = tcg_temp_new_i32();
1961 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1962 (0xffffffc0 | (RRR_R << 2)));
1963 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1964 tcg_temp_free(addr);
1965 }
1966 break;
1967
1968 case 5: /*S32N*/
1969 if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
1970 TCGv_i32 addr = tcg_temp_new_i32();
1971
1972 tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
1973 gen_load_store_alignment(dc, 2, addr, false);
1974 tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
1975 tcg_temp_free(addr);
1976 }
1977 break;
1978
1979 default:
1980 RESERVED();
1981 break;
1982 }
1983 break;
1984
1985 case 10: /*FP0*/
1986 /*DEPBITS*/
1987 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
1988 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1989 break;
1990 }
1991 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
1992 OP2, RRR_R + 1);
1993 break;
1994 }
1995
1996 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1997 switch (OP2) {
1998 case 0: /*ADD.Sf*/
1999 if (gen_check_cpenable(dc, 0)) {
2000 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
2001 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2002 }
2003 break;
2004
2005 case 1: /*SUB.Sf*/
2006 if (gen_check_cpenable(dc, 0)) {
2007 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
2008 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2009 }
2010 break;
2011
2012 case 2: /*MUL.Sf*/
2013 if (gen_check_cpenable(dc, 0)) {
2014 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
2015 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2016 }
2017 break;
2018
2019 case 4: /*MADD.Sf*/
2020 if (gen_check_cpenable(dc, 0)) {
2021 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
2022 cpu_FR[RRR_R], cpu_FR[RRR_S],
2023 cpu_FR[RRR_T]);
2024 }
2025 break;
2026
2027 case 5: /*MSUB.Sf*/
2028 if (gen_check_cpenable(dc, 0)) {
2029 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2030 cpu_FR[RRR_R], cpu_FR[RRR_S],
2031 cpu_FR[RRR_T]);
2032 }
2033 break;
2034
2035 case 8: /*ROUND.Sf*/
2036 case 9: /*TRUNC.Sf*/
2037 case 10: /*FLOOR.Sf*/
2038 case 11: /*CEIL.Sf*/
2039 case 14: /*UTRUNC.Sf*/
2040 if (gen_window_check1(dc, RRR_R) &&
2041 gen_check_cpenable(dc, 0)) {
2042 static const unsigned rounding_mode_const[] = {
2043 float_round_nearest_even,
2044 float_round_to_zero,
2045 float_round_down,
2046 float_round_up,
2047 [6] = float_round_to_zero,
2048 };
2049 TCGv_i32 rounding_mode = tcg_const_i32(
2050 rounding_mode_const[OP2 & 7]);
2051 TCGv_i32 scale = tcg_const_i32(RRR_T);
2052
2053 if (OP2 == 14) {
2054 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2055 rounding_mode, scale);
2056 } else {
2057 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2058 rounding_mode, scale);
2059 }
2060
2061 tcg_temp_free(rounding_mode);
2062 tcg_temp_free(scale);
2063 }
2064 break;
2065
2066 case 12: /*FLOAT.Sf*/
2067 case 13: /*UFLOAT.Sf*/
2068 if (gen_window_check1(dc, RRR_S) &&
2069 gen_check_cpenable(dc, 0)) {
2070 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2071
2072 if (OP2 == 13) {
2073 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2074 cpu_R[RRR_S], scale);
2075 } else {
2076 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2077 cpu_R[RRR_S], scale);
2078 }
2079 tcg_temp_free(scale);
2080 }
2081 break;
2082
2083 case 15: /*FP1OP*/
2084 switch (RRR_T) {
2085 case 0: /*MOV.Sf*/
2086 if (gen_check_cpenable(dc, 0)) {
2087 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2088 }
2089 break;
2090
2091 case 1: /*ABS.Sf*/
2092 if (gen_check_cpenable(dc, 0)) {
2093 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2094 }
2095 break;
2096
2097 case 4: /*RFRf*/
2098 if (gen_window_check1(dc, RRR_R) &&
2099 gen_check_cpenable(dc, 0)) {
2100 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2101 }
2102 break;
2103
2104 case 5: /*WFRf*/
2105 if (gen_window_check1(dc, RRR_S) &&
2106 gen_check_cpenable(dc, 0)) {
2107 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2108 }
2109 break;
2110
2111 case 6: /*NEG.Sf*/
2112 if (gen_check_cpenable(dc, 0)) {
2113 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2114 }
2115 break;
2116
2117 default: /*reserved*/
2118 RESERVED();
2119 break;
2120 }
2121 break;
2122
2123 default: /*reserved*/
2124 RESERVED();
2125 break;
2126 }
2127 break;
2128
2129 case 11: /*FP1*/
2130 /*DEPBITS*/
2131 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
2132 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2133 break;
2134 }
2135 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
2136 OP2 + 16, RRR_R + 1);
2137 break;
2138 }
2139
2140 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2141
2142 #define gen_compare(rel, br, a, b) \
2143 do { \
2144 if (gen_check_cpenable(dc, 0)) { \
2145 TCGv_i32 bit = tcg_const_i32(1 << br); \
2146 \
2147 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2148 tcg_temp_free(bit); \
2149 } \
2150 } while (0)
2151
2152 switch (OP2) {
2153 case 1: /*UN.Sf*/
2154 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2155 break;
2156
2157 case 2: /*OEQ.Sf*/
2158 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2159 break;
2160
2161 case 3: /*UEQ.Sf*/
2162 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2163 break;
2164
2165 case 4: /*OLT.Sf*/
2166 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2167 break;
2168
2169 case 5: /*ULT.Sf*/
2170 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2171 break;
2172
2173 case 6: /*OLE.Sf*/
2174 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2175 break;
2176
2177 case 7: /*ULE.Sf*/
2178 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2179 break;
2180
2181 #undef gen_compare
2182
2183 case 8: /*MOVEQZ.Sf*/
2184 case 9: /*MOVNEZ.Sf*/
2185 case 10: /*MOVLTZ.Sf*/
2186 case 11: /*MOVGEZ.Sf*/
2187 if (gen_window_check1(dc, RRR_T) &&
2188 gen_check_cpenable(dc, 0)) {
2189 static const TCGCond cond[] = {
2190 TCG_COND_EQ,
2191 TCG_COND_NE,
2192 TCG_COND_LT,
2193 TCG_COND_GE,
2194 };
2195 TCGv_i32 zero = tcg_const_i32(0);
2196
2197 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2198 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2199 tcg_temp_free(zero);
2200 }
2201 break;
2202
2203 case 12: /*MOVF.Sf*/
2204 case 13: /*MOVT.Sf*/
2205 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2206 if (gen_check_cpenable(dc, 0)) {
2207 TCGv_i32 zero = tcg_const_i32(0);
2208 TCGv_i32 tmp = tcg_temp_new_i32();
2209
2210 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2211 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2212 cpu_FR[RRR_R], tmp, zero,
2213 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2214
2215 tcg_temp_free(tmp);
2216 tcg_temp_free(zero);
2217 }
2218 break;
2219
2220 default: /*reserved*/
2221 RESERVED();
2222 break;
2223 }
2224 break;
2225
2226 default: /*reserved*/
2227 RESERVED();
2228 break;
2229 }
2230 break;
2231
2232 case 1: /*L32R*/
2233 if (gen_window_check1(dc, RRR_T)) {
2234 TCGv_i32 tmp = tcg_const_i32(
2235 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2236 0 : ((dc->pc + 3) & ~3)) +
2237 (0xfffc0000 | (RI16_IMM16 << 2)));
2238
2239 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2240 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2241 }
2242 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
2243 tcg_temp_free(tmp);
2244 }
2245 break;
2246
2247 case 2: /*LSAI*/
2248 #define gen_load_store(type, shift) do { \
2249 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2250 TCGv_i32 addr = tcg_temp_new_i32(); \
2251 \
2252 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2253 if (shift) { \
2254 gen_load_store_alignment(dc, shift, addr, false); \
2255 } \
2256 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2257 tcg_temp_free(addr); \
2258 } \
2259 } while (0)
2260
2261 switch (RRI8_R) {
2262 case 0: /*L8UI*/
2263 gen_load_store(ld8u, 0);
2264 break;
2265
2266 case 1: /*L16UI*/
2267 gen_load_store(ld16u, 1);
2268 break;
2269
2270 case 2: /*L32I*/
2271 gen_load_store(ld32u, 2);
2272 break;
2273
2274 case 4: /*S8I*/
2275 gen_load_store(st8, 0);
2276 break;
2277
2278 case 5: /*S16I*/
2279 gen_load_store(st16, 1);
2280 break;
2281
2282 case 6: /*S32I*/
2283 gen_load_store(st32, 2);
2284 break;
2285
2286 #define gen_dcache_hit_test(w, shift) do { \
2287 if (gen_window_check1(dc, RRI##w##_S)) { \
2288 TCGv_i32 addr = tcg_temp_new_i32(); \
2289 TCGv_i32 res = tcg_temp_new_i32(); \
2290 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2291 RRI##w##_IMM##w << shift); \
2292 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2293 tcg_temp_free(addr); \
2294 tcg_temp_free(res); \
2295 } \
2296 } while (0)
2297
2298 #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2299 #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2300
2301 case 7: /*CACHEc*/
2302 if (RRI8_T < 8) {
2303 HAS_OPTION(XTENSA_OPTION_DCACHE);
2304 }
2305
2306 switch (RRI8_T) {
2307 case 0: /*DPFRc*/
2308 gen_window_check1(dc, RRI8_S);
2309 break;
2310
2311 case 1: /*DPFWc*/
2312 gen_window_check1(dc, RRI8_S);
2313 break;
2314
2315 case 2: /*DPFROc*/
2316 gen_window_check1(dc, RRI8_S);
2317 break;
2318
2319 case 3: /*DPFWOc*/
2320 gen_window_check1(dc, RRI8_S);
2321 break;
2322
2323 case 4: /*DHWBc*/
2324 gen_dcache_hit_test8();
2325 break;
2326
2327 case 5: /*DHWBIc*/
2328 gen_dcache_hit_test8();
2329 break;
2330
2331 case 6: /*DHIc*/
2332 if (gen_check_privilege(dc)) {
2333 gen_dcache_hit_test8();
2334 }
2335 break;
2336
2337 case 7: /*DIIc*/
2338 if (gen_check_privilege(dc)) {
2339 gen_window_check1(dc, RRI8_S);
2340 }
2341 break;
2342
2343 case 8: /*DCEc*/
2344 switch (OP1) {
2345 case 0: /*DPFLl*/
2346 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2347 if (gen_check_privilege(dc)) {
2348 gen_dcache_hit_test4();
2349 }
2350 break;
2351
2352 case 2: /*DHUl*/
2353 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2354 if (gen_check_privilege(dc)) {
2355 gen_dcache_hit_test4();
2356 }
2357 break;
2358
2359 case 3: /*DIUl*/
2360 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2361 if (gen_check_privilege(dc)) {
2362 gen_window_check1(dc, RRI4_S);
2363 }
2364 break;
2365
2366 case 4: /*DIWBc*/
2367 HAS_OPTION(XTENSA_OPTION_DCACHE);
2368 if (gen_check_privilege(dc)) {
2369 gen_window_check1(dc, RRI4_S);
2370 }
2371 break;
2372
2373 case 5: /*DIWBIc*/
2374 HAS_OPTION(XTENSA_OPTION_DCACHE);
2375 if (gen_check_privilege(dc)) {
2376 gen_window_check1(dc, RRI4_S);
2377 }
2378 break;
2379
2380 default: /*reserved*/
2381 RESERVED();
2382 break;
2383
2384 }
2385 break;
2386
2387 #undef gen_dcache_hit_test
2388 #undef gen_dcache_hit_test4
2389 #undef gen_dcache_hit_test8
2390
2391 #define gen_icache_hit_test(w, shift) do { \
2392 if (gen_window_check1(dc, RRI##w##_S)) { \
2393 TCGv_i32 addr = tcg_temp_new_i32(); \
2394 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2395 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2396 RRI##w##_IMM##w << shift); \
2397 gen_helper_itlb_hit_test(cpu_env, addr); \
2398 tcg_temp_free(addr); \
2399 }\
2400 } while (0)
2401
2402 #define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2403 #define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2404
2405 case 12: /*IPFc*/
2406 HAS_OPTION(XTENSA_OPTION_ICACHE);
2407 gen_window_check1(dc, RRI8_S);
2408 break;
2409
2410 case 13: /*ICEc*/
2411 switch (OP1) {
2412 case 0: /*IPFLl*/
2413 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2414 if (gen_check_privilege(dc)) {
2415 gen_icache_hit_test4();
2416 }
2417 break;
2418
2419 case 2: /*IHUl*/
2420 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2421 if (gen_check_privilege(dc)) {
2422 gen_icache_hit_test4();
2423 }
2424 break;
2425
2426 case 3: /*IIUl*/
2427 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2428 if (gen_check_privilege(dc)) {
2429 gen_window_check1(dc, RRI4_S);
2430 }
2431 break;
2432
2433 default: /*reserved*/
2434 RESERVED();
2435 break;
2436 }
2437 break;
2438
2439 case 14: /*IHIc*/
2440 HAS_OPTION(XTENSA_OPTION_ICACHE);
2441 gen_icache_hit_test8();
2442 break;
2443
2444 case 15: /*IIIc*/
2445 HAS_OPTION(XTENSA_OPTION_ICACHE);
2446 if (gen_check_privilege(dc)) {
2447 gen_window_check1(dc, RRI8_S);
2448 }
2449 break;
2450
2451 default: /*reserved*/
2452 RESERVED();
2453 break;
2454 }
2455 break;
2456
2457 #undef gen_icache_hit_test
2458 #undef gen_icache_hit_test4
2459 #undef gen_icache_hit_test8
2460
2461 case 9: /*L16SI*/
2462 gen_load_store(ld16s, 1);
2463 break;
2464 #undef gen_load_store
2465
2466 case 10: /*MOVI*/
2467 if (gen_window_check1(dc, RRI8_T)) {
2468 tcg_gen_movi_i32(cpu_R[RRI8_T],
2469 RRI8_IMM8 | (RRI8_S << 8) |
2470 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2471 }
2472 break;
2473
2474 #define gen_load_store_no_hw_align(type) do { \
2475 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2476 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2477 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2478 gen_load_store_alignment(dc, 2, addr, true); \
2479 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2480 tcg_temp_free(addr); \
2481 } \
2482 } while (0)
2483
2484 case 11: /*L32AIy*/
2485 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2486 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
2487 break;
2488
2489 case 12: /*ADDI*/
2490 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2491 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2492 }
2493 break;
2494
2495 case 13: /*ADDMI*/
2496 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2497 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S],
2498 RRI8_IMM8_SE << 8);
2499 }
2500 break;
2501
2502 case 14: /*S32C1Iy*/
2503 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2504 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2505 TCGLabel *label = gen_new_label();
2506 TCGv_i32 tmp = tcg_temp_local_new_i32();
2507 TCGv_i32 addr = tcg_temp_local_new_i32();
2508 TCGv_i32 tpc;
2509
2510 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2511 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2512 gen_load_store_alignment(dc, 2, addr, true);
2513
2514 gen_advance_ccount(dc);
2515 tpc = tcg_const_i32(dc->pc);
2516 gen_helper_check_atomctl(cpu_env, tpc, addr);
2517 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2518 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2519 cpu_SR[SCOMPARE1], label);
2520
2521 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2522
2523 gen_set_label(label);
2524 tcg_temp_free(tpc);
2525 tcg_temp_free(addr);
2526 tcg_temp_free(tmp);
2527 }
2528 break;
2529
2530 case 15: /*S32RIy*/
2531 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2532 gen_load_store_no_hw_align(st32); /*TODO release?*/
2533 break;
2534 #undef gen_load_store_no_hw_align
2535
2536 default: /*reserved*/
2537 RESERVED();
2538 break;
2539 }
2540 break;
2541
2542 case 3: /*LSCIp*/
2543 switch (RRI8_R) {
2544 case 0: /*LSIf*/
2545 case 4: /*SSIf*/
2546 case 8: /*LSIUf*/
2547 case 12: /*SSIUf*/
2548 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2549 if (gen_window_check1(dc, RRI8_S) &&
2550 gen_check_cpenable(dc, 0)) {
2551 TCGv_i32 addr = tcg_temp_new_i32();
2552 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2553 gen_load_store_alignment(dc, 2, addr, false);
2554 if (RRI8_R & 0x4) {
2555 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2556 } else {
2557 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2558 }
2559 if (RRI8_R & 0x8) {
2560 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2561 }
2562 tcg_temp_free(addr);
2563 }
2564 break;
2565
2566 default: /*reserved*/
2567 RESERVED();
2568 break;
2569 }
2570 break;
2571
2572 case 4: /*MAC16d*/
2573 HAS_OPTION(XTENSA_OPTION_MAC16);
2574 {
2575 enum {
2576 MAC16_UMUL = 0x0,
2577 MAC16_MUL = 0x4,
2578 MAC16_MULA = 0x8,
2579 MAC16_MULS = 0xc,
2580 MAC16_NONE = 0xf,
2581 } op = OP1 & 0xc;
2582 bool is_m1_sr = (OP2 & 0x3) == 2;
2583 bool is_m2_sr = (OP2 & 0xc) == 0;
2584 uint32_t ld_offset = 0;
2585
2586 if (OP2 > 9) {
2587 RESERVED();
2588 }
2589
2590 switch (OP2 & 2) {
2591 case 0: /*MACI?/MACC?*/
2592 is_m1_sr = true;
2593 ld_offset = (OP2 & 1) ? -4 : 4;
2594
2595 if (OP2 >= 8) { /*MACI/MACC*/
2596 if (OP1 == 0) { /*LDINC/LDDEC*/
2597 op = MAC16_NONE;
2598 } else {
2599 RESERVED();
2600 }
2601 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2602 RESERVED();
2603 }
2604 break;
2605
2606 case 2: /*MACD?/MACA?*/
2607 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2608 RESERVED();
2609 }
2610 break;
2611 }
2612
2613 if (op != MAC16_NONE) {
2614 if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) {
2615 break;
2616 }
2617 if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) {
2618 break;
2619 }
2620 }
2621
2622 if (ld_offset && !gen_window_check1(dc, RRR_S)) {
2623 break;
2624 }
2625
2626 {
2627 TCGv_i32 vaddr = tcg_temp_new_i32();
2628 TCGv_i32 mem32 = tcg_temp_new_i32();
2629
2630 if (ld_offset) {
2631 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2632 gen_load_store_alignment(dc, 2, vaddr, false);
2633 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2634 }
2635 if (op != MAC16_NONE) {
2636 TCGv_i32 m1 = gen_mac16_m(
2637 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2638 OP1 & 1, op == MAC16_UMUL);
2639 TCGv_i32 m2 = gen_mac16_m(
2640 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2641 OP1 & 2, op == MAC16_UMUL);
2642
2643 if (op == MAC16_MUL || op == MAC16_UMUL) {
2644 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2645 if (op == MAC16_UMUL) {
2646 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2647 } else {
2648 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2649 }
2650 } else {
2651 TCGv_i32 lo = tcg_temp_new_i32();
2652 TCGv_i32 hi = tcg_temp_new_i32();
2653
2654 tcg_gen_mul_i32(lo, m1, m2);
2655 tcg_gen_sari_i32(hi, lo, 31);
2656 if (op == MAC16_MULA) {
2657 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2658 cpu_SR[ACCLO], cpu_SR[ACCHI],
2659 lo, hi);
2660 } else {
2661 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2662 cpu_SR[ACCLO], cpu_SR[ACCHI],
2663 lo, hi);
2664 }
2665 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2666
2667 tcg_temp_free_i32(lo);
2668 tcg_temp_free_i32(hi);
2669 }
2670 tcg_temp_free(m1);
2671 tcg_temp_free(m2);
2672 }
2673 if (ld_offset) {
2674 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2675 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2676 }
2677 tcg_temp_free(vaddr);
2678 tcg_temp_free(mem32);
2679 }
2680 }
2681 break;
2682
2683 case 5: /*CALLN*/
2684 switch (CALL_N) {
2685 case 0: /*CALL0*/
2686 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2687 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2688 break;
2689
2690 case 1: /*CALL4w*/
2691 case 2: /*CALL8w*/
2692 case 3: /*CALL12w*/
2693 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2694 if (gen_window_check1(dc, CALL_N << 2)) {
2695 gen_callwi(dc, CALL_N,
2696 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2697 }
2698 break;
2699 }
2700 break;
2701
2702 case 6: /*SI*/
2703 switch (CALL_N) {
2704 case 0: /*J*/
2705 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2706 break;
2707
2708 case 1: /*BZ*/
2709 if (gen_window_check1(dc, BRI12_S)) {
2710 static const TCGCond cond[] = {
2711 TCG_COND_EQ, /*BEQZ*/
2712 TCG_COND_NE, /*BNEZ*/
2713 TCG_COND_LT, /*BLTZ*/
2714 TCG_COND_GE, /*BGEZ*/
2715 };
2716
2717 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2718 4 + BRI12_IMM12_SE);
2719 }
2720 break;
2721
2722 case 2: /*BI0*/
2723 if (gen_window_check1(dc, BRI8_S)) {
2724 static const TCGCond cond[] = {
2725 TCG_COND_EQ, /*BEQI*/
2726 TCG_COND_NE, /*BNEI*/
2727 TCG_COND_LT, /*BLTI*/
2728 TCG_COND_GE, /*BGEI*/
2729 };
2730
2731 gen_brcondi(dc, cond[BRI8_M & 3],
2732 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2733 }
2734 break;
2735
2736 case 3: /*BI1*/
2737 switch (BRI8_M) {
2738 case 0: /*ENTRYw*/
2739 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2740 {
2741 TCGv_i32 pc = tcg_const_i32(dc->pc);
2742 TCGv_i32 s = tcg_const_i32(BRI12_S);
2743 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2744 gen_advance_ccount(dc);
2745 gen_helper_entry(cpu_env, pc, s, imm);
2746 tcg_temp_free(imm);
2747 tcg_temp_free(s);
2748 tcg_temp_free(pc);
2749 /* This can change tb->flags, so exit tb */
2750 gen_jumpi_check_loop_end(dc, -1);
2751 }
2752 break;
2753
2754 case 1: /*B1*/
2755 switch (BRI8_R) {
2756 case 0: /*BFp*/
2757 case 1: /*BTp*/
2758 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2759 {
2760 TCGv_i32 tmp = tcg_temp_new_i32();
2761 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2762 gen_brcondi(dc,
2763 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2764 tmp, 0, 4 + RRI8_IMM8_SE);
2765 tcg_temp_free(tmp);
2766 }
2767 break;
2768
2769 case 8: /*LOOP*/
2770 case 9: /*LOOPNEZ*/
2771 case 10: /*LOOPGTZ*/
2772 HAS_OPTION(XTENSA_OPTION_LOOP);
2773 if (gen_window_check1(dc, RRI8_S)) {
2774 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2775 TCGv_i32 tmp = tcg_const_i32(lend);
2776
2777 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2778 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2779 gen_helper_wsr_lend(cpu_env, tmp);
2780 tcg_temp_free(tmp);
2781
2782 if (BRI8_R > 8) {
2783 TCGLabel *label = gen_new_label();
2784 tcg_gen_brcondi_i32(
2785 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2786 cpu_R[RRI8_S], 0, label);
2787 gen_jumpi(dc, lend, 1);
2788 gen_set_label(label);
2789 }
2790
2791 gen_jumpi(dc, dc->next_pc, 0);
2792 }
2793 break;
2794
2795 default: /*reserved*/
2796 RESERVED();
2797 break;
2798
2799 }
2800 break;
2801
2802 case 2: /*BLTUI*/
2803 case 3: /*BGEUI*/
2804 if (gen_window_check1(dc, BRI8_S)) {
2805 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2806 cpu_R[BRI8_S], B4CONSTU[BRI8_R],
2807 4 + BRI8_IMM8_SE);
2808 }
2809 break;
2810 }
2811 break;
2812
2813 }
2814 break;
2815
2816 case 7: /*B*/
2817 {
2818 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2819
2820 switch (RRI8_R & 7) {
2821 case 0: /*BNONE*/ /*BANY*/
2822 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2823 TCGv_i32 tmp = tcg_temp_new_i32();
2824 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2825 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2826 tcg_temp_free(tmp);
2827 }
2828 break;
2829
2830 case 1: /*BEQ*/ /*BNE*/
2831 case 2: /*BLT*/ /*BGE*/
2832 case 3: /*BLTU*/ /*BGEU*/
2833 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2834 static const TCGCond cond[] = {
2835 [1] = TCG_COND_EQ,
2836 [2] = TCG_COND_LT,
2837 [3] = TCG_COND_LTU,
2838 [9] = TCG_COND_NE,
2839 [10] = TCG_COND_GE,
2840 [11] = TCG_COND_GEU,
2841 };
2842 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2843 4 + RRI8_IMM8_SE);
2844 }
2845 break;
2846
2847 case 4: /*BALL*/ /*BNALL*/
2848 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2849 TCGv_i32 tmp = tcg_temp_new_i32();
2850 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2851 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2852 4 + RRI8_IMM8_SE);
2853 tcg_temp_free(tmp);
2854 }
2855 break;
2856
2857 case 5: /*BBC*/ /*BBS*/
2858 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2859 #ifdef TARGET_WORDS_BIGENDIAN
2860 TCGv_i32 bit = tcg_const_i32(0x80000000);
2861 #else
2862 TCGv_i32 bit = tcg_const_i32(0x00000001);
2863 #endif
2864 TCGv_i32 tmp = tcg_temp_new_i32();
2865 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2866 #ifdef TARGET_WORDS_BIGENDIAN
2867 tcg_gen_shr_i32(bit, bit, tmp);
2868 #else
2869 tcg_gen_shl_i32(bit, bit, tmp);
2870 #endif
2871 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2872 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2873 tcg_temp_free(tmp);
2874 tcg_temp_free(bit);
2875 }
2876 break;
2877
2878 case 6: /*BBCI*/ /*BBSI*/
2879 case 7:
2880 if (gen_window_check1(dc, RRI8_S)) {
2881 TCGv_i32 tmp = tcg_temp_new_i32();
2882 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2883 #ifdef TARGET_WORDS_BIGENDIAN
2884 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2885 #else
2886 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2887 #endif
2888 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2889 tcg_temp_free(tmp);
2890 }
2891 break;
2892
2893 }
2894 }
2895 break;
2896
2897 #define gen_narrow_load_store(type) do { \
2898 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2899 TCGv_i32 addr = tcg_temp_new_i32(); \
2900 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2901 gen_load_store_alignment(dc, 2, addr, false); \
2902 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2903 tcg_temp_free(addr); \
2904 } \
2905 } while (0)
2906
2907 case 8: /*L32I.Nn*/
2908 gen_narrow_load_store(ld32u);
2909 break;
2910
2911 case 9: /*S32I.Nn*/
2912 gen_narrow_load_store(st32);
2913 break;
2914 #undef gen_narrow_load_store
2915
2916 case 10: /*ADD.Nn*/
2917 if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) {
2918 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2919 }
2920 break;
2921
2922 case 11: /*ADDI.Nn*/
2923 if (gen_window_check2(dc, RRRN_R, RRRN_S)) {
2924 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S],
2925 RRRN_T ? RRRN_T : -1);
2926 }
2927 break;
2928
2929 case 12: /*ST2n*/
2930 if (!gen_window_check1(dc, RRRN_S)) {
2931 break;
2932 }
2933 if (RRRN_T < 8) { /*MOVI.Nn*/
2934 tcg_gen_movi_i32(cpu_R[RRRN_S],
2935 RRRN_R | (RRRN_T << 4) |
2936 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2937 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2938 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2939
2940 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2941 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2942 }
2943 break;
2944
2945 case 13: /*ST3n*/
2946 switch (RRRN_R) {
2947 case 0: /*MOV.Nn*/
2948 if (gen_window_check2(dc, RRRN_S, RRRN_T)) {
2949 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2950 }
2951 break;
2952
2953 case 15: /*S3*/
2954 switch (RRRN_T) {
2955 case 0: /*RET.Nn*/
2956 gen_jump(dc, cpu_R[0]);
2957 break;
2958
2959 case 1: /*RETW.Nn*/
2960 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2961 {
2962 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2963 gen_advance_ccount(dc);
2964 gen_helper_retw(tmp, cpu_env, tmp);
2965 gen_jump(dc, tmp);
2966 tcg_temp_free(tmp);
2967 }
2968 break;
2969
2970 case 2: /*BREAK.Nn*/
2971 HAS_OPTION(XTENSA_OPTION_DEBUG);
2972 if (dc->debug) {
2973 gen_debug_exception(dc, DEBUGCAUSE_BN);
2974 }
2975 break;
2976
2977 case 3: /*NOP.Nn*/
2978 break;
2979
2980 case 6: /*ILL.Nn*/
2981 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2982 break;
2983
2984 default: /*reserved*/
2985 RESERVED();
2986 break;
2987 }
2988 break;
2989
2990 default: /*reserved*/
2991 RESERVED();
2992 break;
2993 }
2994 break;
2995
2996 default: /*reserved*/
2997 RESERVED();
2998 break;
2999 }
3000
3001 if (dc->is_jmp == DISAS_NEXT) {
3002 gen_check_loop_end(dc, 0);
3003 }
3004 dc->pc = dc->next_pc;
3005
3006 return;
3007
3008 invalid_opcode:
3009 qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc);
3010 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
3011 #undef HAS_OPTION
3012 }
3013
3014 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
3015 {
3016 uint8_t b0 = cpu_ldub_code(env, dc->pc);
3017 return xtensa_op0_insn_len(OP0);
3018 }
3019
3020 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
3021 {
3022 unsigned i;
3023
3024 for (i = 0; i < dc->config->nibreak; ++i) {
3025 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
3026 env->sregs[IBREAKA + i] == dc->pc) {
3027 gen_debug_exception(dc, DEBUGCAUSE_IB);
3028 break;
3029 }
3030 }
3031 }
3032
3033 void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
3034 {
3035 XtensaCPU *cpu = xtensa_env_get_cpu(env);
3036 CPUState *cs = CPU(cpu);
3037 DisasContext dc;
3038 int insn_count = 0;
3039 int max_insns = tb->cflags & CF_COUNT_MASK;
3040 uint32_t pc_start = tb->pc;
3041 uint32_t next_page_start =
3042 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3043
3044 if (max_insns == 0) {
3045 max_insns = CF_COUNT_MASK;
3046 }
3047 if (max_insns > TCG_MAX_INSNS) {
3048 max_insns = TCG_MAX_INSNS;
3049 }
3050
3051 dc.config = env->config;
3052 dc.singlestep_enabled = cs->singlestep_enabled;
3053 dc.tb = tb;
3054 dc.pc = pc_start;
3055 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3056 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
3057 dc.lbeg = env->sregs[LBEG];
3058 dc.lend = env->sregs[LEND];
3059 dc.is_jmp = DISAS_NEXT;
3060 dc.ccount_delta = 0;
3061 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
3062 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
3063 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3064 XTENSA_TBFLAG_CPENABLE_SHIFT;
3065 dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
3066 XTENSA_TBFLAG_WINDOW_SHIFT);
3067
3068 init_litbase(&dc);
3069 init_sar_tracker(&dc);
3070 if (dc.icount) {
3071 dc.next_icount = tcg_temp_local_new_i32();
3072 }
3073
3074 gen_tb_start(tb);
3075
3076 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
3077 tcg_gen_movi_i32(cpu_pc, dc.pc);
3078 gen_exception(&dc, EXCP_DEBUG);
3079 }
3080
3081 do {
3082 tcg_gen_insn_start(dc.pc);
3083 ++insn_count;
3084
3085 ++dc.ccount_delta;
3086
3087 if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
3088 tcg_gen_movi_i32(cpu_pc, dc.pc);
3089 gen_exception(&dc, EXCP_DEBUG);
3090 dc.is_jmp = DISAS_UPDATE;
3091 /* The address covered by the breakpoint must be included in
3092 [tb->pc, tb->pc + tb->size) in order to for it to be
3093 properly cleared -- thus we increment the PC here so that
3094 the logic setting tb->size below does the right thing. */
3095 dc.pc += 2;
3096 break;
3097 }
3098
3099 if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
3100 gen_io_start();
3101 }
3102
3103 if (dc.icount) {
3104 TCGLabel *label = gen_new_label();
3105
3106 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3107 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3108 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3109 if (dc.debug) {
3110 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3111 }
3112 gen_set_label(label);
3113 }
3114
3115 if (dc.debug) {
3116 gen_ibreak_check(env, &dc);
3117 }
3118
3119 disas_xtensa_insn(env, &dc);
3120 if (dc.icount) {
3121 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3122 }
3123 if (cs->singlestep_enabled) {
3124 tcg_gen_movi_i32(cpu_pc, dc.pc);
3125 gen_exception(&dc, EXCP_DEBUG);
3126 break;
3127 }
3128 } while (dc.is_jmp == DISAS_NEXT &&
3129 insn_count < max_insns &&
3130 dc.pc < next_page_start &&
3131 dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
3132 !tcg_op_buf_full());
3133
3134 reset_litbase(&dc);
3135 reset_sar_tracker(&dc);
3136 if (dc.icount) {
3137 tcg_temp_free(dc.next_icount);
3138 }
3139
3140 if (tb->cflags & CF_LAST_IO) {
3141 gen_io_end();
3142 }
3143
3144 if (dc.is_jmp == DISAS_NEXT) {
3145 gen_jumpi(&dc, dc.pc, 0);
3146 }
3147 gen_tb_end(tb, insn_count);
3148
3149 #ifdef DEBUG_DISAS
3150 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3151 qemu_log("----------------\n");
3152 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3153 log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
3154 qemu_log("\n");
3155 }
3156 #endif
3157 tb->size = dc.pc - pc_start;
3158 tb->icount = insn_count;
3159 }
3160
3161 void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3162 fprintf_function cpu_fprintf, int flags)
3163 {
3164 XtensaCPU *cpu = XTENSA_CPU(cs);
3165 CPUXtensaState *env = &cpu->env;
3166 int i, j;
3167
3168 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3169
3170 for (i = j = 0; i < 256; ++i) {
3171 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3172 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
3173 (j++ % 4) == 3 ? '\n' : ' ');
3174 }
3175 }
3176
3177 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3178
3179 for (i = j = 0; i < 256; ++i) {
3180 if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3181 cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
3182 (j++ % 4) == 3 ? '\n' : ' ');
3183 }
3184 }
3185
3186 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3187
3188 for (i = 0; i < 16; ++i) {
3189 cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
3190 (i % 4) == 3 ? '\n' : ' ');
3191 }
3192
3193 cpu_fprintf(f, "\n");
3194
3195 for (i = 0; i < env->config->nareg; ++i) {
3196 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3197 (i % 4) == 3 ? '\n' : ' ');
3198 }
3199
3200 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3201 cpu_fprintf(f, "\n");
3202
3203 for (i = 0; i < 16; ++i) {
3204 cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3205 float32_val(env->fregs[i].f32[FP_F32_LOW]),
3206 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
3207 (i % 2) == 1 ? '\n' : ' ');
3208 }
3209 }
3210 }
3211
3212 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
3213 target_ulong *data)
3214 {
3215 env->pc = data[0];
3216 }
CRIS target port of Qemu