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Support addr=... in option argument of -drive if=virtio
[qemu/cris-port.git] / hw / pc.c
blob19021eafb692b72340ce5a335c5a6b6de2034e65
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pc.h"
26 #include "fdc.h"
27 #include "pci.h"
28 #include "block.h"
29 #include "sysemu.h"
30 #include "audio/audio.h"
31 #include "net.h"
32 #include "smbus.h"
33 #include "boards.h"
34 #include "monitor.h"
35 #include "fw_cfg.h"
36 #include "hpet_emul.h"
37 #include "watchdog.h"
38 #include "smbios.h"
39
40 /* output Bochs bios info messages */
41 //#define DEBUG_BIOS
42
43 #define BIOS_FILENAME "bios.bin"
44 #define VGABIOS_FILENAME "vgabios.bin"
45 #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
46
47 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
48
49 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
50 #define ACPI_DATA_SIZE 0x10000
51 #define BIOS_CFG_IOPORT 0x510
52 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
53 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
54
55 #define MAX_IDE_BUS 2
56
57 static fdctrl_t *floppy_controller;
58 static RTCState *rtc_state;
59 static PITState *pit;
60 static IOAPICState *ioapic;
61 static PCIDevice *i440fx_state;
62
63 typedef struct rom_reset_data {
64 uint8_t *data;
65 target_phys_addr_t addr;
66 unsigned size;
67 } RomResetData;
68
69 static void option_rom_reset(void *_rrd)
70 {
71 RomResetData *rrd = _rrd;
72
73 cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
74 }
75
76 static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
77 {
78 RomResetData *rrd = qemu_malloc(sizeof *rrd);
79
80 rrd->data = qemu_malloc(size);
81 cpu_physical_memory_read(addr, rrd->data, size);
82 rrd->addr = addr;
83 rrd->size = size;
84 qemu_register_reset(option_rom_reset, 0, rrd);
85 }
86
87 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
88 {
89 }
90
91 /* MSDOS compatibility mode FPU exception support */
92 static qemu_irq ferr_irq;
93 /* XXX: add IGNNE support */
94 void cpu_set_ferr(CPUX86State *s)
95 {
96 qemu_irq_raise(ferr_irq);
97 }
98
99 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
100 {
101 qemu_irq_lower(ferr_irq);
102 }
103
104 /* TSC handling */
105 uint64_t cpu_get_tsc(CPUX86State *env)
106 {
107 /* Note: when using kqemu, it is more logical to return the host TSC
108 because kqemu does not trap the RDTSC instruction for
109 performance reasons */
110 #ifdef CONFIG_KQEMU
111 if (env->kqemu_enabled) {
112 return cpu_get_real_ticks();
113 } else
114 #endif
115 {
116 return cpu_get_ticks();
117 }
118 }
119
120 /* SMM support */
121 void cpu_smm_update(CPUState *env)
122 {
123 if (i440fx_state && env == first_cpu)
124 i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
125 }
126
127
128 /* IRQ handling */
129 int cpu_get_pic_interrupt(CPUState *env)
130 {
131 int intno;
132
133 intno = apic_get_interrupt(env);
134 if (intno >= 0) {
135 /* set irq request if a PIC irq is still pending */
136 /* XXX: improve that */
137 pic_update_irq(isa_pic);
138 return intno;
139 }
140 /* read the irq from the PIC */
141 if (!apic_accept_pic_intr(env))
142 return -1;
143
144 intno = pic_read_irq(isa_pic);
145 return intno;
146 }
147
148 static void pic_irq_request(void *opaque, int irq, int level)
149 {
150 CPUState *env = first_cpu;
151
152 if (env->apic_state) {
153 while (env) {
154 if (apic_accept_pic_intr(env))
155 apic_deliver_pic_intr(env, level);
156 env = env->next_cpu;
157 }
158 } else {
159 if (level)
160 cpu_interrupt(env, CPU_INTERRUPT_HARD);
161 else
162 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
163 }
164 }
165
166 /* PC cmos mappings */
167
168 #define REG_EQUIPMENT_BYTE 0x14
169
170 static int cmos_get_fd_drive_type(int fd0)
171 {
172 int val;
173
174 switch (fd0) {
175 case 0:
176 /* 1.44 Mb 3"5 drive */
177 val = 4;
178 break;
179 case 1:
180 /* 2.88 Mb 3"5 drive */
181 val = 5;
182 break;
183 case 2:
184 /* 1.2 Mb 5"5 drive */
185 val = 2;
186 break;
187 default:
188 val = 0;
189 break;
190 }
191 return val;
192 }
193
194 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
195 {
196 RTCState *s = rtc_state;
197 int cylinders, heads, sectors;
198 bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
199 rtc_set_memory(s, type_ofs, 47);
200 rtc_set_memory(s, info_ofs, cylinders);
201 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
202 rtc_set_memory(s, info_ofs + 2, heads);
203 rtc_set_memory(s, info_ofs + 3, 0xff);
204 rtc_set_memory(s, info_ofs + 4, 0xff);
205 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
206 rtc_set_memory(s, info_ofs + 6, cylinders);
207 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
208 rtc_set_memory(s, info_ofs + 8, sectors);
209 }
210
211 /* convert boot_device letter to something recognizable by the bios */
212 static int boot_device2nibble(char boot_device)
213 {
214 switch(boot_device) {
215 case 'a':
216 case 'b':
217 return 0x01; /* floppy boot */
218 case 'c':
219 return 0x02; /* hard drive boot */
220 case 'd':
221 return 0x03; /* CD-ROM boot */
222 case 'n':
223 return 0x04; /* Network boot */
224 }
225 return 0;
226 }
227
228 /* copy/pasted from cmos_init, should be made a general function
229 and used there as well */
230 static int pc_boot_set(void *opaque, const char *boot_device)
231 {
232 Monitor *mon = cur_mon;
233 #define PC_MAX_BOOT_DEVICES 3
234 RTCState *s = (RTCState *)opaque;
235 int nbds, bds[3] = { 0, };
236 int i;
237
238 nbds = strlen(boot_device);
239 if (nbds > PC_MAX_BOOT_DEVICES) {
240 monitor_printf(mon, "Too many boot devices for PC\n");
241 return(1);
242 }
243 for (i = 0; i < nbds; i++) {
244 bds[i] = boot_device2nibble(boot_device[i]);
245 if (bds[i] == 0) {
246 monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
247 boot_device[i]);
248 return(1);
249 }
250 }
251 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
252 rtc_set_memory(s, 0x38, (bds[2] << 4));
253 return(0);
254 }
255
256 /* hd_table must contain 4 block drivers */
257 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
258 const char *boot_device, BlockDriverState **hd_table)
259 {
260 RTCState *s = rtc_state;
261 int nbds, bds[3] = { 0, };
262 int val;
263 int fd0, fd1, nb;
264 int i;
265
266 /* various important CMOS locations needed by PC/Bochs bios */
267
268 /* memory size */
269 val = 640; /* base memory in K */
270 rtc_set_memory(s, 0x15, val);
271 rtc_set_memory(s, 0x16, val >> 8);
272
273 val = (ram_size / 1024) - 1024;
274 if (val > 65535)
275 val = 65535;
276 rtc_set_memory(s, 0x17, val);
277 rtc_set_memory(s, 0x18, val >> 8);
278 rtc_set_memory(s, 0x30, val);
279 rtc_set_memory(s, 0x31, val >> 8);
280
281 if (above_4g_mem_size) {
282 rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
283 rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
284 rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
285 }
286
287 if (ram_size > (16 * 1024 * 1024))
288 val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
289 else
290 val = 0;
291 if (val > 65535)
292 val = 65535;
293 rtc_set_memory(s, 0x34, val);
294 rtc_set_memory(s, 0x35, val >> 8);
295
296 /* set the number of CPU */
297 rtc_set_memory(s, 0x5f, smp_cpus - 1);
298
299 /* set boot devices, and disable floppy signature check if requested */
300 #define PC_MAX_BOOT_DEVICES 3
301 nbds = strlen(boot_device);
302 if (nbds > PC_MAX_BOOT_DEVICES) {
303 fprintf(stderr, "Too many boot devices for PC\n");
304 exit(1);
305 }
306 for (i = 0; i < nbds; i++) {
307 bds[i] = boot_device2nibble(boot_device[i]);
308 if (bds[i] == 0) {
309 fprintf(stderr, "Invalid boot device for PC: '%c'\n",
310 boot_device[i]);
311 exit(1);
312 }
313 }
314 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
315 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
316
317 /* floppy type */
318
319 fd0 = fdctrl_get_drive_type(floppy_controller, 0);
320 fd1 = fdctrl_get_drive_type(floppy_controller, 1);
321
322 val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
323 rtc_set_memory(s, 0x10, val);
324
325 val = 0;
326 nb = 0;
327 if (fd0 < 3)
328 nb++;
329 if (fd1 < 3)
330 nb++;
331 switch (nb) {
332 case 0:
333 break;
334 case 1:
335 val |= 0x01; /* 1 drive, ready for boot */
336 break;
337 case 2:
338 val |= 0x41; /* 2 drives, ready for boot */
339 break;
340 }
341 val |= 0x02; /* FPU is there */
342 val |= 0x04; /* PS/2 mouse installed */
343 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
344
345 /* hard drives */
346
347 rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
348 if (hd_table[0])
349 cmos_init_hd(0x19, 0x1b, hd_table[0]);
350 if (hd_table[1])
351 cmos_init_hd(0x1a, 0x24, hd_table[1]);
352
353 val = 0;
354 for (i = 0; i < 4; i++) {
355 if (hd_table[i]) {
356 int cylinders, heads, sectors, translation;
357 /* NOTE: bdrv_get_geometry_hint() returns the physical
358 geometry. It is always such that: 1 <= sects <= 63, 1
359 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
360 geometry can be different if a translation is done. */
361 translation = bdrv_get_translation_hint(hd_table[i]);
362 if (translation == BIOS_ATA_TRANSLATION_AUTO) {
363 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
364 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
365 /* No translation. */
366 translation = 0;
367 } else {
368 /* LBA translation. */
369 translation = 1;
370 }
371 } else {
372 translation--;
373 }
374 val |= translation << (i * 2);
375 }
376 }
377 rtc_set_memory(s, 0x39, val);
378 }
379
380 void ioport_set_a20(int enable)
381 {
382 /* XXX: send to all CPUs ? */
383 cpu_x86_set_a20(first_cpu, enable);
384 }
385
386 int ioport_get_a20(void)
387 {
388 return ((first_cpu->a20_mask >> 20) & 1);
389 }
390
391 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
392 {
393 ioport_set_a20((val >> 1) & 1);
394 /* XXX: bit 0 is fast reset */
395 }
396
397 static uint32_t ioport92_read(void *opaque, uint32_t addr)
398 {
399 return ioport_get_a20() << 1;
400 }
401
402 /***********************************************************/
403 /* Bochs BIOS debug ports */
404
405 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
406 {
407 static const char shutdown_str[8] = "Shutdown";
408 static int shutdown_index = 0;
409
410 switch(addr) {
411 /* Bochs BIOS messages */
412 case 0x400:
413 case 0x401:
414 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
415 exit(1);
416 case 0x402:
417 case 0x403:
418 #ifdef DEBUG_BIOS
419 fprintf(stderr, "%c", val);
420 #endif
421 break;
422 case 0x8900:
423 /* same as Bochs power off */
424 if (val == shutdown_str[shutdown_index]) {
425 shutdown_index++;
426 if (shutdown_index == 8) {
427 shutdown_index = 0;
428 qemu_system_shutdown_request();
429 }
430 } else {
431 shutdown_index = 0;
432 }
433 break;
434
435 /* LGPL'ed VGA BIOS messages */
436 case 0x501:
437 case 0x502:
438 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
439 exit(1);
440 case 0x500:
441 case 0x503:
442 #ifdef DEBUG_BIOS
443 fprintf(stderr, "%c", val);
444 #endif
445 break;
446 }
447 }
448
449 extern uint64_t node_cpumask[MAX_NODES];
450
451 static void bochs_bios_init(void)
452 {
453 void *fw_cfg;
454 uint8_t *smbios_table;
455 size_t smbios_len;
456 uint64_t *numa_fw_cfg;
457 int i, j;
458
459 register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
460 register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
461 register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
462 register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
463 register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
464
465 register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
466 register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
467 register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
468 register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
469
470 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
471 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
472 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
473 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
474 acpi_tables_len);
475
476 smbios_table = smbios_get_table(&smbios_len);
477 if (smbios_table)
478 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
479 smbios_table, smbios_len);
480
481 /* allocate memory for the NUMA channel: one (64bit) word for the number
482 * of nodes, one word for each VCPU->node and one word for each node to
483 * hold the amount of memory.
484 */
485 numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
486 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
487 for (i = 0; i < smp_cpus; i++) {
488 for (j = 0; j < nb_numa_nodes; j++) {
489 if (node_cpumask[j] & (1 << i)) {
490 numa_fw_cfg[i + 1] = cpu_to_le64(j);
491 break;
492 }
493 }
494 }
495 for (i = 0; i < nb_numa_nodes; i++) {
496 numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
497 }
498 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
499 (1 + smp_cpus + nb_numa_nodes) * 8);
500 }
501
502 /* Generate an initial boot sector which sets state and jump to
503 a specified vector */
504 static void generate_bootsect(target_phys_addr_t option_rom,
505 uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
506 {
507 uint8_t rom[512], *p, *reloc;
508 uint8_t sum;
509 int i;
510
511 memset(rom, 0, sizeof(rom));
512
513 p = rom;
514 /* Make sure we have an option rom signature */
515 *p++ = 0x55;
516 *p++ = 0xaa;
517
518 /* ROM size in sectors*/
519 *p++ = 1;
520
521 /* Hook int19 */
522
523 *p++ = 0x50; /* push ax */
524 *p++ = 0x1e; /* push ds */
525 *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */
526 *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */
527
528 *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */
529 *p++ = 0x64; *p++ = 0x00;
530 reloc = p;
531 *p++ = 0x00; *p++ = 0x00;
532
533 *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */
534 *p++ = 0x66; *p++ = 0x00;
535
536 *p++ = 0x1f; /* pop ds */
537 *p++ = 0x58; /* pop ax */
538 *p++ = 0xcb; /* lret */
539
540 /* Actual code */
541 *reloc = (p - rom);
542
543 *p++ = 0xfa; /* CLI */
544 *p++ = 0xfc; /* CLD */
545
546 for (i = 0; i < 6; i++) {
547 if (i == 1) /* Skip CS */
548 continue;
549
550 *p++ = 0xb8; /* MOV AX,imm16 */
551 *p++ = segs[i];
552 *p++ = segs[i] >> 8;
553 *p++ = 0x8e; /* MOV <seg>,AX */
554 *p++ = 0xc0 + (i << 3);
555 }
556
557 for (i = 0; i < 8; i++) {
558 *p++ = 0x66; /* 32-bit operand size */
559 *p++ = 0xb8 + i; /* MOV <reg>,imm32 */
560 *p++ = gpr[i];
561 *p++ = gpr[i] >> 8;
562 *p++ = gpr[i] >> 16;
563 *p++ = gpr[i] >> 24;
564 }
565
566 *p++ = 0xea; /* JMP FAR */
567 *p++ = ip; /* IP */
568 *p++ = ip >> 8;
569 *p++ = segs[1]; /* CS */
570 *p++ = segs[1] >> 8;
571
572 /* sign rom */
573 sum = 0;
574 for (i = 0; i < (sizeof(rom) - 1); i++)
575 sum += rom[i];
576 rom[sizeof(rom) - 1] = -sum;
577
578 cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
579 option_rom_setup_reset(option_rom, sizeof (rom));
580 }
581
582 static long get_file_size(FILE *f)
583 {
584 long where, size;
585
586 /* XXX: on Unix systems, using fstat() probably makes more sense */
587
588 where = ftell(f);
589 fseek(f, 0, SEEK_END);
590 size = ftell(f);
591 fseek(f, where, SEEK_SET);
592
593 return size;
594 }
595
596 static void load_linux(target_phys_addr_t option_rom,
597 const char *kernel_filename,
598 const char *initrd_filename,
599 const char *kernel_cmdline,
600 target_phys_addr_t max_ram_size)
601 {
602 uint16_t protocol;
603 uint32_t gpr[8];
604 uint16_t seg[6];
605 uint16_t real_seg;
606 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
607 uint32_t initrd_max;
608 uint8_t header[1024];
609 target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
610 FILE *f, *fi;
611
612 /* Align to 16 bytes as a paranoia measure */
613 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
614
615 /* load the kernel header */
616 f = fopen(kernel_filename, "rb");
617 if (!f || !(kernel_size = get_file_size(f)) ||
618 fread(header, 1, 1024, f) != 1024) {
619 fprintf(stderr, "qemu: could not load kernel '%s'\n",
620 kernel_filename);
621 exit(1);
622 }
623
624 /* kernel protocol version */
625 #if 0
626 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
627 #endif
628 if (ldl_p(header+0x202) == 0x53726448)
629 protocol = lduw_p(header+0x206);
630 else
631 protocol = 0;
632
633 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
634 /* Low kernel */
635 real_addr = 0x90000;
636 cmdline_addr = 0x9a000 - cmdline_size;
637 prot_addr = 0x10000;
638 } else if (protocol < 0x202) {
639 /* High but ancient kernel */
640 real_addr = 0x90000;
641 cmdline_addr = 0x9a000 - cmdline_size;
642 prot_addr = 0x100000;
643 } else {
644 /* High and recent kernel */
645 real_addr = 0x10000;
646 cmdline_addr = 0x20000;
647 prot_addr = 0x100000;
648 }
649
650 #if 0
651 fprintf(stderr,
652 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
653 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
654 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
655 real_addr,
656 cmdline_addr,
657 prot_addr);
658 #endif
659
660 /* highest address for loading the initrd */
661 if (protocol >= 0x203)
662 initrd_max = ldl_p(header+0x22c);
663 else
664 initrd_max = 0x37ffffff;
665
666 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
667 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
668
669 /* kernel command line */
670 pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
671
672 if (protocol >= 0x202) {
673 stl_p(header+0x228, cmdline_addr);
674 } else {
675 stw_p(header+0x20, 0xA33F);
676 stw_p(header+0x22, cmdline_addr-real_addr);
677 }
678
679 /* loader type */
680 /* High nybble = B reserved for Qemu; low nybble is revision number.
681 If this code is substantially changed, you may want to consider
682 incrementing the revision. */
683 if (protocol >= 0x200)
684 header[0x210] = 0xB0;
685
686 /* heap */
687 if (protocol >= 0x201) {
688 header[0x211] |= 0x80; /* CAN_USE_HEAP */
689 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
690 }
691
692 /* load initrd */
693 if (initrd_filename) {
694 if (protocol < 0x200) {
695 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
696 exit(1);
697 }
698
699 fi = fopen(initrd_filename, "rb");
700 if (!fi) {
701 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
702 initrd_filename);
703 exit(1);
704 }
705
706 initrd_size = get_file_size(fi);
707 initrd_addr = (initrd_max-initrd_size) & ~4095;
708
709 if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
710 fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
711 initrd_filename);
712 exit(1);
713 }
714 fclose(fi);
715
716 stl_p(header+0x218, initrd_addr);
717 stl_p(header+0x21c, initrd_size);
718 }
719
720 /* store the finalized header and load the rest of the kernel */
721 cpu_physical_memory_write(real_addr, header, 1024);
722
723 setup_size = header[0x1f1];
724 if (setup_size == 0)
725 setup_size = 4;
726
727 setup_size = (setup_size+1)*512;
728 kernel_size -= setup_size; /* Size of protected-mode code */
729
730 if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
731 !fread_targphys_ok(prot_addr, kernel_size, f)) {
732 fprintf(stderr, "qemu: read error on kernel '%s'\n",
733 kernel_filename);
734 exit(1);
735 }
736 fclose(f);
737
738 /* generate bootsector to set up the initial register state */
739 real_seg = real_addr >> 4;
740 seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
741 seg[1] = real_seg+0x20; /* CS */
742 memset(gpr, 0, sizeof gpr);
743 gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */
744
745 option_rom_setup_reset(real_addr, setup_size);
746 option_rom_setup_reset(prot_addr, kernel_size);
747 option_rom_setup_reset(cmdline_addr, cmdline_size);
748 if (initrd_filename)
749 option_rom_setup_reset(initrd_addr, initrd_size);
750
751 generate_bootsect(option_rom, gpr, seg, 0);
752 }
753
754 static void main_cpu_reset(void *opaque)
755 {
756 CPUState *env = opaque;
757 cpu_reset(env);
758 }
759
760 static const int ide_iobase[2] = { 0x1f0, 0x170 };
761 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
762 static const int ide_irq[2] = { 14, 15 };
763
764 #define NE2000_NB_MAX 6
765
766 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
767 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
768
769 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
770 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
771
772 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
773 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
774
775 #ifdef HAS_AUDIO
776 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
777 {
778 struct soundhw *c;
779
780 for (c = soundhw; c->name; ++c) {
781 if (c->enabled) {
782 if (c->isa) {
783 c->init.init_isa(pic);
784 } else {
785 if (pci_bus) {
786 c->init.init_pci(pci_bus);
787 }
788 }
789 }
790 }
791 }
792 #endif
793
794 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
795 {
796 static int nb_ne2k = 0;
797
798 if (nb_ne2k == NE2000_NB_MAX)
799 return;
800 isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
801 nb_ne2k++;
802 }
803
804 static int load_option_rom(const char *oprom, target_phys_addr_t start,
805 target_phys_addr_t end)
806 {
807 int size;
808 char *filename;
809
810 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom);
811 if (filename) {
812 size = get_image_size(filename);
813 if (size > 0 && start + size > end) {
814 fprintf(stderr, "Not enough space to load option rom '%s'\n",
815 oprom);
816 exit(1);
817 }
818 size = load_image_targphys(filename, start, end - start);
819 qemu_free(filename);
820 } else {
821 size = -1;
822 }
823 if (size < 0) {
824 fprintf(stderr, "Could not load option rom '%s'\n", oprom);
825 exit(1);
826 }
827 /* Round up optiom rom size to the next 2k boundary */
828 size = (size + 2047) & ~2047;
829 option_rom_setup_reset(start, size);
830 return size;
831 }
832
833 int cpu_is_bsp(CPUState *env)
834 {
835 return env->cpuid_apic_id == 0;
836 }
837
838 /* PC hardware initialisation */
839 static void pc_init1(ram_addr_t ram_size,
840 const char *boot_device,
841 const char *kernel_filename, const char *kernel_cmdline,
842 const char *initrd_filename,
843 int pci_enabled, const char *cpu_model)
844 {
845 char *filename;
846 int ret, linux_boot, i;
847 ram_addr_t ram_addr, bios_offset, option_rom_offset;
848 ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
849 int bios_size, isa_bios_size, oprom_area_size;
850 PCIBus *pci_bus;
851 PCIDevice *pci_dev;
852 int piix3_devfn = -1;
853 CPUState *env;
854 qemu_irq *cpu_irq;
855 qemu_irq *i8259;
856 int index;
857 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
858 BlockDriverState *fd[MAX_FD];
859 int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
860
861 if (ram_size >= 0xe0000000 ) {
862 above_4g_mem_size = ram_size - 0xe0000000;
863 below_4g_mem_size = 0xe0000000;
864 } else {
865 below_4g_mem_size = ram_size;
866 }
867
868 linux_boot = (kernel_filename != NULL);
869
870 /* init CPUs */
871 if (cpu_model == NULL) {
872 #ifdef TARGET_X86_64
873 cpu_model = "qemu64";
874 #else
875 cpu_model = "qemu32";
876 #endif
877 }
878
879 for(i = 0; i < smp_cpus; i++) {
880 env = cpu_init(cpu_model);
881 if (!env) {
882 fprintf(stderr, "Unable to find x86 CPU definition\n");
883 exit(1);
884 }
885 if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
886 env->cpuid_apic_id = env->cpu_index;
887 apic_init(env);
888 }
889 qemu_register_reset(main_cpu_reset, 0, env);
890 }
891
892 vmport_init();
893
894 /* allocate RAM */
895 ram_addr = qemu_ram_alloc(0xa0000);
896 cpu_register_physical_memory(0, 0xa0000, ram_addr);
897
898 /* Allocate, even though we won't register, so we don't break the
899 * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
900 * and some bios areas, which will be registered later
901 */
902 ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
903 ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
904 cpu_register_physical_memory(0x100000,
905 below_4g_mem_size - 0x100000,
906 ram_addr);
907
908 /* above 4giga memory allocation */
909 if (above_4g_mem_size > 0) {
910 #if TARGET_PHYS_ADDR_BITS == 32
911 hw_error("To much RAM for 32-bit physical address");
912 #else
913 ram_addr = qemu_ram_alloc(above_4g_mem_size);
914 cpu_register_physical_memory(0x100000000ULL,
915 above_4g_mem_size,
916 ram_addr);
917 #endif
918 }
919
920
921 /* BIOS load */
922 if (bios_name == NULL)
923 bios_name = BIOS_FILENAME;
924 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
925 if (filename) {
926 bios_size = get_image_size(filename);
927 } else {
928 bios_size = -1;
929 }
930 if (bios_size <= 0 ||
931 (bios_size % 65536) != 0) {
932 goto bios_error;
933 }
934 bios_offset = qemu_ram_alloc(bios_size);
935 ret = load_image(filename, qemu_get_ram_ptr(bios_offset));
936 if (ret != bios_size) {
937 bios_error:
938 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
939 exit(1);
940 }
941 if (filename) {
942 qemu_free(filename);
943 }
944 /* map the last 128KB of the BIOS in ISA space */
945 isa_bios_size = bios_size;
946 if (isa_bios_size > (128 * 1024))
947 isa_bios_size = 128 * 1024;
948 cpu_register_physical_memory(0x100000 - isa_bios_size,
949 isa_bios_size,
950 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
951
952
953
954 option_rom_offset = qemu_ram_alloc(0x20000);
955 oprom_area_size = 0;
956 cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset);
957
958 if (using_vga) {
959 const char *vgabios_filename;
960 /* VGA BIOS load */
961 if (cirrus_vga_enabled) {
962 vgabios_filename = VGABIOS_CIRRUS_FILENAME;
963 } else {
964 vgabios_filename = VGABIOS_FILENAME;
965 }
966 oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000);
967 }
968 /* Although video roms can grow larger than 0x8000, the area between
969 * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
970 * for any other kind of option rom inside this area */
971 if (oprom_area_size < 0x8000)
972 oprom_area_size = 0x8000;
973
974 if (linux_boot) {
975 load_linux(0xc0000 + oprom_area_size,
976 kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
977 oprom_area_size += 2048;
978 }
979
980 for (i = 0; i < nb_option_roms; i++) {
981 oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size,
982 0xe0000);
983 }
984
985 for (i = 0; i < nb_nics; i++) {
986 char nic_oprom[1024];
987 const char *model = nd_table[i].model;
988
989 if (!nd_table[i].bootable)
990 continue;
991
992 if (model == NULL)
993 model = "ne2k_pci";
994 snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model);
995
996 oprom_area_size += load_option_rom(nic_oprom, 0xc0000 + oprom_area_size,
997 0xe0000);
998 }
999
1000 /* map all the bios at the top of memory */
1001 cpu_register_physical_memory((uint32_t)(-bios_size),
1002 bios_size, bios_offset | IO_MEM_ROM);
1003
1004 bochs_bios_init();
1005
1006 cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
1007 i8259 = i8259_init(cpu_irq[0]);
1008 ferr_irq = i8259[13];
1009
1010 if (pci_enabled) {
1011 pci_bus = i440fx_init(&i440fx_state, i8259);
1012 piix3_devfn = piix3_init(pci_bus, -1);
1013 } else {
1014 pci_bus = NULL;
1015 }
1016
1017 /* init basic PC hardware */
1018 register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1019
1020 register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1021
1022 if (cirrus_vga_enabled) {
1023 if (pci_enabled) {
1024 pci_cirrus_vga_init(pci_bus);
1025 } else {
1026 isa_cirrus_vga_init();
1027 }
1028 } else if (vmsvga_enabled) {
1029 if (pci_enabled)
1030 pci_vmsvga_init(pci_bus);
1031 else
1032 fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1033 } else if (std_vga_enabled) {
1034 if (pci_enabled) {
1035 pci_vga_init(pci_bus, 0, 0);
1036 } else {
1037 isa_vga_init();
1038 }
1039 }
1040
1041 rtc_state = rtc_init(0x70, i8259[8], 2000);
1042
1043 qemu_register_boot_set(pc_boot_set, rtc_state);
1044
1045 register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1046 register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1047
1048 if (pci_enabled) {
1049 ioapic = ioapic_init();
1050 }
1051 pit = pit_init(0x40, i8259[0]);
1052 pcspk_init(pit);
1053 if (!no_hpet) {
1054 hpet_init(i8259);
1055 }
1056 if (pci_enabled) {
1057 pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
1058 }
1059
1060 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1061 if (serial_hds[i]) {
1062 serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
1063 serial_hds[i]);
1064 }
1065 }
1066
1067 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1068 if (parallel_hds[i]) {
1069 parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1070 parallel_hds[i]);
1071 }
1072 }
1073
1074 watchdog_pc_init(pci_bus);
1075
1076 for(i = 0; i < nb_nics; i++) {
1077 NICInfo *nd = &nd_table[i];
1078
1079 if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1080 pc_init_ne2k_isa(nd, i8259);
1081 else
1082 pci_nic_init(nd, "ne2k_pci", NULL);
1083 }
1084
1085 piix4_acpi_system_hot_add_init();
1086
1087 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1088 fprintf(stderr, "qemu: too many IDE bus\n");
1089 exit(1);
1090 }
1091
1092 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1093 index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1094 if (index != -1)
1095 hd[i] = drives_table[index].bdrv;
1096 else
1097 hd[i] = NULL;
1098 }
1099
1100 if (pci_enabled) {
1101 pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1102 } else {
1103 for(i = 0; i < MAX_IDE_BUS; i++) {
1104 isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1105 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1106 }
1107 }
1108
1109 i8042_init(i8259[1], i8259[12], 0x60);
1110 DMA_init(0);
1111 #ifdef HAS_AUDIO
1112 audio_init(pci_enabled ? pci_bus : NULL, i8259);
1113 #endif
1114
1115 for(i = 0; i < MAX_FD; i++) {
1116 index = drive_get_index(IF_FLOPPY, 0, i);
1117 if (index != -1)
1118 fd[i] = drives_table[index].bdrv;
1119 else
1120 fd[i] = NULL;
1121 }
1122 floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1123
1124 cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1125
1126 if (pci_enabled && usb_enabled) {
1127 usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1128 }
1129
1130 if (pci_enabled && acpi_enabled) {
1131 uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1132 i2c_bus *smbus;
1133
1134 /* TODO: Populate SPD eeprom data. */
1135 smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1136 for (i = 0; i < 8; i++) {
1137 DeviceState *eeprom;
1138 eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1139 qdev_set_prop_int(eeprom, "address", 0x50 + i);
1140 qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));
1141 qdev_init(eeprom);
1142 }
1143 }
1144
1145 if (i440fx_state) {
1146 i440fx_init_memory_mappings(i440fx_state);
1147 }
1148
1149 if (pci_enabled) {
1150 int max_bus;
1151 int bus;
1152
1153 max_bus = drive_get_max_bus(IF_SCSI);
1154 for (bus = 0; bus <= max_bus; bus++) {
1155 pci_create_simple(pci_bus, -1, "lsi53c895a");
1156 }
1157 }
1158
1159 /* Add virtio block devices */
1160 if (pci_enabled) {
1161 int index;
1162 int unit_id = 0;
1163
1164 while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
1165 pci_dev = pci_create("virtio-blk-pci",
1166 drives_table[index].devaddr);
1167 qdev_init(&pci_dev->qdev);
1168 unit_id++;
1169 }
1170 }
1171
1172 /* Add virtio balloon device */
1173 if (pci_enabled && !no_virtio_balloon) {
1174 pci_create_simple(pci_bus, -1, "virtio-balloon-pci");
1175 }
1176
1177 /* Add virtio console devices */
1178 if (pci_enabled) {
1179 for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1180 if (virtcon_hds[i]) {
1181 pci_create_simple(pci_bus, -1, "virtio-console-pci");
1182 }
1183 }
1184 }
1185 }
1186
1187 static void pc_init_pci(ram_addr_t ram_size,
1188 const char *boot_device,
1189 const char *kernel_filename,
1190 const char *kernel_cmdline,
1191 const char *initrd_filename,
1192 const char *cpu_model)
1193 {
1194 pc_init1(ram_size, boot_device,
1195 kernel_filename, kernel_cmdline,
1196 initrd_filename, 1, cpu_model);
1197 }
1198
1199 static void pc_init_isa(ram_addr_t ram_size,
1200 const char *boot_device,
1201 const char *kernel_filename,
1202 const char *kernel_cmdline,
1203 const char *initrd_filename,
1204 const char *cpu_model)
1205 {
1206 pc_init1(ram_size, boot_device,
1207 kernel_filename, kernel_cmdline,
1208 initrd_filename, 0, cpu_model);
1209 }
1210
1211 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1212 BIOS will read it and start S3 resume at POST Entry */
1213 void cmos_set_s3_resume(void)
1214 {
1215 if (rtc_state)
1216 rtc_set_memory(rtc_state, 0xF, 0xFE);
1217 }
1218
1219 static QEMUMachine pc_machine = {
1220 .name = "pc",
1221 .desc = "Standard PC",
1222 .init = pc_init_pci,
1223 .max_cpus = 255,
1224 .is_default = 1,
1225 };
1226
1227 static QEMUMachine isapc_machine = {
1228 .name = "isapc",
1229 .desc = "ISA-only PC",
1230 .init = pc_init_isa,
1231 .max_cpus = 1,
1232 };
1233
1234 static void pc_machine_init(void)
1235 {
1236 qemu_register_machine(&pc_machine);
1237 qemu_register_machine(&isapc_machine);
1238 }
1239
1240 machine_init(pc_machine_init);
CRIS target port of Qemu