target-i386/fpu_helper.c

   1 /*
   2  *  x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <math.h>
  21 #include "cpu.h"
  22 #include "exec/helper-proto.h"
  23 #include "qemu/aes.h"
  24 #include "qemu/host-utils.h"
  25 #include "exec/cpu_ldst.h"
  26
  27 #define FPU_RC_MASK         0xc00
  28 #define FPU_RC_NEAR         0x000
  29 #define FPU_RC_DOWN         0x400
  30 #define FPU_RC_UP           0x800
  31 #define FPU_RC_CHOP         0xc00
  32
  33 #define MAXTAN 9223372036854775808.0
  34
  35 /* the following deal with x86 long double-precision numbers */
  36 #define MAXEXPD 0x7fff
  37 #define EXPBIAS 16383
  38 #define EXPD(fp)        (fp.l.upper & 0x7fff)
  39 #define SIGND(fp)       ((fp.l.upper) & 0x8000)
  40 #define MANTD(fp)       (fp.l.lower)
  41 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
  42
  43 #define FPUS_IE (1 << 0)
  44 #define FPUS_DE (1 << 1)
  45 #define FPUS_ZE (1 << 2)
  46 #define FPUS_OE (1 << 3)
  47 #define FPUS_UE (1 << 4)
  48 #define FPUS_PE (1 << 5)
  49 #define FPUS_SF (1 << 6)
  50 #define FPUS_SE (1 << 7)
  51 #define FPUS_B  (1 << 15)
  52
  53 #define FPUC_EM 0x3f
  54
  55 #define floatx80_lg2 make_floatx80(0x3ffd, 0x9a209a84fbcff799LL)
  56 #define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
  57 #define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
  58
  59 static inline void fpush(CPUX86State *env)
  60 {
  61     env->fpstt = (env->fpstt - 1) & 7;
  62     env->fptags[env->fpstt] = 0; /* validate stack entry */
  63 }
  64
  65 static inline void fpop(CPUX86State *env)
  66 {
  67     env->fptags[env->fpstt] = 1; /* invalidate stack entry */
  68     env->fpstt = (env->fpstt + 1) & 7;
  69 }
  70
  71 static inline floatx80 helper_fldt(CPUX86State *env, target_ulong ptr)
  72 {
  73     CPU_LDoubleU temp;
  74
  75     temp.l.lower = cpu_ldq_data(env, ptr);
  76     temp.l.upper = cpu_lduw_data(env, ptr + 8);
  77     return temp.d;
  78 }
  79
  80 static inline void helper_fstt(CPUX86State *env, floatx80 f, target_ulong ptr)
  81 {
  82     CPU_LDoubleU temp;
  83
  84     temp.d = f;
  85     cpu_stq_data(env, ptr, temp.l.lower);
  86     cpu_stw_data(env, ptr + 8, temp.l.upper);
  87 }
  88
  89 /* x87 FPU helpers */
  90
  91 static inline double floatx80_to_double(CPUX86State *env, floatx80 a)
  92 {
  93     union {
  94         float64 f64;
  95         double d;
  96     } u;
  97
  98     u.f64 = floatx80_to_float64(a, &env->fp_status);
  99     return u.d;
 100 }
 101
 102 static inline floatx80 double_to_floatx80(CPUX86State *env, double a)
 103 {
 104     union {
 105         float64 f64;
 106         double d;
 107     } u;
 108
 109     u.d = a;
 110     return float64_to_floatx80(u.f64, &env->fp_status);
 111 }
 112
 113 static void fpu_set_exception(CPUX86State *env, int mask)
 114 {
 115     env->fpus |= mask;
 116     if (env->fpus & (~env->fpuc & FPUC_EM)) {
 117         env->fpus |= FPUS_SE | FPUS_B;
 118     }
 119 }
 120
 121 static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)
 122 {
 123     if (floatx80_is_zero(b)) {
 124         fpu_set_exception(env, FPUS_ZE);
 125     }
 126     return floatx80_div(a, b, &env->fp_status);
 127 }
 128
 129 static void fpu_raise_exception(CPUX86State *env)
 130 {
 131     if (env->cr[0] & CR0_NE_MASK) {
 132         raise_exception(env, EXCP10_COPR);
 133     }
 134 #if !defined(CONFIG_USER_ONLY)
 135     else {
 136         cpu_set_ferr(env);
 137     }
 138 #endif
 139 }
 140
 141 void helper_flds_FT0(CPUX86State *env, uint32_t val)
 142 {
 143     union {
 144         float32 f;
 145         uint32_t i;
 146     } u;
 147
 148     u.i = val;
 149     FT0 = float32_to_floatx80(u.f, &env->fp_status);
 150 }
 151
 152 void helper_fldl_FT0(CPUX86State *env, uint64_t val)
 153 {
 154     union {
 155         float64 f;
 156         uint64_t i;
 157     } u;
 158
 159     u.i = val;
 160     FT0 = float64_to_floatx80(u.f, &env->fp_status);
 161 }
 162
 163 void helper_fildl_FT0(CPUX86State *env, int32_t val)
 164 {
 165     FT0 = int32_to_floatx80(val, &env->fp_status);
 166 }
 167
 168 void helper_flds_ST0(CPUX86State *env, uint32_t val)
 169 {
 170     int new_fpstt;
 171     union {
 172         float32 f;
 173         uint32_t i;
 174     } u;
 175
 176     new_fpstt = (env->fpstt - 1) & 7;
 177     u.i = val;
 178     env->fpregs[new_fpstt].d = float32_to_floatx80(u.f, &env->fp_status);
 179     env->fpstt = new_fpstt;
 180     env->fptags[new_fpstt] = 0; /* validate stack entry */
 181 }
 182
 183 void helper_fldl_ST0(CPUX86State *env, uint64_t val)
 184 {
 185     int new_fpstt;
 186     union {
 187         float64 f;
 188         uint64_t i;
 189     } u;
 190
 191     new_fpstt = (env->fpstt - 1) & 7;
 192     u.i = val;
 193     env->fpregs[new_fpstt].d = float64_to_floatx80(u.f, &env->fp_status);
 194     env->fpstt = new_fpstt;
 195     env->fptags[new_fpstt] = 0; /* validate stack entry */
 196 }
 197
 198 void helper_fildl_ST0(CPUX86State *env, int32_t val)
 199 {
 200     int new_fpstt;
 201
 202     new_fpstt = (env->fpstt - 1) & 7;
 203     env->fpregs[new_fpstt].d = int32_to_floatx80(val, &env->fp_status);
 204     env->fpstt = new_fpstt;
 205     env->fptags[new_fpstt] = 0; /* validate stack entry */
 206 }
 207
 208 void helper_fildll_ST0(CPUX86State *env, int64_t val)
 209 {
 210     int new_fpstt;
 211
 212     new_fpstt = (env->fpstt - 1) & 7;
 213     env->fpregs[new_fpstt].d = int64_to_floatx80(val, &env->fp_status);
 214     env->fpstt = new_fpstt;
 215     env->fptags[new_fpstt] = 0; /* validate stack entry */
 216 }
 217
 218 uint32_t helper_fsts_ST0(CPUX86State *env)
 219 {
 220     union {
 221         float32 f;
 222         uint32_t i;
 223     } u;
 224
 225     u.f = floatx80_to_float32(ST0, &env->fp_status);
 226     return u.i;
 227 }
 228
 229 uint64_t helper_fstl_ST0(CPUX86State *env)
 230 {
 231     union {
 232         float64 f;
 233         uint64_t i;
 234     } u;
 235
 236     u.f = floatx80_to_float64(ST0, &env->fp_status);
 237     return u.i;
 238 }
 239
 240 int32_t helper_fist_ST0(CPUX86State *env)
 241 {
 242     int32_t val;
 243
 244     val = floatx80_to_int32(ST0, &env->fp_status);
 245     if (val != (int16_t)val) {
 246         val = -32768;
 247     }
 248     return val;
 249 }
 250
 251 int32_t helper_fistl_ST0(CPUX86State *env)
 252 {
 253     int32_t val;
 254     signed char old_exp_flags;
 255
 256     old_exp_flags = get_float_exception_flags(&env->fp_status);
 257     set_float_exception_flags(0, &env->fp_status);
 258
 259     val = floatx80_to_int32(ST0, &env->fp_status);
 260     if (get_float_exception_flags(&env->fp_status) & float_flag_invalid) {
 261         val = 0x80000000;
 262     }
 263     set_float_exception_flags(get_float_exception_flags(&env->fp_status)
 264                                 | old_exp_flags, &env->fp_status);
 265     return val;
 266 }
 267
 268 int64_t helper_fistll_ST0(CPUX86State *env)
 269 {
 270     int64_t val;
 271     signed char old_exp_flags;
 272
 273     old_exp_flags = get_float_exception_flags(&env->fp_status);
 274     set_float_exception_flags(0, &env->fp_status);
 275
 276     val = floatx80_to_int32(ST0, &env->fp_status);
 277     if (get_float_exception_flags(&env->fp_status) & float_flag_invalid) {
 278         val = 0x8000000000000000ULL;
 279     }
 280     set_float_exception_flags(get_float_exception_flags(&env->fp_status)
 281                                 | old_exp_flags, &env->fp_status);
 282     return val;
 283 }
 284
 285 int32_t helper_fistt_ST0(CPUX86State *env)
 286 {
 287     int32_t val;
 288
 289     val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
 290     if (val != (int16_t)val) {
 291         val = -32768;
 292     }
 293     return val;
 294 }
 295
 296 int32_t helper_fisttl_ST0(CPUX86State *env)
 297 {
 298     int32_t val;
 299
 300     val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
 301     return val;
 302 }
 303
 304 int64_t helper_fisttll_ST0(CPUX86State *env)
 305 {
 306     int64_t val;
 307
 308     val = floatx80_to_int64_round_to_zero(ST0, &env->fp_status);
 309     return val;
 310 }
 311
 312 void helper_fldt_ST0(CPUX86State *env, target_ulong ptr)
 313 {
 314     int new_fpstt;
 315
 316     new_fpstt = (env->fpstt - 1) & 7;
 317     env->fpregs[new_fpstt].d = helper_fldt(env, ptr);
 318     env->fpstt = new_fpstt;
 319     env->fptags[new_fpstt] = 0; /* validate stack entry */
 320 }
 321
 322 void helper_fstt_ST0(CPUX86State *env, target_ulong ptr)
 323 {
 324     helper_fstt(env, ST0, ptr);
 325 }
 326
 327 void helper_fpush(CPUX86State *env)
 328 {
 329     fpush(env);
 330 }
 331
 332 void helper_fpop(CPUX86State *env)
 333 {
 334     fpop(env);
 335 }
 336
 337 void helper_fdecstp(CPUX86State *env)
 338 {
 339     env->fpstt = (env->fpstt - 1) & 7;
 340     env->fpus &= ~0x4700;
 341 }
 342
 343 void helper_fincstp(CPUX86State *env)
 344 {
 345     env->fpstt = (env->fpstt + 1) & 7;
 346     env->fpus &= ~0x4700;
 347 }
 348
 349 /* FPU move */
 350
 351 void helper_ffree_STN(CPUX86State *env, int st_index)
 352 {
 353     env->fptags[(env->fpstt + st_index) & 7] = 1;
 354 }
 355
 356 void helper_fmov_ST0_FT0(CPUX86State *env)
 357 {
 358     ST0 = FT0;
 359 }
 360
 361 void helper_fmov_FT0_STN(CPUX86State *env, int st_index)
 362 {
 363     FT0 = ST(st_index);
 364 }
 365
 366 void helper_fmov_ST0_STN(CPUX86State *env, int st_index)
 367 {
 368     ST0 = ST(st_index);
 369 }
 370
 371 void helper_fmov_STN_ST0(CPUX86State *env, int st_index)
 372 {
 373     ST(st_index) = ST0;
 374 }
 375
 376 void helper_fxchg_ST0_STN(CPUX86State *env, int st_index)
 377 {
 378     floatx80 tmp;
 379
 380     tmp = ST(st_index);
 381     ST(st_index) = ST0;
 382     ST0 = tmp;
 383 }
 384
 385 /* FPU operations */
 386
 387 static const int fcom_ccval[4] = {0x0100, 0x4000, 0x0000, 0x4500};
 388
 389 void helper_fcom_ST0_FT0(CPUX86State *env)
 390 {
 391     int ret;
 392
 393     ret = floatx80_compare(ST0, FT0, &env->fp_status);
 394     env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
 395 }
 396
 397 void helper_fucom_ST0_FT0(CPUX86State *env)
 398 {
 399     int ret;
 400
 401     ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
 402     env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
 403 }
 404
 405 static const int fcomi_ccval[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
 406
 407 void helper_fcomi_ST0_FT0(CPUX86State *env)
 408 {
 409     int eflags;
 410     int ret;
 411
 412     ret = floatx80_compare(ST0, FT0, &env->fp_status);
 413     eflags = cpu_cc_compute_all(env, CC_OP);
 414     eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
 415     CC_SRC = eflags;
 416 }
 417
 418 void helper_fucomi_ST0_FT0(CPUX86State *env)
 419 {
 420     int eflags;
 421     int ret;
 422
 423     ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
 424     eflags = cpu_cc_compute_all(env, CC_OP);
 425     eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
 426     CC_SRC = eflags;
 427 }
 428
 429 void helper_fadd_ST0_FT0(CPUX86State *env)
 430 {
 431     ST0 = floatx80_add(ST0, FT0, &env->fp_status);
 432 }
 433
 434 void helper_fmul_ST0_FT0(CPUX86State *env)
 435 {
 436     ST0 = floatx80_mul(ST0, FT0, &env->fp_status);
 437 }
 438
 439 void helper_fsub_ST0_FT0(CPUX86State *env)
 440 {
 441     ST0 = floatx80_sub(ST0, FT0, &env->fp_status);
 442 }
 443
 444 void helper_fsubr_ST0_FT0(CPUX86State *env)
 445 {
 446     ST0 = floatx80_sub(FT0, ST0, &env->fp_status);
 447 }
 448
 449 void helper_fdiv_ST0_FT0(CPUX86State *env)
 450 {
 451     ST0 = helper_fdiv(env, ST0, FT0);
 452 }
 453
 454 void helper_fdivr_ST0_FT0(CPUX86State *env)
 455 {
 456     ST0 = helper_fdiv(env, FT0, ST0);
 457 }
 458
 459 /* fp operations between STN and ST0 */
 460
 461 void helper_fadd_STN_ST0(CPUX86State *env, int st_index)
 462 {
 463     ST(st_index) = floatx80_add(ST(st_index), ST0, &env->fp_status);
 464 }
 465
 466 void helper_fmul_STN_ST0(CPUX86State *env, int st_index)
 467 {
 468     ST(st_index) = floatx80_mul(ST(st_index), ST0, &env->fp_status);
 469 }
 470
 471 void helper_fsub_STN_ST0(CPUX86State *env, int st_index)
 472 {
 473     ST(st_index) = floatx80_sub(ST(st_index), ST0, &env->fp_status);
 474 }
 475
 476 void helper_fsubr_STN_ST0(CPUX86State *env, int st_index)
 477 {
 478     ST(st_index) = floatx80_sub(ST0, ST(st_index), &env->fp_status);
 479 }
 480
 481 void helper_fdiv_STN_ST0(CPUX86State *env, int st_index)
 482 {
 483     floatx80 *p;
 484
 485     p = &ST(st_index);
 486     *p = helper_fdiv(env, *p, ST0);
 487 }
 488
 489 void helper_fdivr_STN_ST0(CPUX86State *env, int st_index)
 490 {
 491     floatx80 *p;
 492
 493     p = &ST(st_index);
 494     *p = helper_fdiv(env, ST0, *p);
 495 }
 496
 497 /* misc FPU operations */
 498 void helper_fchs_ST0(CPUX86State *env)
 499 {
 500     ST0 = floatx80_chs(ST0);
 501 }
 502
 503 void helper_fabs_ST0(CPUX86State *env)
 504 {
 505     ST0 = floatx80_abs(ST0);
 506 }
 507
 508 void helper_fld1_ST0(CPUX86State *env)
 509 {
 510     ST0 = floatx80_one;
 511 }
 512
 513 void helper_fldl2t_ST0(CPUX86State *env)
 514 {
 515     ST0 = floatx80_l2t;
 516 }
 517
 518 void helper_fldl2e_ST0(CPUX86State *env)
 519 {
 520     ST0 = floatx80_l2e;
 521 }
 522
 523 void helper_fldpi_ST0(CPUX86State *env)
 524 {
 525     ST0 = floatx80_pi;
 526 }
 527
 528 void helper_fldlg2_ST0(CPUX86State *env)
 529 {
 530     ST0 = floatx80_lg2;
 531 }
 532
 533 void helper_fldln2_ST0(CPUX86State *env)
 534 {
 535     ST0 = floatx80_ln2;
 536 }
 537
 538 void helper_fldz_ST0(CPUX86State *env)
 539 {
 540     ST0 = floatx80_zero;
 541 }
 542
 543 void helper_fldz_FT0(CPUX86State *env)
 544 {
 545     FT0 = floatx80_zero;
 546 }
 547
 548 uint32_t helper_fnstsw(CPUX86State *env)
 549 {
 550     return (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 551 }
 552
 553 uint32_t helper_fnstcw(CPUX86State *env)
 554 {
 555     return env->fpuc;
 556 }
 557
 558 void update_fp_status(CPUX86State *env)
 559 {
 560     int rnd_type;
 561
 562     /* set rounding mode */
 563     switch (env->fpuc & FPU_RC_MASK) {
 564     default:
 565     case FPU_RC_NEAR:
 566         rnd_type = float_round_nearest_even;
 567         break;
 568     case FPU_RC_DOWN:
 569         rnd_type = float_round_down;
 570         break;
 571     case FPU_RC_UP:
 572         rnd_type = float_round_up;
 573         break;
 574     case FPU_RC_CHOP:
 575         rnd_type = float_round_to_zero;
 576         break;
 577     }
 578     set_float_rounding_mode(rnd_type, &env->fp_status);
 579     switch ((env->fpuc >> 8) & 3) {
 580     case 0:
 581         rnd_type = 32;
 582         break;
 583     case 2:
 584         rnd_type = 64;
 585         break;
 586     case 3:
 587     default:
 588         rnd_type = 80;
 589         break;
 590     }
 591     set_floatx80_rounding_precision(rnd_type, &env->fp_status);
 592 }
 593
 594 void helper_fldcw(CPUX86State *env, uint32_t val)
 595 {
 596     cpu_set_fpuc(env, val);
 597 }
 598
 599 void helper_fclex(CPUX86State *env)
 600 {
 601     env->fpus &= 0x7f00;
 602 }
 603
 604 void helper_fwait(CPUX86State *env)
 605 {
 606     if (env->fpus & FPUS_SE) {
 607         fpu_raise_exception(env);
 608     }
 609 }
 610
 611 void helper_fninit(CPUX86State *env)
 612 {
 613     env->fpus = 0;
 614     env->fpstt = 0;
 615     cpu_set_fpuc(env, 0x37f);
 616     env->fptags[0] = 1;
 617     env->fptags[1] = 1;
 618     env->fptags[2] = 1;
 619     env->fptags[3] = 1;
 620     env->fptags[4] = 1;
 621     env->fptags[5] = 1;
 622     env->fptags[6] = 1;
 623     env->fptags[7] = 1;
 624 }
 625
 626 /* BCD ops */
 627
 628 void helper_fbld_ST0(CPUX86State *env, target_ulong ptr)
 629 {
 630     floatx80 tmp;
 631     uint64_t val;
 632     unsigned int v;
 633     int i;
 634
 635     val = 0;
 636     for (i = 8; i >= 0; i--) {
 637         v = cpu_ldub_data(env, ptr + i);
 638         val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
 639     }
 640     tmp = int64_to_floatx80(val, &env->fp_status);
 641     if (cpu_ldub_data(env, ptr + 9) & 0x80) {
 642         tmp = floatx80_chs(tmp);
 643     }
 644     fpush(env);
 645     ST0 = tmp;
 646 }
 647
 648 void helper_fbst_ST0(CPUX86State *env, target_ulong ptr)
 649 {
 650     int v;
 651     target_ulong mem_ref, mem_end;
 652     int64_t val;
 653
 654     val = floatx80_to_int64(ST0, &env->fp_status);
 655     mem_ref = ptr;
 656     mem_end = mem_ref + 9;
 657     if (val < 0) {
 658         cpu_stb_data(env, mem_end, 0x80);
 659         val = -val;
 660     } else {
 661         cpu_stb_data(env, mem_end, 0x00);
 662     }
 663     while (mem_ref < mem_end) {
 664         if (val == 0) {
 665             break;
 666         }
 667         v = val % 100;
 668         val = val / 100;
 669         v = ((v / 10) << 4) | (v % 10);
 670         cpu_stb_data(env, mem_ref++, v);
 671     }
 672     while (mem_ref < mem_end) {
 673         cpu_stb_data(env, mem_ref++, 0);
 674     }
 675 }
 676
 677 void helper_f2xm1(CPUX86State *env)
 678 {
 679     double val = floatx80_to_double(env, ST0);
 680
 681     val = pow(2.0, val) - 1.0;
 682     ST0 = double_to_floatx80(env, val);
 683 }
 684
 685 void helper_fyl2x(CPUX86State *env)
 686 {
 687     double fptemp = floatx80_to_double(env, ST0);
 688
 689     if (fptemp > 0.0) {
 690         fptemp = log(fptemp) / log(2.0); /* log2(ST) */
 691         fptemp *= floatx80_to_double(env, ST1);
 692         ST1 = double_to_floatx80(env, fptemp);
 693         fpop(env);
 694     } else {
 695         env->fpus &= ~0x4700;
 696         env->fpus |= 0x400;
 697     }
 698 }
 699
 700 void helper_fptan(CPUX86State *env)
 701 {
 702     double fptemp = floatx80_to_double(env, ST0);
 703
 704     if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
 705         env->fpus |= 0x400;
 706     } else {
 707         fptemp = tan(fptemp);
 708         ST0 = double_to_floatx80(env, fptemp);
 709         fpush(env);
 710         ST0 = floatx80_one;
 711         env->fpus &= ~0x400; /* C2 <-- 0 */
 712         /* the above code is for |arg| < 2**52 only */
 713     }
 714 }
 715
 716 void helper_fpatan(CPUX86State *env)
 717 {
 718     double fptemp, fpsrcop;
 719
 720     fpsrcop = floatx80_to_double(env, ST1);
 721     fptemp = floatx80_to_double(env, ST0);
 722     ST1 = double_to_floatx80(env, atan2(fpsrcop, fptemp));
 723     fpop(env);
 724 }
 725
 726 void helper_fxtract(CPUX86State *env)
 727 {
 728     CPU_LDoubleU temp;
 729
 730     temp.d = ST0;
 731
 732     if (floatx80_is_zero(ST0)) {
 733         /* Easy way to generate -inf and raising division by 0 exception */
 734         ST0 = floatx80_div(floatx80_chs(floatx80_one), floatx80_zero,
 735                            &env->fp_status);
 736         fpush(env);
 737         ST0 = temp.d;
 738     } else {
 739         int expdif;
 740
 741         expdif = EXPD(temp) - EXPBIAS;
 742         /* DP exponent bias */
 743         ST0 = int32_to_floatx80(expdif, &env->fp_status);
 744         fpush(env);
 745         BIASEXPONENT(temp);
 746         ST0 = temp.d;
 747     }
 748 }
 749
 750 void helper_fprem1(CPUX86State *env)
 751 {
 752     double st0, st1, dblq, fpsrcop, fptemp;
 753     CPU_LDoubleU fpsrcop1, fptemp1;
 754     int expdif;
 755     signed long long int q;
 756
 757     st0 = floatx80_to_double(env, ST0);
 758     st1 = floatx80_to_double(env, ST1);
 759
 760     if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
 761         ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
 762         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 763         return;
 764     }
 765
 766     fpsrcop = st0;
 767     fptemp = st1;
 768     fpsrcop1.d = ST0;
 769     fptemp1.d = ST1;
 770     expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
 771
 772     if (expdif < 0) {
 773         /* optimisation? taken from the AMD docs */
 774         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 775         /* ST0 is unchanged */
 776         return;
 777     }
 778
 779     if (expdif < 53) {
 780         dblq = fpsrcop / fptemp;
 781         /* round dblq towards nearest integer */
 782         dblq = rint(dblq);
 783         st0 = fpsrcop - fptemp * dblq;
 784
 785         /* convert dblq to q by truncating towards zero */
 786         if (dblq < 0.0) {
 787             q = (signed long long int)(-dblq);
 788         } else {
 789             q = (signed long long int)dblq;
 790         }
 791
 792         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 793         /* (C0,C3,C1) <-- (q2,q1,q0) */
 794         env->fpus |= (q & 0x4) << (8 - 2);  /* (C0) <-- q2 */
 795         env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
 796         env->fpus |= (q & 0x1) << (9 - 0);  /* (C1) <-- q0 */
 797     } else {
 798         env->fpus |= 0x400;  /* C2 <-- 1 */
 799         fptemp = pow(2.0, expdif - 50);
 800         fpsrcop = (st0 / st1) / fptemp;
 801         /* fpsrcop = integer obtained by chopping */
 802         fpsrcop = (fpsrcop < 0.0) ?
 803                   -(floor(fabs(fpsrcop))) : floor(fpsrcop);
 804         st0 -= (st1 * fpsrcop * fptemp);
 805     }
 806     ST0 = double_to_floatx80(env, st0);
 807 }
 808
 809 void helper_fprem(CPUX86State *env)
 810 {
 811     double st0, st1, dblq, fpsrcop, fptemp;
 812     CPU_LDoubleU fpsrcop1, fptemp1;
 813     int expdif;
 814     signed long long int q;
 815
 816     st0 = floatx80_to_double(env, ST0);
 817     st1 = floatx80_to_double(env, ST1);
 818
 819     if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
 820         ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
 821         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 822         return;
 823     }
 824
 825     fpsrcop = st0;
 826     fptemp = st1;
 827     fpsrcop1.d = ST0;
 828     fptemp1.d = ST1;
 829     expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
 830
 831     if (expdif < 0) {
 832         /* optimisation? taken from the AMD docs */
 833         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 834         /* ST0 is unchanged */
 835         return;
 836     }
 837
 838     if (expdif < 53) {
 839         dblq = fpsrcop / fptemp; /* ST0 / ST1 */
 840         /* round dblq towards zero */
 841         dblq = (dblq < 0.0) ? ceil(dblq) : floor(dblq);
 842         st0 = fpsrcop - fptemp * dblq; /* fpsrcop is ST0 */
 843
 844         /* convert dblq to q by truncating towards zero */
 845         if (dblq < 0.0) {
 846             q = (signed long long int)(-dblq);
 847         } else {
 848             q = (signed long long int)dblq;
 849         }
 850
 851         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 852         /* (C0,C3,C1) <-- (q2,q1,q0) */
 853         env->fpus |= (q & 0x4) << (8 - 2);  /* (C0) <-- q2 */
 854         env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
 855         env->fpus |= (q & 0x1) << (9 - 0);  /* (C1) <-- q0 */
 856     } else {
 857         int N = 32 + (expdif % 32); /* as per AMD docs */
 858
 859         env->fpus |= 0x400;  /* C2 <-- 1 */
 860         fptemp = pow(2.0, (double)(expdif - N));
 861         fpsrcop = (st0 / st1) / fptemp;
 862         /* fpsrcop = integer obtained by chopping */
 863         fpsrcop = (fpsrcop < 0.0) ?
 864                   -(floor(fabs(fpsrcop))) : floor(fpsrcop);
 865         st0 -= (st1 * fpsrcop * fptemp);
 866     }
 867     ST0 = double_to_floatx80(env, st0);
 868 }
 869
 870 void helper_fyl2xp1(CPUX86State *env)
 871 {
 872     double fptemp = floatx80_to_double(env, ST0);
 873
 874     if ((fptemp + 1.0) > 0.0) {
 875         fptemp = log(fptemp + 1.0) / log(2.0); /* log2(ST + 1.0) */
 876         fptemp *= floatx80_to_double(env, ST1);
 877         ST1 = double_to_floatx80(env, fptemp);
 878         fpop(env);
 879     } else {
 880         env->fpus &= ~0x4700;
 881         env->fpus |= 0x400;
 882     }
 883 }
 884
 885 void helper_fsqrt(CPUX86State *env)
 886 {
 887     if (floatx80_is_neg(ST0)) {
 888         env->fpus &= ~0x4700;  /* (C3,C2,C1,C0) <-- 0000 */
 889         env->fpus |= 0x400;
 890     }
 891     ST0 = floatx80_sqrt(ST0, &env->fp_status);
 892 }
 893
 894 void helper_fsincos(CPUX86State *env)
 895 {
 896     double fptemp = floatx80_to_double(env, ST0);
 897
 898     if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
 899         env->fpus |= 0x400;
 900     } else {
 901         ST0 = double_to_floatx80(env, sin(fptemp));
 902         fpush(env);
 903         ST0 = double_to_floatx80(env, cos(fptemp));
 904         env->fpus &= ~0x400;  /* C2 <-- 0 */
 905         /* the above code is for |arg| < 2**63 only */
 906     }
 907 }
 908
 909 void helper_frndint(CPUX86State *env)
 910 {
 911     ST0 = floatx80_round_to_int(ST0, &env->fp_status);
 912 }
 913
 914 void helper_fscale(CPUX86State *env)
 915 {
 916     if (floatx80_is_any_nan(ST1)) {
 917         ST0 = ST1;
 918     } else {
 919         int n = floatx80_to_int32_round_to_zero(ST1, &env->fp_status);
 920         ST0 = floatx80_scalbn(ST0, n, &env->fp_status);
 921     }
 922 }
 923
 924 void helper_fsin(CPUX86State *env)
 925 {
 926     double fptemp = floatx80_to_double(env, ST0);
 927
 928     if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
 929         env->fpus |= 0x400;
 930     } else {
 931         ST0 = double_to_floatx80(env, sin(fptemp));
 932         env->fpus &= ~0x400;  /* C2 <-- 0 */
 933         /* the above code is for |arg| < 2**53 only */
 934     }
 935 }
 936
 937 void helper_fcos(CPUX86State *env)
 938 {
 939     double fptemp = floatx80_to_double(env, ST0);
 940
 941     if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
 942         env->fpus |= 0x400;
 943     } else {
 944         ST0 = double_to_floatx80(env, cos(fptemp));
 945         env->fpus &= ~0x400;  /* C2 <-- 0 */
 946         /* the above code is for |arg| < 2**63 only */
 947     }
 948 }
 949
 950 void helper_fxam_ST0(CPUX86State *env)
 951 {
 952     CPU_LDoubleU temp;
 953     int expdif;
 954
 955     temp.d = ST0;
 956
 957     env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 958     if (SIGND(temp)) {
 959         env->fpus |= 0x200; /* C1 <-- 1 */
 960     }
 961
 962     /* XXX: test fptags too */
 963     expdif = EXPD(temp);
 964     if (expdif == MAXEXPD) {
 965         if (MANTD(temp) == 0x8000000000000000ULL) {
 966             env->fpus |= 0x500; /* Infinity */
 967         } else {
 968             env->fpus |= 0x100; /* NaN */
 969         }
 970     } else if (expdif == 0) {
 971         if (MANTD(temp) == 0) {
 972             env->fpus |=  0x4000; /* Zero */
 973         } else {
 974             env->fpus |= 0x4400; /* Denormal */
 975         }
 976     } else {
 977         env->fpus |= 0x400;
 978     }
 979 }
 980
 981 void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
 982 {
 983     int fpus, fptag, exp, i;
 984     uint64_t mant;
 985     CPU_LDoubleU tmp;
 986
 987     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 988     fptag = 0;
 989     for (i = 7; i >= 0; i--) {
 990         fptag <<= 2;
 991         if (env->fptags[i]) {
 992             fptag |= 3;
 993         } else {
 994             tmp.d = env->fpregs[i].d;
 995             exp = EXPD(tmp);
 996             mant = MANTD(tmp);
 997             if (exp == 0 && mant == 0) {
 998                 /* zero */
 999                 fptag |= 1;
1000             } else if (exp == 0 || exp == MAXEXPD
1001                        || (mant & (1LL << 63)) == 0) {
1002                 /* NaNs, infinity, denormal */
1003                 fptag |= 2;
1004             }
1005         }
1006     }
1007     if (data32) {
1008         /* 32 bit */
1009         cpu_stl_data(env, ptr, env->fpuc);
1010         cpu_stl_data(env, ptr + 4, fpus);
1011         cpu_stl_data(env, ptr + 8, fptag);
1012         cpu_stl_data(env, ptr + 12, 0); /* fpip */
1013         cpu_stl_data(env, ptr + 16, 0); /* fpcs */
1014         cpu_stl_data(env, ptr + 20, 0); /* fpoo */
1015         cpu_stl_data(env, ptr + 24, 0); /* fpos */
1016     } else {
1017         /* 16 bit */
1018         cpu_stw_data(env, ptr, env->fpuc);
1019         cpu_stw_data(env, ptr + 2, fpus);
1020         cpu_stw_data(env, ptr + 4, fptag);
1021         cpu_stw_data(env, ptr + 6, 0);
1022         cpu_stw_data(env, ptr + 8, 0);
1023         cpu_stw_data(env, ptr + 10, 0);
1024         cpu_stw_data(env, ptr + 12, 0);
1025     }
1026 }
1027
1028 void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32)
1029 {
1030     int i, fpus, fptag;
1031
1032     if (data32) {
1033         cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1034         fpus = cpu_lduw_data(env, ptr + 4);
1035         fptag = cpu_lduw_data(env, ptr + 8);
1036     } else {
1037         cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1038         fpus = cpu_lduw_data(env, ptr + 2);
1039         fptag = cpu_lduw_data(env, ptr + 4);
1040     }
1041     env->fpstt = (fpus >> 11) & 7;
1042     env->fpus = fpus & ~0x3800;
1043     for (i = 0; i < 8; i++) {
1044         env->fptags[i] = ((fptag & 3) == 3);
1045         fptag >>= 2;
1046     }
1047 }
1048
1049 void helper_fsave(CPUX86State *env, target_ulong ptr, int data32)
1050 {
1051     floatx80 tmp;
1052     int i;
1053
1054     helper_fstenv(env, ptr, data32);
1055
1056     ptr += (14 << data32);
1057     for (i = 0; i < 8; i++) {
1058         tmp = ST(i);
1059         helper_fstt(env, tmp, ptr);
1060         ptr += 10;
1061     }
1062
1063     /* fninit */
1064     env->fpus = 0;
1065     env->fpstt = 0;
1066     cpu_set_fpuc(env, 0x37f);
1067     env->fptags[0] = 1;
1068     env->fptags[1] = 1;
1069     env->fptags[2] = 1;
1070     env->fptags[3] = 1;
1071     env->fptags[4] = 1;
1072     env->fptags[5] = 1;
1073     env->fptags[6] = 1;
1074     env->fptags[7] = 1;
1075 }
1076
1077 void helper_frstor(CPUX86State *env, target_ulong ptr, int data32)
1078 {
1079     floatx80 tmp;
1080     int i;
1081
1082     helper_fldenv(env, ptr, data32);
1083     ptr += (14 << data32);
1084
1085     for (i = 0; i < 8; i++) {
1086         tmp = helper_fldt(env, ptr);
1087         ST(i) = tmp;
1088         ptr += 10;
1089     }
1090 }
1091
1092 #if defined(CONFIG_USER_ONLY)
1093 void cpu_x86_fsave(CPUX86State *env, target_ulong ptr, int data32)
1094 {
1095     helper_fsave(env, ptr, data32);
1096 }
1097
1098 void cpu_x86_frstor(CPUX86State *env, target_ulong ptr, int data32)
1099 {
1100     helper_frstor(env, ptr, data32);
1101 }
1102 #endif
1103
1104 void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)
1105 {
1106     int fpus, fptag, i, nb_xmm_regs;
1107     floatx80 tmp;
1108     target_ulong addr;
1109
1110     /* The operand must be 16 byte aligned */
1111     if (ptr & 0xf) {
1112         raise_exception(env, EXCP0D_GPF);
1113     }
1114
1115     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1116     fptag = 0;
1117     for (i = 0; i < 8; i++) {
1118         fptag |= (env->fptags[i] << i);
1119     }
1120     cpu_stw_data(env, ptr, env->fpuc);
1121     cpu_stw_data(env, ptr + 2, fpus);
1122     cpu_stw_data(env, ptr + 4, fptag ^ 0xff);
1123 #ifdef TARGET_X86_64
1124     if (data64) {
1125         cpu_stq_data(env, ptr + 0x08, 0); /* rip */
1126         cpu_stq_data(env, ptr + 0x10, 0); /* rdp */
1127     } else
1128 #endif
1129     {
1130         cpu_stl_data(env, ptr + 0x08, 0); /* eip */
1131         cpu_stl_data(env, ptr + 0x0c, 0); /* sel  */
1132         cpu_stl_data(env, ptr + 0x10, 0); /* dp */
1133         cpu_stl_data(env, ptr + 0x14, 0); /* sel  */
1134     }
1135
1136     addr = ptr + 0x20;
1137     for (i = 0; i < 8; i++) {
1138         tmp = ST(i);
1139         helper_fstt(env, tmp, addr);
1140         addr += 16;
1141     }
1142
1143     if (env->cr[4] & CR4_OSFXSR_MASK) {
1144         /* XXX: finish it */
1145         cpu_stl_data(env, ptr + 0x18, env->mxcsr); /* mxcsr */
1146         cpu_stl_data(env, ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
1147         if (env->hflags & HF_CS64_MASK) {
1148             nb_xmm_regs = 16;
1149         } else {
1150             nb_xmm_regs = 8;
1151         }
1152         addr = ptr + 0xa0;
1153         /* Fast FXSAVE leaves out the XMM registers */
1154         if (!(env->efer & MSR_EFER_FFXSR)
1155             || (env->hflags & HF_CPL_MASK)
1156             || !(env->hflags & HF_LMA_MASK)) {
1157             for (i = 0; i < nb_xmm_regs; i++) {
1158                 cpu_stq_data(env, addr, env->xmm_regs[i].XMM_Q(0));
1159                 cpu_stq_data(env, addr + 8, env->xmm_regs[i].XMM_Q(1));
1160                 addr += 16;
1161             }
1162         }
1163     }
1164 }
1165
1166 void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)
1167 {
1168     int i, fpus, fptag, nb_xmm_regs;
1169     floatx80 tmp;
1170     target_ulong addr;
1171
1172     /* The operand must be 16 byte aligned */
1173     if (ptr & 0xf) {
1174         raise_exception(env, EXCP0D_GPF);
1175     }
1176
1177     cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1178     fpus = cpu_lduw_data(env, ptr + 2);
1179     fptag = cpu_lduw_data(env, ptr + 4);
1180     env->fpstt = (fpus >> 11) & 7;
1181     env->fpus = fpus & ~0x3800;
1182     fptag ^= 0xff;
1183     for (i = 0; i < 8; i++) {
1184         env->fptags[i] = ((fptag >> i) & 1);
1185     }
1186
1187     addr = ptr + 0x20;
1188     for (i = 0; i < 8; i++) {
1189         tmp = helper_fldt(env, addr);
1190         ST(i) = tmp;
1191         addr += 16;
1192     }
1193
1194     if (env->cr[4] & CR4_OSFXSR_MASK) {
1195         /* XXX: finish it */
1196         cpu_set_mxcsr(env, cpu_ldl_data(env, ptr + 0x18));
1197         /* cpu_ldl_data(env, ptr + 0x1c); */
1198         if (env->hflags & HF_CS64_MASK) {
1199             nb_xmm_regs = 16;
1200         } else {
1201             nb_xmm_regs = 8;
1202         }
1203         addr = ptr + 0xa0;
1204         /* Fast FXRESTORE leaves out the XMM registers */
1205         if (!(env->efer & MSR_EFER_FFXSR)
1206             || (env->hflags & HF_CPL_MASK)
1207             || !(env->hflags & HF_LMA_MASK)) {
1208             for (i = 0; i < nb_xmm_regs; i++) {
1209                 env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data(env, addr);
1210                 env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data(env, addr + 8);
1211                 addr += 16;
1212             }
1213         }
1214     }
1215 }
1216
1217 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f)
1218 {
1219     CPU_LDoubleU temp;
1220
1221     temp.d = f;
1222     *pmant = temp.l.lower;
1223     *pexp = temp.l.upper;
1224 }
1225
1226 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper)
1227 {
1228     CPU_LDoubleU temp;
1229
1230     temp.l.upper = upper;
1231     temp.l.lower = mant;
1232     return temp.d;
1233 }
1234
1235 /* MMX/SSE */
1236 /* XXX: optimize by storing fptt and fptags in the static cpu state */
1237
1238 #define SSE_DAZ             0x0040
1239 #define SSE_RC_MASK         0x6000
1240 #define SSE_RC_NEAR         0x0000
1241 #define SSE_RC_DOWN         0x2000
1242 #define SSE_RC_UP           0x4000
1243 #define SSE_RC_CHOP         0x6000
1244 #define SSE_FZ              0x8000
1245
1246 void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1247 {
1248     int rnd_type;
1249
1250     env->mxcsr = mxcsr;
1251
1252     /* set rounding mode */
1253     switch (mxcsr & SSE_RC_MASK) {
1254     default:
1255     case SSE_RC_NEAR:
1256         rnd_type = float_round_nearest_even;
1257         break;
1258     case SSE_RC_DOWN:
1259         rnd_type = float_round_down;
1260         break;
1261     case SSE_RC_UP:
1262         rnd_type = float_round_up;
1263         break;
1264     case SSE_RC_CHOP:
1265         rnd_type = float_round_to_zero;
1266         break;
1267     }
1268     set_float_rounding_mode(rnd_type, &env->sse_status);
1269
1270     /* set denormals are zero */
1271     set_flush_inputs_to_zero((mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status);
1272
1273     /* set flush to zero */
1274     set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status);
1275 }
1276
1277 void cpu_set_fpuc(CPUX86State *env, uint16_t val)
1278 {
1279     env->fpuc = val;
1280     update_fp_status(env);
1281 }
1282
1283 void helper_ldmxcsr(CPUX86State *env, uint32_t val)
1284 {
1285     cpu_set_mxcsr(env, val);
1286 }
1287
1288 void helper_enter_mmx(CPUX86State *env)
1289 {
1290     env->fpstt = 0;
1291     *(uint32_t *)(env->fptags) = 0;
1292     *(uint32_t *)(env->fptags + 4) = 0;
1293 }
1294
1295 void helper_emms(CPUX86State *env)
1296 {
1297     /* set to empty state */
1298     *(uint32_t *)(env->fptags) = 0x01010101;
1299     *(uint32_t *)(env->fptags + 4) = 0x01010101;
1300 }
1301
1302 /* XXX: suppress */
1303 void helper_movq(CPUX86State *env, void *d, void *s)
1304 {
1305     *(uint64_t *)d = *(uint64_t *)s;
1306 }
1307
1308 #define SHIFT 0
1309 #include "ops_sse.h"
1310
1311 #define SHIFT 1
1312 #include "ops_sse.h"