4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
22 #include "internals.h"
23 #include "qemu-common.h"
24 #include "hw/qdev-properties.h"
25 #include "qapi/qmp/qerror.h"
26 #if !defined(CONFIG_USER_ONLY)
27 #include "hw/loader.h"
29 #include "hw/arm/arm.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/kvm.h"
34 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
36 ARMCPU
*cpu
= ARM_CPU(cs
);
38 cpu
->env
.regs
[15] = value
;
41 static bool arm_cpu_has_work(CPUState
*cs
)
43 ARMCPU
*cpu
= ARM_CPU(cs
);
45 return !cpu
->powered_off
46 && cs
->interrupt_request
&
47 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
48 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
49 | CPU_INTERRUPT_EXITTB
);
52 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
54 /* Reset a single ARMCPRegInfo register */
55 ARMCPRegInfo
*ri
= value
;
58 if (ri
->type
& ARM_CP_SPECIAL
) {
63 ri
->resetfn(&cpu
->env
, ri
);
67 /* A zero offset is never possible as it would be regs[0]
68 * so we use it to indicate that reset is being handled elsewhere.
69 * This is basically only used for fields in non-core coprocessors
70 * (like the pxa2xx ones).
72 if (!ri
->fieldoffset
) {
76 if (cpreg_field_is_64bit(ri
)) {
77 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
79 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
83 /* CPUClass::reset() */
84 static void arm_cpu_reset(CPUState
*s
)
86 ARMCPU
*cpu
= ARM_CPU(s
);
87 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
88 CPUARMState
*env
= &cpu
->env
;
92 memset(env
, 0, offsetof(CPUARMState
, features
));
93 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
94 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
95 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
96 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
97 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
99 cpu
->powered_off
= cpu
->start_powered_off
;
100 s
->halted
= cpu
->start_powered_off
;
102 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
103 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
106 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
107 /* 64 bit CPUs always start in 64 bit mode */
109 #if defined(CONFIG_USER_ONLY)
110 env
->pstate
= PSTATE_MODE_EL0t
;
111 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
112 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
113 /* and to the FP/Neon instructions */
114 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
116 /* Reset into the highest available EL */
117 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
118 env
->pstate
= PSTATE_MODE_EL3h
;
119 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
120 env
->pstate
= PSTATE_MODE_EL2h
;
122 env
->pstate
= PSTATE_MODE_EL1h
;
124 env
->pc
= cpu
->rvbar
;
127 #if defined(CONFIG_USER_ONLY)
128 /* Userspace expects access to cp10 and cp11 for FP/Neon */
129 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
133 #if defined(CONFIG_USER_ONLY)
134 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
135 /* For user mode we must enable access to coprocessors */
136 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
137 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
138 env
->cp15
.c15_cpar
= 3;
139 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
140 env
->cp15
.c15_cpar
= 1;
143 /* SVC mode with interrupts disabled. */
144 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
145 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
146 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
147 * clear at reset. Initial SP and PC are loaded from ROM.
150 uint32_t initial_msp
; /* Loaded from 0x0 */
151 uint32_t initial_pc
; /* Loaded from 0x4 */
154 env
->daif
&= ~PSTATE_I
;
157 /* Address zero is covered by ROM which hasn't yet been
158 * copied into physical memory.
160 initial_msp
= ldl_p(rom
);
161 initial_pc
= ldl_p(rom
+ 4);
163 /* Address zero not covered by a ROM blob, or the ROM blob
164 * is in non-modifiable memory and this is a second reset after
165 * it got copied into memory. In the latter case, rom_ptr
166 * will return a NULL pointer and we should use ldl_phys instead.
168 initial_msp
= ldl_phys(s
->as
, 0);
169 initial_pc
= ldl_phys(s
->as
, 4);
172 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
173 env
->regs
[15] = initial_pc
& ~1;
174 env
->thumb
= initial_pc
& 1;
177 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
178 * executing as AArch32 then check if highvecs are enabled and
179 * adjust the PC accordingly.
181 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
182 env
->regs
[15] = 0xFFFF0000;
185 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
187 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
188 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
189 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
190 set_float_detect_tininess(float_tininess_before_rounding
,
191 &env
->vfp
.fp_status
);
192 set_float_detect_tininess(float_tininess_before_rounding
,
193 &env
->vfp
.standard_fp_status
);
196 #ifndef CONFIG_USER_ONLY
198 kvm_arm_reset_vcpu(cpu
);
202 hw_breakpoint_update_all(cpu
);
203 hw_watchpoint_update_all(cpu
);
206 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
208 CPUClass
*cc
= CPU_GET_CLASS(cs
);
209 CPUARMState
*env
= cs
->env_ptr
;
210 uint32_t cur_el
= arm_current_el(env
);
211 bool secure
= arm_is_secure(env
);
216 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
218 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
219 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
220 cs
->exception_index
= excp_idx
;
221 env
->exception
.target_el
= target_el
;
222 cc
->do_interrupt(cs
);
226 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
228 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
229 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
230 cs
->exception_index
= excp_idx
;
231 env
->exception
.target_el
= target_el
;
232 cc
->do_interrupt(cs
);
236 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
237 excp_idx
= EXCP_VIRQ
;
239 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
240 cs
->exception_index
= excp_idx
;
241 env
->exception
.target_el
= target_el
;
242 cc
->do_interrupt(cs
);
246 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
247 excp_idx
= EXCP_VFIQ
;
249 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
250 cs
->exception_index
= excp_idx
;
251 env
->exception
.target_el
= target_el
;
252 cc
->do_interrupt(cs
);
260 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
261 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
263 CPUClass
*cc
= CPU_GET_CLASS(cs
);
264 ARMCPU
*cpu
= ARM_CPU(cs
);
265 CPUARMState
*env
= &cpu
->env
;
269 if (interrupt_request
& CPU_INTERRUPT_FIQ
270 && !(env
->daif
& PSTATE_F
)) {
271 cs
->exception_index
= EXCP_FIQ
;
272 cc
->do_interrupt(cs
);
275 /* ARMv7-M interrupt return works by loading a magic value
276 * into the PC. On real hardware the load causes the
277 * return to occur. The qemu implementation performs the
278 * jump normally, then does the exception return when the
279 * CPU tries to execute code at the magic address.
280 * This will cause the magic PC value to be pushed to
281 * the stack if an interrupt occurred at the wrong time.
282 * We avoid this by disabling interrupts when
283 * pc contains a magic address.
285 if (interrupt_request
& CPU_INTERRUPT_HARD
286 && !(env
->daif
& PSTATE_I
)
287 && (env
->regs
[15] < 0xfffffff0)) {
288 cs
->exception_index
= EXCP_IRQ
;
289 cc
->do_interrupt(cs
);
296 #ifndef CONFIG_USER_ONLY
297 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
299 ARMCPU
*cpu
= opaque
;
300 CPUARMState
*env
= &cpu
->env
;
301 CPUState
*cs
= CPU(cpu
);
302 static const int mask
[] = {
303 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
304 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
305 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
306 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
312 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
313 hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
320 cpu_interrupt(cs
, mask
[irq
]);
322 cpu_reset_interrupt(cs
, mask
[irq
]);
326 hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq
);
330 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
333 ARMCPU
*cpu
= opaque
;
334 CPUState
*cs
= CPU(cpu
);
335 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
339 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
342 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
345 hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq
);
347 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
348 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
352 static bool arm_cpu_is_big_endian(CPUState
*cs
)
354 ARMCPU
*cpu
= ARM_CPU(cs
);
355 CPUARMState
*env
= &cpu
->env
;
358 cpu_synchronize_state(cs
);
360 /* In 32bit guest endianness is determined by looking at CPSR's E bit */
362 return (env
->uncached_cpsr
& CPSR_E
) ? 1 : 0;
365 cur_el
= arm_current_el(env
);
368 return (env
->cp15
.sctlr_el
[1] & SCTLR_E0E
) != 0;
371 return (env
->cp15
.sctlr_el
[cur_el
] & SCTLR_EE
) != 0;
376 static inline void set_feature(CPUARMState
*env
, int feature
)
378 env
->features
|= 1ULL << feature
;
381 static inline void unset_feature(CPUARMState
*env
, int feature
)
383 env
->features
&= ~(1ULL << feature
);
386 #define ARM_CPUS_PER_CLUSTER 8
388 static void arm_cpu_initfn(Object
*obj
)
390 CPUState
*cs
= CPU(obj
);
391 ARMCPU
*cpu
= ARM_CPU(obj
);
395 cs
->env_ptr
= &cpu
->env
;
396 cpu_exec_init(&cpu
->env
);
397 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
400 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
401 * We don't support setting cluster ID ([16..23]) (known as Aff2
402 * in later ARM ARM versions), or any of the higher affinity level fields,
403 * so these bits always RAZ.
405 Aff1
= cs
->cpu_index
/ ARM_CPUS_PER_CLUSTER
;
406 Aff0
= cs
->cpu_index
% ARM_CPUS_PER_CLUSTER
;
407 cpu
->mp_affinity
= (Aff1
<< 8) | Aff0
;
409 #ifndef CONFIG_USER_ONLY
410 /* Our inbound IRQ and FIQ lines */
412 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
413 * the same interface as non-KVM CPUs.
415 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
417 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
420 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
421 arm_gt_ptimer_cb
, cpu
);
422 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
423 arm_gt_vtimer_cb
, cpu
);
424 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
425 ARRAY_SIZE(cpu
->gt_timer_outputs
));
428 /* DTB consumers generally don't in fact care what the 'compatible'
429 * string is, so always provide some string and trust that a hypothetical
430 * picky DTB consumer will also provide a helpful error message.
432 cpu
->dtb_compatible
= "qemu,unknown";
433 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
434 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
437 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
440 arm_translate_init();
445 static Property arm_cpu_reset_cbar_property
=
446 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
448 static Property arm_cpu_reset_hivecs_property
=
449 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
451 static Property arm_cpu_rvbar_property
=
452 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
454 static Property arm_cpu_has_el3_property
=
455 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
457 static Property arm_cpu_has_mpu_property
=
458 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
460 static void arm_cpu_post_init(Object
*obj
)
462 ARMCPU
*cpu
= ARM_CPU(obj
);
464 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
465 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
466 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
470 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
471 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
475 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
476 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
480 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
481 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
482 * prevent "has_el3" from existing on CPUs which cannot support EL3.
484 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
488 if (arm_feature(&cpu
->env
, ARM_FEATURE_MPU
)) {
489 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
495 static void arm_cpu_finalizefn(Object
*obj
)
497 ARMCPU
*cpu
= ARM_CPU(obj
);
498 g_hash_table_destroy(cpu
->cp_regs
);
501 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
503 CPUState
*cs
= CPU(dev
);
504 ARMCPU
*cpu
= ARM_CPU(dev
);
505 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
506 CPUARMState
*env
= &cpu
->env
;
508 /* Some features automatically imply others: */
509 if (arm_feature(env
, ARM_FEATURE_V8
)) {
510 set_feature(env
, ARM_FEATURE_V7
);
511 set_feature(env
, ARM_FEATURE_ARM_DIV
);
512 set_feature(env
, ARM_FEATURE_LPAE
);
514 if (arm_feature(env
, ARM_FEATURE_V7
)) {
515 set_feature(env
, ARM_FEATURE_VAPA
);
516 set_feature(env
, ARM_FEATURE_THUMB2
);
517 set_feature(env
, ARM_FEATURE_MPIDR
);
518 if (!arm_feature(env
, ARM_FEATURE_M
)) {
519 set_feature(env
, ARM_FEATURE_V6K
);
521 set_feature(env
, ARM_FEATURE_V6
);
524 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
525 set_feature(env
, ARM_FEATURE_V6
);
526 set_feature(env
, ARM_FEATURE_MVFR
);
528 if (arm_feature(env
, ARM_FEATURE_V6
)) {
529 set_feature(env
, ARM_FEATURE_V5
);
530 if (!arm_feature(env
, ARM_FEATURE_M
)) {
531 set_feature(env
, ARM_FEATURE_AUXCR
);
534 if (arm_feature(env
, ARM_FEATURE_V5
)) {
535 set_feature(env
, ARM_FEATURE_V4T
);
537 if (arm_feature(env
, ARM_FEATURE_M
)) {
538 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
540 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
541 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
543 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
544 set_feature(env
, ARM_FEATURE_VFP3
);
545 set_feature(env
, ARM_FEATURE_VFP_FP16
);
547 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
548 set_feature(env
, ARM_FEATURE_VFP
);
550 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
551 set_feature(env
, ARM_FEATURE_V7MP
);
552 set_feature(env
, ARM_FEATURE_PXN
);
554 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
555 set_feature(env
, ARM_FEATURE_CBAR
);
557 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
558 !arm_feature(env
, ARM_FEATURE_M
)) {
559 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
562 if (cpu
->reset_hivecs
) {
563 cpu
->reset_sctlr
|= (1 << 13);
567 /* If the has_el3 CPU property is disabled then we need to disable the
570 unset_feature(env
, ARM_FEATURE_EL3
);
572 /* Disable the security extension feature bits in the processor feature
573 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
575 cpu
->id_pfr1
&= ~0xf0;
576 cpu
->id_aa64pfr0
&= ~0xf000;
580 unset_feature(env
, ARM_FEATURE_MPU
);
583 register_cp_regs_for_features(cpu
);
584 arm_cpu_register_gdb_regs_for_features(cpu
);
586 init_cpreg_list(cpu
);
591 acc
->parent_realize(dev
, errp
);
594 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
604 cpuname
= g_strsplit(cpu_model
, ",", 1);
605 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpuname
[0]);
606 oc
= object_class_by_name(typename
);
609 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
610 object_class_is_abstract(oc
)) {
616 /* CPU models. These are not needed for the AArch64 linux-user build. */
617 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
619 static void arm926_initfn(Object
*obj
)
621 ARMCPU
*cpu
= ARM_CPU(obj
);
623 cpu
->dtb_compatible
= "arm,arm926";
624 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
625 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
626 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
627 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
628 cpu
->midr
= 0x41069265;
629 cpu
->reset_fpsid
= 0x41011090;
630 cpu
->ctr
= 0x1dd20d2;
631 cpu
->reset_sctlr
= 0x00090078;
634 static void arm946_initfn(Object
*obj
)
636 ARMCPU
*cpu
= ARM_CPU(obj
);
638 cpu
->dtb_compatible
= "arm,arm946";
639 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
640 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
641 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
642 cpu
->midr
= 0x41059461;
643 cpu
->ctr
= 0x0f004006;
644 cpu
->reset_sctlr
= 0x00000078;
647 static void arm1026_initfn(Object
*obj
)
649 ARMCPU
*cpu
= ARM_CPU(obj
);
651 cpu
->dtb_compatible
= "arm,arm1026";
652 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
653 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
654 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
655 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
656 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
657 cpu
->midr
= 0x4106a262;
658 cpu
->reset_fpsid
= 0x410110a0;
659 cpu
->ctr
= 0x1dd20d2;
660 cpu
->reset_sctlr
= 0x00090078;
661 cpu
->reset_auxcr
= 1;
663 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
664 ARMCPRegInfo ifar
= {
665 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
667 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
670 define_one_arm_cp_reg(cpu
, &ifar
);
674 static void arm1136_r2_initfn(Object
*obj
)
676 ARMCPU
*cpu
= ARM_CPU(obj
);
677 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
678 * older core than plain "arm1136". In particular this does not
679 * have the v6K features.
680 * These ID register values are correct for 1136 but may be wrong
681 * for 1136_r2 (in particular r0p2 does not actually implement most
682 * of the ID registers).
685 cpu
->dtb_compatible
= "arm,arm1136";
686 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
687 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
688 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
689 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
690 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
691 cpu
->midr
= 0x4107b362;
692 cpu
->reset_fpsid
= 0x410120b4;
693 cpu
->mvfr0
= 0x11111111;
694 cpu
->mvfr1
= 0x00000000;
695 cpu
->ctr
= 0x1dd20d2;
696 cpu
->reset_sctlr
= 0x00050078;
697 cpu
->id_pfr0
= 0x111;
701 cpu
->id_mmfr0
= 0x01130003;
702 cpu
->id_mmfr1
= 0x10030302;
703 cpu
->id_mmfr2
= 0x01222110;
704 cpu
->id_isar0
= 0x00140011;
705 cpu
->id_isar1
= 0x12002111;
706 cpu
->id_isar2
= 0x11231111;
707 cpu
->id_isar3
= 0x01102131;
708 cpu
->id_isar4
= 0x141;
709 cpu
->reset_auxcr
= 7;
712 static void arm1136_initfn(Object
*obj
)
714 ARMCPU
*cpu
= ARM_CPU(obj
);
716 cpu
->dtb_compatible
= "arm,arm1136";
717 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
718 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
719 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
720 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
721 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
722 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
723 cpu
->midr
= 0x4117b363;
724 cpu
->reset_fpsid
= 0x410120b4;
725 cpu
->mvfr0
= 0x11111111;
726 cpu
->mvfr1
= 0x00000000;
727 cpu
->ctr
= 0x1dd20d2;
728 cpu
->reset_sctlr
= 0x00050078;
729 cpu
->id_pfr0
= 0x111;
733 cpu
->id_mmfr0
= 0x01130003;
734 cpu
->id_mmfr1
= 0x10030302;
735 cpu
->id_mmfr2
= 0x01222110;
736 cpu
->id_isar0
= 0x00140011;
737 cpu
->id_isar1
= 0x12002111;
738 cpu
->id_isar2
= 0x11231111;
739 cpu
->id_isar3
= 0x01102131;
740 cpu
->id_isar4
= 0x141;
741 cpu
->reset_auxcr
= 7;
744 static void arm1176_initfn(Object
*obj
)
746 ARMCPU
*cpu
= ARM_CPU(obj
);
748 cpu
->dtb_compatible
= "arm,arm1176";
749 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
750 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
751 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
752 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
753 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
754 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
755 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
756 cpu
->midr
= 0x410fb767;
757 cpu
->reset_fpsid
= 0x410120b5;
758 cpu
->mvfr0
= 0x11111111;
759 cpu
->mvfr1
= 0x00000000;
760 cpu
->ctr
= 0x1dd20d2;
761 cpu
->reset_sctlr
= 0x00050078;
762 cpu
->id_pfr0
= 0x111;
766 cpu
->id_mmfr0
= 0x01130003;
767 cpu
->id_mmfr1
= 0x10030302;
768 cpu
->id_mmfr2
= 0x01222100;
769 cpu
->id_isar0
= 0x0140011;
770 cpu
->id_isar1
= 0x12002111;
771 cpu
->id_isar2
= 0x11231121;
772 cpu
->id_isar3
= 0x01102131;
773 cpu
->id_isar4
= 0x01141;
774 cpu
->reset_auxcr
= 7;
777 static void arm11mpcore_initfn(Object
*obj
)
779 ARMCPU
*cpu
= ARM_CPU(obj
);
781 cpu
->dtb_compatible
= "arm,arm11mpcore";
782 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
783 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
784 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
785 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
786 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
787 cpu
->midr
= 0x410fb022;
788 cpu
->reset_fpsid
= 0x410120b4;
789 cpu
->mvfr0
= 0x11111111;
790 cpu
->mvfr1
= 0x00000000;
791 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
792 cpu
->id_pfr0
= 0x111;
796 cpu
->id_mmfr0
= 0x01100103;
797 cpu
->id_mmfr1
= 0x10020302;
798 cpu
->id_mmfr2
= 0x01222000;
799 cpu
->id_isar0
= 0x00100011;
800 cpu
->id_isar1
= 0x12002111;
801 cpu
->id_isar2
= 0x11221011;
802 cpu
->id_isar3
= 0x01102131;
803 cpu
->id_isar4
= 0x141;
804 cpu
->reset_auxcr
= 1;
807 static void cortex_m3_initfn(Object
*obj
)
809 ARMCPU
*cpu
= ARM_CPU(obj
);
810 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
811 set_feature(&cpu
->env
, ARM_FEATURE_M
);
812 cpu
->midr
= 0x410fc231;
815 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
817 CPUClass
*cc
= CPU_CLASS(oc
);
819 #ifndef CONFIG_USER_ONLY
820 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
823 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
826 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
827 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
828 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
829 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
830 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
834 static void cortex_a8_initfn(Object
*obj
)
836 ARMCPU
*cpu
= ARM_CPU(obj
);
838 cpu
->dtb_compatible
= "arm,cortex-a8";
839 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
840 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
841 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
842 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
843 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
844 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
845 cpu
->midr
= 0x410fc080;
846 cpu
->reset_fpsid
= 0x410330c0;
847 cpu
->mvfr0
= 0x11110222;
848 cpu
->mvfr1
= 0x00011100;
849 cpu
->ctr
= 0x82048004;
850 cpu
->reset_sctlr
= 0x00c50078;
851 cpu
->id_pfr0
= 0x1031;
853 cpu
->id_dfr0
= 0x400;
855 cpu
->id_mmfr0
= 0x31100003;
856 cpu
->id_mmfr1
= 0x20000000;
857 cpu
->id_mmfr2
= 0x01202000;
858 cpu
->id_mmfr3
= 0x11;
859 cpu
->id_isar0
= 0x00101111;
860 cpu
->id_isar1
= 0x12112111;
861 cpu
->id_isar2
= 0x21232031;
862 cpu
->id_isar3
= 0x11112131;
863 cpu
->id_isar4
= 0x00111142;
864 cpu
->dbgdidr
= 0x15141000;
865 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
866 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
867 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
868 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
869 cpu
->reset_auxcr
= 2;
870 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
873 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
874 /* power_control should be set to maximum latency. Again,
875 * default to 0 and set by private hook
877 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
878 .access
= PL1_RW
, .resetvalue
= 0,
879 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
880 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
881 .access
= PL1_RW
, .resetvalue
= 0,
882 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
883 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
884 .access
= PL1_RW
, .resetvalue
= 0,
885 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
886 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
887 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
888 /* TLB lockdown control */
889 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
890 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
891 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
892 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
893 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
894 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
895 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
896 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
897 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
898 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
902 static void cortex_a9_initfn(Object
*obj
)
904 ARMCPU
*cpu
= ARM_CPU(obj
);
906 cpu
->dtb_compatible
= "arm,cortex-a9";
907 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
908 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
909 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
910 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
911 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
912 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
913 /* Note that A9 supports the MP extensions even for
914 * A9UP and single-core A9MP (which are both different
915 * and valid configurations; we don't model A9UP).
917 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
918 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
919 cpu
->midr
= 0x410fc090;
920 cpu
->reset_fpsid
= 0x41033090;
921 cpu
->mvfr0
= 0x11110222;
922 cpu
->mvfr1
= 0x01111111;
923 cpu
->ctr
= 0x80038003;
924 cpu
->reset_sctlr
= 0x00c50078;
925 cpu
->id_pfr0
= 0x1031;
927 cpu
->id_dfr0
= 0x000;
929 cpu
->id_mmfr0
= 0x00100103;
930 cpu
->id_mmfr1
= 0x20000000;
931 cpu
->id_mmfr2
= 0x01230000;
932 cpu
->id_mmfr3
= 0x00002111;
933 cpu
->id_isar0
= 0x00101111;
934 cpu
->id_isar1
= 0x13112111;
935 cpu
->id_isar2
= 0x21232041;
936 cpu
->id_isar3
= 0x11112131;
937 cpu
->id_isar4
= 0x00111142;
938 cpu
->dbgdidr
= 0x35141000;
939 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
940 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
941 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
942 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
945 #ifndef CONFIG_USER_ONLY
946 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
948 /* Linux wants the number of processors from here.
949 * Might as well set the interrupt-controller bit too.
951 return ((smp_cpus
- 1) << 24) | (1 << 23);
955 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
956 #ifndef CONFIG_USER_ONLY
957 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
958 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
959 .writefn
= arm_cp_write_ignore
, },
961 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
962 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
966 static void cortex_a15_initfn(Object
*obj
)
968 ARMCPU
*cpu
= ARM_CPU(obj
);
970 cpu
->dtb_compatible
= "arm,cortex-a15";
971 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
972 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
973 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
974 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
975 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
976 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
977 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
978 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
979 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
980 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
981 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
982 cpu
->midr
= 0x412fc0f1;
983 cpu
->reset_fpsid
= 0x410430f0;
984 cpu
->mvfr0
= 0x10110222;
985 cpu
->mvfr1
= 0x11111111;
986 cpu
->ctr
= 0x8444c004;
987 cpu
->reset_sctlr
= 0x00c50078;
988 cpu
->id_pfr0
= 0x00001131;
989 cpu
->id_pfr1
= 0x00011011;
990 cpu
->id_dfr0
= 0x02010555;
991 cpu
->id_afr0
= 0x00000000;
992 cpu
->id_mmfr0
= 0x10201105;
993 cpu
->id_mmfr1
= 0x20000000;
994 cpu
->id_mmfr2
= 0x01240000;
995 cpu
->id_mmfr3
= 0x02102211;
996 cpu
->id_isar0
= 0x02101110;
997 cpu
->id_isar1
= 0x13112111;
998 cpu
->id_isar2
= 0x21232041;
999 cpu
->id_isar3
= 0x11112131;
1000 cpu
->id_isar4
= 0x10011142;
1001 cpu
->dbgdidr
= 0x3515f021;
1002 cpu
->clidr
= 0x0a200023;
1003 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1004 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1005 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1006 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1009 static void ti925t_initfn(Object
*obj
)
1011 ARMCPU
*cpu
= ARM_CPU(obj
);
1012 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1013 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1014 cpu
->midr
= ARM_CPUID_TI925T
;
1015 cpu
->ctr
= 0x5109149;
1016 cpu
->reset_sctlr
= 0x00000070;
1019 static void sa1100_initfn(Object
*obj
)
1021 ARMCPU
*cpu
= ARM_CPU(obj
);
1023 cpu
->dtb_compatible
= "intel,sa1100";
1024 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1025 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1026 cpu
->midr
= 0x4401A11B;
1027 cpu
->reset_sctlr
= 0x00000070;
1030 static void sa1110_initfn(Object
*obj
)
1032 ARMCPU
*cpu
= ARM_CPU(obj
);
1033 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1034 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1035 cpu
->midr
= 0x6901B119;
1036 cpu
->reset_sctlr
= 0x00000070;
1039 static void pxa250_initfn(Object
*obj
)
1041 ARMCPU
*cpu
= ARM_CPU(obj
);
1043 cpu
->dtb_compatible
= "marvell,xscale";
1044 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1045 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1046 cpu
->midr
= 0x69052100;
1047 cpu
->ctr
= 0xd172172;
1048 cpu
->reset_sctlr
= 0x00000078;
1051 static void pxa255_initfn(Object
*obj
)
1053 ARMCPU
*cpu
= ARM_CPU(obj
);
1055 cpu
->dtb_compatible
= "marvell,xscale";
1056 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1057 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1058 cpu
->midr
= 0x69052d00;
1059 cpu
->ctr
= 0xd172172;
1060 cpu
->reset_sctlr
= 0x00000078;
1063 static void pxa260_initfn(Object
*obj
)
1065 ARMCPU
*cpu
= ARM_CPU(obj
);
1067 cpu
->dtb_compatible
= "marvell,xscale";
1068 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1069 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1070 cpu
->midr
= 0x69052903;
1071 cpu
->ctr
= 0xd172172;
1072 cpu
->reset_sctlr
= 0x00000078;
1075 static void pxa261_initfn(Object
*obj
)
1077 ARMCPU
*cpu
= ARM_CPU(obj
);
1079 cpu
->dtb_compatible
= "marvell,xscale";
1080 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1081 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1082 cpu
->midr
= 0x69052d05;
1083 cpu
->ctr
= 0xd172172;
1084 cpu
->reset_sctlr
= 0x00000078;
1087 static void pxa262_initfn(Object
*obj
)
1089 ARMCPU
*cpu
= ARM_CPU(obj
);
1091 cpu
->dtb_compatible
= "marvell,xscale";
1092 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1093 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1094 cpu
->midr
= 0x69052d06;
1095 cpu
->ctr
= 0xd172172;
1096 cpu
->reset_sctlr
= 0x00000078;
1099 static void pxa270a0_initfn(Object
*obj
)
1101 ARMCPU
*cpu
= ARM_CPU(obj
);
1103 cpu
->dtb_compatible
= "marvell,xscale";
1104 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1105 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1106 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1107 cpu
->midr
= 0x69054110;
1108 cpu
->ctr
= 0xd172172;
1109 cpu
->reset_sctlr
= 0x00000078;
1112 static void pxa270a1_initfn(Object
*obj
)
1114 ARMCPU
*cpu
= ARM_CPU(obj
);
1116 cpu
->dtb_compatible
= "marvell,xscale";
1117 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1118 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1119 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1120 cpu
->midr
= 0x69054111;
1121 cpu
->ctr
= 0xd172172;
1122 cpu
->reset_sctlr
= 0x00000078;
1125 static void pxa270b0_initfn(Object
*obj
)
1127 ARMCPU
*cpu
= ARM_CPU(obj
);
1129 cpu
->dtb_compatible
= "marvell,xscale";
1130 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1131 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1132 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1133 cpu
->midr
= 0x69054112;
1134 cpu
->ctr
= 0xd172172;
1135 cpu
->reset_sctlr
= 0x00000078;
1138 static void pxa270b1_initfn(Object
*obj
)
1140 ARMCPU
*cpu
= ARM_CPU(obj
);
1142 cpu
->dtb_compatible
= "marvell,xscale";
1143 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1144 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1145 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1146 cpu
->midr
= 0x69054113;
1147 cpu
->ctr
= 0xd172172;
1148 cpu
->reset_sctlr
= 0x00000078;
1151 static void pxa270c0_initfn(Object
*obj
)
1153 ARMCPU
*cpu
= ARM_CPU(obj
);
1155 cpu
->dtb_compatible
= "marvell,xscale";
1156 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1157 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1158 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1159 cpu
->midr
= 0x69054114;
1160 cpu
->ctr
= 0xd172172;
1161 cpu
->reset_sctlr
= 0x00000078;
1164 static void pxa270c5_initfn(Object
*obj
)
1166 ARMCPU
*cpu
= ARM_CPU(obj
);
1168 cpu
->dtb_compatible
= "marvell,xscale";
1169 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1170 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1171 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1172 cpu
->midr
= 0x69054117;
1173 cpu
->ctr
= 0xd172172;
1174 cpu
->reset_sctlr
= 0x00000078;
1177 #ifdef CONFIG_USER_ONLY
1178 static void arm_any_initfn(Object
*obj
)
1180 ARMCPU
*cpu
= ARM_CPU(obj
);
1181 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1182 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1183 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1184 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1185 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1186 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1187 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1188 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1189 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1190 cpu
->midr
= 0xffffffff;
1194 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1196 typedef struct ARMCPUInfo
{
1198 void (*initfn
)(Object
*obj
);
1199 void (*class_init
)(ObjectClass
*oc
, void *data
);
1202 static const ARMCPUInfo arm_cpus
[] = {
1203 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1204 { .name
= "arm926", .initfn
= arm926_initfn
},
1205 { .name
= "arm946", .initfn
= arm946_initfn
},
1206 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1207 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1208 * older core than plain "arm1136". In particular this does not
1209 * have the v6K features.
1211 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1212 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1213 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1214 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1215 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1216 .class_init
= arm_v7m_class_init
},
1217 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1218 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1219 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1220 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1221 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1222 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1223 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1224 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1225 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1226 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1227 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1228 /* "pxa270" is an alias for "pxa270-a0" */
1229 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1230 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1231 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1232 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1233 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1234 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1235 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1236 #ifdef CONFIG_USER_ONLY
1237 { .name
= "any", .initfn
= arm_any_initfn
},
1243 static Property arm_cpu_properties
[] = {
1244 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1245 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1246 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1247 DEFINE_PROP_END_OF_LIST()
1250 #ifdef CONFIG_USER_ONLY
1251 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
1254 ARMCPU
*cpu
= ARM_CPU(cs
);
1255 CPUARMState
*env
= &cpu
->env
;
1257 env
->exception
.vaddress
= address
;
1259 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1261 cs
->exception_index
= EXCP_DATA_ABORT
;
1267 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1269 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1270 CPUClass
*cc
= CPU_CLASS(acc
);
1271 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1273 acc
->parent_realize
= dc
->realize
;
1274 dc
->realize
= arm_cpu_realizefn
;
1275 dc
->props
= arm_cpu_properties
;
1277 acc
->parent_reset
= cc
->reset
;
1278 cc
->reset
= arm_cpu_reset
;
1280 cc
->class_by_name
= arm_cpu_class_by_name
;
1281 cc
->has_work
= arm_cpu_has_work
;
1282 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1283 cc
->dump_state
= arm_cpu_dump_state
;
1284 cc
->set_pc
= arm_cpu_set_pc
;
1285 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1286 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1287 #ifdef CONFIG_USER_ONLY
1288 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1290 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1291 cc
->get_phys_page_debug
= arm_cpu_get_phys_page_debug
;
1292 cc
->vmsd
= &vmstate_arm_cpu
;
1293 cc
->virtio_is_big_endian
= arm_cpu_is_big_endian
;
1295 cc
->gdb_num_core_regs
= 26;
1296 cc
->gdb_core_xml_file
= "arm-core.xml";
1297 cc
->gdb_stop_before_watchpoint
= true;
1298 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1301 static void cpu_register(const ARMCPUInfo
*info
)
1303 TypeInfo type_info
= {
1304 .parent
= TYPE_ARM_CPU
,
1305 .instance_size
= sizeof(ARMCPU
),
1306 .instance_init
= info
->initfn
,
1307 .class_size
= sizeof(ARMCPUClass
),
1308 .class_init
= info
->class_init
,
1311 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1312 type_register(&type_info
);
1313 g_free((void *)type_info
.name
);
1316 static const TypeInfo arm_cpu_type_info
= {
1317 .name
= TYPE_ARM_CPU
,
1319 .instance_size
= sizeof(ARMCPU
),
1320 .instance_init
= arm_cpu_initfn
,
1321 .instance_post_init
= arm_cpu_post_init
,
1322 .instance_finalize
= arm_cpu_finalizefn
,
1324 .class_size
= sizeof(ARMCPUClass
),
1325 .class_init
= arm_cpu_class_init
,
1328 static void arm_cpu_register_types(void)
1330 const ARMCPUInfo
*info
= arm_cpus
;
1332 type_register_static(&arm_cpu_type_info
);
1334 while (info
->name
) {
1340 type_init(arm_cpu_register_types
)