4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "translate.h"
29 #include "qemu/host-utils.h"
31 #include "exec/gen-icount.h"
37 static TCGv_i64 cpu_X
[32];
38 static TCGv_i64 cpu_pc
;
39 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_addr
;
43 static TCGv_i64 cpu_exclusive_val
;
44 static TCGv_i64 cpu_exclusive_high
;
45 #ifdef CONFIG_USER_ONLY
46 static TCGv_i64 cpu_exclusive_test
;
47 static TCGv_i32 cpu_exclusive_info
;
50 static const char *regnames
[] = {
51 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
52 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
53 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
54 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
58 A64_SHIFT_TYPE_LSL
= 0,
59 A64_SHIFT_TYPE_LSR
= 1,
60 A64_SHIFT_TYPE_ASR
= 2,
61 A64_SHIFT_TYPE_ROR
= 3
64 /* Table based decoder typedefs - used when the relevant bits for decode
65 * are too awkwardly scattered across the instruction (eg SIMD).
67 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
69 typedef struct AArch64DecodeTable
{
72 AArch64DecodeFn
*disas_fn
;
75 /* Function prototype for gen_ functions for calling Neon helpers */
76 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
78 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
80 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
81 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
82 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
83 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
84 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
85 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
87 /* initialize TCG globals. */
88 void a64_translate_init(void)
92 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
93 offsetof(CPUARMState
, pc
),
95 for (i
= 0; i
< 32; i
++) {
96 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
97 offsetof(CPUARMState
, xregs
[i
]),
101 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
102 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
103 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
104 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
106 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
107 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
108 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
109 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
110 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
111 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
112 #ifdef CONFIG_USER_ONLY
113 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
114 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
115 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
116 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
120 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
121 fprintf_function cpu_fprintf
, int flags
)
123 ARMCPU
*cpu
= ARM_CPU(cs
);
124 CPUARMState
*env
= &cpu
->env
;
125 uint32_t psr
= pstate_read(env
);
128 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
129 env
->pc
, env
->xregs
[31]);
130 for (i
= 0; i
< 31; i
++) {
131 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
133 cpu_fprintf(f
, "\n");
138 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
140 psr
& PSTATE_N
? 'N' : '-',
141 psr
& PSTATE_Z
? 'Z' : '-',
142 psr
& PSTATE_C
? 'C' : '-',
143 psr
& PSTATE_V
? 'V' : '-');
144 cpu_fprintf(f
, "\n");
146 if (flags
& CPU_DUMP_FPU
) {
148 for (i
= 0; i
< numvfpregs
; i
+= 2) {
149 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
150 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
151 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
153 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
154 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
155 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
158 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
159 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
163 static int get_mem_index(DisasContext
*s
)
165 #ifdef CONFIG_USER_ONLY
172 void gen_a64_set_pc_im(uint64_t val
)
174 tcg_gen_movi_i64(cpu_pc
, val
);
177 static void gen_exception(int excp
)
179 TCGv_i32 tmp
= tcg_temp_new_i32();
180 tcg_gen_movi_i32(tmp
, excp
);
181 gen_helper_exception(cpu_env
, tmp
);
182 tcg_temp_free_i32(tmp
);
185 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
)
187 gen_a64_set_pc_im(s
->pc
- offset
);
189 s
->is_jmp
= DISAS_EXC
;
192 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
194 /* No direct tb linking with singlestep or deterministic io */
195 if (s
->singlestep_enabled
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
199 /* Only link tbs from inside the same guest page */
200 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
207 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
209 TranslationBlock
*tb
;
212 if (use_goto_tb(s
, n
, dest
)) {
214 gen_a64_set_pc_im(dest
);
215 tcg_gen_exit_tb((intptr_t)tb
+ n
);
216 s
->is_jmp
= DISAS_TB_JUMP
;
218 gen_a64_set_pc_im(dest
);
219 if (s
->singlestep_enabled
) {
220 gen_exception(EXCP_DEBUG
);
223 s
->is_jmp
= DISAS_JUMP
;
227 static void unallocated_encoding(DisasContext
*s
)
229 gen_exception_insn(s
, 4, EXCP_UDEF
);
232 #define unsupported_encoding(s, insn) \
234 qemu_log_mask(LOG_UNIMP, \
235 "%s:%d: unsupported instruction encoding 0x%08x " \
236 "at pc=%016" PRIx64 "\n", \
237 __FILE__, __LINE__, insn, s->pc - 4); \
238 unallocated_encoding(s); \
241 static void init_tmp_a64_array(DisasContext
*s
)
243 #ifdef CONFIG_DEBUG_TCG
245 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
246 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
249 s
->tmp_a64_count
= 0;
252 static void free_tmp_a64(DisasContext
*s
)
255 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
256 tcg_temp_free_i64(s
->tmp_a64
[i
]);
258 init_tmp_a64_array(s
);
261 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
263 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
264 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
267 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
269 TCGv_i64 t
= new_tmp_a64(s
);
270 tcg_gen_movi_i64(t
, 0);
275 * Register access functions
277 * These functions are used for directly accessing a register in where
278 * changes to the final register value are likely to be made. If you
279 * need to use a register for temporary calculation (e.g. index type
280 * operations) use the read_* form.
282 * B1.2.1 Register mappings
284 * In instruction register encoding 31 can refer to ZR (zero register) or
285 * the SP (stack pointer) depending on context. In QEMU's case we map SP
286 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
287 * This is the point of the _sp forms.
289 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
292 return new_tmp_a64_zero(s
);
298 /* register access for when 31 == SP */
299 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
304 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
305 * representing the register contents. This TCGv is an auto-freed
306 * temporary so it need not be explicitly freed, and may be modified.
308 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
310 TCGv_i64 v
= new_tmp_a64(s
);
313 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
315 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
318 tcg_gen_movi_i64(v
, 0);
323 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
325 TCGv_i64 v
= new_tmp_a64(s
);
327 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
329 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
334 /* Return the offset into CPUARMState of an element of specified
335 * size, 'element' places in from the least significant end of
336 * the FP/vector register Qn.
338 static inline int vec_reg_offset(int regno
, int element
, TCGMemOp size
)
340 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
341 #ifdef HOST_WORDS_BIGENDIAN
342 /* This is complicated slightly because vfp.regs[2n] is
343 * still the low half and vfp.regs[2n+1] the high half
344 * of the 128 bit vector, even on big endian systems.
345 * Calculate the offset assuming a fully bigendian 128 bits,
346 * then XOR to account for the order of the two 64 bit halves.
348 offs
+= (16 - ((element
+ 1) * (1 << size
)));
351 offs
+= element
* (1 << size
);
356 /* Return the offset into CPUARMState of a slice (from
357 * the least significant end) of FP register Qn (ie
359 * (Note that this is not the same mapping as for A32; see cpu.h)
361 static inline int fp_reg_offset(int regno
, TCGMemOp size
)
363 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
364 #ifdef HOST_WORDS_BIGENDIAN
365 offs
+= (8 - (1 << size
));
370 /* Offset of the high half of the 128 bit vector Qn */
371 static inline int fp_reg_hi_offset(int regno
)
373 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
376 /* Convenience accessors for reading and writing single and double
377 * FP registers. Writing clears the upper parts of the associated
378 * 128 bit vector register, as required by the architecture.
379 * Note that unlike the GP register accessors, the values returned
380 * by the read functions must be manually freed.
382 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
384 TCGv_i64 v
= tcg_temp_new_i64();
386 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(reg
, MO_64
));
390 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
392 TCGv_i32 v
= tcg_temp_new_i32();
394 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(reg
, MO_32
));
398 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
400 TCGv_i64 tcg_zero
= tcg_const_i64(0);
402 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(reg
, MO_64
));
403 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(reg
));
404 tcg_temp_free_i64(tcg_zero
);
407 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
409 TCGv_i64 tmp
= tcg_temp_new_i64();
411 tcg_gen_extu_i32_i64(tmp
, v
);
412 write_fp_dreg(s
, reg
, tmp
);
413 tcg_temp_free_i64(tmp
);
416 static TCGv_ptr
get_fpstatus_ptr(void)
418 TCGv_ptr statusptr
= tcg_temp_new_ptr();
421 /* In A64 all instructions (both FP and Neon) use the FPCR;
422 * there is no equivalent of the A32 Neon "standard FPSCR value"
423 * and all operations use vfp.fp_status.
425 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
426 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
430 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
431 * than the 32 bit equivalent.
433 static inline void gen_set_NZ64(TCGv_i64 result
)
435 TCGv_i64 flag
= tcg_temp_new_i64();
437 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
438 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
439 tcg_gen_shri_i64(flag
, result
, 32);
440 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
441 tcg_temp_free_i64(flag
);
444 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
445 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
448 gen_set_NZ64(result
);
450 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
451 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
453 tcg_gen_movi_i32(cpu_CF
, 0);
454 tcg_gen_movi_i32(cpu_VF
, 0);
457 /* dest = T0 + T1; compute C, N, V and Z flags */
458 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
461 TCGv_i64 result
, flag
, tmp
;
462 result
= tcg_temp_new_i64();
463 flag
= tcg_temp_new_i64();
464 tmp
= tcg_temp_new_i64();
466 tcg_gen_movi_i64(tmp
, 0);
467 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
469 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
471 gen_set_NZ64(result
);
473 tcg_gen_xor_i64(flag
, result
, t0
);
474 tcg_gen_xor_i64(tmp
, t0
, t1
);
475 tcg_gen_andc_i64(flag
, flag
, tmp
);
476 tcg_temp_free_i64(tmp
);
477 tcg_gen_shri_i64(flag
, flag
, 32);
478 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
480 tcg_gen_mov_i64(dest
, result
);
481 tcg_temp_free_i64(result
);
482 tcg_temp_free_i64(flag
);
484 /* 32 bit arithmetic */
485 TCGv_i32 t0_32
= tcg_temp_new_i32();
486 TCGv_i32 t1_32
= tcg_temp_new_i32();
487 TCGv_i32 tmp
= tcg_temp_new_i32();
489 tcg_gen_movi_i32(tmp
, 0);
490 tcg_gen_trunc_i64_i32(t0_32
, t0
);
491 tcg_gen_trunc_i64_i32(t1_32
, t1
);
492 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
493 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
494 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
495 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
496 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
497 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
499 tcg_temp_free_i32(tmp
);
500 tcg_temp_free_i32(t0_32
);
501 tcg_temp_free_i32(t1_32
);
505 /* dest = T0 - T1; compute C, N, V and Z flags */
506 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
509 /* 64 bit arithmetic */
510 TCGv_i64 result
, flag
, tmp
;
512 result
= tcg_temp_new_i64();
513 flag
= tcg_temp_new_i64();
514 tcg_gen_sub_i64(result
, t0
, t1
);
516 gen_set_NZ64(result
);
518 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
519 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
521 tcg_gen_xor_i64(flag
, result
, t0
);
522 tmp
= tcg_temp_new_i64();
523 tcg_gen_xor_i64(tmp
, t0
, t1
);
524 tcg_gen_and_i64(flag
, flag
, tmp
);
525 tcg_temp_free_i64(tmp
);
526 tcg_gen_shri_i64(flag
, flag
, 32);
527 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
528 tcg_gen_mov_i64(dest
, result
);
529 tcg_temp_free_i64(flag
);
530 tcg_temp_free_i64(result
);
532 /* 32 bit arithmetic */
533 TCGv_i32 t0_32
= tcg_temp_new_i32();
534 TCGv_i32 t1_32
= tcg_temp_new_i32();
537 tcg_gen_trunc_i64_i32(t0_32
, t0
);
538 tcg_gen_trunc_i64_i32(t1_32
, t1
);
539 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
540 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
541 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
542 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
543 tmp
= tcg_temp_new_i32();
544 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
545 tcg_temp_free_i32(t0_32
);
546 tcg_temp_free_i32(t1_32
);
547 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
548 tcg_temp_free_i32(tmp
);
549 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
553 /* dest = T0 + T1 + CF; do not compute flags. */
554 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
556 TCGv_i64 flag
= tcg_temp_new_i64();
557 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
558 tcg_gen_add_i64(dest
, t0
, t1
);
559 tcg_gen_add_i64(dest
, dest
, flag
);
560 tcg_temp_free_i64(flag
);
563 tcg_gen_ext32u_i64(dest
, dest
);
567 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
568 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
571 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
572 result
= tcg_temp_new_i64();
573 cf_64
= tcg_temp_new_i64();
574 vf_64
= tcg_temp_new_i64();
575 tmp
= tcg_const_i64(0);
577 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
578 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
579 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
580 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
581 gen_set_NZ64(result
);
583 tcg_gen_xor_i64(vf_64
, result
, t0
);
584 tcg_gen_xor_i64(tmp
, t0
, t1
);
585 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
586 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
587 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
589 tcg_gen_mov_i64(dest
, result
);
591 tcg_temp_free_i64(tmp
);
592 tcg_temp_free_i64(vf_64
);
593 tcg_temp_free_i64(cf_64
);
594 tcg_temp_free_i64(result
);
596 TCGv_i32 t0_32
, t1_32
, tmp
;
597 t0_32
= tcg_temp_new_i32();
598 t1_32
= tcg_temp_new_i32();
599 tmp
= tcg_const_i32(0);
601 tcg_gen_trunc_i64_i32(t0_32
, t0
);
602 tcg_gen_trunc_i64_i32(t1_32
, t1
);
603 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
604 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
606 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
607 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
608 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
609 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
610 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
612 tcg_temp_free_i32(tmp
);
613 tcg_temp_free_i32(t1_32
);
614 tcg_temp_free_i32(t0_32
);
619 * Load/Store generators
623 * Store from GPR register to memory.
625 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
626 TCGv_i64 tcg_addr
, int size
, int memidx
)
629 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
632 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
633 TCGv_i64 tcg_addr
, int size
)
635 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
639 * Load from memory to GPR register
641 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
642 int size
, bool is_signed
, bool extend
, int memidx
)
644 TCGMemOp memop
= MO_TE
+ size
;
652 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
654 if (extend
&& is_signed
) {
656 tcg_gen_ext32u_i64(dest
, dest
);
660 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
661 int size
, bool is_signed
, bool extend
)
663 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
668 * Store from FP register to memory
670 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
672 /* This writes the bottom N bits of a 128 bit wide vector to memory */
673 TCGv_i64 tmp
= tcg_temp_new_i64();
674 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(srcidx
, MO_64
));
676 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
678 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
679 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
680 tcg_gen_qemu_st64(tmp
, tcg_addr
, get_mem_index(s
));
681 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(srcidx
));
682 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
683 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
684 tcg_temp_free_i64(tcg_hiaddr
);
687 tcg_temp_free_i64(tmp
);
691 * Load from memory to FP register
693 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
695 /* This always zero-extends and writes to a full 128 bit wide vector */
696 TCGv_i64 tmplo
= tcg_temp_new_i64();
700 TCGMemOp memop
= MO_TE
+ size
;
701 tmphi
= tcg_const_i64(0);
702 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
705 tmphi
= tcg_temp_new_i64();
706 tcg_hiaddr
= tcg_temp_new_i64();
708 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
709 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
710 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
711 tcg_temp_free_i64(tcg_hiaddr
);
714 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(destidx
, MO_64
));
715 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(destidx
));
717 tcg_temp_free_i64(tmplo
);
718 tcg_temp_free_i64(tmphi
);
722 * Vector load/store helpers.
724 * The principal difference between this and a FP load is that we don't
725 * zero extend as we are filling a partial chunk of the vector register.
726 * These functions don't support 128 bit loads/stores, which would be
727 * normal load/store operations.
729 * The _i32 versions are useful when operating on 32 bit quantities
730 * (eg for floating point single or using Neon helper functions).
733 /* Get value of an element within a vector register */
734 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
735 int element
, TCGMemOp memop
)
737 int vect_off
= vec_reg_offset(srcidx
, element
, memop
& MO_SIZE
);
740 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
743 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
746 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
749 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
752 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
755 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
759 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
762 g_assert_not_reached();
766 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
767 int element
, TCGMemOp memop
)
769 int vect_off
= vec_reg_offset(srcidx
, element
, memop
& MO_SIZE
);
772 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
775 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
778 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
781 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
785 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
788 g_assert_not_reached();
792 /* Set value of an element within a vector register */
793 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
794 int element
, TCGMemOp memop
)
796 int vect_off
= vec_reg_offset(destidx
, element
, memop
& MO_SIZE
);
799 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
802 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
805 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
808 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
811 g_assert_not_reached();
815 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
816 int destidx
, int element
, TCGMemOp memop
)
818 int vect_off
= vec_reg_offset(destidx
, element
, memop
& MO_SIZE
);
821 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
824 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
827 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
830 g_assert_not_reached();
834 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
835 * vector ops all need to do this).
837 static void clear_vec_high(DisasContext
*s
, int rd
)
839 TCGv_i64 tcg_zero
= tcg_const_i64(0);
841 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
842 tcg_temp_free_i64(tcg_zero
);
845 /* Store from vector register to memory */
846 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
847 TCGv_i64 tcg_addr
, int size
)
849 TCGMemOp memop
= MO_TE
+ size
;
850 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
852 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
853 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
855 tcg_temp_free_i64(tcg_tmp
);
858 /* Load from memory to vector register */
859 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
860 TCGv_i64 tcg_addr
, int size
)
862 TCGMemOp memop
= MO_TE
+ size
;
863 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
865 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
866 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
868 tcg_temp_free_i64(tcg_tmp
);
872 * This utility function is for doing register extension with an
873 * optional shift. You will likely want to pass a temporary for the
874 * destination register. See DecodeRegExtend() in the ARM ARM.
876 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
877 int option
, unsigned int shift
)
879 int extsize
= extract32(option
, 0, 2);
880 bool is_signed
= extract32(option
, 2, 1);
885 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
888 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
891 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
894 tcg_gen_mov_i64(tcg_out
, tcg_in
);
900 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
903 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
906 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
909 tcg_gen_mov_i64(tcg_out
, tcg_in
);
915 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
919 static inline void gen_check_sp_alignment(DisasContext
*s
)
921 /* The AArch64 architecture mandates that (if enabled via PSTATE
922 * or SCTLR bits) there is a check that SP is 16-aligned on every
923 * SP-relative load or store (with an exception generated if it is not).
924 * In line with general QEMU practice regarding misaligned accesses,
925 * we omit these checks for the sake of guest program performance.
926 * This function is provided as a hook so we can more easily add these
927 * checks in future (possibly as a "favour catching guest program bugs
928 * over speed" user selectable option).
933 * This provides a simple table based table lookup decoder. It is
934 * intended to be used when the relevant bits for decode are too
935 * awkwardly placed and switch/if based logic would be confusing and
936 * deeply nested. Since it's a linear search through the table, tables
937 * should be kept small.
939 * It returns the first handler where insn & mask == pattern, or
940 * NULL if there is no match.
941 * The table is terminated by an empty mask (i.e. 0)
943 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
946 const AArch64DecodeTable
*tptr
= table
;
949 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
950 return tptr
->disas_fn
;
958 * the instruction disassembly implemented here matches
959 * the instruction encoding classifications in chapter 3 (C3)
960 * of the ARM Architecture Reference Manual (DDI0487A_a)
963 /* C3.2.7 Unconditional branch (immediate)
965 * +----+-----------+-------------------------------------+
966 * | op | 0 0 1 0 1 | imm26 |
967 * +----+-----------+-------------------------------------+
969 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
971 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
973 if (insn
& (1 << 31)) {
974 /* C5.6.26 BL Branch with link */
975 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
978 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
979 gen_goto_tb(s
, 0, addr
);
982 /* C3.2.1 Compare & branch (immediate)
983 * 31 30 25 24 23 5 4 0
984 * +----+-------------+----+---------------------+--------+
985 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
986 * +----+-------------+----+---------------------+--------+
988 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
990 unsigned int sf
, op
, rt
;
995 sf
= extract32(insn
, 31, 1);
996 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
997 rt
= extract32(insn
, 0, 5);
998 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1000 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1001 label_match
= gen_new_label();
1003 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1004 tcg_cmp
, 0, label_match
);
1006 gen_goto_tb(s
, 0, s
->pc
);
1007 gen_set_label(label_match
);
1008 gen_goto_tb(s
, 1, addr
);
1011 /* C3.2.5 Test & branch (immediate)
1012 * 31 30 25 24 23 19 18 5 4 0
1013 * +----+-------------+----+-------+-------------+------+
1014 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1015 * +----+-------------+----+-------+-------------+------+
1017 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1019 unsigned int bit_pos
, op
, rt
;
1024 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1025 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1026 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1027 rt
= extract32(insn
, 0, 5);
1029 tcg_cmp
= tcg_temp_new_i64();
1030 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1031 label_match
= gen_new_label();
1032 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1033 tcg_cmp
, 0, label_match
);
1034 tcg_temp_free_i64(tcg_cmp
);
1035 gen_goto_tb(s
, 0, s
->pc
);
1036 gen_set_label(label_match
);
1037 gen_goto_tb(s
, 1, addr
);
1040 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1041 * 31 25 24 23 5 4 3 0
1042 * +---------------+----+---------------------+----+------+
1043 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1044 * +---------------+----+---------------------+----+------+
1046 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1051 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1052 unallocated_encoding(s
);
1055 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1056 cond
= extract32(insn
, 0, 4);
1059 /* genuinely conditional branches */
1060 int label_match
= gen_new_label();
1061 arm_gen_test_cc(cond
, label_match
);
1062 gen_goto_tb(s
, 0, s
->pc
);
1063 gen_set_label(label_match
);
1064 gen_goto_tb(s
, 1, addr
);
1066 /* 0xe and 0xf are both "always" conditions */
1067 gen_goto_tb(s
, 0, addr
);
1072 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1073 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1075 unsigned int selector
= crm
<< 3 | op2
;
1078 unallocated_encoding(s
);
1086 s
->is_jmp
= DISAS_WFI
;
1092 /* we treat all as NOP at least for now */
1095 /* default specified as NOP equivalent */
1100 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1102 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1105 /* CLREX, DSB, DMB, ISB */
1106 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1107 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1110 unallocated_encoding(s
);
1121 /* We don't emulate caches so barriers are no-ops */
1124 unallocated_encoding(s
);
1129 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1130 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1131 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1133 int op
= op1
<< 3 | op2
;
1135 case 0x05: /* SPSel */
1136 if (s
->current_pl
== 0) {
1137 unallocated_encoding(s
);
1141 case 0x1e: /* DAIFSet */
1142 case 0x1f: /* DAIFClear */
1144 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1145 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1146 gen_a64_set_pc_im(s
->pc
- 4);
1147 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1148 tcg_temp_free_i32(tcg_imm
);
1149 tcg_temp_free_i32(tcg_op
);
1150 s
->is_jmp
= DISAS_UPDATE
;
1154 unallocated_encoding(s
);
1159 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1161 TCGv_i32 tmp
= tcg_temp_new_i32();
1162 TCGv_i32 nzcv
= tcg_temp_new_i32();
1164 /* build bit 31, N */
1165 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
1166 /* build bit 30, Z */
1167 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1168 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1169 /* build bit 29, C */
1170 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1171 /* build bit 28, V */
1172 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1173 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1174 /* generate result */
1175 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1177 tcg_temp_free_i32(nzcv
);
1178 tcg_temp_free_i32(tmp
);
1181 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1184 TCGv_i32 nzcv
= tcg_temp_new_i32();
1186 /* take NZCV from R[t] */
1187 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
1190 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
1192 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1193 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1195 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1196 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1198 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1199 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1200 tcg_temp_free_i32(nzcv
);
1203 /* C5.6.129 MRS - move from system register
1204 * C5.6.131 MSR (register) - move to system register
1207 * These are all essentially the same insn in 'read' and 'write'
1208 * versions, with varying op0 fields.
1210 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1211 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1212 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1214 const ARMCPRegInfo
*ri
;
1217 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1218 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1219 crn
, crm
, op0
, op1
, op2
));
1222 /* Unknown register; this might be a guest error or a QEMU
1223 * unimplemented feature.
1225 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1226 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1227 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1228 unallocated_encoding(s
);
1232 /* Check access permissions */
1233 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
1234 unallocated_encoding(s
);
1239 /* Emit code to perform further access permissions checks at
1240 * runtime; this may result in an exception.
1243 gen_a64_set_pc_im(s
->pc
- 4);
1244 tmpptr
= tcg_const_ptr(ri
);
1245 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
);
1246 tcg_temp_free_ptr(tmpptr
);
1249 /* Handle special cases first */
1250 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1254 tcg_rt
= cpu_reg(s
, rt
);
1256 gen_get_nzcv(tcg_rt
);
1258 gen_set_nzcv(tcg_rt
);
1261 case ARM_CP_CURRENTEL
:
1262 /* Reads as current EL value from pstate, which is
1263 * guaranteed to be constant by the tb flags.
1265 tcg_rt
= cpu_reg(s
, rt
);
1266 tcg_gen_movi_i64(tcg_rt
, s
->current_pl
<< 2);
1272 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1276 tcg_rt
= cpu_reg(s
, rt
);
1279 if (ri
->type
& ARM_CP_CONST
) {
1280 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1281 } else if (ri
->readfn
) {
1283 tmpptr
= tcg_const_ptr(ri
);
1284 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1285 tcg_temp_free_ptr(tmpptr
);
1287 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1290 if (ri
->type
& ARM_CP_CONST
) {
1291 /* If not forbidden by access permissions, treat as WI */
1293 } else if (ri
->writefn
) {
1295 tmpptr
= tcg_const_ptr(ri
);
1296 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1297 tcg_temp_free_ptr(tmpptr
);
1299 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1303 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1304 /* I/O operations must end the TB here (whether read or write) */
1306 s
->is_jmp
= DISAS_UPDATE
;
1307 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1308 /* We default to ending the TB on a coprocessor register write,
1309 * but allow this to be suppressed by the register definition
1310 * (usually only necessary to work around guest bugs).
1312 s
->is_jmp
= DISAS_UPDATE
;
1317 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1318 * +---------------------+---+-----+-----+-------+-------+-----+------+
1319 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1320 * +---------------------+---+-----+-----+-------+-------+-----+------+
1322 static void disas_system(DisasContext
*s
, uint32_t insn
)
1324 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1325 l
= extract32(insn
, 21, 1);
1326 op0
= extract32(insn
, 19, 2);
1327 op1
= extract32(insn
, 16, 3);
1328 crn
= extract32(insn
, 12, 4);
1329 crm
= extract32(insn
, 8, 4);
1330 op2
= extract32(insn
, 5, 3);
1331 rt
= extract32(insn
, 0, 5);
1334 if (l
|| rt
!= 31) {
1335 unallocated_encoding(s
);
1339 case 2: /* C5.6.68 HINT */
1340 handle_hint(s
, insn
, op1
, op2
, crm
);
1342 case 3: /* CLREX, DSB, DMB, ISB */
1343 handle_sync(s
, insn
, op1
, op2
, crm
);
1345 case 4: /* C5.6.130 MSR (immediate) */
1346 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1349 unallocated_encoding(s
);
1354 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1357 /* C3.2.3 Exception generation
1359 * 31 24 23 21 20 5 4 2 1 0
1360 * +-----------------+-----+------------------------+-----+----+
1361 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1362 * +-----------------------+------------------------+----------+
1364 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1366 int opc
= extract32(insn
, 21, 3);
1367 int op2_ll
= extract32(insn
, 0, 5);
1371 /* SVC, HVC, SMC; since we don't support the Virtualization
1372 * or TrustZone extensions these all UNDEF except SVC.
1375 unallocated_encoding(s
);
1378 gen_exception_insn(s
, 0, EXCP_SWI
);
1382 unallocated_encoding(s
);
1386 gen_exception_insn(s
, 0, EXCP_BKPT
);
1390 unallocated_encoding(s
);
1394 unsupported_encoding(s
, insn
);
1397 if (op2_ll
< 1 || op2_ll
> 3) {
1398 unallocated_encoding(s
);
1401 /* DCPS1, DCPS2, DCPS3 */
1402 unsupported_encoding(s
, insn
);
1405 unallocated_encoding(s
);
1410 /* C3.2.7 Unconditional branch (register)
1411 * 31 25 24 21 20 16 15 10 9 5 4 0
1412 * +---------------+-------+-------+-------+------+-------+
1413 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1414 * +---------------+-------+-------+-------+------+-------+
1416 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1418 unsigned int opc
, op2
, op3
, rn
, op4
;
1420 opc
= extract32(insn
, 21, 4);
1421 op2
= extract32(insn
, 16, 5);
1422 op3
= extract32(insn
, 10, 6);
1423 rn
= extract32(insn
, 5, 5);
1424 op4
= extract32(insn
, 0, 5);
1426 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1427 unallocated_encoding(s
);
1436 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1441 unallocated_encoding(s
);
1443 unsupported_encoding(s
, insn
);
1447 unallocated_encoding(s
);
1451 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1452 s
->is_jmp
= DISAS_JUMP
;
1455 /* C3.2 Branches, exception generating and system instructions */
1456 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1458 switch (extract32(insn
, 25, 7)) {
1459 case 0x0a: case 0x0b:
1460 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1461 disas_uncond_b_imm(s
, insn
);
1463 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1464 disas_comp_b_imm(s
, insn
);
1466 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1467 disas_test_b_imm(s
, insn
);
1469 case 0x2a: /* Conditional branch (immediate) */
1470 disas_cond_b_imm(s
, insn
);
1472 case 0x6a: /* Exception generation / System */
1473 if (insn
& (1 << 24)) {
1474 disas_system(s
, insn
);
1479 case 0x6b: /* Unconditional branch (register) */
1480 disas_uncond_b_reg(s
, insn
);
1483 unallocated_encoding(s
);
1489 * Load/Store exclusive instructions are implemented by remembering
1490 * the value/address loaded, and seeing if these are the same
1491 * when the store is performed. This is not actually the architecturally
1492 * mandated semantics, but it works for typical guest code sequences
1493 * and avoids having to monitor regular stores.
1495 * In system emulation mode only one CPU will be running at once, so
1496 * this sequence is effectively atomic. In user emulation mode we
1497 * throw an exception and handle the atomic operation elsewhere.
1499 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1500 TCGv_i64 addr
, int size
, bool is_pair
)
1502 TCGv_i64 tmp
= tcg_temp_new_i64();
1503 TCGMemOp memop
= MO_TE
+ size
;
1505 g_assert(size
<= 3);
1506 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1509 TCGv_i64 addr2
= tcg_temp_new_i64();
1510 TCGv_i64 hitmp
= tcg_temp_new_i64();
1512 g_assert(size
>= 2);
1513 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1514 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1515 tcg_temp_free_i64(addr2
);
1516 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1517 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1518 tcg_temp_free_i64(hitmp
);
1521 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1522 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1524 tcg_temp_free_i64(tmp
);
1525 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1528 #ifdef CONFIG_USER_ONLY
1529 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1530 TCGv_i64 addr
, int size
, int is_pair
)
1532 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1533 tcg_gen_movi_i32(cpu_exclusive_info
,
1534 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1535 gen_exception_insn(s
, 4, EXCP_STREX
);
1538 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1539 TCGv_i64 inaddr
, int size
, int is_pair
)
1541 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1542 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1545 * [addr + datasize] = {Rt2};
1551 * env->exclusive_addr = -1;
1553 int fail_label
= gen_new_label();
1554 int done_label
= gen_new_label();
1555 TCGv_i64 addr
= tcg_temp_local_new_i64();
1558 /* Copy input into a local temp so it is not trashed when the
1559 * basic block ends at the branch insn.
1561 tcg_gen_mov_i64(addr
, inaddr
);
1562 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1564 tmp
= tcg_temp_new_i64();
1565 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1566 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1567 tcg_temp_free_i64(tmp
);
1570 TCGv_i64 addrhi
= tcg_temp_new_i64();
1571 TCGv_i64 tmphi
= tcg_temp_new_i64();
1573 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1574 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1575 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1577 tcg_temp_free_i64(tmphi
);
1578 tcg_temp_free_i64(addrhi
);
1581 /* We seem to still have the exclusive monitor, so do the store */
1582 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1584 TCGv_i64 addrhi
= tcg_temp_new_i64();
1586 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1587 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1588 get_mem_index(s
), MO_TE
+ size
);
1589 tcg_temp_free_i64(addrhi
);
1592 tcg_temp_free_i64(addr
);
1594 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1595 tcg_gen_br(done_label
);
1596 gen_set_label(fail_label
);
1597 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1598 gen_set_label(done_label
);
1599 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1604 /* C3.3.6 Load/store exclusive
1606 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1607 * +-----+-------------+----+---+----+------+----+-------+------+------+
1608 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1609 * +-----+-------------+----+---+----+------+----+-------+------+------+
1611 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1612 * L: 0 -> store, 1 -> load
1613 * o2: 0 -> exclusive, 1 -> not
1614 * o1: 0 -> single register, 1 -> register pair
1615 * o0: 1 -> load-acquire/store-release, 0 -> not
1617 * o0 == 0 AND o2 == 1 is un-allocated
1618 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1620 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1622 int rt
= extract32(insn
, 0, 5);
1623 int rn
= extract32(insn
, 5, 5);
1624 int rt2
= extract32(insn
, 10, 5);
1625 int is_lasr
= extract32(insn
, 15, 1);
1626 int rs
= extract32(insn
, 16, 5);
1627 int is_pair
= extract32(insn
, 21, 1);
1628 int is_store
= !extract32(insn
, 22, 1);
1629 int is_excl
= !extract32(insn
, 23, 1);
1630 int size
= extract32(insn
, 30, 2);
1633 if ((!is_excl
&& !is_lasr
) ||
1634 (is_pair
&& size
< 2)) {
1635 unallocated_encoding(s
);
1640 gen_check_sp_alignment(s
);
1642 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1644 /* Note that since TCG is single threaded load-acquire/store-release
1645 * semantics require no extra if (is_lasr) { ... } handling.
1650 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1652 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1655 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1657 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1659 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1662 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1663 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1665 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1667 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1674 * C3.3.5 Load register (literal)
1676 * 31 30 29 27 26 25 24 23 5 4 0
1677 * +-----+-------+---+-----+-------------------+-------+
1678 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1679 * +-----+-------+---+-----+-------------------+-------+
1681 * V: 1 -> vector (simd/fp)
1682 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1683 * 10-> 32 bit signed, 11 -> prefetch
1684 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1686 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1688 int rt
= extract32(insn
, 0, 5);
1689 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1690 bool is_vector
= extract32(insn
, 26, 1);
1691 int opc
= extract32(insn
, 30, 2);
1692 bool is_signed
= false;
1694 TCGv_i64 tcg_rt
, tcg_addr
;
1698 unallocated_encoding(s
);
1704 /* PRFM (literal) : prefetch */
1707 size
= 2 + extract32(opc
, 0, 1);
1708 is_signed
= extract32(opc
, 1, 1);
1711 tcg_rt
= cpu_reg(s
, rt
);
1713 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1715 do_fp_ld(s
, rt
, tcg_addr
, size
);
1717 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1719 tcg_temp_free_i64(tcg_addr
);
1723 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1724 * C5.6.81 LDP (Load Pair - non vector)
1725 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1726 * C5.6.176 STNP (Store Pair - non-temporal hint)
1727 * C5.6.177 STP (Store Pair - non vector)
1728 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1729 * C6.3.165 LDP (Load Pair of SIMD&FP)
1730 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1731 * C6.3.284 STP (Store Pair of SIMD&FP)
1733 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1734 * +-----+-------+---+---+-------+---+-----------------------------+
1735 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1736 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1738 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1740 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1741 * V: 0 -> GPR, 1 -> Vector
1742 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1743 * 10 -> signed offset, 11 -> pre-index
1744 * L: 0 -> Store 1 -> Load
1746 * Rt, Rt2 = GPR or SIMD registers to be stored
1747 * Rn = general purpose register containing address
1748 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1750 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1752 int rt
= extract32(insn
, 0, 5);
1753 int rn
= extract32(insn
, 5, 5);
1754 int rt2
= extract32(insn
, 10, 5);
1755 int64_t offset
= sextract32(insn
, 15, 7);
1756 int index
= extract32(insn
, 23, 2);
1757 bool is_vector
= extract32(insn
, 26, 1);
1758 bool is_load
= extract32(insn
, 22, 1);
1759 int opc
= extract32(insn
, 30, 2);
1761 bool is_signed
= false;
1762 bool postindex
= false;
1765 TCGv_i64 tcg_addr
; /* calculated address */
1769 unallocated_encoding(s
);
1776 size
= 2 + extract32(opc
, 1, 1);
1777 is_signed
= extract32(opc
, 0, 1);
1778 if (!is_load
&& is_signed
) {
1779 unallocated_encoding(s
);
1785 case 1: /* post-index */
1790 /* signed offset with "non-temporal" hint. Since we don't emulate
1791 * caches we don't care about hints to the cache system about
1792 * data access patterns, and handle this identically to plain
1796 /* There is no non-temporal-hint version of LDPSW */
1797 unallocated_encoding(s
);
1802 case 2: /* signed offset, rn not updated */
1805 case 3: /* pre-index */
1814 gen_check_sp_alignment(s
);
1817 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1820 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1825 do_fp_ld(s
, rt
, tcg_addr
, size
);
1827 do_fp_st(s
, rt
, tcg_addr
, size
);
1830 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1832 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1834 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1837 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1840 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1842 do_fp_st(s
, rt2
, tcg_addr
, size
);
1845 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
1847 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
1849 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1855 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
1857 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1859 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
1864 * C3.3.8 Load/store (immediate post-indexed)
1865 * C3.3.9 Load/store (immediate pre-indexed)
1866 * C3.3.12 Load/store (unscaled immediate)
1868 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1869 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1870 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1871 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1873 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1875 * V = 0 -> non-vector
1876 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1877 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1879 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
1881 int rt
= extract32(insn
, 0, 5);
1882 int rn
= extract32(insn
, 5, 5);
1883 int imm9
= sextract32(insn
, 12, 9);
1884 int opc
= extract32(insn
, 22, 2);
1885 int size
= extract32(insn
, 30, 2);
1886 int idx
= extract32(insn
, 10, 2);
1887 bool is_signed
= false;
1888 bool is_store
= false;
1889 bool is_extended
= false;
1890 bool is_unpriv
= (idx
== 2);
1891 bool is_vector
= extract32(insn
, 26, 1);
1898 size
|= (opc
& 2) << 1;
1899 if (size
> 4 || is_unpriv
) {
1900 unallocated_encoding(s
);
1903 is_store
= ((opc
& 1) == 0);
1905 if (size
== 3 && opc
== 2) {
1906 /* PRFM - prefetch */
1908 unallocated_encoding(s
);
1913 if (opc
== 3 && size
> 1) {
1914 unallocated_encoding(s
);
1917 is_store
= (opc
== 0);
1918 is_signed
= opc
& (1<<1);
1919 is_extended
= (size
< 3) && (opc
& 1);
1939 gen_check_sp_alignment(s
);
1941 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1944 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1949 do_fp_st(s
, rt
, tcg_addr
, size
);
1951 do_fp_ld(s
, rt
, tcg_addr
, size
);
1954 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1955 int memidx
= is_unpriv
? 1 : get_mem_index(s
);
1958 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
1960 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
1961 is_signed
, is_extended
, memidx
);
1966 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
1968 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1970 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
1975 * C3.3.10 Load/store (register offset)
1977 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
1978 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1979 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
1980 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1983 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1984 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1986 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1987 * opc<0>: 0 -> store, 1 -> load
1988 * V: 1 -> vector/simd
1989 * opt: extend encoding (see DecodeRegExtend)
1990 * S: if S=1 then scale (essentially index by sizeof(size))
1991 * Rt: register to transfer into/out of
1992 * Rn: address register or SP for base
1993 * Rm: offset register or ZR for offset
1995 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
1997 int rt
= extract32(insn
, 0, 5);
1998 int rn
= extract32(insn
, 5, 5);
1999 int shift
= extract32(insn
, 12, 1);
2000 int rm
= extract32(insn
, 16, 5);
2001 int opc
= extract32(insn
, 22, 2);
2002 int opt
= extract32(insn
, 13, 3);
2003 int size
= extract32(insn
, 30, 2);
2004 bool is_signed
= false;
2005 bool is_store
= false;
2006 bool is_extended
= false;
2007 bool is_vector
= extract32(insn
, 26, 1);
2012 if (extract32(opt
, 1, 1) == 0) {
2013 unallocated_encoding(s
);
2018 size
|= (opc
& 2) << 1;
2020 unallocated_encoding(s
);
2023 is_store
= !extract32(opc
, 0, 1);
2025 if (size
== 3 && opc
== 2) {
2026 /* PRFM - prefetch */
2029 if (opc
== 3 && size
> 1) {
2030 unallocated_encoding(s
);
2033 is_store
= (opc
== 0);
2034 is_signed
= extract32(opc
, 1, 1);
2035 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2039 gen_check_sp_alignment(s
);
2041 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2043 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2044 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2046 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2050 do_fp_st(s
, rt
, tcg_addr
, size
);
2052 do_fp_ld(s
, rt
, tcg_addr
, size
);
2055 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2057 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2059 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2065 * C3.3.13 Load/store (unsigned immediate)
2067 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2068 * +----+-------+---+-----+-----+------------+-------+------+
2069 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2070 * +----+-------+---+-----+-----+------------+-------+------+
2073 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2074 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2076 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2077 * opc<0>: 0 -> store, 1 -> load
2078 * Rn: base address register (inc SP)
2079 * Rt: target register
2081 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2083 int rt
= extract32(insn
, 0, 5);
2084 int rn
= extract32(insn
, 5, 5);
2085 unsigned int imm12
= extract32(insn
, 10, 12);
2086 bool is_vector
= extract32(insn
, 26, 1);
2087 int size
= extract32(insn
, 30, 2);
2088 int opc
= extract32(insn
, 22, 2);
2089 unsigned int offset
;
2094 bool is_signed
= false;
2095 bool is_extended
= false;
2098 size
|= (opc
& 2) << 1;
2100 unallocated_encoding(s
);
2103 is_store
= !extract32(opc
, 0, 1);
2105 if (size
== 3 && opc
== 2) {
2106 /* PRFM - prefetch */
2109 if (opc
== 3 && size
> 1) {
2110 unallocated_encoding(s
);
2113 is_store
= (opc
== 0);
2114 is_signed
= extract32(opc
, 1, 1);
2115 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2119 gen_check_sp_alignment(s
);
2121 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2122 offset
= imm12
<< size
;
2123 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2127 do_fp_st(s
, rt
, tcg_addr
, size
);
2129 do_fp_ld(s
, rt
, tcg_addr
, size
);
2132 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2134 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2136 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2141 /* Load/store register (all forms) */
2142 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2144 switch (extract32(insn
, 24, 2)) {
2146 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2147 disas_ldst_reg_roffset(s
, insn
);
2149 /* Load/store register (unscaled immediate)
2150 * Load/store immediate pre/post-indexed
2151 * Load/store register unprivileged
2153 disas_ldst_reg_imm9(s
, insn
);
2157 disas_ldst_reg_unsigned_imm(s
, insn
);
2160 unallocated_encoding(s
);
2165 /* C3.3.1 AdvSIMD load/store multiple structures
2167 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2168 * +---+---+---------------+---+-------------+--------+------+------+------+
2169 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2170 * +---+---+---------------+---+-------------+--------+------+------+------+
2172 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2174 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2175 * +---+---+---------------+---+---+---------+--------+------+------+------+
2176 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2177 * +---+---+---------------+---+---+---------+--------+------+------+------+
2179 * Rt: first (or only) SIMD&FP register to be transferred
2180 * Rn: base address or SP
2181 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2183 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2185 int rt
= extract32(insn
, 0, 5);
2186 int rn
= extract32(insn
, 5, 5);
2187 int size
= extract32(insn
, 10, 2);
2188 int opcode
= extract32(insn
, 12, 4);
2189 bool is_store
= !extract32(insn
, 22, 1);
2190 bool is_postidx
= extract32(insn
, 23, 1);
2191 bool is_q
= extract32(insn
, 30, 1);
2192 TCGv_i64 tcg_addr
, tcg_rn
;
2194 int ebytes
= 1 << size
;
2195 int elements
= (is_q
? 128 : 64) / (8 << size
);
2196 int rpt
; /* num iterations */
2197 int selem
; /* structure elements */
2200 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2201 unallocated_encoding(s
);
2205 /* From the shared decode logic */
2236 unallocated_encoding(s
);
2240 if (size
== 3 && !is_q
&& selem
!= 1) {
2242 unallocated_encoding(s
);
2247 gen_check_sp_alignment(s
);
2250 tcg_rn
= cpu_reg_sp(s
, rn
);
2251 tcg_addr
= tcg_temp_new_i64();
2252 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2254 for (r
= 0; r
< rpt
; r
++) {
2256 for (e
= 0; e
< elements
; e
++) {
2257 int tt
= (rt
+ r
) % 32;
2259 for (xs
= 0; xs
< selem
; xs
++) {
2261 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2263 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2265 /* For non-quad operations, setting a slice of the low
2266 * 64 bits of the register clears the high 64 bits (in
2267 * the ARM ARM pseudocode this is implicit in the fact
2268 * that 'rval' is a 64 bit wide variable). We optimize
2269 * by noticing that we only need to do this the first
2270 * time we touch a register.
2272 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2273 clear_vec_high(s
, tt
);
2276 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2283 int rm
= extract32(insn
, 16, 5);
2285 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2287 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2290 tcg_temp_free_i64(tcg_addr
);
2293 /* C3.3.3 AdvSIMD load/store single structure
2295 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2296 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2297 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2298 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2300 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2302 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2303 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2304 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2305 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2307 * Rt: first (or only) SIMD&FP register to be transferred
2308 * Rn: base address or SP
2309 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2310 * index = encoded in Q:S:size dependent on size
2312 * lane_size = encoded in R, opc
2313 * transfer width = encoded in opc, S, size
2315 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2317 int rt
= extract32(insn
, 0, 5);
2318 int rn
= extract32(insn
, 5, 5);
2319 int size
= extract32(insn
, 10, 2);
2320 int S
= extract32(insn
, 12, 1);
2321 int opc
= extract32(insn
, 13, 3);
2322 int R
= extract32(insn
, 21, 1);
2323 int is_load
= extract32(insn
, 22, 1);
2324 int is_postidx
= extract32(insn
, 23, 1);
2325 int is_q
= extract32(insn
, 30, 1);
2327 int scale
= extract32(opc
, 1, 2);
2328 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2329 bool replicate
= false;
2330 int index
= is_q
<< 3 | S
<< 2 | size
;
2332 TCGv_i64 tcg_addr
, tcg_rn
;
2336 if (!is_load
|| S
) {
2337 unallocated_encoding(s
);
2346 if (extract32(size
, 0, 1)) {
2347 unallocated_encoding(s
);
2353 if (extract32(size
, 1, 1)) {
2354 unallocated_encoding(s
);
2357 if (!extract32(size
, 0, 1)) {
2361 unallocated_encoding(s
);
2369 g_assert_not_reached();
2372 ebytes
= 1 << scale
;
2375 gen_check_sp_alignment(s
);
2378 tcg_rn
= cpu_reg_sp(s
, rn
);
2379 tcg_addr
= tcg_temp_new_i64();
2380 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2382 for (xs
= 0; xs
< selem
; xs
++) {
2384 /* Load and replicate to all elements */
2386 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2388 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2389 get_mem_index(s
), MO_TE
+ scale
);
2392 mulconst
= 0x0101010101010101ULL
;
2395 mulconst
= 0x0001000100010001ULL
;
2398 mulconst
= 0x0000000100000001ULL
;
2404 g_assert_not_reached();
2407 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2409 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2411 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2413 clear_vec_high(s
, rt
);
2415 tcg_temp_free_i64(tcg_tmp
);
2417 /* Load/store one element per register */
2419 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2421 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2424 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2429 int rm
= extract32(insn
, 16, 5);
2431 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2433 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2436 tcg_temp_free_i64(tcg_addr
);
2439 /* C3.3 Loads and stores */
2440 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2442 switch (extract32(insn
, 24, 6)) {
2443 case 0x08: /* Load/store exclusive */
2444 disas_ldst_excl(s
, insn
);
2446 case 0x18: case 0x1c: /* Load register (literal) */
2447 disas_ld_lit(s
, insn
);
2449 case 0x28: case 0x29:
2450 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2451 disas_ldst_pair(s
, insn
);
2453 case 0x38: case 0x39:
2454 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2455 disas_ldst_reg(s
, insn
);
2457 case 0x0c: /* AdvSIMD load/store multiple structures */
2458 disas_ldst_multiple_struct(s
, insn
);
2460 case 0x0d: /* AdvSIMD load/store single structure */
2461 disas_ldst_single_struct(s
, insn
);
2464 unallocated_encoding(s
);
2469 /* C3.4.6 PC-rel. addressing
2470 * 31 30 29 28 24 23 5 4 0
2471 * +----+-------+-----------+-------------------+------+
2472 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2473 * +----+-------+-----------+-------------------+------+
2475 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2477 unsigned int page
, rd
;
2481 page
= extract32(insn
, 31, 1);
2482 /* SignExtend(immhi:immlo) -> offset */
2483 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
2484 rd
= extract32(insn
, 0, 5);
2488 /* ADRP (page based) */
2493 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2497 * C3.4.1 Add/subtract (immediate)
2499 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2500 * +--+--+--+-----------+-----+-------------+-----+-----+
2501 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2502 * +--+--+--+-----------+-----+-------------+-----+-----+
2504 * sf: 0 -> 32bit, 1 -> 64bit
2505 * op: 0 -> add , 1 -> sub
2507 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2509 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2511 int rd
= extract32(insn
, 0, 5);
2512 int rn
= extract32(insn
, 5, 5);
2513 uint64_t imm
= extract32(insn
, 10, 12);
2514 int shift
= extract32(insn
, 22, 2);
2515 bool setflags
= extract32(insn
, 29, 1);
2516 bool sub_op
= extract32(insn
, 30, 1);
2517 bool is_64bit
= extract32(insn
, 31, 1);
2519 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2520 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2521 TCGv_i64 tcg_result
;
2530 unallocated_encoding(s
);
2534 tcg_result
= tcg_temp_new_i64();
2537 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2539 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2542 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2544 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2546 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2548 tcg_temp_free_i64(tcg_imm
);
2552 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2554 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2557 tcg_temp_free_i64(tcg_result
);
2560 /* The input should be a value in the bottom e bits (with higher
2561 * bits zero); returns that value replicated into every element
2562 * of size e in a 64 bit integer.
2564 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2574 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2575 static inline uint64_t bitmask64(unsigned int length
)
2577 assert(length
> 0 && length
<= 64);
2578 return ~0ULL >> (64 - length
);
2581 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2582 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2583 * value (ie should cause a guest UNDEF exception), and true if they are
2584 * valid, in which case the decoded bit pattern is written to result.
2586 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2587 unsigned int imms
, unsigned int immr
)
2590 unsigned e
, levels
, s
, r
;
2593 assert(immn
< 2 && imms
< 64 && immr
< 64);
2595 /* The bit patterns we create here are 64 bit patterns which
2596 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2597 * 64 bits each. Each element contains the same value: a run
2598 * of between 1 and e-1 non-zero bits, rotated within the
2599 * element by between 0 and e-1 bits.
2601 * The element size and run length are encoded into immn (1 bit)
2602 * and imms (6 bits) as follows:
2603 * 64 bit elements: immn = 1, imms = <length of run - 1>
2604 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2605 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2606 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2607 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2608 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2609 * Notice that immn = 0, imms = 11111x is the only combination
2610 * not covered by one of the above options; this is reserved.
2611 * Further, <length of run - 1> all-ones is a reserved pattern.
2613 * In all cases the rotation is by immr % e (and immr is 6 bits).
2616 /* First determine the element size */
2617 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2619 /* This is the immn == 0, imms == 0x11111x case */
2629 /* <length of run - 1> mustn't be all-ones. */
2633 /* Create the value of one element: s+1 set bits rotated
2634 * by r within the element (which is e bits wide)...
2636 mask
= bitmask64(s
+ 1);
2637 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2638 /* ...then replicate the element over the whole 64 bit value */
2639 mask
= bitfield_replicate(mask
, e
);
2644 /* C3.4.4 Logical (immediate)
2645 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2646 * +----+-----+-------------+---+------+------+------+------+
2647 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2648 * +----+-----+-------------+---+------+------+------+------+
2650 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2652 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2653 TCGv_i64 tcg_rd
, tcg_rn
;
2655 bool is_and
= false;
2657 sf
= extract32(insn
, 31, 1);
2658 opc
= extract32(insn
, 29, 2);
2659 is_n
= extract32(insn
, 22, 1);
2660 immr
= extract32(insn
, 16, 6);
2661 imms
= extract32(insn
, 10, 6);
2662 rn
= extract32(insn
, 5, 5);
2663 rd
= extract32(insn
, 0, 5);
2666 unallocated_encoding(s
);
2670 if (opc
== 0x3) { /* ANDS */
2671 tcg_rd
= cpu_reg(s
, rd
);
2673 tcg_rd
= cpu_reg_sp(s
, rd
);
2675 tcg_rn
= cpu_reg(s
, rn
);
2677 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2678 /* some immediate field values are reserved */
2679 unallocated_encoding(s
);
2684 wmask
&= 0xffffffff;
2688 case 0x3: /* ANDS */
2690 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2694 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2697 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2700 assert(FALSE
); /* must handle all above */
2704 if (!sf
&& !is_and
) {
2705 /* zero extend final result; we know we can skip this for AND
2706 * since the immediate had the high 32 bits clear.
2708 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2711 if (opc
== 3) { /* ANDS */
2712 gen_logic_CC(sf
, tcg_rd
);
2717 * C3.4.5 Move wide (immediate)
2719 * 31 30 29 28 23 22 21 20 5 4 0
2720 * +--+-----+-------------+-----+----------------+------+
2721 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2722 * +--+-----+-------------+-----+----------------+------+
2724 * sf: 0 -> 32 bit, 1 -> 64 bit
2725 * opc: 00 -> N, 10 -> Z, 11 -> K
2726 * hw: shift/16 (0,16, and sf only 32, 48)
2728 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2730 int rd
= extract32(insn
, 0, 5);
2731 uint64_t imm
= extract32(insn
, 5, 16);
2732 int sf
= extract32(insn
, 31, 1);
2733 int opc
= extract32(insn
, 29, 2);
2734 int pos
= extract32(insn
, 21, 2) << 4;
2735 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2738 if (!sf
&& (pos
>= 32)) {
2739 unallocated_encoding(s
);
2753 tcg_gen_movi_i64(tcg_rd
, imm
);
2756 tcg_imm
= tcg_const_i64(imm
);
2757 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2758 tcg_temp_free_i64(tcg_imm
);
2760 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2764 unallocated_encoding(s
);
2770 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2771 * +----+-----+-------------+---+------+------+------+------+
2772 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2773 * +----+-----+-------------+---+------+------+------+------+
2775 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2777 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2778 TCGv_i64 tcg_rd
, tcg_tmp
;
2780 sf
= extract32(insn
, 31, 1);
2781 opc
= extract32(insn
, 29, 2);
2782 n
= extract32(insn
, 22, 1);
2783 ri
= extract32(insn
, 16, 6);
2784 si
= extract32(insn
, 10, 6);
2785 rn
= extract32(insn
, 5, 5);
2786 rd
= extract32(insn
, 0, 5);
2787 bitsize
= sf
? 64 : 32;
2789 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2790 unallocated_encoding(s
);
2794 tcg_rd
= cpu_reg(s
, rd
);
2795 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2797 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2799 if (opc
!= 1) { /* SBFM or UBFM */
2800 tcg_gen_movi_i64(tcg_rd
, 0);
2803 /* do the bit move operation */
2805 /* Wd<s-r:0> = Wn<s:r> */
2806 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2808 len
= (si
- ri
) + 1;
2810 /* Wd<32+s-r,32-r> = Wn<s:0> */
2815 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2817 if (opc
== 0) { /* SBFM - sign extend the destination field */
2818 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2819 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2822 if (!sf
) { /* zero extend final result */
2823 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2828 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2829 * +----+------+-------------+---+----+------+--------+------+------+
2830 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2831 * +----+------+-------------+---+----+------+--------+------+------+
2833 static void disas_extract(DisasContext
*s
, uint32_t insn
)
2835 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
2837 sf
= extract32(insn
, 31, 1);
2838 n
= extract32(insn
, 22, 1);
2839 rm
= extract32(insn
, 16, 5);
2840 imm
= extract32(insn
, 10, 6);
2841 rn
= extract32(insn
, 5, 5);
2842 rd
= extract32(insn
, 0, 5);
2843 op21
= extract32(insn
, 29, 2);
2844 op0
= extract32(insn
, 21, 1);
2845 bitsize
= sf
? 64 : 32;
2847 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
2848 unallocated_encoding(s
);
2850 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
2852 tcg_rd
= cpu_reg(s
, rd
);
2855 /* OPTME: we can special case rm==rn as a rotate */
2856 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2857 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2858 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
2859 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
2860 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
2862 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2865 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2866 * so an extract from bit 0 is a special case.
2869 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
2871 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
2878 /* C3.4 Data processing - immediate */
2879 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
2881 switch (extract32(insn
, 23, 6)) {
2882 case 0x20: case 0x21: /* PC-rel. addressing */
2883 disas_pc_rel_adr(s
, insn
);
2885 case 0x22: case 0x23: /* Add/subtract (immediate) */
2886 disas_add_sub_imm(s
, insn
);
2888 case 0x24: /* Logical (immediate) */
2889 disas_logic_imm(s
, insn
);
2891 case 0x25: /* Move wide (immediate) */
2892 disas_movw_imm(s
, insn
);
2894 case 0x26: /* Bitfield */
2895 disas_bitfield(s
, insn
);
2897 case 0x27: /* Extract */
2898 disas_extract(s
, insn
);
2901 unallocated_encoding(s
);
2906 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
2907 * Note that it is the caller's responsibility to ensure that the
2908 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
2909 * mandated semantics for out of range shifts.
2911 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2912 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
2914 switch (shift_type
) {
2915 case A64_SHIFT_TYPE_LSL
:
2916 tcg_gen_shl_i64(dst
, src
, shift_amount
);
2918 case A64_SHIFT_TYPE_LSR
:
2919 tcg_gen_shr_i64(dst
, src
, shift_amount
);
2921 case A64_SHIFT_TYPE_ASR
:
2923 tcg_gen_ext32s_i64(dst
, src
);
2925 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
2927 case A64_SHIFT_TYPE_ROR
:
2929 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
2932 t0
= tcg_temp_new_i32();
2933 t1
= tcg_temp_new_i32();
2934 tcg_gen_trunc_i64_i32(t0
, src
);
2935 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
2936 tcg_gen_rotr_i32(t0
, t0
, t1
);
2937 tcg_gen_extu_i32_i64(dst
, t0
);
2938 tcg_temp_free_i32(t0
);
2939 tcg_temp_free_i32(t1
);
2943 assert(FALSE
); /* all shift types should be handled */
2947 if (!sf
) { /* zero extend final result */
2948 tcg_gen_ext32u_i64(dst
, dst
);
2952 /* Shift a TCGv src by immediate, put result in dst.
2953 * The shift amount must be in range (this should always be true as the
2954 * relevant instructions will UNDEF on bad shift immediates).
2956 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2957 enum a64_shift_type shift_type
, unsigned int shift_i
)
2959 assert(shift_i
< (sf
? 64 : 32));
2962 tcg_gen_mov_i64(dst
, src
);
2964 TCGv_i64 shift_const
;
2966 shift_const
= tcg_const_i64(shift_i
);
2967 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
2968 tcg_temp_free_i64(shift_const
);
2972 /* C3.5.10 Logical (shifted register)
2973 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2974 * +----+-----+-----------+-------+---+------+--------+------+------+
2975 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
2976 * +----+-----+-----------+-------+---+------+--------+------+------+
2978 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
2980 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
2981 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
2983 sf
= extract32(insn
, 31, 1);
2984 opc
= extract32(insn
, 29, 2);
2985 shift_type
= extract32(insn
, 22, 2);
2986 invert
= extract32(insn
, 21, 1);
2987 rm
= extract32(insn
, 16, 5);
2988 shift_amount
= extract32(insn
, 10, 6);
2989 rn
= extract32(insn
, 5, 5);
2990 rd
= extract32(insn
, 0, 5);
2992 if (!sf
&& (shift_amount
& (1 << 5))) {
2993 unallocated_encoding(s
);
2997 tcg_rd
= cpu_reg(s
, rd
);
2999 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3000 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3001 * register-register MOV and MVN, so it is worth special casing.
3003 tcg_rm
= cpu_reg(s
, rm
);
3005 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3007 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3011 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3013 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3019 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3022 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3025 tcg_rn
= cpu_reg(s
, rn
);
3027 switch (opc
| (invert
<< 2)) {
3030 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3033 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3036 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3040 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3043 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3046 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3054 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3058 gen_logic_CC(sf
, tcg_rd
);
3063 * C3.5.1 Add/subtract (extended register)
3065 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3066 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3067 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3068 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3070 * sf: 0 -> 32bit, 1 -> 64bit
3071 * op: 0 -> add , 1 -> sub
3074 * option: extension type (see DecodeRegExtend)
3075 * imm3: optional shift to Rm
3077 * Rd = Rn + LSL(extend(Rm), amount)
3079 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3081 int rd
= extract32(insn
, 0, 5);
3082 int rn
= extract32(insn
, 5, 5);
3083 int imm3
= extract32(insn
, 10, 3);
3084 int option
= extract32(insn
, 13, 3);
3085 int rm
= extract32(insn
, 16, 5);
3086 bool setflags
= extract32(insn
, 29, 1);
3087 bool sub_op
= extract32(insn
, 30, 1);
3088 bool sf
= extract32(insn
, 31, 1);
3090 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3092 TCGv_i64 tcg_result
;
3095 unallocated_encoding(s
);
3099 /* non-flag setting ops may use SP */
3101 tcg_rd
= cpu_reg_sp(s
, rd
);
3103 tcg_rd
= cpu_reg(s
, rd
);
3105 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3107 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3108 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3110 tcg_result
= tcg_temp_new_i64();
3114 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3116 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3120 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3122 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3127 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3129 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3132 tcg_temp_free_i64(tcg_result
);
3136 * C3.5.2 Add/subtract (shifted register)
3138 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3139 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3140 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3141 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3143 * sf: 0 -> 32bit, 1 -> 64bit
3144 * op: 0 -> add , 1 -> sub
3146 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3147 * imm6: Shift amount to apply to Rm before the add/sub
3149 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3151 int rd
= extract32(insn
, 0, 5);
3152 int rn
= extract32(insn
, 5, 5);
3153 int imm6
= extract32(insn
, 10, 6);
3154 int rm
= extract32(insn
, 16, 5);
3155 int shift_type
= extract32(insn
, 22, 2);
3156 bool setflags
= extract32(insn
, 29, 1);
3157 bool sub_op
= extract32(insn
, 30, 1);
3158 bool sf
= extract32(insn
, 31, 1);
3160 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3161 TCGv_i64 tcg_rn
, tcg_rm
;
3162 TCGv_i64 tcg_result
;
3164 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3165 unallocated_encoding(s
);
3169 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3170 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3172 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3174 tcg_result
= tcg_temp_new_i64();
3178 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3180 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3184 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3186 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3191 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3193 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3196 tcg_temp_free_i64(tcg_result
);
3199 /* C3.5.9 Data-processing (3 source)
3201 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3202 +--+------+-----------+------+------+----+------+------+------+
3203 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3204 +--+------+-----------+------+------+----+------+------+------+
3207 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3209 int rd
= extract32(insn
, 0, 5);
3210 int rn
= extract32(insn
, 5, 5);
3211 int ra
= extract32(insn
, 10, 5);
3212 int rm
= extract32(insn
, 16, 5);
3213 int op_id
= (extract32(insn
, 29, 3) << 4) |
3214 (extract32(insn
, 21, 3) << 1) |
3215 extract32(insn
, 15, 1);
3216 bool sf
= extract32(insn
, 31, 1);
3217 bool is_sub
= extract32(op_id
, 0, 1);
3218 bool is_high
= extract32(op_id
, 2, 1);
3219 bool is_signed
= false;
3224 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3226 case 0x42: /* SMADDL */
3227 case 0x43: /* SMSUBL */
3228 case 0x44: /* SMULH */
3231 case 0x0: /* MADD (32bit) */
3232 case 0x1: /* MSUB (32bit) */
3233 case 0x40: /* MADD (64bit) */
3234 case 0x41: /* MSUB (64bit) */
3235 case 0x4a: /* UMADDL */
3236 case 0x4b: /* UMSUBL */
3237 case 0x4c: /* UMULH */
3240 unallocated_encoding(s
);
3245 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3246 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3247 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3248 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3251 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3253 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3256 tcg_temp_free_i64(low_bits
);
3260 tcg_op1
= tcg_temp_new_i64();
3261 tcg_op2
= tcg_temp_new_i64();
3262 tcg_tmp
= tcg_temp_new_i64();
3265 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3266 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3269 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3270 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3272 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3273 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3277 if (ra
== 31 && !is_sub
) {
3278 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3279 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3281 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3283 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3285 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3290 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3293 tcg_temp_free_i64(tcg_op1
);
3294 tcg_temp_free_i64(tcg_op2
);
3295 tcg_temp_free_i64(tcg_tmp
);
3298 /* C3.5.3 - Add/subtract (with carry)
3299 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3300 * +--+--+--+------------------------+------+---------+------+-----+
3301 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3302 * +--+--+--+------------------------+------+---------+------+-----+
3306 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3308 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3309 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3311 if (extract32(insn
, 10, 6) != 0) {
3312 unallocated_encoding(s
);
3316 sf
= extract32(insn
, 31, 1);
3317 op
= extract32(insn
, 30, 1);
3318 setflags
= extract32(insn
, 29, 1);
3319 rm
= extract32(insn
, 16, 5);
3320 rn
= extract32(insn
, 5, 5);
3321 rd
= extract32(insn
, 0, 5);
3323 tcg_rd
= cpu_reg(s
, rd
);
3324 tcg_rn
= cpu_reg(s
, rn
);
3327 tcg_y
= new_tmp_a64(s
);
3328 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3330 tcg_y
= cpu_reg(s
, rm
);
3334 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3336 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3340 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3341 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3342 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3343 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3344 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3347 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3349 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3350 int label_continue
= -1;
3351 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3353 if (!extract32(insn
, 29, 1)) {
3354 unallocated_encoding(s
);
3357 if (insn
& (1 << 10 | 1 << 4)) {
3358 unallocated_encoding(s
);
3361 sf
= extract32(insn
, 31, 1);
3362 op
= extract32(insn
, 30, 1);
3363 is_imm
= extract32(insn
, 11, 1);
3364 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3365 cond
= extract32(insn
, 12, 4);
3366 rn
= extract32(insn
, 5, 5);
3367 nzcv
= extract32(insn
, 0, 4);
3369 if (cond
< 0x0e) { /* not always */
3370 int label_match
= gen_new_label();
3371 label_continue
= gen_new_label();
3372 arm_gen_test_cc(cond
, label_match
);
3374 tcg_tmp
= tcg_temp_new_i64();
3375 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
3376 gen_set_nzcv(tcg_tmp
);
3377 tcg_temp_free_i64(tcg_tmp
);
3378 tcg_gen_br(label_continue
);
3379 gen_set_label(label_match
);
3381 /* match, or condition is always */
3383 tcg_y
= new_tmp_a64(s
);
3384 tcg_gen_movi_i64(tcg_y
, y
);
3386 tcg_y
= cpu_reg(s
, y
);
3388 tcg_rn
= cpu_reg(s
, rn
);
3390 tcg_tmp
= tcg_temp_new_i64();
3392 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3394 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3396 tcg_temp_free_i64(tcg_tmp
);
3398 if (cond
< 0x0e) { /* continue */
3399 gen_set_label(label_continue
);
3403 /* C3.5.6 Conditional select
3404 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3405 * +----+----+---+-----------------+------+------+-----+------+------+
3406 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3407 * +----+----+---+-----------------+------+------+-----+------+------+
3409 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3411 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3412 TCGv_i64 tcg_rd
, tcg_src
;
3414 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3415 /* S == 1 or op2<1> == 1 */
3416 unallocated_encoding(s
);
3419 sf
= extract32(insn
, 31, 1);
3420 else_inv
= extract32(insn
, 30, 1);
3421 rm
= extract32(insn
, 16, 5);
3422 cond
= extract32(insn
, 12, 4);
3423 else_inc
= extract32(insn
, 10, 1);
3424 rn
= extract32(insn
, 5, 5);
3425 rd
= extract32(insn
, 0, 5);
3428 /* silly no-op write; until we use movcond we must special-case
3429 * this to avoid a dead temporary across basic blocks.
3434 tcg_rd
= cpu_reg(s
, rd
);
3436 if (cond
>= 0x0e) { /* condition "always" */
3437 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3438 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3440 /* OPTME: we could use movcond here, at the cost of duplicating
3441 * a lot of the arm_gen_test_cc() logic.
3443 int label_match
= gen_new_label();
3444 int label_continue
= gen_new_label();
3446 arm_gen_test_cc(cond
, label_match
);
3448 tcg_src
= cpu_reg(s
, rm
);
3450 if (else_inv
&& else_inc
) {
3451 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
3452 } else if (else_inv
) {
3453 tcg_gen_not_i64(tcg_rd
, tcg_src
);
3454 } else if (else_inc
) {
3455 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
3457 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3460 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3462 tcg_gen_br(label_continue
);
3464 gen_set_label(label_match
);
3465 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3466 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3468 gen_set_label(label_continue
);
3472 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3473 unsigned int rn
, unsigned int rd
)
3475 TCGv_i64 tcg_rd
, tcg_rn
;
3476 tcg_rd
= cpu_reg(s
, rd
);
3477 tcg_rn
= cpu_reg(s
, rn
);
3480 gen_helper_clz64(tcg_rd
, tcg_rn
);
3482 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3483 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3484 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3485 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3486 tcg_temp_free_i32(tcg_tmp32
);
3490 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3491 unsigned int rn
, unsigned int rd
)
3493 TCGv_i64 tcg_rd
, tcg_rn
;
3494 tcg_rd
= cpu_reg(s
, rd
);
3495 tcg_rn
= cpu_reg(s
, rn
);
3498 gen_helper_cls64(tcg_rd
, tcg_rn
);
3500 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3501 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3502 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3503 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3504 tcg_temp_free_i32(tcg_tmp32
);
3508 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3509 unsigned int rn
, unsigned int rd
)
3511 TCGv_i64 tcg_rd
, tcg_rn
;
3512 tcg_rd
= cpu_reg(s
, rd
);
3513 tcg_rn
= cpu_reg(s
, rn
);
3516 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3518 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3519 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3520 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3521 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3522 tcg_temp_free_i32(tcg_tmp32
);
3526 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3527 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3528 unsigned int rn
, unsigned int rd
)
3531 unallocated_encoding(s
);
3534 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3537 /* C5.6.149 REV with sf==0, opcode==2
3538 * C5.6.151 REV32 (sf==1, opcode==2)
3540 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3541 unsigned int rn
, unsigned int rd
)
3543 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3546 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3547 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3549 /* bswap32_i64 requires zero high word */
3550 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3551 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3552 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3553 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3554 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3556 tcg_temp_free_i64(tcg_tmp
);
3558 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3559 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3563 /* C5.6.150 REV16 (opcode==1) */
3564 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3565 unsigned int rn
, unsigned int rd
)
3567 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3568 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3569 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3571 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3572 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3574 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3575 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3576 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3577 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3580 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3581 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3582 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3583 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3585 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3586 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3587 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3590 tcg_temp_free_i64(tcg_tmp
);
3593 /* C3.5.7 Data-processing (1 source)
3594 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3595 * +----+---+---+-----------------+---------+--------+------+------+
3596 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3597 * +----+---+---+-----------------+---------+--------+------+------+
3599 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3601 unsigned int sf
, opcode
, rn
, rd
;
3603 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3604 unallocated_encoding(s
);
3608 sf
= extract32(insn
, 31, 1);
3609 opcode
= extract32(insn
, 10, 6);
3610 rn
= extract32(insn
, 5, 5);
3611 rd
= extract32(insn
, 0, 5);
3615 handle_rbit(s
, sf
, rn
, rd
);
3618 handle_rev16(s
, sf
, rn
, rd
);
3621 handle_rev32(s
, sf
, rn
, rd
);
3624 handle_rev64(s
, sf
, rn
, rd
);
3627 handle_clz(s
, sf
, rn
, rd
);
3630 handle_cls(s
, sf
, rn
, rd
);
3635 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3636 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3638 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3639 tcg_rd
= cpu_reg(s
, rd
);
3641 if (!sf
&& is_signed
) {
3642 tcg_n
= new_tmp_a64(s
);
3643 tcg_m
= new_tmp_a64(s
);
3644 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3645 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3647 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3648 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3652 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3654 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3657 if (!sf
) { /* zero extend final result */
3658 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3662 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3663 static void handle_shift_reg(DisasContext
*s
,
3664 enum a64_shift_type shift_type
, unsigned int sf
,
3665 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3667 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3668 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3669 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3671 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3672 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3673 tcg_temp_free_i64(tcg_shift
);
3676 /* C3.5.8 Data-processing (2 source)
3677 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3678 * +----+---+---+-----------------+------+--------+------+------+
3679 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3680 * +----+---+---+-----------------+------+--------+------+------+
3682 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3684 unsigned int sf
, rm
, opcode
, rn
, rd
;
3685 sf
= extract32(insn
, 31, 1);
3686 rm
= extract32(insn
, 16, 5);
3687 opcode
= extract32(insn
, 10, 6);
3688 rn
= extract32(insn
, 5, 5);
3689 rd
= extract32(insn
, 0, 5);
3691 if (extract32(insn
, 29, 1)) {
3692 unallocated_encoding(s
);
3698 handle_div(s
, false, sf
, rm
, rn
, rd
);
3701 handle_div(s
, true, sf
, rm
, rn
, rd
);
3704 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3707 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3710 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3713 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3722 case 23: /* CRC32 */
3723 unsupported_encoding(s
, insn
);
3726 unallocated_encoding(s
);
3731 /* C3.5 Data processing - register */
3732 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3734 switch (extract32(insn
, 24, 5)) {
3735 case 0x0a: /* Logical (shifted register) */
3736 disas_logic_reg(s
, insn
);
3738 case 0x0b: /* Add/subtract */
3739 if (insn
& (1 << 21)) { /* (extended register) */
3740 disas_add_sub_ext_reg(s
, insn
);
3742 disas_add_sub_reg(s
, insn
);
3745 case 0x1b: /* Data-processing (3 source) */
3746 disas_data_proc_3src(s
, insn
);
3749 switch (extract32(insn
, 21, 3)) {
3750 case 0x0: /* Add/subtract (with carry) */
3751 disas_adc_sbc(s
, insn
);
3753 case 0x2: /* Conditional compare */
3754 disas_cc(s
, insn
); /* both imm and reg forms */
3756 case 0x4: /* Conditional select */
3757 disas_cond_select(s
, insn
);
3759 case 0x6: /* Data-processing */
3760 if (insn
& (1 << 30)) { /* (1 source) */
3761 disas_data_proc_1src(s
, insn
);
3762 } else { /* (2 source) */
3763 disas_data_proc_2src(s
, insn
);
3767 unallocated_encoding(s
);
3772 unallocated_encoding(s
);
3777 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
3778 unsigned int rn
, unsigned int rm
,
3779 bool cmp_with_zero
, bool signal_all_nans
)
3781 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
3782 TCGv_ptr fpst
= get_fpstatus_ptr();
3785 TCGv_i64 tcg_vn
, tcg_vm
;
3787 tcg_vn
= read_fp_dreg(s
, rn
);
3788 if (cmp_with_zero
) {
3789 tcg_vm
= tcg_const_i64(0);
3791 tcg_vm
= read_fp_dreg(s
, rm
);
3793 if (signal_all_nans
) {
3794 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3796 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3798 tcg_temp_free_i64(tcg_vn
);
3799 tcg_temp_free_i64(tcg_vm
);
3801 TCGv_i32 tcg_vn
, tcg_vm
;
3803 tcg_vn
= read_fp_sreg(s
, rn
);
3804 if (cmp_with_zero
) {
3805 tcg_vm
= tcg_const_i32(0);
3807 tcg_vm
= read_fp_sreg(s
, rm
);
3809 if (signal_all_nans
) {
3810 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3812 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3814 tcg_temp_free_i32(tcg_vn
);
3815 tcg_temp_free_i32(tcg_vm
);
3818 tcg_temp_free_ptr(fpst
);
3820 gen_set_nzcv(tcg_flags
);
3822 tcg_temp_free_i64(tcg_flags
);
3825 /* C3.6.22 Floating point compare
3826 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
3827 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3828 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
3829 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3831 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
3833 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
3835 mos
= extract32(insn
, 29, 3);
3836 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3837 rm
= extract32(insn
, 16, 5);
3838 op
= extract32(insn
, 14, 2);
3839 rn
= extract32(insn
, 5, 5);
3840 opc
= extract32(insn
, 3, 2);
3841 op2r
= extract32(insn
, 0, 3);
3843 if (mos
|| op
|| op2r
|| type
> 1) {
3844 unallocated_encoding(s
);
3848 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
3851 /* C3.6.23 Floating point conditional compare
3852 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3853 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3854 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
3855 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3857 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
3859 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
3861 int label_continue
= -1;
3863 mos
= extract32(insn
, 29, 3);
3864 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3865 rm
= extract32(insn
, 16, 5);
3866 cond
= extract32(insn
, 12, 4);
3867 rn
= extract32(insn
, 5, 5);
3868 op
= extract32(insn
, 4, 1);
3869 nzcv
= extract32(insn
, 0, 4);
3871 if (mos
|| type
> 1) {
3872 unallocated_encoding(s
);
3876 if (cond
< 0x0e) { /* not always */
3877 int label_match
= gen_new_label();
3878 label_continue
= gen_new_label();
3879 arm_gen_test_cc(cond
, label_match
);
3881 tcg_flags
= tcg_const_i64(nzcv
<< 28);
3882 gen_set_nzcv(tcg_flags
);
3883 tcg_temp_free_i64(tcg_flags
);
3884 tcg_gen_br(label_continue
);
3885 gen_set_label(label_match
);
3888 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
3891 gen_set_label(label_continue
);
3895 /* copy src FP register to dst FP register; type specifies single or double */
3896 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
3899 TCGv_i64 v
= read_fp_dreg(s
, src
);
3900 write_fp_dreg(s
, dst
, v
);
3901 tcg_temp_free_i64(v
);
3903 TCGv_i32 v
= read_fp_sreg(s
, src
);
3904 write_fp_sreg(s
, dst
, v
);
3905 tcg_temp_free_i32(v
);
3909 /* C3.6.24 Floating point conditional select
3910 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
3911 * +---+---+---+-----------+------+---+------+------+-----+------+------+
3912 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
3913 * +---+---+---+-----------+------+---+------+------+-----+------+------+
3915 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
3917 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
3918 int label_continue
= -1;
3920 mos
= extract32(insn
, 29, 3);
3921 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3922 rm
= extract32(insn
, 16, 5);
3923 cond
= extract32(insn
, 12, 4);
3924 rn
= extract32(insn
, 5, 5);
3925 rd
= extract32(insn
, 0, 5);
3927 if (mos
|| type
> 1) {
3928 unallocated_encoding(s
);
3932 if (cond
< 0x0e) { /* not always */
3933 int label_match
= gen_new_label();
3934 label_continue
= gen_new_label();
3935 arm_gen_test_cc(cond
, label_match
);
3937 gen_mov_fp2fp(s
, type
, rd
, rm
);
3938 tcg_gen_br(label_continue
);
3939 gen_set_label(label_match
);
3942 gen_mov_fp2fp(s
, type
, rd
, rn
);
3944 if (cond
< 0x0e) { /* continue */
3945 gen_set_label(label_continue
);
3949 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
3950 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
3956 fpst
= get_fpstatus_ptr();
3957 tcg_op
= read_fp_sreg(s
, rn
);
3958 tcg_res
= tcg_temp_new_i32();
3961 case 0x0: /* FMOV */
3962 tcg_gen_mov_i32(tcg_res
, tcg_op
);
3964 case 0x1: /* FABS */
3965 gen_helper_vfp_abss(tcg_res
, tcg_op
);
3967 case 0x2: /* FNEG */
3968 gen_helper_vfp_negs(tcg_res
, tcg_op
);
3970 case 0x3: /* FSQRT */
3971 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
3973 case 0x8: /* FRINTN */
3974 case 0x9: /* FRINTP */
3975 case 0xa: /* FRINTM */
3976 case 0xb: /* FRINTZ */
3977 case 0xc: /* FRINTA */
3979 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
3981 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3982 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
3984 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3985 tcg_temp_free_i32(tcg_rmode
);
3988 case 0xe: /* FRINTX */
3989 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
3991 case 0xf: /* FRINTI */
3992 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
3998 write_fp_sreg(s
, rd
, tcg_res
);
4000 tcg_temp_free_ptr(fpst
);
4001 tcg_temp_free_i32(tcg_op
);
4002 tcg_temp_free_i32(tcg_res
);
4005 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4006 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4012 fpst
= get_fpstatus_ptr();
4013 tcg_op
= read_fp_dreg(s
, rn
);
4014 tcg_res
= tcg_temp_new_i64();
4017 case 0x0: /* FMOV */
4018 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4020 case 0x1: /* FABS */
4021 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4023 case 0x2: /* FNEG */
4024 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4026 case 0x3: /* FSQRT */
4027 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4029 case 0x8: /* FRINTN */
4030 case 0x9: /* FRINTP */
4031 case 0xa: /* FRINTM */
4032 case 0xb: /* FRINTZ */
4033 case 0xc: /* FRINTA */
4035 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4037 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4038 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4040 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4041 tcg_temp_free_i32(tcg_rmode
);
4044 case 0xe: /* FRINTX */
4045 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4047 case 0xf: /* FRINTI */
4048 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4054 write_fp_dreg(s
, rd
, tcg_res
);
4056 tcg_temp_free_ptr(fpst
);
4057 tcg_temp_free_i64(tcg_op
);
4058 tcg_temp_free_i64(tcg_res
);
4061 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4062 int rd
, int rn
, int dtype
, int ntype
)
4067 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4069 /* Single to double */
4070 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4071 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4072 write_fp_dreg(s
, rd
, tcg_rd
);
4073 tcg_temp_free_i64(tcg_rd
);
4075 /* Single to half */
4076 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4077 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4078 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4079 write_fp_sreg(s
, rd
, tcg_rd
);
4080 tcg_temp_free_i32(tcg_rd
);
4082 tcg_temp_free_i32(tcg_rn
);
4087 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4088 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4090 /* Double to single */
4091 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4093 /* Double to half */
4094 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4095 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4097 write_fp_sreg(s
, rd
, tcg_rd
);
4098 tcg_temp_free_i32(tcg_rd
);
4099 tcg_temp_free_i64(tcg_rn
);
4104 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4105 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4107 /* Half to single */
4108 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4109 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4110 write_fp_sreg(s
, rd
, tcg_rd
);
4111 tcg_temp_free_i32(tcg_rd
);
4113 /* Half to double */
4114 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4115 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4116 write_fp_dreg(s
, rd
, tcg_rd
);
4117 tcg_temp_free_i64(tcg_rd
);
4119 tcg_temp_free_i32(tcg_rn
);
4127 /* C3.6.25 Floating point data-processing (1 source)
4128 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4129 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4130 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4131 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4133 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4135 int type
= extract32(insn
, 22, 2);
4136 int opcode
= extract32(insn
, 15, 6);
4137 int rn
= extract32(insn
, 5, 5);
4138 int rd
= extract32(insn
, 0, 5);
4141 case 0x4: case 0x5: case 0x7:
4143 /* FCVT between half, single and double precision */
4144 int dtype
= extract32(opcode
, 0, 2);
4145 if (type
== 2 || dtype
== type
) {
4146 unallocated_encoding(s
);
4149 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4155 /* 32-to-32 and 64-to-64 ops */
4158 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4161 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4164 unallocated_encoding(s
);
4168 unallocated_encoding(s
);
4173 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4174 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4175 int rd
, int rn
, int rm
)
4182 tcg_res
= tcg_temp_new_i32();
4183 fpst
= get_fpstatus_ptr();
4184 tcg_op1
= read_fp_sreg(s
, rn
);
4185 tcg_op2
= read_fp_sreg(s
, rm
);
4188 case 0x0: /* FMUL */
4189 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4191 case 0x1: /* FDIV */
4192 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4194 case 0x2: /* FADD */
4195 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4197 case 0x3: /* FSUB */
4198 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4200 case 0x4: /* FMAX */
4201 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4203 case 0x5: /* FMIN */
4204 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4206 case 0x6: /* FMAXNM */
4207 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4209 case 0x7: /* FMINNM */
4210 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4212 case 0x8: /* FNMUL */
4213 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4214 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4218 write_fp_sreg(s
, rd
, tcg_res
);
4220 tcg_temp_free_ptr(fpst
);
4221 tcg_temp_free_i32(tcg_op1
);
4222 tcg_temp_free_i32(tcg_op2
);
4223 tcg_temp_free_i32(tcg_res
);
4226 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4227 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4228 int rd
, int rn
, int rm
)
4235 tcg_res
= tcg_temp_new_i64();
4236 fpst
= get_fpstatus_ptr();
4237 tcg_op1
= read_fp_dreg(s
, rn
);
4238 tcg_op2
= read_fp_dreg(s
, rm
);
4241 case 0x0: /* FMUL */
4242 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4244 case 0x1: /* FDIV */
4245 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4247 case 0x2: /* FADD */
4248 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4250 case 0x3: /* FSUB */
4251 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4253 case 0x4: /* FMAX */
4254 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4256 case 0x5: /* FMIN */
4257 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4259 case 0x6: /* FMAXNM */
4260 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4262 case 0x7: /* FMINNM */
4263 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4265 case 0x8: /* FNMUL */
4266 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4267 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4271 write_fp_dreg(s
, rd
, tcg_res
);
4273 tcg_temp_free_ptr(fpst
);
4274 tcg_temp_free_i64(tcg_op1
);
4275 tcg_temp_free_i64(tcg_op2
);
4276 tcg_temp_free_i64(tcg_res
);
4279 /* C3.6.26 Floating point data-processing (2 source)
4280 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4281 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4282 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4283 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4285 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4287 int type
= extract32(insn
, 22, 2);
4288 int rd
= extract32(insn
, 0, 5);
4289 int rn
= extract32(insn
, 5, 5);
4290 int rm
= extract32(insn
, 16, 5);
4291 int opcode
= extract32(insn
, 12, 4);
4294 unallocated_encoding(s
);
4300 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4303 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4306 unallocated_encoding(s
);
4310 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4311 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4312 int rd
, int rn
, int rm
, int ra
)
4314 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4315 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4316 TCGv_ptr fpst
= get_fpstatus_ptr();
4318 tcg_op1
= read_fp_sreg(s
, rn
);
4319 tcg_op2
= read_fp_sreg(s
, rm
);
4320 tcg_op3
= read_fp_sreg(s
, ra
);
4322 /* These are fused multiply-add, and must be done as one
4323 * floating point operation with no rounding between the
4324 * multiplication and addition steps.
4325 * NB that doing the negations here as separate steps is
4326 * correct : an input NaN should come out with its sign bit
4327 * flipped if it is a negated-input.
4330 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4334 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4337 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4339 write_fp_sreg(s
, rd
, tcg_res
);
4341 tcg_temp_free_ptr(fpst
);
4342 tcg_temp_free_i32(tcg_op1
);
4343 tcg_temp_free_i32(tcg_op2
);
4344 tcg_temp_free_i32(tcg_op3
);
4345 tcg_temp_free_i32(tcg_res
);
4348 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4349 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4350 int rd
, int rn
, int rm
, int ra
)
4352 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4353 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4354 TCGv_ptr fpst
= get_fpstatus_ptr();
4356 tcg_op1
= read_fp_dreg(s
, rn
);
4357 tcg_op2
= read_fp_dreg(s
, rm
);
4358 tcg_op3
= read_fp_dreg(s
, ra
);
4360 /* These are fused multiply-add, and must be done as one
4361 * floating point operation with no rounding between the
4362 * multiplication and addition steps.
4363 * NB that doing the negations here as separate steps is
4364 * correct : an input NaN should come out with its sign bit
4365 * flipped if it is a negated-input.
4368 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4372 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4375 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4377 write_fp_dreg(s
, rd
, tcg_res
);
4379 tcg_temp_free_ptr(fpst
);
4380 tcg_temp_free_i64(tcg_op1
);
4381 tcg_temp_free_i64(tcg_op2
);
4382 tcg_temp_free_i64(tcg_op3
);
4383 tcg_temp_free_i64(tcg_res
);
4386 /* C3.6.27 Floating point data-processing (3 source)
4387 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4388 * +---+---+---+-----------+------+----+------+----+------+------+------+
4389 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4390 * +---+---+---+-----------+------+----+------+----+------+------+------+
4392 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4394 int type
= extract32(insn
, 22, 2);
4395 int rd
= extract32(insn
, 0, 5);
4396 int rn
= extract32(insn
, 5, 5);
4397 int ra
= extract32(insn
, 10, 5);
4398 int rm
= extract32(insn
, 16, 5);
4399 bool o0
= extract32(insn
, 15, 1);
4400 bool o1
= extract32(insn
, 21, 1);
4404 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4407 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4410 unallocated_encoding(s
);
4414 /* C3.6.28 Floating point immediate
4415 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4416 * +---+---+---+-----------+------+---+------------+-------+------+------+
4417 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4418 * +---+---+---+-----------+------+---+------------+-------+------+------+
4420 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4422 int rd
= extract32(insn
, 0, 5);
4423 int imm8
= extract32(insn
, 13, 8);
4424 int is_double
= extract32(insn
, 22, 2);
4428 if (is_double
> 1) {
4429 unallocated_encoding(s
);
4433 /* The imm8 encodes the sign bit, enough bits to represent
4434 * an exponent in the range 01....1xx to 10....0xx,
4435 * and the most significant 4 bits of the mantissa; see
4436 * VFPExpandImm() in the v8 ARM ARM.
4439 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4440 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4441 extract32(imm8
, 0, 6);
4444 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4445 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4446 (extract32(imm8
, 0, 6) << 3);
4450 tcg_res
= tcg_const_i64(imm
);
4451 write_fp_dreg(s
, rd
, tcg_res
);
4452 tcg_temp_free_i64(tcg_res
);
4455 /* Handle floating point <=> fixed point conversions. Note that we can
4456 * also deal with fp <=> integer conversions as a special case (scale == 64)
4457 * OPTME: consider handling that special case specially or at least skipping
4458 * the call to scalbn in the helpers for zero shifts.
4460 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4461 bool itof
, int rmode
, int scale
, int sf
, int type
)
4463 bool is_signed
= !(opcode
& 1);
4464 bool is_double
= type
;
4465 TCGv_ptr tcg_fpstatus
;
4468 tcg_fpstatus
= get_fpstatus_ptr();
4470 tcg_shift
= tcg_const_i32(64 - scale
);
4473 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4475 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4478 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4480 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4483 tcg_int
= tcg_extend
;
4487 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4489 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4490 tcg_shift
, tcg_fpstatus
);
4492 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4493 tcg_shift
, tcg_fpstatus
);
4495 write_fp_dreg(s
, rd
, tcg_double
);
4496 tcg_temp_free_i64(tcg_double
);
4498 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4500 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4501 tcg_shift
, tcg_fpstatus
);
4503 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4504 tcg_shift
, tcg_fpstatus
);
4506 write_fp_sreg(s
, rd
, tcg_single
);
4507 tcg_temp_free_i32(tcg_single
);
4510 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4513 if (extract32(opcode
, 2, 1)) {
4514 /* There are too many rounding modes to all fit into rmode,
4515 * so FCVTA[US] is a special case.
4517 rmode
= FPROUNDING_TIEAWAY
;
4520 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4522 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4525 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4528 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4529 tcg_shift
, tcg_fpstatus
);
4531 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4532 tcg_shift
, tcg_fpstatus
);
4536 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4537 tcg_shift
, tcg_fpstatus
);
4539 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4540 tcg_shift
, tcg_fpstatus
);
4543 tcg_temp_free_i64(tcg_double
);
4545 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4548 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4549 tcg_shift
, tcg_fpstatus
);
4551 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4552 tcg_shift
, tcg_fpstatus
);
4555 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4557 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4558 tcg_shift
, tcg_fpstatus
);
4560 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4561 tcg_shift
, tcg_fpstatus
);
4563 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4564 tcg_temp_free_i32(tcg_dest
);
4566 tcg_temp_free_i32(tcg_single
);
4569 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4570 tcg_temp_free_i32(tcg_rmode
);
4573 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4577 tcg_temp_free_ptr(tcg_fpstatus
);
4578 tcg_temp_free_i32(tcg_shift
);
4581 /* C3.6.29 Floating point <-> fixed point conversions
4582 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4583 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4584 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4585 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4587 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4589 int rd
= extract32(insn
, 0, 5);
4590 int rn
= extract32(insn
, 5, 5);
4591 int scale
= extract32(insn
, 10, 6);
4592 int opcode
= extract32(insn
, 16, 3);
4593 int rmode
= extract32(insn
, 19, 2);
4594 int type
= extract32(insn
, 22, 2);
4595 bool sbit
= extract32(insn
, 29, 1);
4596 bool sf
= extract32(insn
, 31, 1);
4599 if (sbit
|| (type
> 1)
4600 || (!sf
&& scale
< 32)) {
4601 unallocated_encoding(s
);
4605 switch ((rmode
<< 3) | opcode
) {
4606 case 0x2: /* SCVTF */
4607 case 0x3: /* UCVTF */
4610 case 0x18: /* FCVTZS */
4611 case 0x19: /* FCVTZU */
4615 unallocated_encoding(s
);
4619 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
4622 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
4624 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4625 * without conversion.
4629 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4635 TCGv_i64 tmp
= tcg_temp_new_i64();
4636 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
4637 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(rd
, MO_64
));
4638 tcg_gen_movi_i64(tmp
, 0);
4639 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(rd
));
4640 tcg_temp_free_i64(tmp
);
4646 TCGv_i64 tmp
= tcg_const_i64(0);
4647 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(rd
, MO_64
));
4648 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(rd
));
4649 tcg_temp_free_i64(tmp
);
4653 /* 64 bit to top half. */
4654 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(rd
));
4658 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4663 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(rn
, MO_32
));
4667 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(rn
, MO_64
));
4670 /* 64 bits from top half */
4671 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(rn
));
4677 /* C3.6.30 Floating point <-> integer conversions
4678 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4679 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4680 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4681 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4683 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
4685 int rd
= extract32(insn
, 0, 5);
4686 int rn
= extract32(insn
, 5, 5);
4687 int opcode
= extract32(insn
, 16, 3);
4688 int rmode
= extract32(insn
, 19, 2);
4689 int type
= extract32(insn
, 22, 2);
4690 bool sbit
= extract32(insn
, 29, 1);
4691 bool sf
= extract32(insn
, 31, 1);
4694 unallocated_encoding(s
);
4700 bool itof
= opcode
& 1;
4703 unallocated_encoding(s
);
4707 switch (sf
<< 3 | type
<< 1 | rmode
) {
4708 case 0x0: /* 32 bit */
4709 case 0xa: /* 64 bit */
4710 case 0xd: /* 64 bit to top half of quad */
4713 /* all other sf/type/rmode combinations are invalid */
4714 unallocated_encoding(s
);
4718 handle_fmov(s
, rd
, rn
, type
, itof
);
4720 /* actual FP conversions */
4721 bool itof
= extract32(opcode
, 1, 1);
4723 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
4724 unallocated_encoding(s
);
4728 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
4732 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
4733 * 31 30 29 28 25 24 0
4734 * +---+---+---+---------+-----------------------------+
4735 * | | 0 | | 1 1 1 1 | |
4736 * +---+---+---+---------+-----------------------------+
4738 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
4740 if (extract32(insn
, 24, 1)) {
4741 /* Floating point data-processing (3 source) */
4742 disas_fp_3src(s
, insn
);
4743 } else if (extract32(insn
, 21, 1) == 0) {
4744 /* Floating point to fixed point conversions */
4745 disas_fp_fixed_conv(s
, insn
);
4747 switch (extract32(insn
, 10, 2)) {
4749 /* Floating point conditional compare */
4750 disas_fp_ccomp(s
, insn
);
4753 /* Floating point data-processing (2 source) */
4754 disas_fp_2src(s
, insn
);
4757 /* Floating point conditional select */
4758 disas_fp_csel(s
, insn
);
4761 switch (ctz32(extract32(insn
, 12, 4))) {
4762 case 0: /* [15:12] == xxx1 */
4763 /* Floating point immediate */
4764 disas_fp_imm(s
, insn
);
4766 case 1: /* [15:12] == xx10 */
4767 /* Floating point compare */
4768 disas_fp_compare(s
, insn
);
4770 case 2: /* [15:12] == x100 */
4771 /* Floating point data-processing (1 source) */
4772 disas_fp_1src(s
, insn
);
4774 case 3: /* [15:12] == 1000 */
4775 unallocated_encoding(s
);
4777 default: /* [15:12] == 0000 */
4778 /* Floating point <-> integer conversions */
4779 disas_fp_int_conv(s
, insn
);
4787 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
4790 /* Extract 64 bits from the middle of two concatenated 64 bit
4791 * vector register slices left:right. The extracted bits start
4792 * at 'pos' bits into the right (least significant) side.
4793 * We return the result in tcg_right, and guarantee not to
4796 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4797 assert(pos
> 0 && pos
< 64);
4799 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
4800 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
4801 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
4803 tcg_temp_free_i64(tcg_tmp
);
4807 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
4808 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4809 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
4810 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4812 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
4814 int is_q
= extract32(insn
, 30, 1);
4815 int op2
= extract32(insn
, 22, 2);
4816 int imm4
= extract32(insn
, 11, 4);
4817 int rm
= extract32(insn
, 16, 5);
4818 int rn
= extract32(insn
, 5, 5);
4819 int rd
= extract32(insn
, 0, 5);
4820 int pos
= imm4
<< 3;
4821 TCGv_i64 tcg_resl
, tcg_resh
;
4823 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
4824 unallocated_encoding(s
);
4828 tcg_resh
= tcg_temp_new_i64();
4829 tcg_resl
= tcg_temp_new_i64();
4831 /* Vd gets bits starting at pos bits into Vm:Vn. This is
4832 * either extracting 128 bits from a 128:128 concatenation, or
4833 * extracting 64 bits from a 64:64 concatenation.
4836 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
4838 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
4839 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
4841 tcg_gen_movi_i64(tcg_resh
, 0);
4848 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
4849 EltPosns
*elt
= eltposns
;
4856 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
4858 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
4861 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
4862 tcg_hh
= tcg_temp_new_i64();
4863 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
4864 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
4865 tcg_temp_free_i64(tcg_hh
);
4869 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
4870 tcg_temp_free_i64(tcg_resl
);
4871 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
4872 tcg_temp_free_i64(tcg_resh
);
4876 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
4877 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
4878 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
4879 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
4881 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
4883 int op2
= extract32(insn
, 22, 2);
4884 int is_q
= extract32(insn
, 30, 1);
4885 int rm
= extract32(insn
, 16, 5);
4886 int rn
= extract32(insn
, 5, 5);
4887 int rd
= extract32(insn
, 0, 5);
4888 int is_tblx
= extract32(insn
, 12, 1);
4889 int len
= extract32(insn
, 13, 2);
4890 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
4891 TCGv_i32 tcg_regno
, tcg_numregs
;
4894 unallocated_encoding(s
);
4898 /* This does a table lookup: for every byte element in the input
4899 * we index into a table formed from up to four vector registers,
4900 * and then the output is the result of the lookups. Our helper
4901 * function does the lookup operation for a single 64 bit part of
4904 tcg_resl
= tcg_temp_new_i64();
4905 tcg_resh
= tcg_temp_new_i64();
4908 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
4910 tcg_gen_movi_i64(tcg_resl
, 0);
4912 if (is_tblx
&& is_q
) {
4913 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
4915 tcg_gen_movi_i64(tcg_resh
, 0);
4918 tcg_idx
= tcg_temp_new_i64();
4919 tcg_regno
= tcg_const_i32(rn
);
4920 tcg_numregs
= tcg_const_i32(len
+ 1);
4921 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
4922 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
4923 tcg_regno
, tcg_numregs
);
4925 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
4926 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
4927 tcg_regno
, tcg_numregs
);
4929 tcg_temp_free_i64(tcg_idx
);
4930 tcg_temp_free_i32(tcg_regno
);
4931 tcg_temp_free_i32(tcg_numregs
);
4933 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
4934 tcg_temp_free_i64(tcg_resl
);
4935 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
4936 tcg_temp_free_i64(tcg_resh
);
4939 /* C3.6.3 ZIP/UZP/TRN
4940 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
4941 * +---+---+-------------+------+---+------+---+------------------+------+
4942 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
4943 * +---+---+-------------+------+---+------+---+------------------+------+
4945 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
4947 int rd
= extract32(insn
, 0, 5);
4948 int rn
= extract32(insn
, 5, 5);
4949 int rm
= extract32(insn
, 16, 5);
4950 int size
= extract32(insn
, 22, 2);
4951 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
4952 * bit 2 indicates 1 vs 2 variant of the insn.
4954 int opcode
= extract32(insn
, 12, 2);
4955 bool part
= extract32(insn
, 14, 1);
4956 bool is_q
= extract32(insn
, 30, 1);
4957 int esize
= 8 << size
;
4959 int datasize
= is_q
? 128 : 64;
4960 int elements
= datasize
/ esize
;
4961 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
4963 if (opcode
== 0 || (size
== 3 && !is_q
)) {
4964 unallocated_encoding(s
);
4968 tcg_resl
= tcg_const_i64(0);
4969 tcg_resh
= tcg_const_i64(0);
4970 tcg_res
= tcg_temp_new_i64();
4972 for (i
= 0; i
< elements
; i
++) {
4974 case 1: /* UZP1/2 */
4976 int midpoint
= elements
/ 2;
4978 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
4980 read_vec_element(s
, tcg_res
, rm
,
4981 2 * (i
- midpoint
) + part
, size
);
4985 case 2: /* TRN1/2 */
4987 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
4989 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
4992 case 3: /* ZIP1/2 */
4994 int base
= part
* elements
/ 2;
4996 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
4998 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5003 g_assert_not_reached();
5008 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5009 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5011 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5012 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5016 tcg_temp_free_i64(tcg_res
);
5018 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5019 tcg_temp_free_i64(tcg_resl
);
5020 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5021 tcg_temp_free_i64(tcg_resh
);
5024 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5025 int opc
, bool is_min
, TCGv_ptr fpst
)
5027 /* Helper function for disas_simd_across_lanes: do a single precision
5028 * min/max operation on the specified two inputs,
5029 * and return the result in tcg_elt1.
5033 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5035 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5040 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5042 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5047 /* C3.6.4 AdvSIMD across lanes
5048 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5049 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5050 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5051 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5053 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5055 int rd
= extract32(insn
, 0, 5);
5056 int rn
= extract32(insn
, 5, 5);
5057 int size
= extract32(insn
, 22, 2);
5058 int opcode
= extract32(insn
, 12, 5);
5059 bool is_q
= extract32(insn
, 30, 1);
5060 bool is_u
= extract32(insn
, 29, 1);
5062 bool is_min
= false;
5066 TCGv_i64 tcg_res
, tcg_elt
;
5069 case 0x1b: /* ADDV */
5071 unallocated_encoding(s
);
5075 case 0x3: /* SADDLV, UADDLV */
5076 case 0xa: /* SMAXV, UMAXV */
5077 case 0x1a: /* SMINV, UMINV */
5078 if (size
== 3 || (size
== 2 && !is_q
)) {
5079 unallocated_encoding(s
);
5083 case 0xc: /* FMAXNMV, FMINNMV */
5084 case 0xf: /* FMAXV, FMINV */
5085 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5086 unallocated_encoding(s
);
5089 /* Bit 1 of size field encodes min vs max, and actual size is always
5090 * 32 bits: adjust the size variable so following code can rely on it
5092 is_min
= extract32(size
, 1, 1);
5097 unallocated_encoding(s
);
5102 elements
= (is_q
? 128 : 64) / esize
;
5104 tcg_res
= tcg_temp_new_i64();
5105 tcg_elt
= tcg_temp_new_i64();
5107 /* These instructions operate across all lanes of a vector
5108 * to produce a single result. We can guarantee that a 64
5109 * bit intermediate is sufficient:
5110 * + for [US]ADDLV the maximum element size is 32 bits, and
5111 * the result type is 64 bits
5112 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5113 * same as the element size, which is 32 bits at most
5114 * For the integer operations we can choose to work at 64
5115 * or 32 bits and truncate at the end; for simplicity
5116 * we use 64 bits always. The floating point
5117 * ops do require 32 bit intermediates, though.
5120 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5122 for (i
= 1; i
< elements
; i
++) {
5123 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5126 case 0x03: /* SADDLV / UADDLV */
5127 case 0x1b: /* ADDV */
5128 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5130 case 0x0a: /* SMAXV / UMAXV */
5131 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5133 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5135 case 0x1a: /* SMINV / UMINV */
5136 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5138 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5142 g_assert_not_reached();
5147 /* Floating point ops which work on 32 bit (single) intermediates.
5148 * Note that correct NaN propagation requires that we do these
5149 * operations in exactly the order specified by the pseudocode.
5151 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5152 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5153 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5154 TCGv_ptr fpst
= get_fpstatus_ptr();
5156 assert(esize
== 32);
5157 assert(elements
== 4);
5159 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5160 tcg_gen_trunc_i64_i32(tcg_elt1
, tcg_elt
);
5161 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5162 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5164 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5166 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5167 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5168 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5169 tcg_gen_trunc_i64_i32(tcg_elt3
, tcg_elt
);
5171 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5173 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5175 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5176 tcg_temp_free_i32(tcg_elt1
);
5177 tcg_temp_free_i32(tcg_elt2
);
5178 tcg_temp_free_i32(tcg_elt3
);
5179 tcg_temp_free_ptr(fpst
);
5182 tcg_temp_free_i64(tcg_elt
);
5184 /* Now truncate the result to the width required for the final output */
5185 if (opcode
== 0x03) {
5186 /* SADDLV, UADDLV: result is 2*esize */
5192 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5195 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5198 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5203 g_assert_not_reached();
5206 write_fp_dreg(s
, rd
, tcg_res
);
5207 tcg_temp_free_i64(tcg_res
);
5210 /* C6.3.31 DUP (Element, Vector)
5212 * 31 30 29 21 20 16 15 10 9 5 4 0
5213 * +---+---+-------------------+--------+-------------+------+------+
5214 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5215 * +---+---+-------------------+--------+-------------+------+------+
5217 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5219 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5222 int size
= ctz32(imm5
);
5223 int esize
= 8 << size
;
5224 int elements
= (is_q
? 128 : 64) / esize
;
5228 if (size
> 3 || (size
== 3 && !is_q
)) {
5229 unallocated_encoding(s
);
5233 index
= imm5
>> (size
+ 1);
5235 tmp
= tcg_temp_new_i64();
5236 read_vec_element(s
, tmp
, rn
, index
, size
);
5238 for (i
= 0; i
< elements
; i
++) {
5239 write_vec_element(s
, tmp
, rd
, i
, size
);
5243 clear_vec_high(s
, rd
);
5246 tcg_temp_free_i64(tmp
);
5249 /* C6.3.31 DUP (element, scalar)
5250 * 31 21 20 16 15 10 9 5 4 0
5251 * +-----------------------+--------+-------------+------+------+
5252 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5253 * +-----------------------+--------+-------------+------+------+
5255 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5258 int size
= ctz32(imm5
);
5263 unallocated_encoding(s
);
5267 index
= imm5
>> (size
+ 1);
5269 /* This instruction just extracts the specified element and
5270 * zero-extends it into the bottom of the destination register.
5272 tmp
= tcg_temp_new_i64();
5273 read_vec_element(s
, tmp
, rn
, index
, size
);
5274 write_fp_dreg(s
, rd
, tmp
);
5275 tcg_temp_free_i64(tmp
);
5278 /* C6.3.32 DUP (General)
5280 * 31 30 29 21 20 16 15 10 9 5 4 0
5281 * +---+---+-------------------+--------+-------------+------+------+
5282 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5283 * +---+---+-------------------+--------+-------------+------+------+
5285 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5287 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5290 int size
= ctz32(imm5
);
5291 int esize
= 8 << size
;
5292 int elements
= (is_q
? 128 : 64)/esize
;
5295 if (size
> 3 || ((size
== 3) && !is_q
)) {
5296 unallocated_encoding(s
);
5299 for (i
= 0; i
< elements
; i
++) {
5300 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5303 clear_vec_high(s
, rd
);
5307 /* C6.3.150 INS (Element)
5309 * 31 21 20 16 15 14 11 10 9 5 4 0
5310 * +-----------------------+--------+------------+---+------+------+
5311 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5312 * +-----------------------+--------+------------+---+------+------+
5314 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5315 * index: encoded in imm5<4:size+1>
5317 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5320 int size
= ctz32(imm5
);
5321 int src_index
, dst_index
;
5325 unallocated_encoding(s
);
5328 dst_index
= extract32(imm5
, 1+size
, 5);
5329 src_index
= extract32(imm4
, size
, 4);
5331 tmp
= tcg_temp_new_i64();
5333 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5334 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5336 tcg_temp_free_i64(tmp
);
5340 /* C6.3.151 INS (General)
5342 * 31 21 20 16 15 10 9 5 4 0
5343 * +-----------------------+--------+-------------+------+------+
5344 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5345 * +-----------------------+--------+-------------+------+------+
5347 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5348 * index: encoded in imm5<4:size+1>
5350 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5352 int size
= ctz32(imm5
);
5356 unallocated_encoding(s
);
5360 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5361 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5365 * C6.3.321 UMOV (General)
5366 * C6.3.237 SMOV (General)
5368 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5369 * +---+---+-------------------+--------+-------------+------+------+
5370 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5371 * +---+---+-------------------+--------+-------------+------+------+
5373 * U: unsigned when set
5374 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5376 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5377 int rn
, int rd
, int imm5
)
5379 int size
= ctz32(imm5
);
5383 /* Check for UnallocatedEncodings */
5385 if (size
> 2 || (size
== 2 && !is_q
)) {
5386 unallocated_encoding(s
);
5391 || (size
< 3 && is_q
)
5392 || (size
== 3 && !is_q
)) {
5393 unallocated_encoding(s
);
5397 element
= extract32(imm5
, 1+size
, 4);
5399 tcg_rd
= cpu_reg(s
, rd
);
5400 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5401 if (is_signed
&& !is_q
) {
5402 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5406 /* C3.6.5 AdvSIMD copy
5407 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5408 * +---+---+----+-----------------+------+---+------+---+------+------+
5409 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5410 * +---+---+----+-----------------+------+---+------+---+------+------+
5412 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5414 int rd
= extract32(insn
, 0, 5);
5415 int rn
= extract32(insn
, 5, 5);
5416 int imm4
= extract32(insn
, 11, 4);
5417 int op
= extract32(insn
, 29, 1);
5418 int is_q
= extract32(insn
, 30, 1);
5419 int imm5
= extract32(insn
, 16, 5);
5424 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5426 unallocated_encoding(s
);
5431 /* DUP (element - vector) */
5432 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5436 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5441 handle_simd_insg(s
, rd
, rn
, imm5
);
5443 unallocated_encoding(s
);
5448 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5449 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5452 unallocated_encoding(s
);
5458 /* C3.6.6 AdvSIMD modified immediate
5459 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5460 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5461 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5462 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5464 * There are a number of operations that can be carried out here:
5465 * MOVI - move (shifted) imm into register
5466 * MVNI - move inverted (shifted) imm into register
5467 * ORR - bitwise OR of (shifted) imm with register
5468 * BIC - bitwise clear of (shifted) imm with register
5470 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5472 int rd
= extract32(insn
, 0, 5);
5473 int cmode
= extract32(insn
, 12, 4);
5474 int cmode_3_1
= extract32(cmode
, 1, 3);
5475 int cmode_0
= extract32(cmode
, 0, 1);
5476 int o2
= extract32(insn
, 11, 1);
5477 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5478 bool is_neg
= extract32(insn
, 29, 1);
5479 bool is_q
= extract32(insn
, 30, 1);
5481 TCGv_i64 tcg_rd
, tcg_imm
;
5484 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5485 unallocated_encoding(s
);
5489 /* See AdvSIMDExpandImm() in ARM ARM */
5490 switch (cmode_3_1
) {
5491 case 0: /* Replicate(Zeros(24):imm8, 2) */
5492 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5493 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5494 case 3: /* Replicate(imm8:Zeros(24), 2) */
5496 int shift
= cmode_3_1
* 8;
5497 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5500 case 4: /* Replicate(Zeros(8):imm8, 4) */
5501 case 5: /* Replicate(imm8:Zeros(8), 4) */
5503 int shift
= (cmode_3_1
& 0x1) * 8;
5504 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5509 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5510 imm
= (abcdefgh
<< 16) | 0xffff;
5512 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5513 imm
= (abcdefgh
<< 8) | 0xff;
5515 imm
= bitfield_replicate(imm
, 32);
5518 if (!cmode_0
&& !is_neg
) {
5519 imm
= bitfield_replicate(abcdefgh
, 8);
5520 } else if (!cmode_0
&& is_neg
) {
5523 for (i
= 0; i
< 8; i
++) {
5524 if ((abcdefgh
) & (1 << i
)) {
5525 imm
|= 0xffULL
<< (i
* 8);
5528 } else if (cmode_0
) {
5530 imm
= (abcdefgh
& 0x3f) << 48;
5531 if (abcdefgh
& 0x80) {
5532 imm
|= 0x8000000000000000ULL
;
5534 if (abcdefgh
& 0x40) {
5535 imm
|= 0x3fc0000000000000ULL
;
5537 imm
|= 0x4000000000000000ULL
;
5540 imm
= (abcdefgh
& 0x3f) << 19;
5541 if (abcdefgh
& 0x80) {
5544 if (abcdefgh
& 0x40) {
5555 if (cmode_3_1
!= 7 && is_neg
) {
5559 tcg_imm
= tcg_const_i64(imm
);
5560 tcg_rd
= new_tmp_a64(s
);
5562 for (i
= 0; i
< 2; i
++) {
5563 int foffs
= i
? fp_reg_hi_offset(rd
) : fp_reg_offset(rd
, MO_64
);
5565 if (i
== 1 && !is_q
) {
5566 /* non-quad ops clear high half of vector */
5567 tcg_gen_movi_i64(tcg_rd
, 0);
5568 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
5569 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
5572 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5575 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5579 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
5581 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
5584 tcg_temp_free_i64(tcg_imm
);
5587 /* C3.6.7 AdvSIMD scalar copy
5588 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5589 * +-----+----+-----------------+------+---+------+---+------+------+
5590 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5591 * +-----+----+-----------------+------+---+------+---+------+------+
5593 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
5595 int rd
= extract32(insn
, 0, 5);
5596 int rn
= extract32(insn
, 5, 5);
5597 int imm4
= extract32(insn
, 11, 4);
5598 int imm5
= extract32(insn
, 16, 5);
5599 int op
= extract32(insn
, 29, 1);
5601 if (op
!= 0 || imm4
!= 0) {
5602 unallocated_encoding(s
);
5606 /* DUP (element, scalar) */
5607 handle_simd_dupes(s
, rd
, rn
, imm5
);
5610 /* C3.6.8 AdvSIMD scalar pairwise
5611 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5612 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5613 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5614 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5616 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
5618 int u
= extract32(insn
, 29, 1);
5619 int size
= extract32(insn
, 22, 2);
5620 int opcode
= extract32(insn
, 12, 5);
5621 int rn
= extract32(insn
, 5, 5);
5622 int rd
= extract32(insn
, 0, 5);
5625 /* For some ops (the FP ones), size[1] is part of the encoding.
5626 * For ADDP strictly it is not but size[1] is always 1 for valid
5629 opcode
|= (extract32(size
, 1, 1) << 5);
5632 case 0x3b: /* ADDP */
5633 if (u
|| size
!= 3) {
5634 unallocated_encoding(s
);
5637 TCGV_UNUSED_PTR(fpst
);
5639 case 0xc: /* FMAXNMP */
5640 case 0xd: /* FADDP */
5641 case 0xf: /* FMAXP */
5642 case 0x2c: /* FMINNMP */
5643 case 0x2f: /* FMINP */
5644 /* FP op, size[0] is 32 or 64 bit */
5646 unallocated_encoding(s
);
5649 size
= extract32(size
, 0, 1) ? 3 : 2;
5650 fpst
= get_fpstatus_ptr();
5653 unallocated_encoding(s
);
5658 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
5659 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
5660 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5662 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
5663 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
5666 case 0x3b: /* ADDP */
5667 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
5669 case 0xc: /* FMAXNMP */
5670 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5672 case 0xd: /* FADDP */
5673 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5675 case 0xf: /* FMAXP */
5676 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5678 case 0x2c: /* FMINNMP */
5679 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5681 case 0x2f: /* FMINP */
5682 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5685 g_assert_not_reached();
5688 write_fp_dreg(s
, rd
, tcg_res
);
5690 tcg_temp_free_i64(tcg_op1
);
5691 tcg_temp_free_i64(tcg_op2
);
5692 tcg_temp_free_i64(tcg_res
);
5694 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
5695 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
5696 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5698 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
5699 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
5702 case 0xc: /* FMAXNMP */
5703 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5705 case 0xd: /* FADDP */
5706 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5708 case 0xf: /* FMAXP */
5709 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5711 case 0x2c: /* FMINNMP */
5712 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5714 case 0x2f: /* FMINP */
5715 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5718 g_assert_not_reached();
5721 write_fp_sreg(s
, rd
, tcg_res
);
5723 tcg_temp_free_i32(tcg_op1
);
5724 tcg_temp_free_i32(tcg_op2
);
5725 tcg_temp_free_i32(tcg_res
);
5728 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
5729 tcg_temp_free_ptr(fpst
);
5734 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
5736 * This code is handles the common shifting code and is used by both
5737 * the vector and scalar code.
5739 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5740 TCGv_i64 tcg_rnd
, bool accumulate
,
5741 bool is_u
, int size
, int shift
)
5743 bool extended_result
= false;
5744 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
5746 TCGv_i64 tcg_src_hi
;
5748 if (round
&& size
== 3) {
5749 extended_result
= true;
5750 ext_lshift
= 64 - shift
;
5751 tcg_src_hi
= tcg_temp_new_i64();
5752 } else if (shift
== 64) {
5753 if (!accumulate
&& is_u
) {
5754 /* result is zero */
5755 tcg_gen_movi_i64(tcg_res
, 0);
5760 /* Deal with the rounding step */
5762 if (extended_result
) {
5763 TCGv_i64 tcg_zero
= tcg_const_i64(0);
5765 /* take care of sign extending tcg_res */
5766 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
5767 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5768 tcg_src
, tcg_src_hi
,
5771 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5775 tcg_temp_free_i64(tcg_zero
);
5777 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
5781 /* Now do the shift right */
5782 if (round
&& extended_result
) {
5783 /* extended case, >64 bit precision required */
5784 if (ext_lshift
== 0) {
5785 /* special case, only high bits matter */
5786 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
5788 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5789 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
5790 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
5795 /* essentially shifting in 64 zeros */
5796 tcg_gen_movi_i64(tcg_src
, 0);
5798 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5802 /* effectively extending the sign-bit */
5803 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
5805 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
5811 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
5813 tcg_gen_mov_i64(tcg_res
, tcg_src
);
5816 if (extended_result
) {
5817 tcg_temp_free_i64(tcg_src_hi
);
5821 /* Common SHL/SLI - Shift left with an optional insert */
5822 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5823 bool insert
, int shift
)
5825 if (insert
) { /* SLI */
5826 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
5828 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
5832 /* SRI: shift right with insert */
5833 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5834 int size
, int shift
)
5836 int esize
= 8 << size
;
5838 /* shift count same as element size is valid but does nothing;
5839 * special case to avoid potential shift by 64.
5841 if (shift
!= esize
) {
5842 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5843 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
5847 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
5848 static void handle_scalar_simd_shri(DisasContext
*s
,
5849 bool is_u
, int immh
, int immb
,
5850 int opcode
, int rn
, int rd
)
5853 int immhb
= immh
<< 3 | immb
;
5854 int shift
= 2 * (8 << size
) - immhb
;
5855 bool accumulate
= false;
5857 bool insert
= false;
5862 if (!extract32(immh
, 3, 1)) {
5863 unallocated_encoding(s
);
5868 case 0x02: /* SSRA / USRA (accumulate) */
5871 case 0x04: /* SRSHR / URSHR (rounding) */
5874 case 0x06: /* SRSRA / URSRA (accum + rounding) */
5875 accumulate
= round
= true;
5877 case 0x08: /* SRI */
5883 uint64_t round_const
= 1ULL << (shift
- 1);
5884 tcg_round
= tcg_const_i64(round_const
);
5886 TCGV_UNUSED_I64(tcg_round
);
5889 tcg_rn
= read_fp_dreg(s
, rn
);
5890 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
5893 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
5895 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
5896 accumulate
, is_u
, size
, shift
);
5899 write_fp_dreg(s
, rd
, tcg_rd
);
5901 tcg_temp_free_i64(tcg_rn
);
5902 tcg_temp_free_i64(tcg_rd
);
5904 tcg_temp_free_i64(tcg_round
);
5908 /* SHL/SLI - Scalar shift left */
5909 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
5910 int immh
, int immb
, int opcode
,
5913 int size
= 32 - clz32(immh
) - 1;
5914 int immhb
= immh
<< 3 | immb
;
5915 int shift
= immhb
- (8 << size
);
5916 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
5917 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
5919 if (!extract32(immh
, 3, 1)) {
5920 unallocated_encoding(s
);
5924 tcg_rn
= read_fp_dreg(s
, rn
);
5925 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
5927 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
5929 write_fp_dreg(s
, rd
, tcg_rd
);
5931 tcg_temp_free_i64(tcg_rn
);
5932 tcg_temp_free_i64(tcg_rd
);
5935 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
5936 * (signed/unsigned) narrowing */
5937 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
5938 bool is_u_shift
, bool is_u_narrow
,
5939 int immh
, int immb
, int opcode
,
5942 int immhb
= immh
<< 3 | immb
;
5943 int size
= 32 - clz32(immh
) - 1;
5944 int esize
= 8 << size
;
5945 int shift
= (2 * esize
) - immhb
;
5946 int elements
= is_scalar
? 1 : (64 / esize
);
5947 bool round
= extract32(opcode
, 0, 1);
5948 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
5949 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
5950 TCGv_i32 tcg_rd_narrowed
;
5953 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
5954 { gen_helper_neon_narrow_sat_s8
,
5955 gen_helper_neon_unarrow_sat8
},
5956 { gen_helper_neon_narrow_sat_s16
,
5957 gen_helper_neon_unarrow_sat16
},
5958 { gen_helper_neon_narrow_sat_s32
,
5959 gen_helper_neon_unarrow_sat32
},
5962 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
5963 gen_helper_neon_narrow_sat_u8
,
5964 gen_helper_neon_narrow_sat_u16
,
5965 gen_helper_neon_narrow_sat_u32
,
5968 NeonGenNarrowEnvFn
*narrowfn
;
5974 if (extract32(immh
, 3, 1)) {
5975 unallocated_encoding(s
);
5980 narrowfn
= unsigned_narrow_fns
[size
];
5982 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
5985 tcg_rn
= tcg_temp_new_i64();
5986 tcg_rd
= tcg_temp_new_i64();
5987 tcg_rd_narrowed
= tcg_temp_new_i32();
5988 tcg_final
= tcg_const_i64(0);
5991 uint64_t round_const
= 1ULL << (shift
- 1);
5992 tcg_round
= tcg_const_i64(round_const
);
5994 TCGV_UNUSED_I64(tcg_round
);
5997 for (i
= 0; i
< elements
; i
++) {
5998 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
5999 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6000 false, is_u_shift
, size
+1, shift
);
6001 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6002 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6003 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6007 clear_vec_high(s
, rd
);
6008 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6010 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6014 tcg_temp_free_i64(tcg_round
);
6016 tcg_temp_free_i64(tcg_rn
);
6017 tcg_temp_free_i64(tcg_rd
);
6018 tcg_temp_free_i32(tcg_rd_narrowed
);
6019 tcg_temp_free_i64(tcg_final
);
6023 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6024 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6025 bool src_unsigned
, bool dst_unsigned
,
6026 int immh
, int immb
, int rn
, int rd
)
6028 int immhb
= immh
<< 3 | immb
;
6029 int size
= 32 - clz32(immh
) - 1;
6030 int shift
= immhb
- (8 << size
);
6034 assert(!(scalar
&& is_q
));
6037 if (!is_q
&& extract32(immh
, 3, 1)) {
6038 unallocated_encoding(s
);
6042 /* Since we use the variable-shift helpers we must
6043 * replicate the shift count into each element of
6044 * the tcg_shift value.
6048 shift
|= shift
<< 8;
6051 shift
|= shift
<< 16;
6057 g_assert_not_reached();
6062 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6063 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6064 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6065 { NULL
, gen_helper_neon_qshl_u64
},
6067 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6068 int maxpass
= is_q
? 2 : 1;
6070 for (pass
= 0; pass
< maxpass
; pass
++) {
6071 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6073 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6074 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6075 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6077 tcg_temp_free_i64(tcg_op
);
6079 tcg_temp_free_i64(tcg_shift
);
6082 clear_vec_high(s
, rd
);
6085 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6086 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6088 { gen_helper_neon_qshl_s8
,
6089 gen_helper_neon_qshl_s16
,
6090 gen_helper_neon_qshl_s32
},
6091 { gen_helper_neon_qshlu_s8
,
6092 gen_helper_neon_qshlu_s16
,
6093 gen_helper_neon_qshlu_s32
}
6095 { NULL
, NULL
, NULL
},
6096 { gen_helper_neon_qshl_u8
,
6097 gen_helper_neon_qshl_u16
,
6098 gen_helper_neon_qshl_u32
}
6101 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6102 TCGMemOp memop
= scalar
? size
: MO_32
;
6103 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6105 for (pass
= 0; pass
< maxpass
; pass
++) {
6106 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6108 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6109 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6113 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6116 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6121 g_assert_not_reached();
6123 write_fp_sreg(s
, rd
, tcg_op
);
6125 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6128 tcg_temp_free_i32(tcg_op
);
6130 tcg_temp_free_i32(tcg_shift
);
6132 if (!is_q
&& !scalar
) {
6133 clear_vec_high(s
, rd
);
6138 /* Common vector code for handling integer to FP conversion */
6139 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6140 int elements
, int is_signed
,
6141 int fracbits
, int size
)
6143 bool is_double
= size
== 3 ? true : false;
6144 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6145 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6146 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6147 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6150 for (pass
= 0; pass
< elements
; pass
++) {
6151 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6154 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6156 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6157 tcg_shift
, tcg_fpst
);
6159 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6160 tcg_shift
, tcg_fpst
);
6162 if (elements
== 1) {
6163 write_fp_dreg(s
, rd
, tcg_double
);
6165 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6167 tcg_temp_free_i64(tcg_double
);
6169 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6171 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6172 tcg_shift
, tcg_fpst
);
6174 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6175 tcg_shift
, tcg_fpst
);
6177 if (elements
== 1) {
6178 write_fp_sreg(s
, rd
, tcg_single
);
6180 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6182 tcg_temp_free_i32(tcg_single
);
6186 if (!is_double
&& elements
== 2) {
6187 clear_vec_high(s
, rd
);
6190 tcg_temp_free_i64(tcg_int
);
6191 tcg_temp_free_ptr(tcg_fpst
);
6192 tcg_temp_free_i32(tcg_shift
);
6195 /* UCVTF/SCVTF - Integer to FP conversion */
6196 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6197 bool is_q
, bool is_u
,
6198 int immh
, int immb
, int opcode
,
6201 bool is_double
= extract32(immh
, 3, 1);
6202 int size
= is_double
? MO_64
: MO_32
;
6204 int immhb
= immh
<< 3 | immb
;
6205 int fracbits
= (is_double
? 128 : 64) - immhb
;
6207 if (!extract32(immh
, 2, 2)) {
6208 unallocated_encoding(s
);
6215 elements
= is_double
? 2 : is_q
? 4 : 2;
6216 if (is_double
&& !is_q
) {
6217 unallocated_encoding(s
);
6221 /* immh == 0 would be a failure of the decode logic */
6224 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6227 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6228 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6229 bool is_q
, bool is_u
,
6230 int immh
, int immb
, int rn
, int rd
)
6232 bool is_double
= extract32(immh
, 3, 1);
6233 int immhb
= immh
<< 3 | immb
;
6234 int fracbits
= (is_double
? 128 : 64) - immhb
;
6236 TCGv_ptr tcg_fpstatus
;
6237 TCGv_i32 tcg_rmode
, tcg_shift
;
6239 if (!extract32(immh
, 2, 2)) {
6240 unallocated_encoding(s
);
6244 if (!is_scalar
&& !is_q
&& is_double
) {
6245 unallocated_encoding(s
);
6249 assert(!(is_scalar
&& is_q
));
6251 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6252 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6253 tcg_fpstatus
= get_fpstatus_ptr();
6254 tcg_shift
= tcg_const_i32(fracbits
);
6257 int maxpass
= is_scalar
? 1 : is_q
? 2 : 1;
6259 for (pass
= 0; pass
< maxpass
; pass
++) {
6260 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6262 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6264 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6266 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6268 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6269 tcg_temp_free_i64(tcg_op
);
6272 clear_vec_high(s
, rd
);
6275 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6276 for (pass
= 0; pass
< maxpass
; pass
++) {
6277 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6279 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6281 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6283 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6286 write_fp_sreg(s
, rd
, tcg_op
);
6288 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6290 tcg_temp_free_i32(tcg_op
);
6292 if (!is_q
&& !is_scalar
) {
6293 clear_vec_high(s
, rd
);
6297 tcg_temp_free_ptr(tcg_fpstatus
);
6298 tcg_temp_free_i32(tcg_shift
);
6299 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6300 tcg_temp_free_i32(tcg_rmode
);
6303 /* C3.6.9 AdvSIMD scalar shift by immediate
6304 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6305 * +-----+---+-------------+------+------+--------+---+------+------+
6306 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6307 * +-----+---+-------------+------+------+--------+---+------+------+
6309 * This is the scalar version so it works on a fixed sized registers
6311 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6313 int rd
= extract32(insn
, 0, 5);
6314 int rn
= extract32(insn
, 5, 5);
6315 int opcode
= extract32(insn
, 11, 5);
6316 int immb
= extract32(insn
, 16, 3);
6317 int immh
= extract32(insn
, 19, 4);
6318 bool is_u
= extract32(insn
, 29, 1);
6321 unallocated_encoding(s
);
6326 case 0x08: /* SRI */
6328 unallocated_encoding(s
);
6332 case 0x00: /* SSHR / USHR */
6333 case 0x02: /* SSRA / USRA */
6334 case 0x04: /* SRSHR / URSHR */
6335 case 0x06: /* SRSRA / URSRA */
6336 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6338 case 0x0a: /* SHL / SLI */
6339 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6341 case 0x1c: /* SCVTF, UCVTF */
6342 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6345 case 0x10: /* SQSHRUN, SQSHRUN2 */
6346 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6348 unallocated_encoding(s
);
6351 handle_vec_simd_sqshrn(s
, true, false, false, true,
6352 immh
, immb
, opcode
, rn
, rd
);
6354 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6355 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6356 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6357 immh
, immb
, opcode
, rn
, rd
);
6359 case 0xc: /* SQSHLU */
6361 unallocated_encoding(s
);
6364 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6366 case 0xe: /* SQSHL, UQSHL */
6367 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6369 case 0x1f: /* FCVTZS, FCVTZU */
6370 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6373 unallocated_encoding(s
);
6378 /* C3.6.10 AdvSIMD scalar three different
6379 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6380 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6381 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6382 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6384 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6386 bool is_u
= extract32(insn
, 29, 1);
6387 int size
= extract32(insn
, 22, 2);
6388 int opcode
= extract32(insn
, 12, 4);
6389 int rm
= extract32(insn
, 16, 5);
6390 int rn
= extract32(insn
, 5, 5);
6391 int rd
= extract32(insn
, 0, 5);
6394 unallocated_encoding(s
);
6399 case 0x9: /* SQDMLAL, SQDMLAL2 */
6400 case 0xb: /* SQDMLSL, SQDMLSL2 */
6401 case 0xd: /* SQDMULL, SQDMULL2 */
6402 if (size
== 0 || size
== 3) {
6403 unallocated_encoding(s
);
6408 unallocated_encoding(s
);
6413 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6414 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6415 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6417 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6418 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6420 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6421 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6424 case 0xd: /* SQDMULL, SQDMULL2 */
6426 case 0xb: /* SQDMLSL, SQDMLSL2 */
6427 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6429 case 0x9: /* SQDMLAL, SQDMLAL2 */
6430 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6431 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6435 g_assert_not_reached();
6438 write_fp_dreg(s
, rd
, tcg_res
);
6440 tcg_temp_free_i64(tcg_op1
);
6441 tcg_temp_free_i64(tcg_op2
);
6442 tcg_temp_free_i64(tcg_res
);
6444 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6445 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6446 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6448 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6449 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6451 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6452 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6455 case 0xd: /* SQDMULL, SQDMULL2 */
6457 case 0xb: /* SQDMLSL, SQDMLSL2 */
6458 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6460 case 0x9: /* SQDMLAL, SQDMLAL2 */
6462 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6463 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6464 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6466 tcg_temp_free_i64(tcg_op3
);
6470 g_assert_not_reached();
6473 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6474 write_fp_dreg(s
, rd
, tcg_res
);
6476 tcg_temp_free_i32(tcg_op1
);
6477 tcg_temp_free_i32(tcg_op2
);
6478 tcg_temp_free_i64(tcg_res
);
6482 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6483 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6485 /* Handle 64x64->64 opcodes which are shared between the scalar
6486 * and vector 3-same groups. We cover every opcode where size == 3
6487 * is valid in either the three-reg-same (integer, not pairwise)
6488 * or scalar-three-reg-same groups. (Some opcodes are not yet
6494 case 0x1: /* SQADD */
6496 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6498 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6501 case 0x5: /* SQSUB */
6503 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6505 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6508 case 0x6: /* CMGT, CMHI */
6509 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6510 * We implement this using setcond (test) and then negating.
6512 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6514 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6515 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6517 case 0x7: /* CMGE, CMHS */
6518 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6520 case 0x11: /* CMTST, CMEQ */
6525 /* CMTST : test is "if (X & Y != 0)". */
6526 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6527 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
6528 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6530 case 0x8: /* SSHL, USHL */
6532 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6534 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6537 case 0x9: /* SQSHL, UQSHL */
6539 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6541 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6544 case 0xa: /* SRSHL, URSHL */
6546 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6548 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6551 case 0xb: /* SQRSHL, UQRSHL */
6553 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6555 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6558 case 0x10: /* ADD, SUB */
6560 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6562 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6566 g_assert_not_reached();
6570 /* Handle the 3-same-operands float operations; shared by the scalar
6571 * and vector encodings. The caller must filter out any encodings
6572 * not allocated for the encoding it is dealing with.
6574 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
6575 int fpopcode
, int rd
, int rn
, int rm
)
6578 TCGv_ptr fpst
= get_fpstatus_ptr();
6580 for (pass
= 0; pass
< elements
; pass
++) {
6583 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6584 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6585 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6587 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
6588 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
6591 case 0x39: /* FMLS */
6592 /* As usual for ARM, separate negation for fused multiply-add */
6593 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6595 case 0x19: /* FMLA */
6596 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6597 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
6600 case 0x18: /* FMAXNM */
6601 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6603 case 0x1a: /* FADD */
6604 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6606 case 0x1b: /* FMULX */
6607 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6609 case 0x1c: /* FCMEQ */
6610 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6612 case 0x1e: /* FMAX */
6613 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6615 case 0x1f: /* FRECPS */
6616 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6618 case 0x38: /* FMINNM */
6619 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6621 case 0x3a: /* FSUB */
6622 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6624 case 0x3e: /* FMIN */
6625 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6627 case 0x3f: /* FRSQRTS */
6628 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6630 case 0x5b: /* FMUL */
6631 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6633 case 0x5c: /* FCMGE */
6634 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6636 case 0x5d: /* FACGE */
6637 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6639 case 0x5f: /* FDIV */
6640 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6642 case 0x7a: /* FABD */
6643 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6644 gen_helper_vfp_absd(tcg_res
, tcg_res
);
6646 case 0x7c: /* FCMGT */
6647 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6649 case 0x7d: /* FACGT */
6650 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6653 g_assert_not_reached();
6656 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6658 tcg_temp_free_i64(tcg_res
);
6659 tcg_temp_free_i64(tcg_op1
);
6660 tcg_temp_free_i64(tcg_op2
);
6663 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6664 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6665 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6667 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
6668 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
6671 case 0x39: /* FMLS */
6672 /* As usual for ARM, separate negation for fused multiply-add */
6673 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6675 case 0x19: /* FMLA */
6676 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6677 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
6680 case 0x1a: /* FADD */
6681 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6683 case 0x1b: /* FMULX */
6684 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6686 case 0x1c: /* FCMEQ */
6687 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6689 case 0x1e: /* FMAX */
6690 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6692 case 0x1f: /* FRECPS */
6693 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6695 case 0x18: /* FMAXNM */
6696 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6698 case 0x38: /* FMINNM */
6699 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6701 case 0x3a: /* FSUB */
6702 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6704 case 0x3e: /* FMIN */
6705 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6707 case 0x3f: /* FRSQRTS */
6708 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6710 case 0x5b: /* FMUL */
6711 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6713 case 0x5c: /* FCMGE */
6714 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6716 case 0x5d: /* FACGE */
6717 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6719 case 0x5f: /* FDIV */
6720 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6722 case 0x7a: /* FABD */
6723 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6724 gen_helper_vfp_abss(tcg_res
, tcg_res
);
6726 case 0x7c: /* FCMGT */
6727 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6729 case 0x7d: /* FACGT */
6730 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6733 g_assert_not_reached();
6736 if (elements
== 1) {
6737 /* scalar single so clear high part */
6738 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6740 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
6741 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
6742 tcg_temp_free_i64(tcg_tmp
);
6744 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6747 tcg_temp_free_i32(tcg_res
);
6748 tcg_temp_free_i32(tcg_op1
);
6749 tcg_temp_free_i32(tcg_op2
);
6753 tcg_temp_free_ptr(fpst
);
6755 if ((elements
<< size
) < 4) {
6756 /* scalar, or non-quad vector op */
6757 clear_vec_high(s
, rd
);
6761 /* C3.6.11 AdvSIMD scalar three same
6762 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
6763 * +-----+---+-----------+------+---+------+--------+---+------+------+
6764 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
6765 * +-----+---+-----------+------+---+------+--------+---+------+------+
6767 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
6769 int rd
= extract32(insn
, 0, 5);
6770 int rn
= extract32(insn
, 5, 5);
6771 int opcode
= extract32(insn
, 11, 5);
6772 int rm
= extract32(insn
, 16, 5);
6773 int size
= extract32(insn
, 22, 2);
6774 bool u
= extract32(insn
, 29, 1);
6777 if (opcode
>= 0x18) {
6778 /* Floating point: U, size[1] and opcode indicate operation */
6779 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
6781 case 0x1b: /* FMULX */
6782 case 0x1f: /* FRECPS */
6783 case 0x3f: /* FRSQRTS */
6784 case 0x5d: /* FACGE */
6785 case 0x7d: /* FACGT */
6786 case 0x1c: /* FCMEQ */
6787 case 0x5c: /* FCMGE */
6788 case 0x7c: /* FCMGT */
6789 case 0x7a: /* FABD */
6792 unallocated_encoding(s
);
6796 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
6801 case 0x1: /* SQADD, UQADD */
6802 case 0x5: /* SQSUB, UQSUB */
6803 case 0x9: /* SQSHL, UQSHL */
6804 case 0xb: /* SQRSHL, UQRSHL */
6806 case 0x8: /* SSHL, USHL */
6807 case 0xa: /* SRSHL, URSHL */
6808 case 0x6: /* CMGT, CMHI */
6809 case 0x7: /* CMGE, CMHS */
6810 case 0x11: /* CMTST, CMEQ */
6811 case 0x10: /* ADD, SUB (vector) */
6813 unallocated_encoding(s
);
6817 case 0x16: /* SQDMULH, SQRDMULH (vector) */
6818 if (size
!= 1 && size
!= 2) {
6819 unallocated_encoding(s
);
6824 unallocated_encoding(s
);
6828 tcg_rd
= tcg_temp_new_i64();
6831 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6832 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
6834 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
6835 tcg_temp_free_i64(tcg_rn
);
6836 tcg_temp_free_i64(tcg_rm
);
6838 /* Do a single operation on the lowest element in the vector.
6839 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
6840 * no side effects for all these operations.
6841 * OPTME: special-purpose helpers would avoid doing some
6842 * unnecessary work in the helper for the 8 and 16 bit cases.
6844 NeonGenTwoOpEnvFn
*genenvfn
;
6845 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
6846 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
6847 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
6849 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
6850 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
6853 case 0x1: /* SQADD, UQADD */
6855 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6856 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
6857 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
6858 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
6860 genenvfn
= fns
[size
][u
];
6863 case 0x5: /* SQSUB, UQSUB */
6865 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6866 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
6867 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
6868 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
6870 genenvfn
= fns
[size
][u
];
6873 case 0x9: /* SQSHL, UQSHL */
6875 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6876 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
6877 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
6878 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
6880 genenvfn
= fns
[size
][u
];
6883 case 0xb: /* SQRSHL, UQRSHL */
6885 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
6886 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
6887 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
6888 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
6890 genenvfn
= fns
[size
][u
];
6893 case 0x16: /* SQDMULH, SQRDMULH */
6895 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
6896 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
6897 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
6899 assert(size
== 1 || size
== 2);
6900 genenvfn
= fns
[size
- 1][u
];
6904 g_assert_not_reached();
6907 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
6908 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
6909 tcg_temp_free_i32(tcg_rd32
);
6910 tcg_temp_free_i32(tcg_rn
);
6911 tcg_temp_free_i32(tcg_rm
);
6914 write_fp_dreg(s
, rd
, tcg_rd
);
6916 tcg_temp_free_i64(tcg_rd
);
6919 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
6920 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
6921 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
6923 /* Handle 64->64 opcodes which are shared between the scalar and
6924 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
6925 * is valid in either group and also the double-precision fp ops.
6926 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
6932 case 0x4: /* CLS, CLZ */
6934 gen_helper_clz64(tcg_rd
, tcg_rn
);
6936 gen_helper_cls64(tcg_rd
, tcg_rn
);
6940 /* This opcode is shared with CNT and RBIT but we have earlier
6941 * enforced that size == 3 if and only if this is the NOT insn.
6943 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
6945 case 0xa: /* CMLT */
6946 /* 64 bit integer comparison against zero, result is
6947 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
6952 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
6953 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6955 case 0x8: /* CMGT, CMGE */
6956 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
6958 case 0x9: /* CMEQ, CMLE */
6959 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
6961 case 0xb: /* ABS, NEG */
6963 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
6965 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6966 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
6967 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
6969 tcg_temp_free_i64(tcg_zero
);
6972 case 0x2f: /* FABS */
6973 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
6975 case 0x6f: /* FNEG */
6976 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
6978 case 0x7f: /* FSQRT */
6979 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
6981 case 0x1a: /* FCVTNS */
6982 case 0x1b: /* FCVTMS */
6983 case 0x1c: /* FCVTAS */
6984 case 0x3a: /* FCVTPS */
6985 case 0x3b: /* FCVTZS */
6987 TCGv_i32 tcg_shift
= tcg_const_i32(0);
6988 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
6989 tcg_temp_free_i32(tcg_shift
);
6992 case 0x5a: /* FCVTNU */
6993 case 0x5b: /* FCVTMU */
6994 case 0x5c: /* FCVTAU */
6995 case 0x7a: /* FCVTPU */
6996 case 0x7b: /* FCVTZU */
6998 TCGv_i32 tcg_shift
= tcg_const_i32(0);
6999 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7000 tcg_temp_free_i32(tcg_shift
);
7003 case 0x18: /* FRINTN */
7004 case 0x19: /* FRINTM */
7005 case 0x38: /* FRINTP */
7006 case 0x39: /* FRINTZ */
7007 case 0x58: /* FRINTA */
7008 case 0x79: /* FRINTI */
7009 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7011 case 0x59: /* FRINTX */
7012 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7015 g_assert_not_reached();
7019 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7020 bool is_scalar
, bool is_u
, bool is_q
,
7021 int size
, int rn
, int rd
)
7023 bool is_double
= (size
== 3);
7024 TCGv_ptr fpst
= get_fpstatus_ptr();
7027 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7028 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7029 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7030 NeonGenTwoDoubleOPFn
*genfn
;
7035 case 0x2e: /* FCMLT (zero) */
7038 case 0x2c: /* FCMGT (zero) */
7039 genfn
= gen_helper_neon_cgt_f64
;
7041 case 0x2d: /* FCMEQ (zero) */
7042 genfn
= gen_helper_neon_ceq_f64
;
7044 case 0x6d: /* FCMLE (zero) */
7047 case 0x6c: /* FCMGE (zero) */
7048 genfn
= gen_helper_neon_cge_f64
;
7051 g_assert_not_reached();
7054 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7055 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7057 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7059 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7061 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7064 clear_vec_high(s
, rd
);
7067 tcg_temp_free_i64(tcg_res
);
7068 tcg_temp_free_i64(tcg_zero
);
7069 tcg_temp_free_i64(tcg_op
);
7071 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7072 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7073 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7074 NeonGenTwoSingleOPFn
*genfn
;
7076 int pass
, maxpasses
;
7079 case 0x2e: /* FCMLT (zero) */
7082 case 0x2c: /* FCMGT (zero) */
7083 genfn
= gen_helper_neon_cgt_f32
;
7085 case 0x2d: /* FCMEQ (zero) */
7086 genfn
= gen_helper_neon_ceq_f32
;
7088 case 0x6d: /* FCMLE (zero) */
7091 case 0x6c: /* FCMGE (zero) */
7092 genfn
= gen_helper_neon_cge_f32
;
7095 g_assert_not_reached();
7101 maxpasses
= is_q
? 4 : 2;
7104 for (pass
= 0; pass
< maxpasses
; pass
++) {
7105 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7107 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7109 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7112 write_fp_sreg(s
, rd
, tcg_res
);
7114 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7117 tcg_temp_free_i32(tcg_res
);
7118 tcg_temp_free_i32(tcg_zero
);
7119 tcg_temp_free_i32(tcg_op
);
7120 if (!is_q
&& !is_scalar
) {
7121 clear_vec_high(s
, rd
);
7125 tcg_temp_free_ptr(fpst
);
7128 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7129 bool is_scalar
, bool is_u
, bool is_q
,
7130 int size
, int rn
, int rd
)
7132 bool is_double
= (size
== 3);
7133 TCGv_ptr fpst
= get_fpstatus_ptr();
7136 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7137 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7140 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7141 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7143 case 0x3d: /* FRECPE */
7144 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7146 case 0x3f: /* FRECPX */
7147 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7149 case 0x7d: /* FRSQRTE */
7150 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7153 g_assert_not_reached();
7155 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7158 clear_vec_high(s
, rd
);
7161 tcg_temp_free_i64(tcg_res
);
7162 tcg_temp_free_i64(tcg_op
);
7164 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7165 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7166 int pass
, maxpasses
;
7171 maxpasses
= is_q
? 4 : 2;
7174 for (pass
= 0; pass
< maxpasses
; pass
++) {
7175 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7178 case 0x3c: /* URECPE */
7179 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7181 case 0x3d: /* FRECPE */
7182 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7184 case 0x3f: /* FRECPX */
7185 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7187 case 0x7d: /* FRSQRTE */
7188 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7191 g_assert_not_reached();
7195 write_fp_sreg(s
, rd
, tcg_res
);
7197 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7200 tcg_temp_free_i32(tcg_res
);
7201 tcg_temp_free_i32(tcg_op
);
7202 if (!is_q
&& !is_scalar
) {
7203 clear_vec_high(s
, rd
);
7206 tcg_temp_free_ptr(fpst
);
7209 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7210 int opcode
, bool u
, bool is_q
,
7211 int size
, int rn
, int rd
)
7213 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7214 * in the source becomes a size element in the destination).
7217 TCGv_i32 tcg_res
[2];
7218 int destelt
= is_q
? 2 : 0;
7219 int passes
= scalar
? 1 : 2;
7222 tcg_res
[1] = tcg_const_i32(0);
7225 for (pass
= 0; pass
< passes
; pass
++) {
7226 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7227 NeonGenNarrowFn
*genfn
= NULL
;
7228 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7231 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7233 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7235 tcg_res
[pass
] = tcg_temp_new_i32();
7238 case 0x12: /* XTN, SQXTUN */
7240 static NeonGenNarrowFn
* const xtnfns
[3] = {
7241 gen_helper_neon_narrow_u8
,
7242 gen_helper_neon_narrow_u16
,
7243 tcg_gen_trunc_i64_i32
,
7245 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7246 gen_helper_neon_unarrow_sat8
,
7247 gen_helper_neon_unarrow_sat16
,
7248 gen_helper_neon_unarrow_sat32
,
7251 genenvfn
= sqxtunfns
[size
];
7253 genfn
= xtnfns
[size
];
7257 case 0x14: /* SQXTN, UQXTN */
7259 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7260 { gen_helper_neon_narrow_sat_s8
,
7261 gen_helper_neon_narrow_sat_u8
},
7262 { gen_helper_neon_narrow_sat_s16
,
7263 gen_helper_neon_narrow_sat_u16
},
7264 { gen_helper_neon_narrow_sat_s32
,
7265 gen_helper_neon_narrow_sat_u32
},
7267 genenvfn
= fns
[size
][u
];
7270 case 0x16: /* FCVTN, FCVTN2 */
7271 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7273 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7275 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7276 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7277 tcg_gen_trunc_i64_i32(tcg_lo
, tcg_op
);
7278 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7279 tcg_gen_shri_i64(tcg_op
, tcg_op
, 32);
7280 tcg_gen_trunc_i64_i32(tcg_hi
, tcg_op
);
7281 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7282 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7283 tcg_temp_free_i32(tcg_lo
);
7284 tcg_temp_free_i32(tcg_hi
);
7287 case 0x56: /* FCVTXN, FCVTXN2 */
7288 /* 64 bit to 32 bit float conversion
7289 * with von Neumann rounding (round to odd)
7292 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7295 g_assert_not_reached();
7299 genfn(tcg_res
[pass
], tcg_op
);
7300 } else if (genenvfn
) {
7301 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7304 tcg_temp_free_i64(tcg_op
);
7307 for (pass
= 0; pass
< 2; pass
++) {
7308 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7309 tcg_temp_free_i32(tcg_res
[pass
]);
7312 clear_vec_high(s
, rd
);
7316 /* C3.6.12 AdvSIMD scalar two reg misc
7317 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7318 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7319 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7320 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7322 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7324 int rd
= extract32(insn
, 0, 5);
7325 int rn
= extract32(insn
, 5, 5);
7326 int opcode
= extract32(insn
, 12, 5);
7327 int size
= extract32(insn
, 22, 2);
7328 bool u
= extract32(insn
, 29, 1);
7329 bool is_fcvt
= false;
7332 TCGv_ptr tcg_fpstatus
;
7335 case 0xa: /* CMLT */
7337 unallocated_encoding(s
);
7341 case 0x8: /* CMGT, CMGE */
7342 case 0x9: /* CMEQ, CMLE */
7343 case 0xb: /* ABS, NEG */
7345 unallocated_encoding(s
);
7349 case 0x12: /* SQXTUN */
7351 unallocated_encoding(s
);
7355 case 0x14: /* SQXTN, UQXTN */
7357 unallocated_encoding(s
);
7360 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7365 /* Floating point: U, size[1] and opcode indicate operation;
7366 * size[0] indicates single or double precision.
7368 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7369 size
= extract32(size
, 0, 1) ? 3 : 2;
7371 case 0x2c: /* FCMGT (zero) */
7372 case 0x2d: /* FCMEQ (zero) */
7373 case 0x2e: /* FCMLT (zero) */
7374 case 0x6c: /* FCMGE (zero) */
7375 case 0x6d: /* FCMLE (zero) */
7376 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7378 case 0x1d: /* SCVTF */
7379 case 0x5d: /* UCVTF */
7381 bool is_signed
= (opcode
== 0x1d);
7382 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7385 case 0x3d: /* FRECPE */
7386 case 0x3f: /* FRECPX */
7387 case 0x7d: /* FRSQRTE */
7388 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7390 case 0x1a: /* FCVTNS */
7391 case 0x1b: /* FCVTMS */
7392 case 0x3a: /* FCVTPS */
7393 case 0x3b: /* FCVTZS */
7394 case 0x5a: /* FCVTNU */
7395 case 0x5b: /* FCVTMU */
7396 case 0x7a: /* FCVTPU */
7397 case 0x7b: /* FCVTZU */
7399 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
7401 case 0x1c: /* FCVTAS */
7402 case 0x5c: /* FCVTAU */
7403 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
7405 rmode
= FPROUNDING_TIEAWAY
;
7407 case 0x56: /* FCVTXN, FCVTXN2 */
7409 unallocated_encoding(s
);
7412 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
7415 unallocated_encoding(s
);
7420 /* Other categories of encoding in this class:
7421 * + SUQADD/USQADD/SQABS/SQNEG : size 8, 16, 32 or 64
7423 unsupported_encoding(s
, insn
);
7428 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7429 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7430 tcg_fpstatus
= get_fpstatus_ptr();
7432 TCGV_UNUSED_I32(tcg_rmode
);
7433 TCGV_UNUSED_PTR(tcg_fpstatus
);
7437 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7438 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7440 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
7441 write_fp_dreg(s
, rd
, tcg_rd
);
7442 tcg_temp_free_i64(tcg_rd
);
7443 tcg_temp_free_i64(tcg_rn
);
7444 } else if (size
== 2) {
7445 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
7446 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7449 case 0x1a: /* FCVTNS */
7450 case 0x1b: /* FCVTMS */
7451 case 0x1c: /* FCVTAS */
7452 case 0x3a: /* FCVTPS */
7453 case 0x3b: /* FCVTZS */
7455 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7456 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7457 tcg_temp_free_i32(tcg_shift
);
7460 case 0x5a: /* FCVTNU */
7461 case 0x5b: /* FCVTMU */
7462 case 0x5c: /* FCVTAU */
7463 case 0x7a: /* FCVTPU */
7464 case 0x7b: /* FCVTZU */
7466 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7467 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7468 tcg_temp_free_i32(tcg_shift
);
7472 g_assert_not_reached();
7475 write_fp_sreg(s
, rd
, tcg_rd
);
7476 tcg_temp_free_i32(tcg_rd
);
7477 tcg_temp_free_i32(tcg_rn
);
7479 g_assert_not_reached();
7483 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7484 tcg_temp_free_i32(tcg_rmode
);
7485 tcg_temp_free_ptr(tcg_fpstatus
);
7489 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
7490 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
7491 int immh
, int immb
, int opcode
, int rn
, int rd
)
7493 int size
= 32 - clz32(immh
) - 1;
7494 int immhb
= immh
<< 3 | immb
;
7495 int shift
= 2 * (8 << size
) - immhb
;
7496 bool accumulate
= false;
7498 bool insert
= false;
7499 int dsize
= is_q
? 128 : 64;
7500 int esize
= 8 << size
;
7501 int elements
= dsize
/esize
;
7502 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
7503 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7504 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7508 if (extract32(immh
, 3, 1) && !is_q
) {
7509 unallocated_encoding(s
);
7513 if (size
> 3 && !is_q
) {
7514 unallocated_encoding(s
);
7519 case 0x02: /* SSRA / USRA (accumulate) */
7522 case 0x04: /* SRSHR / URSHR (rounding) */
7525 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7526 accumulate
= round
= true;
7528 case 0x08: /* SRI */
7534 uint64_t round_const
= 1ULL << (shift
- 1);
7535 tcg_round
= tcg_const_i64(round_const
);
7537 TCGV_UNUSED_I64(tcg_round
);
7540 for (i
= 0; i
< elements
; i
++) {
7541 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
7542 if (accumulate
|| insert
) {
7543 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
7547 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
7549 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7550 accumulate
, is_u
, size
, shift
);
7553 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
7557 clear_vec_high(s
, rd
);
7561 tcg_temp_free_i64(tcg_round
);
7565 /* SHL/SLI - Vector shift left */
7566 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
7567 int immh
, int immb
, int opcode
, int rn
, int rd
)
7569 int size
= 32 - clz32(immh
) - 1;
7570 int immhb
= immh
<< 3 | immb
;
7571 int shift
= immhb
- (8 << size
);
7572 int dsize
= is_q
? 128 : 64;
7573 int esize
= 8 << size
;
7574 int elements
= dsize
/esize
;
7575 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7576 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7579 if (extract32(immh
, 3, 1) && !is_q
) {
7580 unallocated_encoding(s
);
7584 if (size
> 3 && !is_q
) {
7585 unallocated_encoding(s
);
7589 for (i
= 0; i
< elements
; i
++) {
7590 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
7592 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
7595 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
7597 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
7601 clear_vec_high(s
, rd
);
7605 /* USHLL/SHLL - Vector shift left with widening */
7606 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
7607 int immh
, int immb
, int opcode
, int rn
, int rd
)
7609 int size
= 32 - clz32(immh
) - 1;
7610 int immhb
= immh
<< 3 | immb
;
7611 int shift
= immhb
- (8 << size
);
7613 int esize
= 8 << size
;
7614 int elements
= dsize
/esize
;
7615 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7616 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7620 unallocated_encoding(s
);
7624 /* For the LL variants the store is larger than the load,
7625 * so if rd == rn we would overwrite parts of our input.
7626 * So load everything right now and use shifts in the main loop.
7628 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
7630 for (i
= 0; i
< elements
; i
++) {
7631 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
7632 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
7633 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
7634 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
7638 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
7639 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
7640 int immh
, int immb
, int opcode
, int rn
, int rd
)
7642 int immhb
= immh
<< 3 | immb
;
7643 int size
= 32 - clz32(immh
) - 1;
7645 int esize
= 8 << size
;
7646 int elements
= dsize
/esize
;
7647 int shift
= (2 * esize
) - immhb
;
7648 bool round
= extract32(opcode
, 0, 1);
7649 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
7653 if (extract32(immh
, 3, 1)) {
7654 unallocated_encoding(s
);
7658 tcg_rn
= tcg_temp_new_i64();
7659 tcg_rd
= tcg_temp_new_i64();
7660 tcg_final
= tcg_temp_new_i64();
7661 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
7664 uint64_t round_const
= 1ULL << (shift
- 1);
7665 tcg_round
= tcg_const_i64(round_const
);
7667 TCGV_UNUSED_I64(tcg_round
);
7670 for (i
= 0; i
< elements
; i
++) {
7671 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
7672 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7673 false, true, size
+1, shift
);
7675 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7679 clear_vec_high(s
, rd
);
7680 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7682 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7686 tcg_temp_free_i64(tcg_round
);
7688 tcg_temp_free_i64(tcg_rn
);
7689 tcg_temp_free_i64(tcg_rd
);
7690 tcg_temp_free_i64(tcg_final
);
7695 /* C3.6.14 AdvSIMD shift by immediate
7696 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
7697 * +---+---+---+-------------+------+------+--------+---+------+------+
7698 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
7699 * +---+---+---+-------------+------+------+--------+---+------+------+
7701 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
7703 int rd
= extract32(insn
, 0, 5);
7704 int rn
= extract32(insn
, 5, 5);
7705 int opcode
= extract32(insn
, 11, 5);
7706 int immb
= extract32(insn
, 16, 3);
7707 int immh
= extract32(insn
, 19, 4);
7708 bool is_u
= extract32(insn
, 29, 1);
7709 bool is_q
= extract32(insn
, 30, 1);
7712 case 0x08: /* SRI */
7714 unallocated_encoding(s
);
7718 case 0x00: /* SSHR / USHR */
7719 case 0x02: /* SSRA / USRA (accumulate) */
7720 case 0x04: /* SRSHR / URSHR (rounding) */
7721 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7722 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7724 case 0x0a: /* SHL / SLI */
7725 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7727 case 0x10: /* SHRN */
7728 case 0x11: /* RSHRN / SQRSHRUN */
7730 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
7733 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
7736 case 0x12: /* SQSHRN / UQSHRN */
7737 case 0x13: /* SQRSHRN / UQRSHRN */
7738 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
7741 case 0x14: /* SSHLL / USHLL */
7742 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7744 case 0x1c: /* SCVTF / UCVTF */
7745 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
7748 case 0xc: /* SQSHLU */
7750 unallocated_encoding(s
);
7753 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
7755 case 0xe: /* SQSHL, UQSHL */
7756 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
7758 case 0x1f: /* FCVTZS/ FCVTZU */
7759 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
7762 unallocated_encoding(s
);
7767 /* Generate code to do a "long" addition or subtraction, ie one done in
7768 * TCGv_i64 on vector lanes twice the width specified by size.
7770 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
7771 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
7773 static NeonGenTwo64OpFn
* const fns
[3][2] = {
7774 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
7775 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
7776 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
7778 NeonGenTwo64OpFn
*genfn
;
7781 genfn
= fns
[size
][is_sub
];
7782 genfn(tcg_res
, tcg_op1
, tcg_op2
);
7785 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
7786 int opcode
, int rd
, int rn
, int rm
)
7788 /* 3-reg-different widening insns: 64 x 64 -> 128 */
7789 TCGv_i64 tcg_res
[2];
7792 tcg_res
[0] = tcg_temp_new_i64();
7793 tcg_res
[1] = tcg_temp_new_i64();
7795 /* Does this op do an adding accumulate, a subtracting accumulate,
7796 * or no accumulate at all?
7814 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
7815 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
7818 /* size == 2 means two 32x32->64 operations; this is worth special
7819 * casing because we can generally handle it inline.
7822 for (pass
= 0; pass
< 2; pass
++) {
7823 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7824 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7825 TCGv_i64 tcg_passres
;
7826 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
7828 int elt
= pass
+ is_q
* 2;
7830 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
7831 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
7834 tcg_passres
= tcg_res
[pass
];
7836 tcg_passres
= tcg_temp_new_i64();
7840 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
7841 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7843 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
7844 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7846 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
7847 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
7849 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
7850 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
7852 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
7853 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
7854 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
7856 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
7857 tcg_temp_free_i64(tcg_tmp1
);
7858 tcg_temp_free_i64(tcg_tmp2
);
7861 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
7862 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
7863 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
7864 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7866 case 9: /* SQDMLAL, SQDMLAL2 */
7867 case 11: /* SQDMLSL, SQDMLSL2 */
7868 case 13: /* SQDMULL, SQDMULL2 */
7869 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
7870 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
7871 tcg_passres
, tcg_passres
);
7874 g_assert_not_reached();
7877 if (opcode
== 9 || opcode
== 11) {
7878 /* saturating accumulate ops */
7880 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
7882 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
7883 tcg_res
[pass
], tcg_passres
);
7884 } else if (accop
> 0) {
7885 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
7886 } else if (accop
< 0) {
7887 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
7891 tcg_temp_free_i64(tcg_passres
);
7894 tcg_temp_free_i64(tcg_op1
);
7895 tcg_temp_free_i64(tcg_op2
);
7898 /* size 0 or 1, generally helper functions */
7899 for (pass
= 0; pass
< 2; pass
++) {
7900 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7901 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7902 TCGv_i64 tcg_passres
;
7903 int elt
= pass
+ is_q
* 2;
7905 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
7906 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
7909 tcg_passres
= tcg_res
[pass
];
7911 tcg_passres
= tcg_temp_new_i64();
7915 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
7916 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
7918 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
7919 static NeonGenWidenFn
* const widenfns
[2][2] = {
7920 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
7921 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
7923 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
7925 widenfn(tcg_op2_64
, tcg_op2
);
7926 widenfn(tcg_passres
, tcg_op1
);
7927 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
7928 tcg_passres
, tcg_op2_64
);
7929 tcg_temp_free_i64(tcg_op2_64
);
7932 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
7933 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
7936 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
7938 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
7942 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
7944 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
7948 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
7949 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
7950 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
7953 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
7955 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
7959 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
7961 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
7965 case 9: /* SQDMLAL, SQDMLAL2 */
7966 case 11: /* SQDMLSL, SQDMLSL2 */
7967 case 13: /* SQDMULL, SQDMULL2 */
7969 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
7970 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
7971 tcg_passres
, tcg_passres
);
7973 case 14: /* PMULL */
7975 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
7978 g_assert_not_reached();
7980 tcg_temp_free_i32(tcg_op1
);
7981 tcg_temp_free_i32(tcg_op2
);
7984 if (opcode
== 9 || opcode
== 11) {
7985 /* saturating accumulate ops */
7987 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
7989 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
7993 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
7994 tcg_res
[pass
], tcg_passres
);
7996 tcg_temp_free_i64(tcg_passres
);
8001 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8002 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8003 tcg_temp_free_i64(tcg_res
[0]);
8004 tcg_temp_free_i64(tcg_res
[1]);
8007 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8008 int opcode
, int rd
, int rn
, int rm
)
8010 TCGv_i64 tcg_res
[2];
8011 int part
= is_q
? 2 : 0;
8014 for (pass
= 0; pass
< 2; pass
++) {
8015 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8016 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8017 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8018 static NeonGenWidenFn
* const widenfns
[3][2] = {
8019 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8020 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8021 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8023 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8025 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8026 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8027 widenfn(tcg_op2_wide
, tcg_op2
);
8028 tcg_temp_free_i32(tcg_op2
);
8029 tcg_res
[pass
] = tcg_temp_new_i64();
8030 gen_neon_addl(size
, (opcode
== 3),
8031 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8032 tcg_temp_free_i64(tcg_op1
);
8033 tcg_temp_free_i64(tcg_op2_wide
);
8036 for (pass
= 0; pass
< 2; pass
++) {
8037 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8038 tcg_temp_free_i64(tcg_res
[pass
]);
8042 static void do_narrow_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8044 tcg_gen_shri_i64(in
, in
, 32);
8045 tcg_gen_trunc_i64_i32(res
, in
);
8048 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8050 tcg_gen_addi_i64(in
, in
, 1U << 31);
8051 do_narrow_high_u32(res
, in
);
8054 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8055 int opcode
, int rd
, int rn
, int rm
)
8057 TCGv_i32 tcg_res
[2];
8058 int part
= is_q
? 2 : 0;
8061 for (pass
= 0; pass
< 2; pass
++) {
8062 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8063 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8064 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8065 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8066 { gen_helper_neon_narrow_high_u8
,
8067 gen_helper_neon_narrow_round_high_u8
},
8068 { gen_helper_neon_narrow_high_u16
,
8069 gen_helper_neon_narrow_round_high_u16
},
8070 { do_narrow_high_u32
, do_narrow_round_high_u32
},
8072 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8074 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8075 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8077 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8079 tcg_temp_free_i64(tcg_op1
);
8080 tcg_temp_free_i64(tcg_op2
);
8082 tcg_res
[pass
] = tcg_temp_new_i32();
8083 gennarrow(tcg_res
[pass
], tcg_wideres
);
8084 tcg_temp_free_i64(tcg_wideres
);
8087 for (pass
= 0; pass
< 2; pass
++) {
8088 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8089 tcg_temp_free_i32(tcg_res
[pass
]);
8092 clear_vec_high(s
, rd
);
8096 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8098 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8099 * is the only three-reg-diff instruction which produces a
8100 * 128-bit wide result from a single operation. However since
8101 * it's possible to calculate the two halves more or less
8102 * separately we just use two helper calls.
8104 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8105 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8106 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8108 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8109 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8110 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8111 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8112 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8113 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8115 tcg_temp_free_i64(tcg_op1
);
8116 tcg_temp_free_i64(tcg_op2
);
8117 tcg_temp_free_i64(tcg_res
);
8120 /* C3.6.15 AdvSIMD three different
8121 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8122 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8123 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8124 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8126 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8128 /* Instructions in this group fall into three basic classes
8129 * (in each case with the operation working on each element in
8130 * the input vectors):
8131 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8133 * (2) wide 64 x 128 -> 128
8134 * (3) narrowing 128 x 128 -> 64
8135 * Here we do initial decode, catch unallocated cases and
8136 * dispatch to separate functions for each class.
8138 int is_q
= extract32(insn
, 30, 1);
8139 int is_u
= extract32(insn
, 29, 1);
8140 int size
= extract32(insn
, 22, 2);
8141 int opcode
= extract32(insn
, 12, 4);
8142 int rm
= extract32(insn
, 16, 5);
8143 int rn
= extract32(insn
, 5, 5);
8144 int rd
= extract32(insn
, 0, 5);
8147 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8148 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8149 /* 64 x 128 -> 128 */
8151 unallocated_encoding(s
);
8154 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8156 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8157 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8158 /* 128 x 128 -> 64 */
8160 unallocated_encoding(s
);
8163 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8165 case 14: /* PMULL, PMULL2 */
8166 if (is_u
|| size
== 1 || size
== 2) {
8167 unallocated_encoding(s
);
8171 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)) {
8172 unallocated_encoding(s
);
8175 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8179 case 9: /* SQDMLAL, SQDMLAL2 */
8180 case 11: /* SQDMLSL, SQDMLSL2 */
8181 case 13: /* SQDMULL, SQDMULL2 */
8182 if (is_u
|| size
== 0) {
8183 unallocated_encoding(s
);
8187 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8188 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8189 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8190 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8191 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8192 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8193 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8194 /* 64 x 64 -> 128 */
8196 unallocated_encoding(s
);
8200 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8203 /* opcode 15 not allocated */
8204 unallocated_encoding(s
);
8209 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8210 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8212 int rd
= extract32(insn
, 0, 5);
8213 int rn
= extract32(insn
, 5, 5);
8214 int rm
= extract32(insn
, 16, 5);
8215 int size
= extract32(insn
, 22, 2);
8216 bool is_u
= extract32(insn
, 29, 1);
8217 bool is_q
= extract32(insn
, 30, 1);
8218 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8219 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8220 TCGv_i64 tcg_res
[2];
8223 tcg_res
[0] = tcg_temp_new_i64();
8224 tcg_res
[1] = tcg_temp_new_i64();
8226 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8227 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8228 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8233 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8236 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8239 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8242 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8247 /* B* ops need res loaded to operate on */
8248 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8253 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8255 case 1: /* BSL bitwise select */
8256 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8257 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8258 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8260 case 2: /* BIT, bitwise insert if true */
8261 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8262 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8263 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8265 case 3: /* BIF, bitwise insert if false */
8266 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8267 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8268 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8274 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8276 tcg_gen_movi_i64(tcg_res
[1], 0);
8278 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8280 tcg_temp_free_i64(tcg_op1
);
8281 tcg_temp_free_i64(tcg_op2
);
8282 tcg_temp_free_i64(tcg_res
[0]);
8283 tcg_temp_free_i64(tcg_res
[1]);
8286 /* Helper functions for 32 bit comparisons */
8287 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8289 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8292 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8294 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8297 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8299 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8302 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8304 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8307 /* Pairwise op subgroup of C3.6.16.
8309 * This is called directly or via the handle_3same_float for float pairwise
8310 * operations where the opcode and size are calculated differently.
8312 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8313 int size
, int rn
, int rm
, int rd
)
8318 /* Floating point operations need fpst */
8319 if (opcode
>= 0x58) {
8320 fpst
= get_fpstatus_ptr();
8322 TCGV_UNUSED_PTR(fpst
);
8325 /* These operations work on the concatenated rm:rn, with each pair of
8326 * adjacent elements being operated on to produce an element in the result.
8329 TCGv_i64 tcg_res
[2];
8331 for (pass
= 0; pass
< 2; pass
++) {
8332 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8333 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8334 int passreg
= (pass
== 0) ? rn
: rm
;
8336 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
8337 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
8338 tcg_res
[pass
] = tcg_temp_new_i64();
8341 case 0x17: /* ADDP */
8342 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8344 case 0x58: /* FMAXNMP */
8345 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8347 case 0x5a: /* FADDP */
8348 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8350 case 0x5e: /* FMAXP */
8351 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8353 case 0x78: /* FMINNMP */
8354 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8356 case 0x7e: /* FMINP */
8357 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8360 g_assert_not_reached();
8363 tcg_temp_free_i64(tcg_op1
);
8364 tcg_temp_free_i64(tcg_op2
);
8367 for (pass
= 0; pass
< 2; pass
++) {
8368 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8369 tcg_temp_free_i64(tcg_res
[pass
]);
8372 int maxpass
= is_q
? 4 : 2;
8373 TCGv_i32 tcg_res
[4];
8375 for (pass
= 0; pass
< maxpass
; pass
++) {
8376 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8377 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8378 NeonGenTwoOpFn
*genfn
= NULL
;
8379 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
8380 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
8382 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
8383 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
8384 tcg_res
[pass
] = tcg_temp_new_i32();
8387 case 0x17: /* ADDP */
8389 static NeonGenTwoOpFn
* const fns
[3] = {
8390 gen_helper_neon_padd_u8
,
8391 gen_helper_neon_padd_u16
,
8397 case 0x14: /* SMAXP, UMAXP */
8399 static NeonGenTwoOpFn
* const fns
[3][2] = {
8400 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
8401 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
8402 { gen_max_s32
, gen_max_u32
},
8404 genfn
= fns
[size
][u
];
8407 case 0x15: /* SMINP, UMINP */
8409 static NeonGenTwoOpFn
* const fns
[3][2] = {
8410 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
8411 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
8412 { gen_min_s32
, gen_min_u32
},
8414 genfn
= fns
[size
][u
];
8417 /* The FP operations are all on single floats (32 bit) */
8418 case 0x58: /* FMAXNMP */
8419 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8421 case 0x5a: /* FADDP */
8422 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8424 case 0x5e: /* FMAXP */
8425 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8427 case 0x78: /* FMINNMP */
8428 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8430 case 0x7e: /* FMINP */
8431 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8434 g_assert_not_reached();
8437 /* FP ops called directly, otherwise call now */
8439 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8442 tcg_temp_free_i32(tcg_op1
);
8443 tcg_temp_free_i32(tcg_op2
);
8446 for (pass
= 0; pass
< maxpass
; pass
++) {
8447 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
8448 tcg_temp_free_i32(tcg_res
[pass
]);
8451 clear_vec_high(s
, rd
);
8455 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
8456 tcg_temp_free_ptr(fpst
);
8460 /* Floating point op subgroup of C3.6.16. */
8461 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
8463 /* For floating point ops, the U, size[1] and opcode bits
8464 * together indicate the operation. size[0] indicates single
8467 int fpopcode
= extract32(insn
, 11, 5)
8468 | (extract32(insn
, 23, 1) << 5)
8469 | (extract32(insn
, 29, 1) << 6);
8470 int is_q
= extract32(insn
, 30, 1);
8471 int size
= extract32(insn
, 22, 1);
8472 int rm
= extract32(insn
, 16, 5);
8473 int rn
= extract32(insn
, 5, 5);
8474 int rd
= extract32(insn
, 0, 5);
8476 int datasize
= is_q
? 128 : 64;
8477 int esize
= 32 << size
;
8478 int elements
= datasize
/ esize
;
8480 if (size
== 1 && !is_q
) {
8481 unallocated_encoding(s
);
8486 case 0x58: /* FMAXNMP */
8487 case 0x5a: /* FADDP */
8488 case 0x5e: /* FMAXP */
8489 case 0x78: /* FMINNMP */
8490 case 0x7e: /* FMINP */
8491 if (size
&& !is_q
) {
8492 unallocated_encoding(s
);
8495 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
8498 case 0x1b: /* FMULX */
8499 case 0x1f: /* FRECPS */
8500 case 0x3f: /* FRSQRTS */
8501 case 0x5d: /* FACGE */
8502 case 0x7d: /* FACGT */
8503 case 0x19: /* FMLA */
8504 case 0x39: /* FMLS */
8505 case 0x18: /* FMAXNM */
8506 case 0x1a: /* FADD */
8507 case 0x1c: /* FCMEQ */
8508 case 0x1e: /* FMAX */
8509 case 0x38: /* FMINNM */
8510 case 0x3a: /* FSUB */
8511 case 0x3e: /* FMIN */
8512 case 0x5b: /* FMUL */
8513 case 0x5c: /* FCMGE */
8514 case 0x5f: /* FDIV */
8515 case 0x7a: /* FABD */
8516 case 0x7c: /* FCMGT */
8517 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
8520 unallocated_encoding(s
);
8525 /* Integer op subgroup of C3.6.16. */
8526 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
8528 int is_q
= extract32(insn
, 30, 1);
8529 int u
= extract32(insn
, 29, 1);
8530 int size
= extract32(insn
, 22, 2);
8531 int opcode
= extract32(insn
, 11, 5);
8532 int rm
= extract32(insn
, 16, 5);
8533 int rn
= extract32(insn
, 5, 5);
8534 int rd
= extract32(insn
, 0, 5);
8538 case 0x13: /* MUL, PMUL */
8539 if (u
&& size
!= 0) {
8540 unallocated_encoding(s
);
8544 case 0x0: /* SHADD, UHADD */
8545 case 0x2: /* SRHADD, URHADD */
8546 case 0x4: /* SHSUB, UHSUB */
8547 case 0xc: /* SMAX, UMAX */
8548 case 0xd: /* SMIN, UMIN */
8549 case 0xe: /* SABD, UABD */
8550 case 0xf: /* SABA, UABA */
8551 case 0x12: /* MLA, MLS */
8553 unallocated_encoding(s
);
8557 case 0x16: /* SQDMULH, SQRDMULH */
8558 if (size
== 0 || size
== 3) {
8559 unallocated_encoding(s
);
8564 if (size
== 3 && !is_q
) {
8565 unallocated_encoding(s
);
8572 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8573 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8574 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8575 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8577 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8578 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8580 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
8582 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8584 tcg_temp_free_i64(tcg_res
);
8585 tcg_temp_free_i64(tcg_op1
);
8586 tcg_temp_free_i64(tcg_op2
);
8589 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
8590 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8591 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8592 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8593 NeonGenTwoOpFn
*genfn
= NULL
;
8594 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
8596 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8597 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8600 case 0x0: /* SHADD, UHADD */
8602 static NeonGenTwoOpFn
* const fns
[3][2] = {
8603 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
8604 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
8605 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
8607 genfn
= fns
[size
][u
];
8610 case 0x1: /* SQADD, UQADD */
8612 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8613 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8614 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8615 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8617 genenvfn
= fns
[size
][u
];
8620 case 0x2: /* SRHADD, URHADD */
8622 static NeonGenTwoOpFn
* const fns
[3][2] = {
8623 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
8624 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
8625 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
8627 genfn
= fns
[size
][u
];
8630 case 0x4: /* SHSUB, UHSUB */
8632 static NeonGenTwoOpFn
* const fns
[3][2] = {
8633 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
8634 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
8635 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
8637 genfn
= fns
[size
][u
];
8640 case 0x5: /* SQSUB, UQSUB */
8642 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8643 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8644 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8645 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8647 genenvfn
= fns
[size
][u
];
8650 case 0x6: /* CMGT, CMHI */
8652 static NeonGenTwoOpFn
* const fns
[3][2] = {
8653 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
8654 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
8655 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
8657 genfn
= fns
[size
][u
];
8660 case 0x7: /* CMGE, CMHS */
8662 static NeonGenTwoOpFn
* const fns
[3][2] = {
8663 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
8664 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
8665 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
8667 genfn
= fns
[size
][u
];
8670 case 0x8: /* SSHL, USHL */
8672 static NeonGenTwoOpFn
* const fns
[3][2] = {
8673 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
8674 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
8675 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
8677 genfn
= fns
[size
][u
];
8680 case 0x9: /* SQSHL, UQSHL */
8682 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8683 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8684 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8685 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8687 genenvfn
= fns
[size
][u
];
8690 case 0xa: /* SRSHL, URSHL */
8692 static NeonGenTwoOpFn
* const fns
[3][2] = {
8693 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
8694 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
8695 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
8697 genfn
= fns
[size
][u
];
8700 case 0xb: /* SQRSHL, UQRSHL */
8702 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8703 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8704 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8705 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8707 genenvfn
= fns
[size
][u
];
8710 case 0xc: /* SMAX, UMAX */
8712 static NeonGenTwoOpFn
* const fns
[3][2] = {
8713 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
8714 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
8715 { gen_max_s32
, gen_max_u32
},
8717 genfn
= fns
[size
][u
];
8721 case 0xd: /* SMIN, UMIN */
8723 static NeonGenTwoOpFn
* const fns
[3][2] = {
8724 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
8725 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
8726 { gen_min_s32
, gen_min_u32
},
8728 genfn
= fns
[size
][u
];
8731 case 0xe: /* SABD, UABD */
8732 case 0xf: /* SABA, UABA */
8734 static NeonGenTwoOpFn
* const fns
[3][2] = {
8735 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
8736 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
8737 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
8739 genfn
= fns
[size
][u
];
8742 case 0x10: /* ADD, SUB */
8744 static NeonGenTwoOpFn
* const fns
[3][2] = {
8745 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
8746 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
8747 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
8749 genfn
= fns
[size
][u
];
8752 case 0x11: /* CMTST, CMEQ */
8754 static NeonGenTwoOpFn
* const fns
[3][2] = {
8755 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
8756 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
8757 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
8759 genfn
= fns
[size
][u
];
8762 case 0x13: /* MUL, PMUL */
8766 genfn
= gen_helper_neon_mul_p8
;
8769 /* fall through : MUL */
8770 case 0x12: /* MLA, MLS */
8772 static NeonGenTwoOpFn
* const fns
[3] = {
8773 gen_helper_neon_mul_u8
,
8774 gen_helper_neon_mul_u16
,
8780 case 0x16: /* SQDMULH, SQRDMULH */
8782 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8783 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8784 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8786 assert(size
== 1 || size
== 2);
8787 genenvfn
= fns
[size
- 1][u
];
8791 g_assert_not_reached();
8795 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
8797 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8800 if (opcode
== 0xf || opcode
== 0x12) {
8801 /* SABA, UABA, MLA, MLS: accumulating ops */
8802 static NeonGenTwoOpFn
* const fns
[3][2] = {
8803 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
8804 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
8805 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
8807 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
8809 genfn
= fns
[size
][is_sub
];
8810 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
8811 genfn(tcg_res
, tcg_res
, tcg_op1
);
8814 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8816 tcg_temp_free_i32(tcg_res
);
8817 tcg_temp_free_i32(tcg_op1
);
8818 tcg_temp_free_i32(tcg_op2
);
8823 clear_vec_high(s
, rd
);
8827 /* C3.6.16 AdvSIMD three same
8828 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8829 * +---+---+---+-----------+------+---+------+--------+---+------+------+
8830 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8831 * +---+---+---+-----------+------+---+------+--------+---+------+------+
8833 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
8835 int opcode
= extract32(insn
, 11, 5);
8838 case 0x3: /* logic ops */
8839 disas_simd_3same_logic(s
, insn
);
8841 case 0x17: /* ADDP */
8842 case 0x14: /* SMAXP, UMAXP */
8843 case 0x15: /* SMINP, UMINP */
8845 /* Pairwise operations */
8846 int is_q
= extract32(insn
, 30, 1);
8847 int u
= extract32(insn
, 29, 1);
8848 int size
= extract32(insn
, 22, 2);
8849 int rm
= extract32(insn
, 16, 5);
8850 int rn
= extract32(insn
, 5, 5);
8851 int rd
= extract32(insn
, 0, 5);
8852 if (opcode
== 0x17) {
8853 if (u
|| (size
== 3 && !is_q
)) {
8854 unallocated_encoding(s
);
8859 unallocated_encoding(s
);
8863 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
8867 /* floating point ops, sz[1] and U are part of opcode */
8868 disas_simd_3same_float(s
, insn
);
8871 disas_simd_3same_int(s
, insn
);
8876 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
8877 int size
, int rn
, int rd
)
8879 /* Handle 2-reg-misc ops which are widening (so each size element
8880 * in the source becomes a 2*size element in the destination.
8881 * The only instruction like this is FCVTL.
8886 /* 32 -> 64 bit fp conversion */
8887 TCGv_i64 tcg_res
[2];
8888 int srcelt
= is_q
? 2 : 0;
8890 for (pass
= 0; pass
< 2; pass
++) {
8891 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8892 tcg_res
[pass
] = tcg_temp_new_i64();
8894 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
8895 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
8896 tcg_temp_free_i32(tcg_op
);
8898 for (pass
= 0; pass
< 2; pass
++) {
8899 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8900 tcg_temp_free_i64(tcg_res
[pass
]);
8903 /* 16 -> 32 bit fp conversion */
8904 int srcelt
= is_q
? 4 : 0;
8905 TCGv_i32 tcg_res
[4];
8907 for (pass
= 0; pass
< 4; pass
++) {
8908 tcg_res
[pass
] = tcg_temp_new_i32();
8910 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
8911 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
8914 for (pass
= 0; pass
< 4; pass
++) {
8915 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
8916 tcg_temp_free_i32(tcg_res
[pass
]);
8921 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
8922 bool is_q
, int size
, int rn
, int rd
)
8924 int op
= (opcode
<< 1) | u
;
8925 int opsz
= op
+ size
;
8926 int grp_size
= 3 - opsz
;
8927 int dsize
= is_q
? 128 : 64;
8931 unallocated_encoding(s
);
8936 /* Special case bytes, use bswap op on each group of elements */
8937 int groups
= dsize
/ (8 << grp_size
);
8939 for (i
= 0; i
< groups
; i
++) {
8940 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8942 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
8945 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
8948 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
8951 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
8954 g_assert_not_reached();
8956 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
8957 tcg_temp_free_i64(tcg_tmp
);
8960 clear_vec_high(s
, rd
);
8963 int revmask
= (1 << grp_size
) - 1;
8964 int esize
= 8 << size
;
8965 int elements
= dsize
/ esize
;
8966 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
8967 TCGv_i64 tcg_rd
= tcg_const_i64(0);
8968 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
8970 for (i
= 0; i
< elements
; i
++) {
8971 int e_rev
= (i
& 0xf) ^ revmask
;
8972 int off
= e_rev
* esize
;
8973 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8975 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
8976 tcg_rn
, off
- 64, esize
);
8978 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
8981 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
8982 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
8984 tcg_temp_free_i64(tcg_rd_hi
);
8985 tcg_temp_free_i64(tcg_rd
);
8986 tcg_temp_free_i64(tcg_rn
);
8990 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
8991 bool is_q
, int size
, int rn
, int rd
)
8993 /* Implement the pairwise operations from 2-misc:
8994 * SADDLP, UADDLP, SADALP, UADALP.
8995 * These all add pairs of elements in the input to produce a
8996 * double-width result element in the output (possibly accumulating).
8998 bool accum
= (opcode
== 0x6);
8999 int maxpass
= is_q
? 2 : 1;
9001 TCGv_i64 tcg_res
[2];
9004 /* 32 + 32 -> 64 op */
9005 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9007 for (pass
= 0; pass
< maxpass
; pass
++) {
9008 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9009 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9011 tcg_res
[pass
] = tcg_temp_new_i64();
9013 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9014 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9015 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9017 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9018 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9021 tcg_temp_free_i64(tcg_op1
);
9022 tcg_temp_free_i64(tcg_op2
);
9025 for (pass
= 0; pass
< maxpass
; pass
++) {
9026 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9027 NeonGenOneOpFn
*genfn
;
9028 static NeonGenOneOpFn
* const fns
[2][2] = {
9029 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9030 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9033 genfn
= fns
[size
][u
];
9035 tcg_res
[pass
] = tcg_temp_new_i64();
9037 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9038 genfn(tcg_res
[pass
], tcg_op
);
9041 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9043 gen_helper_neon_addl_u16(tcg_res
[pass
],
9044 tcg_res
[pass
], tcg_op
);
9046 gen_helper_neon_addl_u32(tcg_res
[pass
],
9047 tcg_res
[pass
], tcg_op
);
9050 tcg_temp_free_i64(tcg_op
);
9054 tcg_res
[1] = tcg_const_i64(0);
9056 for (pass
= 0; pass
< 2; pass
++) {
9057 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9058 tcg_temp_free_i64(tcg_res
[pass
]);
9062 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9064 /* Implement SHLL and SHLL2 */
9066 int part
= is_q
? 2 : 0;
9067 TCGv_i64 tcg_res
[2];
9069 for (pass
= 0; pass
< 2; pass
++) {
9070 static NeonGenWidenFn
* const widenfns
[3] = {
9071 gen_helper_neon_widen_u8
,
9072 gen_helper_neon_widen_u16
,
9073 tcg_gen_extu_i32_i64
,
9075 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9076 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9078 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9079 tcg_res
[pass
] = tcg_temp_new_i64();
9080 widenfn(tcg_res
[pass
], tcg_op
);
9081 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9083 tcg_temp_free_i32(tcg_op
);
9086 for (pass
= 0; pass
< 2; pass
++) {
9087 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9088 tcg_temp_free_i64(tcg_res
[pass
]);
9092 /* C3.6.17 AdvSIMD two reg misc
9093 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9094 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9095 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9096 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9098 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9100 int size
= extract32(insn
, 22, 2);
9101 int opcode
= extract32(insn
, 12, 5);
9102 bool u
= extract32(insn
, 29, 1);
9103 bool is_q
= extract32(insn
, 30, 1);
9104 int rn
= extract32(insn
, 5, 5);
9105 int rd
= extract32(insn
, 0, 5);
9106 bool need_fpstatus
= false;
9107 bool need_rmode
= false;
9110 TCGv_ptr tcg_fpstatus
;
9113 case 0x0: /* REV64, REV32 */
9114 case 0x1: /* REV16 */
9115 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9117 case 0x5: /* CNT, NOT, RBIT */
9118 if (u
&& size
== 0) {
9119 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9122 } else if (u
&& size
== 1) {
9125 } else if (!u
&& size
== 0) {
9129 unallocated_encoding(s
);
9131 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9132 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9134 unallocated_encoding(s
);
9137 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9139 case 0x4: /* CLS, CLZ */
9141 unallocated_encoding(s
);
9145 case 0x2: /* SADDLP, UADDLP */
9146 case 0x6: /* SADALP, UADALP */
9148 unallocated_encoding(s
);
9151 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9153 case 0x13: /* SHLL, SHLL2 */
9154 if (u
== 0 || size
== 3) {
9155 unallocated_encoding(s
);
9158 handle_shll(s
, is_q
, size
, rn
, rd
);
9160 case 0xa: /* CMLT */
9162 unallocated_encoding(s
);
9166 case 0x8: /* CMGT, CMGE */
9167 case 0x9: /* CMEQ, CMLE */
9168 case 0xb: /* ABS, NEG */
9169 if (size
== 3 && !is_q
) {
9170 unallocated_encoding(s
);
9174 case 0x3: /* SUQADD, USQADD */
9175 case 0x7: /* SQABS, SQNEG */
9176 if (size
== 3 && !is_q
) {
9177 unallocated_encoding(s
);
9180 unsupported_encoding(s
, insn
);
9186 /* Floating point: U, size[1] and opcode indicate operation;
9187 * size[0] indicates single or double precision.
9189 int is_double
= extract32(size
, 0, 1);
9190 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9191 size
= is_double
? 3 : 2;
9193 case 0x2f: /* FABS */
9194 case 0x6f: /* FNEG */
9195 if (size
== 3 && !is_q
) {
9196 unallocated_encoding(s
);
9200 case 0x1d: /* SCVTF */
9201 case 0x5d: /* UCVTF */
9203 bool is_signed
= (opcode
== 0x1d) ? true : false;
9204 int elements
= is_double
? 2 : is_q
? 4 : 2;
9205 if (is_double
&& !is_q
) {
9206 unallocated_encoding(s
);
9209 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9212 case 0x2c: /* FCMGT (zero) */
9213 case 0x2d: /* FCMEQ (zero) */
9214 case 0x2e: /* FCMLT (zero) */
9215 case 0x6c: /* FCMGE (zero) */
9216 case 0x6d: /* FCMLE (zero) */
9217 if (size
== 3 && !is_q
) {
9218 unallocated_encoding(s
);
9221 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9223 case 0x7f: /* FSQRT */
9224 if (size
== 3 && !is_q
) {
9225 unallocated_encoding(s
);
9229 case 0x1a: /* FCVTNS */
9230 case 0x1b: /* FCVTMS */
9231 case 0x3a: /* FCVTPS */
9232 case 0x3b: /* FCVTZS */
9233 case 0x5a: /* FCVTNU */
9234 case 0x5b: /* FCVTMU */
9235 case 0x7a: /* FCVTPU */
9236 case 0x7b: /* FCVTZU */
9237 need_fpstatus
= true;
9239 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9240 if (size
== 3 && !is_q
) {
9241 unallocated_encoding(s
);
9245 case 0x5c: /* FCVTAU */
9246 case 0x1c: /* FCVTAS */
9247 need_fpstatus
= true;
9249 rmode
= FPROUNDING_TIEAWAY
;
9250 if (size
== 3 && !is_q
) {
9251 unallocated_encoding(s
);
9255 case 0x3c: /* URECPE */
9257 unallocated_encoding(s
);
9261 case 0x3d: /* FRECPE */
9262 case 0x7d: /* FRSQRTE */
9263 if (size
== 3 && !is_q
) {
9264 unallocated_encoding(s
);
9267 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9269 case 0x56: /* FCVTXN, FCVTXN2 */
9271 unallocated_encoding(s
);
9275 case 0x16: /* FCVTN, FCVTN2 */
9276 /* handle_2misc_narrow does a 2*size -> size operation, but these
9277 * instructions encode the source size rather than dest size.
9279 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9281 case 0x17: /* FCVTL, FCVTL2 */
9282 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9284 case 0x18: /* FRINTN */
9285 case 0x19: /* FRINTM */
9286 case 0x38: /* FRINTP */
9287 case 0x39: /* FRINTZ */
9289 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9291 case 0x59: /* FRINTX */
9292 case 0x79: /* FRINTI */
9293 need_fpstatus
= true;
9294 if (size
== 3 && !is_q
) {
9295 unallocated_encoding(s
);
9299 case 0x58: /* FRINTA */
9301 rmode
= FPROUNDING_TIEAWAY
;
9302 need_fpstatus
= true;
9303 if (size
== 3 && !is_q
) {
9304 unallocated_encoding(s
);
9308 case 0x7c: /* URSQRTE */
9310 unallocated_encoding(s
);
9313 need_fpstatus
= true;
9316 unallocated_encoding(s
);
9322 unallocated_encoding(s
);
9326 if (need_fpstatus
) {
9327 tcg_fpstatus
= get_fpstatus_ptr();
9329 TCGV_UNUSED_PTR(tcg_fpstatus
);
9332 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9333 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9335 TCGV_UNUSED_I32(tcg_rmode
);
9339 /* All 64-bit element operations can be shared with scalar 2misc */
9342 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9343 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9344 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9346 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9348 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
9349 tcg_rmode
, tcg_fpstatus
);
9351 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9353 tcg_temp_free_i64(tcg_res
);
9354 tcg_temp_free_i64(tcg_op
);
9359 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9360 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9361 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9364 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9367 /* Special cases for 32 bit elements */
9369 case 0xa: /* CMLT */
9370 /* 32 bit integer comparison against zero, result is
9371 * test ? (2^32 - 1) : 0. We implement via setcond(test)
9376 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
9377 tcg_gen_neg_i32(tcg_res
, tcg_res
);
9379 case 0x8: /* CMGT, CMGE */
9380 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9382 case 0x9: /* CMEQ, CMLE */
9383 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9387 gen_helper_clz32(tcg_res
, tcg_op
);
9389 gen_helper_cls32(tcg_res
, tcg_op
);
9392 case 0xb: /* ABS, NEG */
9394 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9396 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9397 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9398 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
9399 tcg_zero
, tcg_op
, tcg_res
);
9400 tcg_temp_free_i32(tcg_zero
);
9403 case 0x2f: /* FABS */
9404 gen_helper_vfp_abss(tcg_res
, tcg_op
);
9406 case 0x6f: /* FNEG */
9407 gen_helper_vfp_negs(tcg_res
, tcg_op
);
9409 case 0x7f: /* FSQRT */
9410 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
9412 case 0x1a: /* FCVTNS */
9413 case 0x1b: /* FCVTMS */
9414 case 0x1c: /* FCVTAS */
9415 case 0x3a: /* FCVTPS */
9416 case 0x3b: /* FCVTZS */
9418 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9419 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
9420 tcg_shift
, tcg_fpstatus
);
9421 tcg_temp_free_i32(tcg_shift
);
9424 case 0x5a: /* FCVTNU */
9425 case 0x5b: /* FCVTMU */
9426 case 0x5c: /* FCVTAU */
9427 case 0x7a: /* FCVTPU */
9428 case 0x7b: /* FCVTZU */
9430 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9431 gen_helper_vfp_touls(tcg_res
, tcg_op
,
9432 tcg_shift
, tcg_fpstatus
);
9433 tcg_temp_free_i32(tcg_shift
);
9436 case 0x18: /* FRINTN */
9437 case 0x19: /* FRINTM */
9438 case 0x38: /* FRINTP */
9439 case 0x39: /* FRINTZ */
9440 case 0x58: /* FRINTA */
9441 case 0x79: /* FRINTI */
9442 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
9444 case 0x59: /* FRINTX */
9445 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
9447 case 0x7c: /* URSQRTE */
9448 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
9451 g_assert_not_reached();
9454 /* Use helpers for 8 and 16 bit elements */
9456 case 0x5: /* CNT, RBIT */
9457 /* For these two insns size is part of the opcode specifier
9458 * (handled earlier); they always operate on byte elements.
9461 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
9463 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
9466 case 0x8: /* CMGT, CMGE */
9467 case 0x9: /* CMEQ, CMLE */
9468 case 0xa: /* CMLT */
9470 static NeonGenTwoOpFn
* const fns
[3][2] = {
9471 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
9472 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
9473 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
9475 NeonGenTwoOpFn
*genfn
;
9478 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9480 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
9481 comp
= (opcode
- 0x8) * 2 + u
;
9482 /* ...but LE, LT are implemented as reverse GE, GT */
9483 reverse
= (comp
> 2);
9487 genfn
= fns
[comp
][size
];
9489 genfn(tcg_res
, tcg_zero
, tcg_op
);
9491 genfn(tcg_res
, tcg_op
, tcg_zero
);
9493 tcg_temp_free_i32(tcg_zero
);
9496 case 0xb: /* ABS, NEG */
9498 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9500 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
9502 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
9504 tcg_temp_free_i32(tcg_zero
);
9507 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
9509 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
9513 case 0x4: /* CLS, CLZ */
9516 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
9518 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
9522 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
9524 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
9529 g_assert_not_reached();
9533 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9535 tcg_temp_free_i32(tcg_res
);
9536 tcg_temp_free_i32(tcg_op
);
9540 clear_vec_high(s
, rd
);
9544 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9545 tcg_temp_free_i32(tcg_rmode
);
9547 if (need_fpstatus
) {
9548 tcg_temp_free_ptr(tcg_fpstatus
);
9552 /* C3.6.13 AdvSIMD scalar x indexed element
9553 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
9554 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
9555 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
9556 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
9557 * C3.6.18 AdvSIMD vector x indexed element
9558 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
9559 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
9560 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
9561 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
9563 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
9565 /* This encoding has two kinds of instruction:
9566 * normal, where we perform elt x idxelt => elt for each
9567 * element in the vector
9568 * long, where we perform elt x idxelt and generate a result of
9569 * double the width of the input element
9570 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
9572 bool is_scalar
= extract32(insn
, 28, 1);
9573 bool is_q
= extract32(insn
, 30, 1);
9574 bool u
= extract32(insn
, 29, 1);
9575 int size
= extract32(insn
, 22, 2);
9576 int l
= extract32(insn
, 21, 1);
9577 int m
= extract32(insn
, 20, 1);
9578 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
9579 int rm
= extract32(insn
, 16, 4);
9580 int opcode
= extract32(insn
, 12, 4);
9581 int h
= extract32(insn
, 11, 1);
9582 int rn
= extract32(insn
, 5, 5);
9583 int rd
= extract32(insn
, 0, 5);
9584 bool is_long
= false;
9592 if (!u
|| is_scalar
) {
9593 unallocated_encoding(s
);
9597 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9598 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9599 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
9601 unallocated_encoding(s
);
9606 case 0x3: /* SQDMLAL, SQDMLAL2 */
9607 case 0x7: /* SQDMLSL, SQDMLSL2 */
9608 case 0xb: /* SQDMULL, SQDMULL2 */
9611 case 0xc: /* SQDMULH */
9612 case 0xd: /* SQRDMULH */
9614 unallocated_encoding(s
);
9619 if (u
|| is_scalar
) {
9620 unallocated_encoding(s
);
9624 case 0x1: /* FMLA */
9625 case 0x5: /* FMLS */
9627 unallocated_encoding(s
);
9631 case 0x9: /* FMUL, FMULX */
9632 if (!extract32(size
, 1, 1)) {
9633 unallocated_encoding(s
);
9639 unallocated_encoding(s
);
9644 /* low bit of size indicates single/double */
9645 size
= extract32(size
, 0, 1) ? 3 : 2;
9650 unallocated_encoding(s
);
9659 index
= h
<< 2 | l
<< 1 | m
;
9666 unallocated_encoding(s
);
9672 fpst
= get_fpstatus_ptr();
9674 TCGV_UNUSED_PTR(fpst
);
9678 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
9681 assert(is_fp
&& is_q
&& !is_long
);
9683 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
9685 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9686 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9687 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9689 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9692 case 0x5: /* FMLS */
9693 /* As usual for ARM, separate negation for fused multiply-add */
9694 gen_helper_vfp_negd(tcg_op
, tcg_op
);
9696 case 0x1: /* FMLA */
9697 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9698 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
9700 case 0x9: /* FMUL, FMULX */
9702 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
9704 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
9708 g_assert_not_reached();
9711 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9712 tcg_temp_free_i64(tcg_op
);
9713 tcg_temp_free_i64(tcg_res
);
9717 clear_vec_high(s
, rd
);
9720 tcg_temp_free_i64(tcg_idx
);
9721 } else if (!is_long
) {
9722 /* 32 bit floating point, or 16 or 32 bit integer.
9723 * For the 16 bit scalar case we use the usual Neon helpers and
9724 * rely on the fact that 0 op 0 == 0 with no side effects.
9726 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
9727 int pass
, maxpasses
;
9732 maxpasses
= is_q
? 4 : 2;
9735 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
9737 if (size
== 1 && !is_scalar
) {
9738 /* The simplest way to handle the 16x16 indexed ops is to duplicate
9739 * the index into both halves of the 32 bit tcg_idx and then use
9740 * the usual Neon helpers.
9742 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
9745 for (pass
= 0; pass
< maxpasses
; pass
++) {
9746 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9747 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9749 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
9756 static NeonGenTwoOpFn
* const fns
[2][2] = {
9757 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9758 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9760 NeonGenTwoOpFn
*genfn
;
9761 bool is_sub
= opcode
== 0x4;
9764 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
9766 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
9768 if (opcode
== 0x8) {
9771 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
9772 genfn
= fns
[size
- 1][is_sub
];
9773 genfn(tcg_res
, tcg_op
, tcg_res
);
9776 case 0x5: /* FMLS */
9777 /* As usual for ARM, separate negation for fused multiply-add */
9778 gen_helper_vfp_negs(tcg_op
, tcg_op
);
9780 case 0x1: /* FMLA */
9781 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9782 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
9784 case 0x9: /* FMUL, FMULX */
9786 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
9788 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
9791 case 0xc: /* SQDMULH */
9793 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
9796 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
9800 case 0xd: /* SQRDMULH */
9802 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
9805 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
9810 g_assert_not_reached();
9814 write_fp_sreg(s
, rd
, tcg_res
);
9816 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9819 tcg_temp_free_i32(tcg_op
);
9820 tcg_temp_free_i32(tcg_res
);
9823 tcg_temp_free_i32(tcg_idx
);
9826 clear_vec_high(s
, rd
);
9829 /* long ops: 16x16->32 or 32x32->64 */
9830 TCGv_i64 tcg_res
[2];
9832 bool satop
= extract32(opcode
, 0, 1);
9833 TCGMemOp memop
= MO_32
;
9840 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
9842 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
9844 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9845 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9846 TCGv_i64 tcg_passres
;
9852 passelt
= pass
+ (is_q
* 2);
9855 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
9857 tcg_res
[pass
] = tcg_temp_new_i64();
9859 if (opcode
== 0xa || opcode
== 0xb) {
9860 /* Non-accumulating ops */
9861 tcg_passres
= tcg_res
[pass
];
9863 tcg_passres
= tcg_temp_new_i64();
9866 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
9867 tcg_temp_free_i64(tcg_op
);
9870 /* saturating, doubling */
9871 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
9872 tcg_passres
, tcg_passres
);
9875 if (opcode
== 0xa || opcode
== 0xb) {
9879 /* Accumulating op: handle accumulate step */
9880 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9883 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9884 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
9886 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9887 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
9889 case 0x7: /* SQDMLSL, SQDMLSL2 */
9890 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
9892 case 0x3: /* SQDMLAL, SQDMLAL2 */
9893 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
9898 g_assert_not_reached();
9900 tcg_temp_free_i64(tcg_passres
);
9902 tcg_temp_free_i64(tcg_idx
);
9905 clear_vec_high(s
, rd
);
9908 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
9911 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
9914 /* The simplest way to handle the 16x16 indexed ops is to
9915 * duplicate the index into both halves of the 32 bit tcg_idx
9916 * and then use the usual Neon helpers.
9918 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
9921 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9922 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9923 TCGv_i64 tcg_passres
;
9926 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9928 read_vec_element_i32(s
, tcg_op
, rn
,
9929 pass
+ (is_q
* 2), MO_32
);
9932 tcg_res
[pass
] = tcg_temp_new_i64();
9934 if (opcode
== 0xa || opcode
== 0xb) {
9935 /* Non-accumulating ops */
9936 tcg_passres
= tcg_res
[pass
];
9938 tcg_passres
= tcg_temp_new_i64();
9941 if (memop
& MO_SIGN
) {
9942 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
9944 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
9947 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
9948 tcg_passres
, tcg_passres
);
9950 tcg_temp_free_i32(tcg_op
);
9952 if (opcode
== 0xa || opcode
== 0xb) {
9956 /* Accumulating op: handle accumulate step */
9957 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9960 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9961 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
9964 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9965 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
9968 case 0x7: /* SQDMLSL, SQDMLSL2 */
9969 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
9971 case 0x3: /* SQDMLAL, SQDMLAL2 */
9972 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
9977 g_assert_not_reached();
9979 tcg_temp_free_i64(tcg_passres
);
9981 tcg_temp_free_i32(tcg_idx
);
9984 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
9989 tcg_res
[1] = tcg_const_i64(0);
9992 for (pass
= 0; pass
< 2; pass
++) {
9993 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9994 tcg_temp_free_i64(tcg_res
[pass
]);
9998 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9999 tcg_temp_free_ptr(fpst
);
10003 /* C3.6.19 Crypto AES
10004 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10005 * +-----------------+------+-----------+--------+-----+------+------+
10006 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10007 * +-----------------+------+-----------+--------+-----+------+------+
10009 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10011 unsupported_encoding(s
, insn
);
10014 /* C3.6.20 Crypto three-reg SHA
10015 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10016 * +-----------------+------+---+------+---+--------+-----+------+------+
10017 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10018 * +-----------------+------+---+------+---+--------+-----+------+------+
10020 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10022 unsupported_encoding(s
, insn
);
10025 /* C3.6.21 Crypto two-reg SHA
10026 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10027 * +-----------------+------+-----------+--------+-----+------+------+
10028 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10029 * +-----------------+------+-----------+--------+-----+------+------+
10031 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10033 unsupported_encoding(s
, insn
);
10036 /* C3.6 Data processing - SIMD, inc Crypto
10038 * As the decode gets a little complex we are using a table based
10039 * approach for this part of the decode.
10041 static const AArch64DecodeTable data_proc_simd
[] = {
10042 /* pattern , mask , fn */
10043 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10044 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10045 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10046 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10047 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10048 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10049 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10050 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10051 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10052 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10053 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10054 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10055 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10056 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10057 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10058 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10059 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10060 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10061 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10062 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10063 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10064 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10065 { 0x00000000, 0x00000000, NULL
}
10068 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10070 /* Note that this is called with all non-FP cases from
10071 * table C3-6 so it must UNDEF for entries not specifically
10072 * allocated to instructions in that table.
10074 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10078 unallocated_encoding(s
);
10082 /* C3.6 Data processing - SIMD and floating point */
10083 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10085 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10086 disas_data_proc_fp(s
, insn
);
10088 /* SIMD, including crypto */
10089 disas_data_proc_simd(s
, insn
);
10093 /* C3.1 A64 instruction index by encoding */
10094 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10098 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
10102 switch (extract32(insn
, 25, 4)) {
10103 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10104 unallocated_encoding(s
);
10106 case 0x8: case 0x9: /* Data processing - immediate */
10107 disas_data_proc_imm(s
, insn
);
10109 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10110 disas_b_exc_sys(s
, insn
);
10115 case 0xe: /* Loads and stores */
10116 disas_ldst(s
, insn
);
10119 case 0xd: /* Data processing - register */
10120 disas_data_proc_reg(s
, insn
);
10123 case 0xf: /* Data processing - SIMD and floating point */
10124 disas_data_proc_simd_fp(s
, insn
);
10127 assert(FALSE
); /* all 15 cases should be handled above */
10131 /* if we allocated any temporaries, free them here */
10135 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
10136 TranslationBlock
*tb
,
10139 CPUState
*cs
= CPU(cpu
);
10140 CPUARMState
*env
= &cpu
->env
;
10141 DisasContext dc1
, *dc
= &dc1
;
10143 uint16_t *gen_opc_end
;
10145 target_ulong pc_start
;
10146 target_ulong next_page_start
;
10154 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
10156 dc
->is_jmp
= DISAS_NEXT
;
10158 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
10163 dc
->bswap_code
= 0;
10164 dc
->condexec_mask
= 0;
10165 dc
->condexec_cond
= 0;
10166 #if !defined(CONFIG_USER_ONLY)
10167 dc
->user
= (ARM_TBFLAG_AA64_EL(tb
->flags
) == 0);
10169 dc
->vfp_enabled
= 0;
10171 dc
->vec_stride
= 0;
10172 dc
->cp_regs
= cpu
->cp_regs
;
10173 dc
->current_pl
= arm_current_pl(env
);
10174 dc
->features
= env
->features
;
10176 init_tmp_a64_array(dc
);
10178 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
10181 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
10182 if (max_insns
== 0) {
10183 max_insns
= CF_COUNT_MASK
;
10188 tcg_clear_temp_count();
10191 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
10192 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
10193 if (bp
->pc
== dc
->pc
) {
10194 gen_exception_insn(dc
, 0, EXCP_DEBUG
);
10195 /* Advance PC so that clearing the breakpoint will
10196 invalidate this TB. */
10198 goto done_generating
;
10204 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10208 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10211 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
10212 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
10213 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
10216 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
10220 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
10221 tcg_gen_debug_insn_start(dc
->pc
);
10224 disas_a64_insn(env
, dc
);
10226 if (tcg_check_temp_count()) {
10227 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
10231 /* Translation stops when a conditional branch is encountered.
10232 * Otherwise the subsequent code could get translated several times.
10233 * Also stop translation when a page boundary is reached. This
10234 * ensures prefetch aborts occur at the right place.
10237 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
10238 !cs
->singlestep_enabled
&&
10240 dc
->pc
< next_page_start
&&
10241 num_insns
< max_insns
);
10243 if (tb
->cflags
& CF_LAST_IO
) {
10247 if (unlikely(cs
->singlestep_enabled
) && dc
->is_jmp
!= DISAS_EXC
) {
10248 /* Note that this means single stepping WFI doesn't halt the CPU.
10249 * For conditional branch insns this is harmless unreachable code as
10250 * gen_goto_tb() has already handled emitting the debug exception
10251 * (and thus a tb-jump is not possible when singlestepping).
10253 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
10254 if (dc
->is_jmp
!= DISAS_JUMP
) {
10255 gen_a64_set_pc_im(dc
->pc
);
10257 gen_exception(EXCP_DEBUG
);
10259 switch (dc
->is_jmp
) {
10261 gen_goto_tb(dc
, 1, dc
->pc
);
10265 gen_a64_set_pc_im(dc
->pc
);
10268 /* indicate that the hash table must be used to find the next TB */
10269 tcg_gen_exit_tb(0);
10271 case DISAS_TB_JUMP
:
10276 /* This is a special case because we don't want to just halt the CPU
10277 * if trying to debug across a WFI.
10279 gen_a64_set_pc_im(dc
->pc
);
10280 gen_helper_wfi(cpu_env
);
10286 gen_tb_end(tb
, num_insns
);
10287 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
10290 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
10291 qemu_log("----------------\n");
10292 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
10293 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
10294 4 | (dc
->bswap_code
<< 1));
10299 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10302 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10305 tb
->size
= dc
->pc
- pc_start
;
10306 tb
->icount
= num_insns
;