2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "exec/address-spaces.h"
25 #include "intel_iommu_internal.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/i386/pc.h"
29 #include "hw/boards.h"
30 #include "hw/i386/x86-iommu.h"
32 /*#define DEBUG_INTEL_IOMMU*/
33 #ifdef DEBUG_INTEL_IOMMU
35 DEBUG_GENERAL
, DEBUG_CSR
, DEBUG_INV
, DEBUG_MMU
, DEBUG_FLOG
,
38 #define VTD_DBGBIT(x) (1 << DEBUG_##x)
39 static int vtd_dbgflags
= VTD_DBGBIT(GENERAL
) | VTD_DBGBIT(CSR
);
41 #define VTD_DPRINTF(what, fmt, ...) do { \
42 if (vtd_dbgflags & VTD_DBGBIT(what)) { \
43 fprintf(stderr, "(vtd)%s: " fmt "\n", __func__, \
47 #define VTD_DPRINTF(what, fmt, ...) do {} while (0)
50 static void vtd_define_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
,
51 uint64_t wmask
, uint64_t w1cmask
)
53 stq_le_p(&s
->csr
[addr
], val
);
54 stq_le_p(&s
->wmask
[addr
], wmask
);
55 stq_le_p(&s
->w1cmask
[addr
], w1cmask
);
58 static void vtd_define_quad_wo(IntelIOMMUState
*s
, hwaddr addr
, uint64_t mask
)
60 stq_le_p(&s
->womask
[addr
], mask
);
63 static void vtd_define_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
,
64 uint32_t wmask
, uint32_t w1cmask
)
66 stl_le_p(&s
->csr
[addr
], val
);
67 stl_le_p(&s
->wmask
[addr
], wmask
);
68 stl_le_p(&s
->w1cmask
[addr
], w1cmask
);
71 static void vtd_define_long_wo(IntelIOMMUState
*s
, hwaddr addr
, uint32_t mask
)
73 stl_le_p(&s
->womask
[addr
], mask
);
76 /* "External" get/set operations */
77 static void vtd_set_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
79 uint64_t oldval
= ldq_le_p(&s
->csr
[addr
]);
80 uint64_t wmask
= ldq_le_p(&s
->wmask
[addr
]);
81 uint64_t w1cmask
= ldq_le_p(&s
->w1cmask
[addr
]);
82 stq_le_p(&s
->csr
[addr
],
83 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
86 static void vtd_set_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
)
88 uint32_t oldval
= ldl_le_p(&s
->csr
[addr
]);
89 uint32_t wmask
= ldl_le_p(&s
->wmask
[addr
]);
90 uint32_t w1cmask
= ldl_le_p(&s
->w1cmask
[addr
]);
91 stl_le_p(&s
->csr
[addr
],
92 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
95 static uint64_t vtd_get_quad(IntelIOMMUState
*s
, hwaddr addr
)
97 uint64_t val
= ldq_le_p(&s
->csr
[addr
]);
98 uint64_t womask
= ldq_le_p(&s
->womask
[addr
]);
102 static uint32_t vtd_get_long(IntelIOMMUState
*s
, hwaddr addr
)
104 uint32_t val
= ldl_le_p(&s
->csr
[addr
]);
105 uint32_t womask
= ldl_le_p(&s
->womask
[addr
]);
106 return val
& ~womask
;
109 /* "Internal" get/set operations */
110 static uint64_t vtd_get_quad_raw(IntelIOMMUState
*s
, hwaddr addr
)
112 return ldq_le_p(&s
->csr
[addr
]);
115 static uint32_t vtd_get_long_raw(IntelIOMMUState
*s
, hwaddr addr
)
117 return ldl_le_p(&s
->csr
[addr
]);
120 static void vtd_set_quad_raw(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
122 stq_le_p(&s
->csr
[addr
], val
);
125 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState
*s
, hwaddr addr
,
126 uint32_t clear
, uint32_t mask
)
128 uint32_t new_val
= (ldl_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
129 stl_le_p(&s
->csr
[addr
], new_val
);
133 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState
*s
, hwaddr addr
,
134 uint64_t clear
, uint64_t mask
)
136 uint64_t new_val
= (ldq_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
137 stq_le_p(&s
->csr
[addr
], new_val
);
141 /* GHashTable functions */
142 static gboolean
vtd_uint64_equal(gconstpointer v1
, gconstpointer v2
)
144 return *((const uint64_t *)v1
) == *((const uint64_t *)v2
);
147 static guint
vtd_uint64_hash(gconstpointer v
)
149 return (guint
)*(const uint64_t *)v
;
152 static gboolean
vtd_hash_remove_by_domain(gpointer key
, gpointer value
,
155 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
156 uint16_t domain_id
= *(uint16_t *)user_data
;
157 return entry
->domain_id
== domain_id
;
160 /* The shift of an addr for a certain level of paging structure */
161 static inline uint32_t vtd_slpt_level_shift(uint32_t level
)
163 return VTD_PAGE_SHIFT_4K
+ (level
- 1) * VTD_SL_LEVEL_BITS
;
166 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level
)
168 return ~((1ULL << vtd_slpt_level_shift(level
)) - 1);
171 static gboolean
vtd_hash_remove_by_page(gpointer key
, gpointer value
,
174 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
175 VTDIOTLBPageInvInfo
*info
= (VTDIOTLBPageInvInfo
*)user_data
;
176 uint64_t gfn
= (info
->addr
>> VTD_PAGE_SHIFT_4K
) & info
->mask
;
177 uint64_t gfn_tlb
= (info
->addr
& entry
->mask
) >> VTD_PAGE_SHIFT_4K
;
178 return (entry
->domain_id
== info
->domain_id
) &&
179 (((entry
->gfn
& info
->mask
) == gfn
) ||
180 (entry
->gfn
== gfn_tlb
));
183 /* Reset all the gen of VTDAddressSpace to zero and set the gen of
184 * IntelIOMMUState to 1.
186 static void vtd_reset_context_cache(IntelIOMMUState
*s
)
188 VTDAddressSpace
*vtd_as
;
190 GHashTableIter bus_it
;
193 g_hash_table_iter_init(&bus_it
, s
->vtd_as_by_busptr
);
195 VTD_DPRINTF(CACHE
, "global context_cache_gen=1");
196 while (g_hash_table_iter_next (&bus_it
, NULL
, (void**)&vtd_bus
)) {
197 for (devfn_it
= 0; devfn_it
< X86_IOMMU_PCI_DEVFN_MAX
; ++devfn_it
) {
198 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
202 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
205 s
->context_cache_gen
= 1;
208 static void vtd_reset_iotlb(IntelIOMMUState
*s
)
211 g_hash_table_remove_all(s
->iotlb
);
214 static uint64_t vtd_get_iotlb_key(uint64_t gfn
, uint8_t source_id
,
217 return gfn
| ((uint64_t)(source_id
) << VTD_IOTLB_SID_SHIFT
) |
218 ((uint64_t)(level
) << VTD_IOTLB_LVL_SHIFT
);
221 static uint64_t vtd_get_iotlb_gfn(hwaddr addr
, uint32_t level
)
223 return (addr
& vtd_slpt_level_page_mask(level
)) >> VTD_PAGE_SHIFT_4K
;
226 static VTDIOTLBEntry
*vtd_lookup_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
229 VTDIOTLBEntry
*entry
;
233 for (level
= VTD_SL_PT_LEVEL
; level
< VTD_SL_PML4_LEVEL
; level
++) {
234 key
= vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr
, level
),
236 entry
= g_hash_table_lookup(s
->iotlb
, &key
);
246 static void vtd_update_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
247 uint16_t domain_id
, hwaddr addr
, uint64_t slpte
,
248 bool read_flags
, bool write_flags
,
251 VTDIOTLBEntry
*entry
= g_malloc(sizeof(*entry
));
252 uint64_t *key
= g_malloc(sizeof(*key
));
253 uint64_t gfn
= vtd_get_iotlb_gfn(addr
, level
);
255 VTD_DPRINTF(CACHE
, "update iotlb sid 0x%"PRIx16
" gpa 0x%"PRIx64
256 " slpte 0x%"PRIx64
" did 0x%"PRIx16
, source_id
, addr
, slpte
,
258 if (g_hash_table_size(s
->iotlb
) >= VTD_IOTLB_MAX_SIZE
) {
259 VTD_DPRINTF(CACHE
, "iotlb exceeds size limit, forced to reset");
264 entry
->domain_id
= domain_id
;
265 entry
->slpte
= slpte
;
266 entry
->read_flags
= read_flags
;
267 entry
->write_flags
= write_flags
;
268 entry
->mask
= vtd_slpt_level_page_mask(level
);
269 *key
= vtd_get_iotlb_key(gfn
, source_id
, level
);
270 g_hash_table_replace(s
->iotlb
, key
, entry
);
273 /* Given the reg addr of both the message data and address, generate an
276 static void vtd_generate_interrupt(IntelIOMMUState
*s
, hwaddr mesg_addr_reg
,
277 hwaddr mesg_data_reg
)
282 assert(mesg_data_reg
< DMAR_REG_SIZE
);
283 assert(mesg_addr_reg
< DMAR_REG_SIZE
);
285 addr
= vtd_get_long_raw(s
, mesg_addr_reg
);
286 data
= vtd_get_long_raw(s
, mesg_data_reg
);
288 VTD_DPRINTF(FLOG
, "msi: addr 0x%"PRIx64
" data 0x%"PRIx32
, addr
, data
);
289 address_space_stl_le(&address_space_memory
, addr
, data
,
290 MEMTXATTRS_UNSPECIFIED
, NULL
);
293 /* Generate a fault event to software via MSI if conditions are met.
294 * Notice that the value of FSTS_REG being passed to it should be the one
297 static void vtd_generate_fault_event(IntelIOMMUState
*s
, uint32_t pre_fsts
)
299 if (pre_fsts
& VTD_FSTS_PPF
|| pre_fsts
& VTD_FSTS_PFO
||
300 pre_fsts
& VTD_FSTS_IQE
) {
301 VTD_DPRINTF(FLOG
, "there are previous interrupt conditions "
302 "to be serviced by software, fault event is not generated "
303 "(FSTS_REG 0x%"PRIx32
")", pre_fsts
);
306 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, 0, VTD_FECTL_IP
);
307 if (vtd_get_long_raw(s
, DMAR_FECTL_REG
) & VTD_FECTL_IM
) {
308 VTD_DPRINTF(FLOG
, "Interrupt Mask set, fault event is not generated");
310 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
311 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
315 /* Check if the Fault (F) field of the Fault Recording Register referenced by
318 static bool vtd_is_frcd_set(IntelIOMMUState
*s
, uint16_t index
)
320 /* Each reg is 128-bit */
321 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
322 addr
+= 8; /* Access the high 64-bit half */
324 assert(index
< DMAR_FRCD_REG_NR
);
326 return vtd_get_quad_raw(s
, addr
) & VTD_FRCD_F
;
329 /* Update the PPF field of Fault Status Register.
330 * Should be called whenever change the F field of any fault recording
333 static void vtd_update_fsts_ppf(IntelIOMMUState
*s
)
336 uint32_t ppf_mask
= 0;
338 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
339 if (vtd_is_frcd_set(s
, i
)) {
340 ppf_mask
= VTD_FSTS_PPF
;
344 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_PPF
, ppf_mask
);
345 VTD_DPRINTF(FLOG
, "set PPF of FSTS_REG to %d", ppf_mask
? 1 : 0);
348 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState
*s
, uint16_t index
)
350 /* Each reg is 128-bit */
351 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
352 addr
+= 8; /* Access the high 64-bit half */
354 assert(index
< DMAR_FRCD_REG_NR
);
356 vtd_set_clear_mask_quad(s
, addr
, 0, VTD_FRCD_F
);
357 vtd_update_fsts_ppf(s
);
360 /* Must not update F field now, should be done later */
361 static void vtd_record_frcd(IntelIOMMUState
*s
, uint16_t index
,
362 uint16_t source_id
, hwaddr addr
,
363 VTDFaultReason fault
, bool is_write
)
366 hwaddr frcd_reg_addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
368 assert(index
< DMAR_FRCD_REG_NR
);
370 lo
= VTD_FRCD_FI(addr
);
371 hi
= VTD_FRCD_SID(source_id
) | VTD_FRCD_FR(fault
);
375 vtd_set_quad_raw(s
, frcd_reg_addr
, lo
);
376 vtd_set_quad_raw(s
, frcd_reg_addr
+ 8, hi
);
377 VTD_DPRINTF(FLOG
, "record to FRCD_REG #%"PRIu16
": hi 0x%"PRIx64
378 ", lo 0x%"PRIx64
, index
, hi
, lo
);
381 /* Try to collapse multiple pending faults from the same requester */
382 static bool vtd_try_collapse_fault(IntelIOMMUState
*s
, uint16_t source_id
)
386 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ 8; /* The high 64-bit half */
388 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
389 frcd_reg
= vtd_get_quad_raw(s
, addr
);
390 VTD_DPRINTF(FLOG
, "frcd_reg #%d 0x%"PRIx64
, i
, frcd_reg
);
391 if ((frcd_reg
& VTD_FRCD_F
) &&
392 ((frcd_reg
& VTD_FRCD_SID_MASK
) == source_id
)) {
395 addr
+= 16; /* 128-bit for each */
400 /* Log and report an DMAR (address translation) fault to software */
401 static void vtd_report_dmar_fault(IntelIOMMUState
*s
, uint16_t source_id
,
402 hwaddr addr
, VTDFaultReason fault
,
405 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
407 assert(fault
< VTD_FR_MAX
);
409 if (fault
== VTD_FR_RESERVED_ERR
) {
410 /* This is not a normal fault reason case. Drop it. */
413 VTD_DPRINTF(FLOG
, "sid 0x%"PRIx16
", fault %d, addr 0x%"PRIx64
414 ", is_write %d", source_id
, fault
, addr
, is_write
);
415 if (fsts_reg
& VTD_FSTS_PFO
) {
416 VTD_DPRINTF(FLOG
, "new fault is not recorded due to "
417 "Primary Fault Overflow");
420 if (vtd_try_collapse_fault(s
, source_id
)) {
421 VTD_DPRINTF(FLOG
, "new fault is not recorded due to "
422 "compression of faults");
425 if (vtd_is_frcd_set(s
, s
->next_frcd_reg
)) {
426 VTD_DPRINTF(FLOG
, "Primary Fault Overflow and "
427 "new fault is not recorded, set PFO field");
428 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_PFO
);
432 vtd_record_frcd(s
, s
->next_frcd_reg
, source_id
, addr
, fault
, is_write
);
434 if (fsts_reg
& VTD_FSTS_PPF
) {
435 VTD_DPRINTF(FLOG
, "there are pending faults already, "
436 "fault event is not generated");
437 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
);
439 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
440 s
->next_frcd_reg
= 0;
443 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_FRI_MASK
,
444 VTD_FSTS_FRI(s
->next_frcd_reg
));
445 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
); /* Will set PPF */
447 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
448 s
->next_frcd_reg
= 0;
450 /* This case actually cause the PPF to be Set.
451 * So generate fault event (interrupt).
453 vtd_generate_fault_event(s
, fsts_reg
);
457 /* Handle Invalidation Queue Errors of queued invalidation interface error
460 static void vtd_handle_inv_queue_error(IntelIOMMUState
*s
)
462 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
464 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_IQE
);
465 vtd_generate_fault_event(s
, fsts_reg
);
468 /* Set the IWC field and try to generate an invalidation completion interrupt */
469 static void vtd_generate_completion_event(IntelIOMMUState
*s
)
471 VTD_DPRINTF(INV
, "completes an invalidation wait command with "
473 if (vtd_get_long_raw(s
, DMAR_ICS_REG
) & VTD_ICS_IWC
) {
474 VTD_DPRINTF(INV
, "there is a previous interrupt condition to be "
475 "serviced by software, "
476 "new invalidation event is not generated");
479 vtd_set_clear_mask_long(s
, DMAR_ICS_REG
, 0, VTD_ICS_IWC
);
480 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, 0, VTD_IECTL_IP
);
481 if (vtd_get_long_raw(s
, DMAR_IECTL_REG
) & VTD_IECTL_IM
) {
482 VTD_DPRINTF(INV
, "IM filed in IECTL_REG is set, new invalidation "
483 "event is not generated");
486 /* Generate the interrupt event */
487 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
488 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
492 static inline bool vtd_root_entry_present(VTDRootEntry
*root
)
494 return root
->val
& VTD_ROOT_ENTRY_P
;
497 static int vtd_get_root_entry(IntelIOMMUState
*s
, uint8_t index
,
502 addr
= s
->root
+ index
* sizeof(*re
);
503 if (dma_memory_read(&address_space_memory
, addr
, re
, sizeof(*re
))) {
504 VTD_DPRINTF(GENERAL
, "error: fail to access root-entry at 0x%"PRIx64
505 " + %"PRIu8
, s
->root
, index
);
507 return -VTD_FR_ROOT_TABLE_INV
;
509 re
->val
= le64_to_cpu(re
->val
);
513 static inline bool vtd_context_entry_present(VTDContextEntry
*context
)
515 return context
->lo
& VTD_CONTEXT_ENTRY_P
;
518 static int vtd_get_context_entry_from_root(VTDRootEntry
*root
, uint8_t index
,
523 if (!vtd_root_entry_present(root
)) {
524 VTD_DPRINTF(GENERAL
, "error: root-entry is not present");
525 return -VTD_FR_ROOT_ENTRY_P
;
527 addr
= (root
->val
& VTD_ROOT_ENTRY_CTP
) + index
* sizeof(*ce
);
528 if (dma_memory_read(&address_space_memory
, addr
, ce
, sizeof(*ce
))) {
529 VTD_DPRINTF(GENERAL
, "error: fail to access context-entry at 0x%"PRIx64
531 (uint64_t)(root
->val
& VTD_ROOT_ENTRY_CTP
), index
);
532 return -VTD_FR_CONTEXT_TABLE_INV
;
534 ce
->lo
= le64_to_cpu(ce
->lo
);
535 ce
->hi
= le64_to_cpu(ce
->hi
);
539 static inline dma_addr_t
vtd_get_slpt_base_from_context(VTDContextEntry
*ce
)
541 return ce
->lo
& VTD_CONTEXT_ENTRY_SLPTPTR
;
544 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte
)
546 return slpte
& VTD_SL_PT_BASE_ADDR_MASK
;
549 /* Whether the pte indicates the address of the page frame */
550 static inline bool vtd_is_last_slpte(uint64_t slpte
, uint32_t level
)
552 return level
== VTD_SL_PT_LEVEL
|| (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
);
555 /* Get the content of a spte located in @base_addr[@index] */
556 static uint64_t vtd_get_slpte(dma_addr_t base_addr
, uint32_t index
)
560 assert(index
< VTD_SL_PT_ENTRY_NR
);
562 if (dma_memory_read(&address_space_memory
,
563 base_addr
+ index
* sizeof(slpte
), &slpte
,
565 slpte
= (uint64_t)-1;
568 slpte
= le64_to_cpu(slpte
);
572 /* Given a gpa and the level of paging structure, return the offset of current
575 static inline uint32_t vtd_gpa_level_offset(uint64_t gpa
, uint32_t level
)
577 return (gpa
>> vtd_slpt_level_shift(level
)) &
578 ((1ULL << VTD_SL_LEVEL_BITS
) - 1);
581 /* Check Capability Register to see if the @level of page-table is supported */
582 static inline bool vtd_is_level_supported(IntelIOMMUState
*s
, uint32_t level
)
584 return VTD_CAP_SAGAW_MASK
& s
->cap
&
585 (1ULL << (level
- 2 + VTD_CAP_SAGAW_SHIFT
));
588 /* Get the page-table level that hardware should use for the second-level
589 * page-table walk from the Address Width field of context-entry.
591 static inline uint32_t vtd_get_level_from_context_entry(VTDContextEntry
*ce
)
593 return 2 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
);
596 static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry
*ce
)
598 return 30 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
) * 9;
601 static const uint64_t vtd_paging_entry_rsvd_field
[] = {
603 /* For not large page */
604 [1] = 0x800ULL
| ~(VTD_HAW_MASK
| VTD_SL_IGN_COM
),
605 [2] = 0x800ULL
| ~(VTD_HAW_MASK
| VTD_SL_IGN_COM
),
606 [3] = 0x800ULL
| ~(VTD_HAW_MASK
| VTD_SL_IGN_COM
),
607 [4] = 0x880ULL
| ~(VTD_HAW_MASK
| VTD_SL_IGN_COM
),
609 [5] = 0x800ULL
| ~(VTD_HAW_MASK
| VTD_SL_IGN_COM
),
610 [6] = 0x1ff800ULL
| ~(VTD_HAW_MASK
| VTD_SL_IGN_COM
),
611 [7] = 0x3ffff800ULL
| ~(VTD_HAW_MASK
| VTD_SL_IGN_COM
),
612 [8] = 0x880ULL
| ~(VTD_HAW_MASK
| VTD_SL_IGN_COM
),
615 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte
, uint32_t level
)
617 if (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
) {
618 /* Maybe large page */
619 return slpte
& vtd_paging_entry_rsvd_field
[level
+ 4];
621 return slpte
& vtd_paging_entry_rsvd_field
[level
];
625 /* Given the @gpa, get relevant @slptep. @slpte_level will be the last level
626 * of the translation, can be used for deciding the size of large page.
628 static int vtd_gpa_to_slpte(VTDContextEntry
*ce
, uint64_t gpa
, bool is_write
,
629 uint64_t *slptep
, uint32_t *slpte_level
,
630 bool *reads
, bool *writes
)
632 dma_addr_t addr
= vtd_get_slpt_base_from_context(ce
);
633 uint32_t level
= vtd_get_level_from_context_entry(ce
);
636 uint32_t ce_agaw
= vtd_get_agaw_from_context_entry(ce
);
637 uint64_t access_right_check
;
639 /* Check if @gpa is above 2^X-1, where X is the minimum of MGAW in CAP_REG
640 * and AW in context-entry.
642 if (gpa
& ~((1ULL << MIN(ce_agaw
, VTD_MGAW
)) - 1)) {
643 VTD_DPRINTF(GENERAL
, "error: gpa 0x%"PRIx64
" exceeds limits", gpa
);
644 return -VTD_FR_ADDR_BEYOND_MGAW
;
647 /* FIXME: what is the Atomics request here? */
648 access_right_check
= is_write
? VTD_SL_W
: VTD_SL_R
;
651 offset
= vtd_gpa_level_offset(gpa
, level
);
652 slpte
= vtd_get_slpte(addr
, offset
);
654 if (slpte
== (uint64_t)-1) {
655 VTD_DPRINTF(GENERAL
, "error: fail to access second-level paging "
656 "entry at level %"PRIu32
" for gpa 0x%"PRIx64
,
658 if (level
== vtd_get_level_from_context_entry(ce
)) {
659 /* Invalid programming of context-entry */
660 return -VTD_FR_CONTEXT_ENTRY_INV
;
662 return -VTD_FR_PAGING_ENTRY_INV
;
665 *reads
= (*reads
) && (slpte
& VTD_SL_R
);
666 *writes
= (*writes
) && (slpte
& VTD_SL_W
);
667 if (!(slpte
& access_right_check
)) {
668 VTD_DPRINTF(GENERAL
, "error: lack of %s permission for "
669 "gpa 0x%"PRIx64
" slpte 0x%"PRIx64
,
670 (is_write
? "write" : "read"), gpa
, slpte
);
671 return is_write
? -VTD_FR_WRITE
: -VTD_FR_READ
;
673 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
674 VTD_DPRINTF(GENERAL
, "error: non-zero reserved field in second "
675 "level paging entry level %"PRIu32
" slpte 0x%"PRIx64
,
677 return -VTD_FR_PAGING_ENTRY_RSVD
;
680 if (vtd_is_last_slpte(slpte
, level
)) {
682 *slpte_level
= level
;
685 addr
= vtd_get_slpte_addr(slpte
);
690 /* Map a device to its corresponding domain (context-entry) */
691 static int vtd_dev_to_context_entry(IntelIOMMUState
*s
, uint8_t bus_num
,
692 uint8_t devfn
, VTDContextEntry
*ce
)
697 ret_fr
= vtd_get_root_entry(s
, bus_num
, &re
);
702 if (!vtd_root_entry_present(&re
)) {
703 VTD_DPRINTF(GENERAL
, "error: root-entry #%"PRIu8
" is not present",
705 return -VTD_FR_ROOT_ENTRY_P
;
706 } else if (re
.rsvd
|| (re
.val
& VTD_ROOT_ENTRY_RSVD
)) {
707 VTD_DPRINTF(GENERAL
, "error: non-zero reserved field in root-entry "
708 "hi 0x%"PRIx64
" lo 0x%"PRIx64
, re
.rsvd
, re
.val
);
709 return -VTD_FR_ROOT_ENTRY_RSVD
;
712 ret_fr
= vtd_get_context_entry_from_root(&re
, devfn
, ce
);
717 if (!vtd_context_entry_present(ce
)) {
719 "error: context-entry #%"PRIu8
"(bus #%"PRIu8
") "
720 "is not present", devfn
, bus_num
);
721 return -VTD_FR_CONTEXT_ENTRY_P
;
722 } else if ((ce
->hi
& VTD_CONTEXT_ENTRY_RSVD_HI
) ||
723 (ce
->lo
& VTD_CONTEXT_ENTRY_RSVD_LO
)) {
725 "error: non-zero reserved field in context-entry "
726 "hi 0x%"PRIx64
" lo 0x%"PRIx64
, ce
->hi
, ce
->lo
);
727 return -VTD_FR_CONTEXT_ENTRY_RSVD
;
729 /* Check if the programming of context-entry is valid */
730 if (!vtd_is_level_supported(s
, vtd_get_level_from_context_entry(ce
))) {
731 VTD_DPRINTF(GENERAL
, "error: unsupported Address Width value in "
732 "context-entry hi 0x%"PRIx64
" lo 0x%"PRIx64
,
734 return -VTD_FR_CONTEXT_ENTRY_INV
;
735 } else if (ce
->lo
& VTD_CONTEXT_ENTRY_TT
) {
736 VTD_DPRINTF(GENERAL
, "error: unsupported Translation Type in "
737 "context-entry hi 0x%"PRIx64
" lo 0x%"PRIx64
,
739 return -VTD_FR_CONTEXT_ENTRY_INV
;
744 static inline uint16_t vtd_make_source_id(uint8_t bus_num
, uint8_t devfn
)
746 return ((bus_num
& 0xffUL
) << 8) | (devfn
& 0xffUL
);
749 static const bool vtd_qualified_faults
[] = {
750 [VTD_FR_RESERVED
] = false,
751 [VTD_FR_ROOT_ENTRY_P
] = false,
752 [VTD_FR_CONTEXT_ENTRY_P
] = true,
753 [VTD_FR_CONTEXT_ENTRY_INV
] = true,
754 [VTD_FR_ADDR_BEYOND_MGAW
] = true,
755 [VTD_FR_WRITE
] = true,
756 [VTD_FR_READ
] = true,
757 [VTD_FR_PAGING_ENTRY_INV
] = true,
758 [VTD_FR_ROOT_TABLE_INV
] = false,
759 [VTD_FR_CONTEXT_TABLE_INV
] = false,
760 [VTD_FR_ROOT_ENTRY_RSVD
] = false,
761 [VTD_FR_PAGING_ENTRY_RSVD
] = true,
762 [VTD_FR_CONTEXT_ENTRY_TT
] = true,
763 [VTD_FR_RESERVED_ERR
] = false,
764 [VTD_FR_MAX
] = false,
767 /* To see if a fault condition is "qualified", which is reported to software
768 * only if the FPD field in the context-entry used to process the faulting
771 static inline bool vtd_is_qualified_fault(VTDFaultReason fault
)
773 return vtd_qualified_faults
[fault
];
776 static inline bool vtd_is_interrupt_addr(hwaddr addr
)
778 return VTD_INTERRUPT_ADDR_FIRST
<= addr
&& addr
<= VTD_INTERRUPT_ADDR_LAST
;
781 /* Map dev to context-entry then do a paging-structures walk to do a iommu
784 * Called from RCU critical section.
786 * @bus_num: The bus number
787 * @devfn: The devfn, which is the combined of device and function number
788 * @is_write: The access is a write operation
789 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
791 static void vtd_do_iommu_translate(VTDAddressSpace
*vtd_as
, PCIBus
*bus
,
792 uint8_t devfn
, hwaddr addr
, bool is_write
,
793 IOMMUTLBEntry
*entry
)
795 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
797 uint8_t bus_num
= pci_bus_num(bus
);
798 VTDContextCacheEntry
*cc_entry
= &vtd_as
->context_cache_entry
;
799 uint64_t slpte
, page_mask
;
801 uint16_t source_id
= vtd_make_source_id(bus_num
, devfn
);
803 bool is_fpd_set
= false;
806 VTDIOTLBEntry
*iotlb_entry
;
808 /* Check if the request is in interrupt address range */
809 if (vtd_is_interrupt_addr(addr
)) {
811 /* FIXME: since we don't know the length of the access here, we
812 * treat Non-DWORD length write requests without PASID as
813 * interrupt requests, too. Withoud interrupt remapping support,
814 * we just use 1:1 mapping.
816 VTD_DPRINTF(MMU
, "write request to interrupt address "
817 "gpa 0x%"PRIx64
, addr
);
818 entry
->iova
= addr
& VTD_PAGE_MASK_4K
;
819 entry
->translated_addr
= addr
& VTD_PAGE_MASK_4K
;
820 entry
->addr_mask
= ~VTD_PAGE_MASK_4K
;
821 entry
->perm
= IOMMU_WO
;
824 VTD_DPRINTF(GENERAL
, "error: read request from interrupt address "
825 "gpa 0x%"PRIx64
, addr
);
826 vtd_report_dmar_fault(s
, source_id
, addr
, VTD_FR_READ
, is_write
);
830 /* Try to fetch slpte form IOTLB */
831 iotlb_entry
= vtd_lookup_iotlb(s
, source_id
, addr
);
833 VTD_DPRINTF(CACHE
, "hit iotlb sid 0x%"PRIx16
" gpa 0x%"PRIx64
834 " slpte 0x%"PRIx64
" did 0x%"PRIx16
, source_id
, addr
,
835 iotlb_entry
->slpte
, iotlb_entry
->domain_id
);
836 slpte
= iotlb_entry
->slpte
;
837 reads
= iotlb_entry
->read_flags
;
838 writes
= iotlb_entry
->write_flags
;
839 page_mask
= iotlb_entry
->mask
;
842 /* Try to fetch context-entry from cache first */
843 if (cc_entry
->context_cache_gen
== s
->context_cache_gen
) {
844 VTD_DPRINTF(CACHE
, "hit context-cache bus %d devfn %d "
845 "(hi %"PRIx64
" lo %"PRIx64
" gen %"PRIu32
")",
846 bus_num
, devfn
, cc_entry
->context_entry
.hi
,
847 cc_entry
->context_entry
.lo
, cc_entry
->context_cache_gen
);
848 ce
= cc_entry
->context_entry
;
849 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
851 ret_fr
= vtd_dev_to_context_entry(s
, bus_num
, devfn
, &ce
);
852 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
855 if (is_fpd_set
&& vtd_is_qualified_fault(ret_fr
)) {
856 VTD_DPRINTF(FLOG
, "fault processing is disabled for DMA "
857 "requests through this context-entry "
860 vtd_report_dmar_fault(s
, source_id
, addr
, ret_fr
, is_write
);
864 /* Update context-cache */
865 VTD_DPRINTF(CACHE
, "update context-cache bus %d devfn %d "
866 "(hi %"PRIx64
" lo %"PRIx64
" gen %"PRIu32
"->%"PRIu32
")",
867 bus_num
, devfn
, ce
.hi
, ce
.lo
,
868 cc_entry
->context_cache_gen
, s
->context_cache_gen
);
869 cc_entry
->context_entry
= ce
;
870 cc_entry
->context_cache_gen
= s
->context_cache_gen
;
873 ret_fr
= vtd_gpa_to_slpte(&ce
, addr
, is_write
, &slpte
, &level
,
877 if (is_fpd_set
&& vtd_is_qualified_fault(ret_fr
)) {
878 VTD_DPRINTF(FLOG
, "fault processing is disabled for DMA requests "
879 "through this context-entry (with FPD Set)");
881 vtd_report_dmar_fault(s
, source_id
, addr
, ret_fr
, is_write
);
886 page_mask
= vtd_slpt_level_page_mask(level
);
887 vtd_update_iotlb(s
, source_id
, VTD_CONTEXT_ENTRY_DID(ce
.hi
), addr
, slpte
,
888 reads
, writes
, level
);
890 entry
->iova
= addr
& page_mask
;
891 entry
->translated_addr
= vtd_get_slpte_addr(slpte
) & page_mask
;
892 entry
->addr_mask
= ~page_mask
;
893 entry
->perm
= (writes
? 2 : 0) + (reads
? 1 : 0);
896 static void vtd_root_table_setup(IntelIOMMUState
*s
)
898 s
->root
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
);
899 s
->root_extended
= s
->root
& VTD_RTADDR_RTT
;
900 s
->root
&= VTD_RTADDR_ADDR_MASK
;
902 VTD_DPRINTF(CSR
, "root_table addr 0x%"PRIx64
" %s", s
->root
,
903 (s
->root_extended
? "(extended)" : ""));
906 static void vtd_context_global_invalidate(IntelIOMMUState
*s
)
908 s
->context_cache_gen
++;
909 if (s
->context_cache_gen
== VTD_CONTEXT_CACHE_GEN_MAX
) {
910 vtd_reset_context_cache(s
);
915 /* Find the VTD address space currently associated with a given bus number,
917 static VTDBus
*vtd_find_as_from_bus_num(IntelIOMMUState
*s
, uint8_t bus_num
)
919 VTDBus
*vtd_bus
= s
->vtd_as_by_bus_num
[bus_num
];
921 /* Iterate over the registered buses to find the one
922 * which currently hold this bus number, and update the bus_num lookup table:
926 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
927 while (g_hash_table_iter_next (&iter
, NULL
, (void**)&vtd_bus
)) {
928 if (pci_bus_num(vtd_bus
->bus
) == bus_num
) {
929 s
->vtd_as_by_bus_num
[bus_num
] = vtd_bus
;
937 /* Do a context-cache device-selective invalidation.
938 * @func_mask: FM field after shifting
940 static void vtd_context_device_invalidate(IntelIOMMUState
*s
,
946 VTDAddressSpace
*vtd_as
;
950 switch (func_mask
& 3) {
952 mask
= 0; /* No bits in the SID field masked */
955 mask
= 4; /* Mask bit 2 in the SID field */
958 mask
= 6; /* Mask bit 2:1 in the SID field */
961 mask
= 7; /* Mask bit 2:0 in the SID field */
964 VTD_DPRINTF(INV
, "device-selective invalidation source 0x%"PRIx16
965 " mask %"PRIu16
, source_id
, mask
);
966 vtd_bus
= vtd_find_as_from_bus_num(s
, VTD_SID_TO_BUS(source_id
));
968 devfn
= VTD_SID_TO_DEVFN(source_id
);
969 for (devfn_it
= 0; devfn_it
< X86_IOMMU_PCI_DEVFN_MAX
; ++devfn_it
) {
970 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
971 if (vtd_as
&& ((devfn_it
& mask
) == (devfn
& mask
))) {
972 VTD_DPRINTF(INV
, "invalidate context-cahce of devfn 0x%"PRIx16
,
974 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
980 /* Context-cache invalidation
981 * Returns the Context Actual Invalidation Granularity.
982 * @val: the content of the CCMD_REG
984 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState
*s
, uint64_t val
)
987 uint64_t type
= val
& VTD_CCMD_CIRG_MASK
;
990 case VTD_CCMD_DOMAIN_INVL
:
991 VTD_DPRINTF(INV
, "domain-selective invalidation domain 0x%"PRIx16
,
992 (uint16_t)VTD_CCMD_DID(val
));
994 case VTD_CCMD_GLOBAL_INVL
:
995 VTD_DPRINTF(INV
, "global invalidation");
996 caig
= VTD_CCMD_GLOBAL_INVL_A
;
997 vtd_context_global_invalidate(s
);
1000 case VTD_CCMD_DEVICE_INVL
:
1001 caig
= VTD_CCMD_DEVICE_INVL_A
;
1002 vtd_context_device_invalidate(s
, VTD_CCMD_SID(val
), VTD_CCMD_FM(val
));
1006 VTD_DPRINTF(GENERAL
, "error: invalid granularity");
1012 static void vtd_iotlb_global_invalidate(IntelIOMMUState
*s
)
1017 static void vtd_iotlb_domain_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
)
1019 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_domain
,
1023 static void vtd_iotlb_page_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
,
1024 hwaddr addr
, uint8_t am
)
1026 VTDIOTLBPageInvInfo info
;
1028 assert(am
<= VTD_MAMV
);
1029 info
.domain_id
= domain_id
;
1031 info
.mask
= ~((1 << am
) - 1);
1032 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_page
, &info
);
1036 * Returns the IOTLB Actual Invalidation Granularity.
1037 * @val: the content of the IOTLB_REG
1039 static uint64_t vtd_iotlb_flush(IntelIOMMUState
*s
, uint64_t val
)
1042 uint64_t type
= val
& VTD_TLB_FLUSH_GRANU_MASK
;
1048 case VTD_TLB_GLOBAL_FLUSH
:
1049 VTD_DPRINTF(INV
, "global invalidation");
1050 iaig
= VTD_TLB_GLOBAL_FLUSH_A
;
1051 vtd_iotlb_global_invalidate(s
);
1054 case VTD_TLB_DSI_FLUSH
:
1055 domain_id
= VTD_TLB_DID(val
);
1056 VTD_DPRINTF(INV
, "domain-selective invalidation domain 0x%"PRIx16
,
1058 iaig
= VTD_TLB_DSI_FLUSH_A
;
1059 vtd_iotlb_domain_invalidate(s
, domain_id
);
1062 case VTD_TLB_PSI_FLUSH
:
1063 domain_id
= VTD_TLB_DID(val
);
1064 addr
= vtd_get_quad_raw(s
, DMAR_IVA_REG
);
1065 am
= VTD_IVA_AM(addr
);
1066 addr
= VTD_IVA_ADDR(addr
);
1067 VTD_DPRINTF(INV
, "page-selective invalidation domain 0x%"PRIx16
1068 " addr 0x%"PRIx64
" mask %"PRIu8
, domain_id
, addr
, am
);
1069 if (am
> VTD_MAMV
) {
1070 VTD_DPRINTF(GENERAL
, "error: supported max address mask value is "
1071 "%"PRIu8
, (uint8_t)VTD_MAMV
);
1075 iaig
= VTD_TLB_PSI_FLUSH_A
;
1076 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
1080 VTD_DPRINTF(GENERAL
, "error: invalid granularity");
1086 static inline bool vtd_queued_inv_enable_check(IntelIOMMUState
*s
)
1088 return s
->iq_tail
== 0;
1091 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState
*s
)
1093 return s
->qi_enabled
&& (s
->iq_tail
== s
->iq_head
) &&
1094 (s
->iq_last_desc_type
== VTD_INV_DESC_WAIT
);
1097 static void vtd_handle_gcmd_qie(IntelIOMMUState
*s
, bool en
)
1099 uint64_t iqa_val
= vtd_get_quad_raw(s
, DMAR_IQA_REG
);
1101 VTD_DPRINTF(INV
, "Queued Invalidation Enable %s", (en
? "on" : "off"));
1103 if (vtd_queued_inv_enable_check(s
)) {
1104 s
->iq
= iqa_val
& VTD_IQA_IQA_MASK
;
1105 /* 2^(x+8) entries */
1106 s
->iq_size
= 1UL << ((iqa_val
& VTD_IQA_QS
) + 8);
1107 s
->qi_enabled
= true;
1108 VTD_DPRINTF(INV
, "DMAR_IQA_REG 0x%"PRIx64
, iqa_val
);
1109 VTD_DPRINTF(INV
, "Invalidation Queue addr 0x%"PRIx64
" size %d",
1111 /* Ok - report back to driver */
1112 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_QIES
);
1114 VTD_DPRINTF(GENERAL
, "error: can't enable Queued Invalidation: "
1115 "tail %"PRIu16
, s
->iq_tail
);
1118 if (vtd_queued_inv_disable_check(s
)) {
1119 /* disable Queued Invalidation */
1120 vtd_set_quad_raw(s
, DMAR_IQH_REG
, 0);
1122 s
->qi_enabled
= false;
1123 /* Ok - report back to driver */
1124 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_QIES
, 0);
1126 VTD_DPRINTF(GENERAL
, "error: can't disable Queued Invalidation: "
1127 "head %"PRIu16
", tail %"PRIu16
1128 ", last_descriptor %"PRIu8
,
1129 s
->iq_head
, s
->iq_tail
, s
->iq_last_desc_type
);
1134 /* Set Root Table Pointer */
1135 static void vtd_handle_gcmd_srtp(IntelIOMMUState
*s
)
1137 VTD_DPRINTF(CSR
, "set Root Table Pointer");
1139 vtd_root_table_setup(s
);
1140 /* Ok - report back to driver */
1141 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_RTPS
);
1144 /* Handle Translation Enable/Disable */
1145 static void vtd_handle_gcmd_te(IntelIOMMUState
*s
, bool en
)
1147 VTD_DPRINTF(CSR
, "Translation Enable %s", (en
? "on" : "off"));
1150 s
->dmar_enabled
= true;
1151 /* Ok - report back to driver */
1152 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_TES
);
1154 s
->dmar_enabled
= false;
1156 /* Clear the index of Fault Recording Register */
1157 s
->next_frcd_reg
= 0;
1158 /* Ok - report back to driver */
1159 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_TES
, 0);
1163 /* Handle write to Global Command Register */
1164 static void vtd_handle_gcmd_write(IntelIOMMUState
*s
)
1166 uint32_t status
= vtd_get_long_raw(s
, DMAR_GSTS_REG
);
1167 uint32_t val
= vtd_get_long_raw(s
, DMAR_GCMD_REG
);
1168 uint32_t changed
= status
^ val
;
1170 VTD_DPRINTF(CSR
, "value 0x%"PRIx32
" status 0x%"PRIx32
, val
, status
);
1171 if (changed
& VTD_GCMD_TE
) {
1172 /* Translation enable/disable */
1173 vtd_handle_gcmd_te(s
, val
& VTD_GCMD_TE
);
1175 if (val
& VTD_GCMD_SRTP
) {
1176 /* Set/update the root-table pointer */
1177 vtd_handle_gcmd_srtp(s
);
1179 if (changed
& VTD_GCMD_QIE
) {
1180 /* Queued Invalidation Enable */
1181 vtd_handle_gcmd_qie(s
, val
& VTD_GCMD_QIE
);
1185 /* Handle write to Context Command Register */
1186 static void vtd_handle_ccmd_write(IntelIOMMUState
*s
)
1189 uint64_t val
= vtd_get_quad_raw(s
, DMAR_CCMD_REG
);
1191 /* Context-cache invalidation request */
1192 if (val
& VTD_CCMD_ICC
) {
1193 if (s
->qi_enabled
) {
1194 VTD_DPRINTF(GENERAL
, "error: Queued Invalidation enabled, "
1195 "should not use register-based invalidation");
1198 ret
= vtd_context_cache_invalidate(s
, val
);
1199 /* Invalidation completed. Change something to show */
1200 vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_ICC
, 0ULL);
1201 ret
= vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_CAIG_MASK
,
1203 VTD_DPRINTF(INV
, "CCMD_REG write-back val: 0x%"PRIx64
, ret
);
1207 /* Handle write to IOTLB Invalidation Register */
1208 static void vtd_handle_iotlb_write(IntelIOMMUState
*s
)
1211 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IOTLB_REG
);
1213 /* IOTLB invalidation request */
1214 if (val
& VTD_TLB_IVT
) {
1215 if (s
->qi_enabled
) {
1216 VTD_DPRINTF(GENERAL
, "error: Queued Invalidation enabled, "
1217 "should not use register-based invalidation");
1220 ret
= vtd_iotlb_flush(s
, val
);
1221 /* Invalidation completed. Change something to show */
1222 vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
, VTD_TLB_IVT
, 0ULL);
1223 ret
= vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
,
1224 VTD_TLB_FLUSH_GRANU_MASK_A
, ret
);
1225 VTD_DPRINTF(INV
, "IOTLB_REG write-back val: 0x%"PRIx64
, ret
);
1229 /* Fetch an Invalidation Descriptor from the Invalidation Queue */
1230 static bool vtd_get_inv_desc(dma_addr_t base_addr
, uint32_t offset
,
1231 VTDInvDesc
*inv_desc
)
1233 dma_addr_t addr
= base_addr
+ offset
* sizeof(*inv_desc
);
1234 if (dma_memory_read(&address_space_memory
, addr
, inv_desc
,
1235 sizeof(*inv_desc
))) {
1236 VTD_DPRINTF(GENERAL
, "error: fail to fetch Invalidation Descriptor "
1237 "base_addr 0x%"PRIx64
" offset %"PRIu32
, base_addr
, offset
);
1243 inv_desc
->lo
= le64_to_cpu(inv_desc
->lo
);
1244 inv_desc
->hi
= le64_to_cpu(inv_desc
->hi
);
1248 static bool vtd_process_wait_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
1250 if ((inv_desc
->hi
& VTD_INV_DESC_WAIT_RSVD_HI
) ||
1251 (inv_desc
->lo
& VTD_INV_DESC_WAIT_RSVD_LO
)) {
1252 VTD_DPRINTF(GENERAL
, "error: non-zero reserved field in Invalidation "
1253 "Wait Descriptor hi 0x%"PRIx64
" lo 0x%"PRIx64
,
1254 inv_desc
->hi
, inv_desc
->lo
);
1257 if (inv_desc
->lo
& VTD_INV_DESC_WAIT_SW
) {
1259 uint32_t status_data
= (uint32_t)(inv_desc
->lo
>>
1260 VTD_INV_DESC_WAIT_DATA_SHIFT
);
1262 assert(!(inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
));
1264 /* FIXME: need to be masked with HAW? */
1265 dma_addr_t status_addr
= inv_desc
->hi
;
1266 VTD_DPRINTF(INV
, "status data 0x%x, status addr 0x%"PRIx64
,
1267 status_data
, status_addr
);
1268 status_data
= cpu_to_le32(status_data
);
1269 if (dma_memory_write(&address_space_memory
, status_addr
, &status_data
,
1270 sizeof(status_data
))) {
1271 VTD_DPRINTF(GENERAL
, "error: fail to perform a coherent write");
1274 } else if (inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
) {
1275 /* Interrupt flag */
1276 VTD_DPRINTF(INV
, "Invalidation Wait Descriptor interrupt completion");
1277 vtd_generate_completion_event(s
);
1279 VTD_DPRINTF(GENERAL
, "error: invalid Invalidation Wait Descriptor: "
1280 "hi 0x%"PRIx64
" lo 0x%"PRIx64
, inv_desc
->hi
, inv_desc
->lo
);
1286 static bool vtd_process_context_cache_desc(IntelIOMMUState
*s
,
1287 VTDInvDesc
*inv_desc
)
1289 if ((inv_desc
->lo
& VTD_INV_DESC_CC_RSVD
) || inv_desc
->hi
) {
1290 VTD_DPRINTF(GENERAL
, "error: non-zero reserved field in Context-cache "
1291 "Invalidate Descriptor");
1294 switch (inv_desc
->lo
& VTD_INV_DESC_CC_G
) {
1295 case VTD_INV_DESC_CC_DOMAIN
:
1296 VTD_DPRINTF(INV
, "domain-selective invalidation domain 0x%"PRIx16
,
1297 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc
->lo
));
1299 case VTD_INV_DESC_CC_GLOBAL
:
1300 VTD_DPRINTF(INV
, "global invalidation");
1301 vtd_context_global_invalidate(s
);
1304 case VTD_INV_DESC_CC_DEVICE
:
1305 vtd_context_device_invalidate(s
, VTD_INV_DESC_CC_SID(inv_desc
->lo
),
1306 VTD_INV_DESC_CC_FM(inv_desc
->lo
));
1310 VTD_DPRINTF(GENERAL
, "error: invalid granularity in Context-cache "
1311 "Invalidate Descriptor hi 0x%"PRIx64
" lo 0x%"PRIx64
,
1312 inv_desc
->hi
, inv_desc
->lo
);
1318 static bool vtd_process_iotlb_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
1324 if ((inv_desc
->lo
& VTD_INV_DESC_IOTLB_RSVD_LO
) ||
1325 (inv_desc
->hi
& VTD_INV_DESC_IOTLB_RSVD_HI
)) {
1326 VTD_DPRINTF(GENERAL
, "error: non-zero reserved field in IOTLB "
1327 "Invalidate Descriptor hi 0x%"PRIx64
" lo 0x%"PRIx64
,
1328 inv_desc
->hi
, inv_desc
->lo
);
1332 switch (inv_desc
->lo
& VTD_INV_DESC_IOTLB_G
) {
1333 case VTD_INV_DESC_IOTLB_GLOBAL
:
1334 VTD_DPRINTF(INV
, "global invalidation");
1335 vtd_iotlb_global_invalidate(s
);
1338 case VTD_INV_DESC_IOTLB_DOMAIN
:
1339 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
1340 VTD_DPRINTF(INV
, "domain-selective invalidation domain 0x%"PRIx16
,
1342 vtd_iotlb_domain_invalidate(s
, domain_id
);
1345 case VTD_INV_DESC_IOTLB_PAGE
:
1346 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
1347 addr
= VTD_INV_DESC_IOTLB_ADDR(inv_desc
->hi
);
1348 am
= VTD_INV_DESC_IOTLB_AM(inv_desc
->hi
);
1349 VTD_DPRINTF(INV
, "page-selective invalidation domain 0x%"PRIx16
1350 " addr 0x%"PRIx64
" mask %"PRIu8
, domain_id
, addr
, am
);
1351 if (am
> VTD_MAMV
) {
1352 VTD_DPRINTF(GENERAL
, "error: supported max address mask value is "
1353 "%"PRIu8
, (uint8_t)VTD_MAMV
);
1356 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
1360 VTD_DPRINTF(GENERAL
, "error: invalid granularity in IOTLB Invalidate "
1361 "Descriptor hi 0x%"PRIx64
" lo 0x%"PRIx64
,
1362 inv_desc
->hi
, inv_desc
->lo
);
1368 static bool vtd_process_inv_desc(IntelIOMMUState
*s
)
1370 VTDInvDesc inv_desc
;
1373 VTD_DPRINTF(INV
, "iq head %"PRIu16
, s
->iq_head
);
1374 if (!vtd_get_inv_desc(s
->iq
, s
->iq_head
, &inv_desc
)) {
1375 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
1378 desc_type
= inv_desc
.lo
& VTD_INV_DESC_TYPE
;
1379 /* FIXME: should update at first or at last? */
1380 s
->iq_last_desc_type
= desc_type
;
1382 switch (desc_type
) {
1383 case VTD_INV_DESC_CC
:
1384 VTD_DPRINTF(INV
, "Context-cache Invalidate Descriptor hi 0x%"PRIx64
1385 " lo 0x%"PRIx64
, inv_desc
.hi
, inv_desc
.lo
);
1386 if (!vtd_process_context_cache_desc(s
, &inv_desc
)) {
1391 case VTD_INV_DESC_IOTLB
:
1392 VTD_DPRINTF(INV
, "IOTLB Invalidate Descriptor hi 0x%"PRIx64
1393 " lo 0x%"PRIx64
, inv_desc
.hi
, inv_desc
.lo
);
1394 if (!vtd_process_iotlb_desc(s
, &inv_desc
)) {
1399 case VTD_INV_DESC_WAIT
:
1400 VTD_DPRINTF(INV
, "Invalidation Wait Descriptor hi 0x%"PRIx64
1401 " lo 0x%"PRIx64
, inv_desc
.hi
, inv_desc
.lo
);
1402 if (!vtd_process_wait_desc(s
, &inv_desc
)) {
1407 case VTD_INV_DESC_IEC
:
1408 VTD_DPRINTF(INV
, "Interrupt Entry Cache Invalidation "
1409 "not implemented yet");
1411 * Since currently we do not cache interrupt entries, we can
1412 * just mark this descriptor as "good" and move on.
1417 VTD_DPRINTF(GENERAL
, "error: unkonw Invalidation Descriptor type "
1418 "hi 0x%"PRIx64
" lo 0x%"PRIx64
" type %"PRIu8
,
1419 inv_desc
.hi
, inv_desc
.lo
, desc_type
);
1423 if (s
->iq_head
== s
->iq_size
) {
1429 /* Try to fetch and process more Invalidation Descriptors */
1430 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
)
1432 VTD_DPRINTF(INV
, "fetch Invalidation Descriptors");
1433 if (s
->iq_tail
>= s
->iq_size
) {
1434 /* Detects an invalid Tail pointer */
1435 VTD_DPRINTF(GENERAL
, "error: iq_tail is %"PRIu16
1436 " while iq_size is %"PRIu16
, s
->iq_tail
, s
->iq_size
);
1437 vtd_handle_inv_queue_error(s
);
1440 while (s
->iq_head
!= s
->iq_tail
) {
1441 if (!vtd_process_inv_desc(s
)) {
1442 /* Invalidation Queue Errors */
1443 vtd_handle_inv_queue_error(s
);
1446 /* Must update the IQH_REG in time */
1447 vtd_set_quad_raw(s
, DMAR_IQH_REG
,
1448 (((uint64_t)(s
->iq_head
)) << VTD_IQH_QH_SHIFT
) &
1453 /* Handle write to Invalidation Queue Tail Register */
1454 static void vtd_handle_iqt_write(IntelIOMMUState
*s
)
1456 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IQT_REG
);
1458 s
->iq_tail
= VTD_IQT_QT(val
);
1459 VTD_DPRINTF(INV
, "set iq tail %"PRIu16
, s
->iq_tail
);
1460 if (s
->qi_enabled
&& !(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
1461 /* Process Invalidation Queue here */
1462 vtd_fetch_inv_desc(s
);
1466 static void vtd_handle_fsts_write(IntelIOMMUState
*s
)
1468 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
1469 uint32_t fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
1470 uint32_t status_fields
= VTD_FSTS_PFO
| VTD_FSTS_PPF
| VTD_FSTS_IQE
;
1472 if ((fectl_reg
& VTD_FECTL_IP
) && !(fsts_reg
& status_fields
)) {
1473 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
1474 VTD_DPRINTF(FLOG
, "all pending interrupt conditions serviced, clear "
1475 "IP field of FECTL_REG");
1477 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
1478 * Descriptors if there are any when Queued Invalidation is enabled?
1482 static void vtd_handle_fectl_write(IntelIOMMUState
*s
)
1485 /* FIXME: when software clears the IM field, check the IP field. But do we
1486 * need to compare the old value and the new value to conclude that
1487 * software clears the IM field? Or just check if the IM field is zero?
1489 fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
1490 if ((fectl_reg
& VTD_FECTL_IP
) && !(fectl_reg
& VTD_FECTL_IM
)) {
1491 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
1492 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
1493 VTD_DPRINTF(FLOG
, "IM field is cleared, generate "
1494 "fault event interrupt");
1498 static void vtd_handle_ics_write(IntelIOMMUState
*s
)
1500 uint32_t ics_reg
= vtd_get_long_raw(s
, DMAR_ICS_REG
);
1501 uint32_t iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
1503 if ((iectl_reg
& VTD_IECTL_IP
) && !(ics_reg
& VTD_ICS_IWC
)) {
1504 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
1505 VTD_DPRINTF(INV
, "pending completion interrupt condition serviced, "
1506 "clear IP field of IECTL_REG");
1510 static void vtd_handle_iectl_write(IntelIOMMUState
*s
)
1513 /* FIXME: when software clears the IM field, check the IP field. But do we
1514 * need to compare the old value and the new value to conclude that
1515 * software clears the IM field? Or just check if the IM field is zero?
1517 iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
1518 if ((iectl_reg
& VTD_IECTL_IP
) && !(iectl_reg
& VTD_IECTL_IM
)) {
1519 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
1520 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
1521 VTD_DPRINTF(INV
, "IM field is cleared, generate "
1522 "invalidation event interrupt");
1526 static uint64_t vtd_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
1528 IntelIOMMUState
*s
= opaque
;
1531 if (addr
+ size
> DMAR_REG_SIZE
) {
1532 VTD_DPRINTF(GENERAL
, "error: addr outside region: max 0x%"PRIx64
1533 ", got 0x%"PRIx64
" %d",
1534 (uint64_t)DMAR_REG_SIZE
, addr
, size
);
1535 return (uint64_t)-1;
1539 /* Root Table Address Register, 64-bit */
1540 case DMAR_RTADDR_REG
:
1542 val
= s
->root
& ((1ULL << 32) - 1);
1548 case DMAR_RTADDR_REG_HI
:
1550 val
= s
->root
>> 32;
1553 /* Invalidation Queue Address Register, 64-bit */
1555 val
= s
->iq
| (vtd_get_quad(s
, DMAR_IQA_REG
) & VTD_IQA_QS
);
1557 val
= val
& ((1ULL << 32) - 1);
1561 case DMAR_IQA_REG_HI
:
1568 val
= vtd_get_long(s
, addr
);
1570 val
= vtd_get_quad(s
, addr
);
1573 VTD_DPRINTF(CSR
, "addr 0x%"PRIx64
" size %d val 0x%"PRIx64
,
1578 static void vtd_mem_write(void *opaque
, hwaddr addr
,
1579 uint64_t val
, unsigned size
)
1581 IntelIOMMUState
*s
= opaque
;
1583 if (addr
+ size
> DMAR_REG_SIZE
) {
1584 VTD_DPRINTF(GENERAL
, "error: addr outside region: max 0x%"PRIx64
1585 ", got 0x%"PRIx64
" %d",
1586 (uint64_t)DMAR_REG_SIZE
, addr
, size
);
1591 /* Global Command Register, 32-bit */
1593 VTD_DPRINTF(CSR
, "DMAR_GCMD_REG write addr 0x%"PRIx64
1594 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1595 vtd_set_long(s
, addr
, val
);
1596 vtd_handle_gcmd_write(s
);
1599 /* Context Command Register, 64-bit */
1601 VTD_DPRINTF(CSR
, "DMAR_CCMD_REG write addr 0x%"PRIx64
1602 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1604 vtd_set_long(s
, addr
, val
);
1606 vtd_set_quad(s
, addr
, val
);
1607 vtd_handle_ccmd_write(s
);
1611 case DMAR_CCMD_REG_HI
:
1612 VTD_DPRINTF(CSR
, "DMAR_CCMD_REG_HI write addr 0x%"PRIx64
1613 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1615 vtd_set_long(s
, addr
, val
);
1616 vtd_handle_ccmd_write(s
);
1619 /* IOTLB Invalidation Register, 64-bit */
1620 case DMAR_IOTLB_REG
:
1621 VTD_DPRINTF(INV
, "DMAR_IOTLB_REG write addr 0x%"PRIx64
1622 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1624 vtd_set_long(s
, addr
, val
);
1626 vtd_set_quad(s
, addr
, val
);
1627 vtd_handle_iotlb_write(s
);
1631 case DMAR_IOTLB_REG_HI
:
1632 VTD_DPRINTF(INV
, "DMAR_IOTLB_REG_HI write addr 0x%"PRIx64
1633 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1635 vtd_set_long(s
, addr
, val
);
1636 vtd_handle_iotlb_write(s
);
1639 /* Invalidate Address Register, 64-bit */
1641 VTD_DPRINTF(INV
, "DMAR_IVA_REG write addr 0x%"PRIx64
1642 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1644 vtd_set_long(s
, addr
, val
);
1646 vtd_set_quad(s
, addr
, val
);
1650 case DMAR_IVA_REG_HI
:
1651 VTD_DPRINTF(INV
, "DMAR_IVA_REG_HI write addr 0x%"PRIx64
1652 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1654 vtd_set_long(s
, addr
, val
);
1657 /* Fault Status Register, 32-bit */
1659 VTD_DPRINTF(FLOG
, "DMAR_FSTS_REG write addr 0x%"PRIx64
1660 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1662 vtd_set_long(s
, addr
, val
);
1663 vtd_handle_fsts_write(s
);
1666 /* Fault Event Control Register, 32-bit */
1667 case DMAR_FECTL_REG
:
1668 VTD_DPRINTF(FLOG
, "DMAR_FECTL_REG write addr 0x%"PRIx64
1669 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1671 vtd_set_long(s
, addr
, val
);
1672 vtd_handle_fectl_write(s
);
1675 /* Fault Event Data Register, 32-bit */
1676 case DMAR_FEDATA_REG
:
1677 VTD_DPRINTF(FLOG
, "DMAR_FEDATA_REG write addr 0x%"PRIx64
1678 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1680 vtd_set_long(s
, addr
, val
);
1683 /* Fault Event Address Register, 32-bit */
1684 case DMAR_FEADDR_REG
:
1685 VTD_DPRINTF(FLOG
, "DMAR_FEADDR_REG write addr 0x%"PRIx64
1686 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1688 vtd_set_long(s
, addr
, val
);
1691 /* Fault Event Upper Address Register, 32-bit */
1692 case DMAR_FEUADDR_REG
:
1693 VTD_DPRINTF(FLOG
, "DMAR_FEUADDR_REG write addr 0x%"PRIx64
1694 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1696 vtd_set_long(s
, addr
, val
);
1699 /* Protected Memory Enable Register, 32-bit */
1701 VTD_DPRINTF(CSR
, "DMAR_PMEN_REG write addr 0x%"PRIx64
1702 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1704 vtd_set_long(s
, addr
, val
);
1707 /* Root Table Address Register, 64-bit */
1708 case DMAR_RTADDR_REG
:
1709 VTD_DPRINTF(CSR
, "DMAR_RTADDR_REG write addr 0x%"PRIx64
1710 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1712 vtd_set_long(s
, addr
, val
);
1714 vtd_set_quad(s
, addr
, val
);
1718 case DMAR_RTADDR_REG_HI
:
1719 VTD_DPRINTF(CSR
, "DMAR_RTADDR_REG_HI write addr 0x%"PRIx64
1720 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1722 vtd_set_long(s
, addr
, val
);
1725 /* Invalidation Queue Tail Register, 64-bit */
1727 VTD_DPRINTF(INV
, "DMAR_IQT_REG write addr 0x%"PRIx64
1728 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1730 vtd_set_long(s
, addr
, val
);
1732 vtd_set_quad(s
, addr
, val
);
1734 vtd_handle_iqt_write(s
);
1737 case DMAR_IQT_REG_HI
:
1738 VTD_DPRINTF(INV
, "DMAR_IQT_REG_HI write addr 0x%"PRIx64
1739 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1741 vtd_set_long(s
, addr
, val
);
1742 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
1745 /* Invalidation Queue Address Register, 64-bit */
1747 VTD_DPRINTF(INV
, "DMAR_IQA_REG write addr 0x%"PRIx64
1748 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1750 vtd_set_long(s
, addr
, val
);
1752 vtd_set_quad(s
, addr
, val
);
1756 case DMAR_IQA_REG_HI
:
1757 VTD_DPRINTF(INV
, "DMAR_IQA_REG_HI write addr 0x%"PRIx64
1758 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1760 vtd_set_long(s
, addr
, val
);
1763 /* Invalidation Completion Status Register, 32-bit */
1765 VTD_DPRINTF(INV
, "DMAR_ICS_REG write addr 0x%"PRIx64
1766 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1768 vtd_set_long(s
, addr
, val
);
1769 vtd_handle_ics_write(s
);
1772 /* Invalidation Event Control Register, 32-bit */
1773 case DMAR_IECTL_REG
:
1774 VTD_DPRINTF(INV
, "DMAR_IECTL_REG write addr 0x%"PRIx64
1775 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1777 vtd_set_long(s
, addr
, val
);
1778 vtd_handle_iectl_write(s
);
1781 /* Invalidation Event Data Register, 32-bit */
1782 case DMAR_IEDATA_REG
:
1783 VTD_DPRINTF(INV
, "DMAR_IEDATA_REG write addr 0x%"PRIx64
1784 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1786 vtd_set_long(s
, addr
, val
);
1789 /* Invalidation Event Address Register, 32-bit */
1790 case DMAR_IEADDR_REG
:
1791 VTD_DPRINTF(INV
, "DMAR_IEADDR_REG write addr 0x%"PRIx64
1792 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1794 vtd_set_long(s
, addr
, val
);
1797 /* Invalidation Event Upper Address Register, 32-bit */
1798 case DMAR_IEUADDR_REG
:
1799 VTD_DPRINTF(INV
, "DMAR_IEUADDR_REG write addr 0x%"PRIx64
1800 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1802 vtd_set_long(s
, addr
, val
);
1805 /* Fault Recording Registers, 128-bit */
1806 case DMAR_FRCD_REG_0_0
:
1807 VTD_DPRINTF(FLOG
, "DMAR_FRCD_REG_0_0 write addr 0x%"PRIx64
1808 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1810 vtd_set_long(s
, addr
, val
);
1812 vtd_set_quad(s
, addr
, val
);
1816 case DMAR_FRCD_REG_0_1
:
1817 VTD_DPRINTF(FLOG
, "DMAR_FRCD_REG_0_1 write addr 0x%"PRIx64
1818 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1820 vtd_set_long(s
, addr
, val
);
1823 case DMAR_FRCD_REG_0_2
:
1824 VTD_DPRINTF(FLOG
, "DMAR_FRCD_REG_0_2 write addr 0x%"PRIx64
1825 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1827 vtd_set_long(s
, addr
, val
);
1829 vtd_set_quad(s
, addr
, val
);
1830 /* May clear bit 127 (Fault), update PPF */
1831 vtd_update_fsts_ppf(s
);
1835 case DMAR_FRCD_REG_0_3
:
1836 VTD_DPRINTF(FLOG
, "DMAR_FRCD_REG_0_3 write addr 0x%"PRIx64
1837 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1839 vtd_set_long(s
, addr
, val
);
1840 /* May clear bit 127 (Fault), update PPF */
1841 vtd_update_fsts_ppf(s
);
1845 VTD_DPRINTF(GENERAL
, "error: unhandled reg write addr 0x%"PRIx64
1846 ", size %d, val 0x%"PRIx64
, addr
, size
, val
);
1848 vtd_set_long(s
, addr
, val
);
1850 vtd_set_quad(s
, addr
, val
);
1855 static IOMMUTLBEntry
vtd_iommu_translate(MemoryRegion
*iommu
, hwaddr addr
,
1858 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
1859 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
1860 IOMMUTLBEntry ret
= {
1861 .target_as
= &address_space_memory
,
1863 .translated_addr
= 0,
1864 .addr_mask
= ~(hwaddr
)0,
1868 if (!s
->dmar_enabled
) {
1869 /* DMAR disabled, passthrough, use 4k-page*/
1870 ret
.iova
= addr
& VTD_PAGE_MASK_4K
;
1871 ret
.translated_addr
= addr
& VTD_PAGE_MASK_4K
;
1872 ret
.addr_mask
= ~VTD_PAGE_MASK_4K
;
1873 ret
.perm
= IOMMU_RW
;
1877 vtd_do_iommu_translate(vtd_as
, vtd_as
->bus
, vtd_as
->devfn
, addr
,
1880 "bus %"PRIu8
" slot %"PRIu8
" func %"PRIu8
" devfn %"PRIu8
1881 " gpa 0x%"PRIx64
" hpa 0x%"PRIx64
, pci_bus_num(vtd_as
->bus
),
1882 VTD_PCI_SLOT(vtd_as
->devfn
), VTD_PCI_FUNC(vtd_as
->devfn
),
1883 vtd_as
->devfn
, addr
, ret
.translated_addr
);
1887 static void vtd_iommu_notify_started(MemoryRegion
*iommu
)
1889 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
1891 hw_error("Device at bus %s addr %02x.%d requires iommu notifier which "
1892 "is currently not supported by intel-iommu emulation",
1893 vtd_as
->bus
->qbus
.name
, PCI_SLOT(vtd_as
->devfn
),
1894 PCI_FUNC(vtd_as
->devfn
));
1897 static const VMStateDescription vtd_vmstate
= {
1898 .name
= "iommu-intel",
1902 static const MemoryRegionOps vtd_mem_ops
= {
1903 .read
= vtd_mem_read
,
1904 .write
= vtd_mem_write
,
1905 .endianness
= DEVICE_LITTLE_ENDIAN
,
1907 .min_access_size
= 4,
1908 .max_access_size
= 8,
1911 .min_access_size
= 4,
1912 .max_access_size
= 8,
1916 static Property vtd_properties
[] = {
1917 DEFINE_PROP_UINT32("version", IntelIOMMUState
, version
, 0),
1918 DEFINE_PROP_END_OF_LIST(),
1922 VTDAddressSpace
*vtd_find_add_as(IntelIOMMUState
*s
, PCIBus
*bus
, int devfn
)
1924 uintptr_t key
= (uintptr_t)bus
;
1925 VTDBus
*vtd_bus
= g_hash_table_lookup(s
->vtd_as_by_busptr
, &key
);
1926 VTDAddressSpace
*vtd_dev_as
;
1929 /* No corresponding free() */
1930 vtd_bus
= g_malloc0(sizeof(VTDBus
) + sizeof(VTDAddressSpace
*) * \
1931 X86_IOMMU_PCI_DEVFN_MAX
);
1933 key
= (uintptr_t)bus
;
1934 g_hash_table_insert(s
->vtd_as_by_busptr
, &key
, vtd_bus
);
1937 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
1940 vtd_bus
->dev_as
[devfn
] = vtd_dev_as
= g_malloc0(sizeof(VTDAddressSpace
));
1942 vtd_dev_as
->bus
= bus
;
1943 vtd_dev_as
->devfn
= (uint8_t)devfn
;
1944 vtd_dev_as
->iommu_state
= s
;
1945 vtd_dev_as
->context_cache_entry
.context_cache_gen
= 0;
1946 memory_region_init_iommu(&vtd_dev_as
->iommu
, OBJECT(s
),
1947 &s
->iommu_ops
, "intel_iommu", UINT64_MAX
);
1948 address_space_init(&vtd_dev_as
->as
,
1949 &vtd_dev_as
->iommu
, "intel_iommu");
1954 /* Do the initialization. It will also be called when reset, so pay
1955 * attention when adding new initialization stuff.
1957 static void vtd_init(IntelIOMMUState
*s
)
1959 memset(s
->csr
, 0, DMAR_REG_SIZE
);
1960 memset(s
->wmask
, 0, DMAR_REG_SIZE
);
1961 memset(s
->w1cmask
, 0, DMAR_REG_SIZE
);
1962 memset(s
->womask
, 0, DMAR_REG_SIZE
);
1964 s
->iommu_ops
.translate
= vtd_iommu_translate
;
1965 s
->iommu_ops
.notify_started
= vtd_iommu_notify_started
;
1967 s
->root_extended
= false;
1968 s
->dmar_enabled
= false;
1973 s
->qi_enabled
= false;
1974 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
1975 s
->next_frcd_reg
= 0;
1976 s
->cap
= VTD_CAP_FRO
| VTD_CAP_NFR
| VTD_CAP_ND
| VTD_CAP_MGAW
|
1977 VTD_CAP_SAGAW
| VTD_CAP_MAMV
| VTD_CAP_PSI
| VTD_CAP_SLLPS
;
1978 s
->ecap
= VTD_ECAP_QI
| VTD_ECAP_IRO
;
1980 vtd_reset_context_cache(s
);
1983 /* Define registers with default values and bit semantics */
1984 vtd_define_long(s
, DMAR_VER_REG
, 0x10UL
, 0, 0);
1985 vtd_define_quad(s
, DMAR_CAP_REG
, s
->cap
, 0, 0);
1986 vtd_define_quad(s
, DMAR_ECAP_REG
, s
->ecap
, 0, 0);
1987 vtd_define_long(s
, DMAR_GCMD_REG
, 0, 0xff800000UL
, 0);
1988 vtd_define_long_wo(s
, DMAR_GCMD_REG
, 0xff800000UL
);
1989 vtd_define_long(s
, DMAR_GSTS_REG
, 0, 0, 0);
1990 vtd_define_quad(s
, DMAR_RTADDR_REG
, 0, 0xfffffffffffff000ULL
, 0);
1991 vtd_define_quad(s
, DMAR_CCMD_REG
, 0, 0xe0000003ffffffffULL
, 0);
1992 vtd_define_quad_wo(s
, DMAR_CCMD_REG
, 0x3ffff0000ULL
);
1994 /* Advanced Fault Logging not supported */
1995 vtd_define_long(s
, DMAR_FSTS_REG
, 0, 0, 0x11UL
);
1996 vtd_define_long(s
, DMAR_FECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
1997 vtd_define_long(s
, DMAR_FEDATA_REG
, 0, 0x0000ffffUL
, 0);
1998 vtd_define_long(s
, DMAR_FEADDR_REG
, 0, 0xfffffffcUL
, 0);
2000 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
2001 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
2003 vtd_define_long(s
, DMAR_FEUADDR_REG
, 0, 0, 0);
2005 /* Treated as RO for implementations that PLMR and PHMR fields reported
2006 * as Clear in the CAP_REG.
2007 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
2009 vtd_define_long(s
, DMAR_PMEN_REG
, 0, 0, 0);
2011 vtd_define_quad(s
, DMAR_IQH_REG
, 0, 0, 0);
2012 vtd_define_quad(s
, DMAR_IQT_REG
, 0, 0x7fff0ULL
, 0);
2013 vtd_define_quad(s
, DMAR_IQA_REG
, 0, 0xfffffffffffff007ULL
, 0);
2014 vtd_define_long(s
, DMAR_ICS_REG
, 0, 0, 0x1UL
);
2015 vtd_define_long(s
, DMAR_IECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
2016 vtd_define_long(s
, DMAR_IEDATA_REG
, 0, 0xffffffffUL
, 0);
2017 vtd_define_long(s
, DMAR_IEADDR_REG
, 0, 0xfffffffcUL
, 0);
2018 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
2019 vtd_define_long(s
, DMAR_IEUADDR_REG
, 0, 0, 0);
2021 /* IOTLB registers */
2022 vtd_define_quad(s
, DMAR_IOTLB_REG
, 0, 0Xb003ffff00000000ULL
, 0);
2023 vtd_define_quad(s
, DMAR_IVA_REG
, 0, 0xfffffffffffff07fULL
, 0);
2024 vtd_define_quad_wo(s
, DMAR_IVA_REG
, 0xfffffffffffff07fULL
);
2026 /* Fault Recording Registers, 128-bit */
2027 vtd_define_quad(s
, DMAR_FRCD_REG_0_0
, 0, 0, 0);
2028 vtd_define_quad(s
, DMAR_FRCD_REG_0_2
, 0, 0, 0x8000000000000000ULL
);
2031 /* Should not reset address_spaces when reset because devices will still use
2032 * the address space they got at first (won't ask the bus again).
2034 static void vtd_reset(DeviceState
*dev
)
2036 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
2038 VTD_DPRINTF(GENERAL
, "");
2042 static AddressSpace
*vtd_host_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
2044 IntelIOMMUState
*s
= opaque
;
2045 VTDAddressSpace
*vtd_as
;
2047 assert(0 <= devfn
&& devfn
<= X86_IOMMU_PCI_DEVFN_MAX
);
2049 vtd_as
= vtd_find_add_as(s
, bus
, devfn
);
2053 static void vtd_realize(DeviceState
*dev
, Error
**errp
)
2055 PCIBus
*bus
= PC_MACHINE(qdev_get_machine())->bus
;
2056 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
2058 VTD_DPRINTF(GENERAL
, "");
2059 memset(s
->vtd_as_by_bus_num
, 0, sizeof(s
->vtd_as_by_bus_num
));
2060 memory_region_init_io(&s
->csrmem
, OBJECT(s
), &vtd_mem_ops
, s
,
2061 "intel_iommu", DMAR_REG_SIZE
);
2062 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->csrmem
);
2063 /* No corresponding destroy */
2064 s
->iotlb
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
2066 s
->vtd_as_by_busptr
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
2069 sysbus_mmio_map(SYS_BUS_DEVICE(s
), 0, Q35_HOST_BRIDGE_IOMMU_ADDR
);
2070 pci_setup_iommu(bus
, vtd_host_dma_iommu
, dev
);
2073 static void vtd_class_init(ObjectClass
*klass
, void *data
)
2075 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2076 X86IOMMUClass
*x86_class
= X86_IOMMU_CLASS(klass
);
2078 dc
->reset
= vtd_reset
;
2079 dc
->vmsd
= &vtd_vmstate
;
2080 dc
->props
= vtd_properties
;
2081 dc
->hotpluggable
= false;
2082 x86_class
->realize
= vtd_realize
;
2085 static const TypeInfo vtd_info
= {
2086 .name
= TYPE_INTEL_IOMMU_DEVICE
,
2087 .parent
= TYPE_X86_IOMMU_DEVICE
,
2088 .instance_size
= sizeof(IntelIOMMUState
),
2089 .class_init
= vtd_class_init
,
2092 static void vtd_register_types(void)
2094 VTD_DPRINTF(GENERAL
, "");
2095 type_register_static(&vtd_info
);
2098 type_init(vtd_register_types
)