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Port PS2 devices to VMState design
[qemu/cris-port.git] / hw / sun4m.c
blob17854dbbd2711471919bf73aecc51c893d444c90
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "qdev-addr.h"
40
41 //#define DEBUG_IRQ
42
43 /*
44 * Sun4m architecture was used in the following machines:
45 *
46 * SPARCserver 6xxMP/xx
47 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
48 * SPARCclassic X (4/10)
49 * SPARCstation LX/ZX (4/30)
50 * SPARCstation Voyager
51 * SPARCstation 10/xx, SPARCserver 10/xx
52 * SPARCstation 5, SPARCserver 5
53 * SPARCstation 20/xx, SPARCserver 20
54 * SPARCstation 4
55 *
56 * Sun4d architecture was used in the following machines:
57 *
58 * SPARCcenter 2000
59 * SPARCserver 1000
60 *
61 * Sun4c architecture was used in the following machines:
62 * SPARCstation 1/1+, SPARCserver 1/1+
63 * SPARCstation SLC
64 * SPARCstation IPC
65 * SPARCstation ELC
66 * SPARCstation IPX
67 *
68 * See for example: http://www.sunhelp.org/faq/sunref1.html
69 */
70
71 #ifdef DEBUG_IRQ
72 #define DPRINTF(fmt, ...) \
73 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
74 #else
75 #define DPRINTF(fmt, ...)
76 #endif
77
78 #define KERNEL_LOAD_ADDR 0x00004000
79 #define CMDLINE_ADDR 0x007ff000
80 #define INITRD_LOAD_ADDR 0x00800000
81 #define PROM_SIZE_MAX (1024 * 1024)
82 #define PROM_VADDR 0xffd00000
83 #define PROM_FILENAME "openbios-sparc32"
84 #define CFG_ADDR 0xd00000510ULL
85 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
86
87 #define MAX_CPUS 16
88 #define MAX_PILS 16
89
90 #define ESCC_CLOCK 4915200
91
92 struct sun4m_hwdef {
93 target_phys_addr_t iommu_base, slavio_base;
94 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
95 target_phys_addr_t serial_base, fd_base;
96 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
97 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
98 target_phys_addr_t ecc_base;
99 uint32_t ecc_version;
100 uint8_t nvram_machine_id;
101 uint16_t machine_id;
102 uint32_t iommu_version;
103 uint64_t max_mem;
104 const char * const default_cpu_model;
105 };
106
107 #define MAX_IOUNITS 5
108
109 struct sun4d_hwdef {
110 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
111 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
112 target_phys_addr_t serial_base;
113 target_phys_addr_t espdma_base, esp_base;
114 target_phys_addr_t ledma_base, le_base;
115 target_phys_addr_t tcx_base;
116 target_phys_addr_t sbi_base;
117 uint8_t nvram_machine_id;
118 uint16_t machine_id;
119 uint32_t iounit_version;
120 uint64_t max_mem;
121 const char * const default_cpu_model;
122 };
123
124 struct sun4c_hwdef {
125 target_phys_addr_t iommu_base, slavio_base;
126 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
127 target_phys_addr_t serial_base, fd_base;
128 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
129 target_phys_addr_t tcx_base, aux1_base;
130 uint8_t nvram_machine_id;
131 uint16_t machine_id;
132 uint32_t iommu_version;
133 uint64_t max_mem;
134 const char * const default_cpu_model;
135 };
136
137 int DMA_get_channel_mode (int nchan)
138 {
139 return 0;
140 }
141 int DMA_read_memory (int nchan, void *buf, int pos, int size)
142 {
143 return 0;
144 }
145 int DMA_write_memory (int nchan, void *buf, int pos, int size)
146 {
147 return 0;
148 }
149 void DMA_hold_DREQ (int nchan) {}
150 void DMA_release_DREQ (int nchan) {}
151 void DMA_schedule(int nchan) {}
152 void DMA_init (int high_page_enable) {}
153 void DMA_register_channel (int nchan,
154 DMA_transfer_handler transfer_handler,
155 void *opaque)
156 {
157 }
158
159 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
160 {
161 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
162 return 0;
163 }
164
165 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
166 const char *boot_devices, ram_addr_t RAM_size,
167 uint32_t kernel_size,
168 int width, int height, int depth,
169 int nvram_machine_id, const char *arch)
170 {
171 unsigned int i;
172 uint32_t start, end;
173 uint8_t image[0x1ff0];
174 struct OpenBIOS_nvpart_v1 *part_header;
175
176 memset(image, '\0', sizeof(image));
177
178 start = 0;
179
180 // OpenBIOS nvram variables
181 // Variable partition
182 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
183 part_header->signature = OPENBIOS_PART_SYSTEM;
184 pstrcpy(part_header->name, sizeof(part_header->name), "system");
185
186 end = start + sizeof(struct OpenBIOS_nvpart_v1);
187 for (i = 0; i < nb_prom_envs; i++)
188 end = OpenBIOS_set_var(image, end, prom_envs[i]);
189
190 // End marker
191 image[end++] = '\0';
192
193 end = start + ((end - start + 15) & ~15);
194 OpenBIOS_finish_partition(part_header, end - start);
195
196 // free partition
197 start = end;
198 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
199 part_header->signature = OPENBIOS_PART_FREE;
200 pstrcpy(part_header->name, sizeof(part_header->name), "free");
201
202 end = 0x1fd0;
203 OpenBIOS_finish_partition(part_header, end - start);
204
205 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
206 nvram_machine_id);
207
208 for (i = 0; i < sizeof(image); i++)
209 m48t59_write(nvram, i, image[i]);
210 }
211
212 static DeviceState *slavio_intctl;
213
214 void pic_info(Monitor *mon)
215 {
216 if (slavio_intctl)
217 slavio_pic_info(mon, slavio_intctl);
218 }
219
220 void irq_info(Monitor *mon)
221 {
222 if (slavio_intctl)
223 slavio_irq_info(mon, slavio_intctl);
224 }
225
226 void cpu_check_irqs(CPUState *env)
227 {
228 if (env->pil_in && (env->interrupt_index == 0 ||
229 (env->interrupt_index & ~15) == TT_EXTINT)) {
230 unsigned int i;
231
232 for (i = 15; i > 0; i--) {
233 if (env->pil_in & (1 << i)) {
234 int old_interrupt = env->interrupt_index;
235
236 env->interrupt_index = TT_EXTINT | i;
237 if (old_interrupt != env->interrupt_index) {
238 DPRINTF("Set CPU IRQ %d\n", i);
239 cpu_interrupt(env, CPU_INTERRUPT_HARD);
240 }
241 break;
242 }
243 }
244 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
245 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
246 env->interrupt_index = 0;
247 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
248 }
249 }
250
251 static void cpu_set_irq(void *opaque, int irq, int level)
252 {
253 CPUState *env = opaque;
254
255 if (level) {
256 DPRINTF("Raise CPU IRQ %d\n", irq);
257 env->halted = 0;
258 env->pil_in |= 1 << irq;
259 cpu_check_irqs(env);
260 } else {
261 DPRINTF("Lower CPU IRQ %d\n", irq);
262 env->pil_in &= ~(1 << irq);
263 cpu_check_irqs(env);
264 }
265 }
266
267 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
268 {
269 }
270
271 static void main_cpu_reset(void *opaque)
272 {
273 CPUState *env = opaque;
274
275 cpu_reset(env);
276 env->halted = 0;
277 }
278
279 static void secondary_cpu_reset(void *opaque)
280 {
281 CPUState *env = opaque;
282
283 cpu_reset(env);
284 env->halted = 1;
285 }
286
287 static void cpu_halt_signal(void *opaque, int irq, int level)
288 {
289 if (level && cpu_single_env)
290 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
291 }
292
293 static unsigned long sun4m_load_kernel(const char *kernel_filename,
294 const char *initrd_filename,
295 ram_addr_t RAM_size)
296 {
297 int linux_boot;
298 unsigned int i;
299 long initrd_size, kernel_size;
300
301 linux_boot = (kernel_filename != NULL);
302
303 kernel_size = 0;
304 if (linux_boot) {
305 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
306 NULL);
307 if (kernel_size < 0)
308 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
309 RAM_size - KERNEL_LOAD_ADDR);
310 if (kernel_size < 0)
311 kernel_size = load_image_targphys(kernel_filename,
312 KERNEL_LOAD_ADDR,
313 RAM_size - KERNEL_LOAD_ADDR);
314 if (kernel_size < 0) {
315 fprintf(stderr, "qemu: could not load kernel '%s'\n",
316 kernel_filename);
317 exit(1);
318 }
319
320 /* load initrd */
321 initrd_size = 0;
322 if (initrd_filename) {
323 initrd_size = load_image_targphys(initrd_filename,
324 INITRD_LOAD_ADDR,
325 RAM_size - INITRD_LOAD_ADDR);
326 if (initrd_size < 0) {
327 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
328 initrd_filename);
329 exit(1);
330 }
331 }
332 if (initrd_size > 0) {
333 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
334 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
335 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
336 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
337 break;
338 }
339 }
340 }
341 }
342 return kernel_size;
343 }
344
345 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
346 {
347 DeviceState *dev;
348 SysBusDevice *s;
349
350 dev = qdev_create(NULL, "iommu");
351 qdev_prop_set_uint32(dev, "version", version);
352 qdev_init(dev);
353 s = sysbus_from_qdev(dev);
354 sysbus_connect_irq(s, 0, irq);
355 sysbus_mmio_map(s, 0, addr);
356
357 return s;
358 }
359
360 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
361 void *iommu, qemu_irq *dev_irq)
362 {
363 DeviceState *dev;
364 SysBusDevice *s;
365
366 dev = qdev_create(NULL, "sparc32_dma");
367 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
368 qdev_init(dev);
369 s = sysbus_from_qdev(dev);
370 sysbus_connect_irq(s, 0, parent_irq);
371 *dev_irq = qdev_get_gpio_in(dev, 0);
372 sysbus_mmio_map(s, 0, daddr);
373
374 return s;
375 }
376
377 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
378 void *dma_opaque, qemu_irq irq)
379 {
380 DeviceState *dev;
381 SysBusDevice *s;
382 qemu_irq reset;
383
384 qemu_check_nic_model(&nd_table[0], "lance");
385
386 dev = qdev_create(NULL, "lance");
387 dev->nd = nd;
388 qdev_prop_set_ptr(dev, "dma", dma_opaque);
389 qdev_init(dev);
390 s = sysbus_from_qdev(dev);
391 sysbus_mmio_map(s, 0, leaddr);
392 sysbus_connect_irq(s, 0, irq);
393 reset = qdev_get_gpio_in(dev, 0);
394 qdev_connect_gpio_out(dma_opaque, 0, reset);
395 }
396
397 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
398 target_phys_addr_t addrg,
399 qemu_irq **parent_irq)
400 {
401 DeviceState *dev;
402 SysBusDevice *s;
403 unsigned int i, j;
404
405 dev = qdev_create(NULL, "slavio_intctl");
406 qdev_init(dev);
407
408 s = sysbus_from_qdev(dev);
409
410 for (i = 0; i < MAX_CPUS; i++) {
411 for (j = 0; j < MAX_PILS; j++) {
412 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
413 }
414 }
415 sysbus_mmio_map(s, 0, addrg);
416 for (i = 0; i < MAX_CPUS; i++) {
417 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
418 }
419
420 return dev;
421 }
422
423 #define SYS_TIMER_OFFSET 0x10000ULL
424 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
425
426 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
427 qemu_irq *cpu_irqs, unsigned int num_cpus)
428 {
429 DeviceState *dev;
430 SysBusDevice *s;
431 unsigned int i;
432
433 dev = qdev_create(NULL, "slavio_timer");
434 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
435 qdev_init(dev);
436 s = sysbus_from_qdev(dev);
437 sysbus_connect_irq(s, 0, master_irq);
438 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
439
440 for (i = 0; i < MAX_CPUS; i++) {
441 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
442 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
443 }
444 }
445
446 #define MISC_LEDS 0x01600000
447 #define MISC_CFG 0x01800000
448 #define MISC_DIAG 0x01a00000
449 #define MISC_MDM 0x01b00000
450 #define MISC_SYS 0x01f00000
451
452 static void slavio_misc_init(target_phys_addr_t base,
453 target_phys_addr_t aux1_base,
454 target_phys_addr_t aux2_base, qemu_irq irq,
455 qemu_irq fdc_tc)
456 {
457 DeviceState *dev;
458 SysBusDevice *s;
459
460 dev = qdev_create(NULL, "slavio_misc");
461 qdev_init(dev);
462 s = sysbus_from_qdev(dev);
463 if (base) {
464 /* 8 bit registers */
465 /* Slavio control */
466 sysbus_mmio_map(s, 0, base + MISC_CFG);
467 /* Diagnostics */
468 sysbus_mmio_map(s, 1, base + MISC_DIAG);
469 /* Modem control */
470 sysbus_mmio_map(s, 2, base + MISC_MDM);
471 /* 16 bit registers */
472 /* ss600mp diag LEDs */
473 sysbus_mmio_map(s, 3, base + MISC_LEDS);
474 /* 32 bit registers */
475 /* System control */
476 sysbus_mmio_map(s, 4, base + MISC_SYS);
477 }
478 if (aux1_base) {
479 /* AUX 1 (Misc System Functions) */
480 sysbus_mmio_map(s, 5, aux1_base);
481 }
482 if (aux2_base) {
483 /* AUX 2 (Software Powerdown Control) */
484 sysbus_mmio_map(s, 6, aux2_base);
485 }
486 sysbus_connect_irq(s, 0, irq);
487 sysbus_connect_irq(s, 1, fdc_tc);
488 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
489 }
490
491 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
492 {
493 DeviceState *dev;
494 SysBusDevice *s;
495
496 dev = qdev_create(NULL, "eccmemctl");
497 qdev_prop_set_uint32(dev, "version", version);
498 qdev_init(dev);
499 s = sysbus_from_qdev(dev);
500 sysbus_connect_irq(s, 0, irq);
501 sysbus_mmio_map(s, 0, base);
502 if (version == 0) { // SS-600MP only
503 sysbus_mmio_map(s, 1, base + 0x1000);
504 }
505 }
506
507 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
508 {
509 DeviceState *dev;
510 SysBusDevice *s;
511
512 dev = qdev_create(NULL, "apc");
513 qdev_init(dev);
514 s = sysbus_from_qdev(dev);
515 /* Power management (APC) XXX: not a Slavio device */
516 sysbus_mmio_map(s, 0, power_base);
517 sysbus_connect_irq(s, 0, cpu_halt);
518 }
519
520 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
521 int height, int depth)
522 {
523 DeviceState *dev;
524 SysBusDevice *s;
525
526 dev = qdev_create(NULL, "SUNW,tcx");
527 qdev_prop_set_taddr(dev, "addr", addr);
528 qdev_prop_set_uint32(dev, "vram_size", vram_size);
529 qdev_prop_set_uint16(dev, "width", width);
530 qdev_prop_set_uint16(dev, "height", height);
531 qdev_prop_set_uint16(dev, "depth", depth);
532 qdev_init(dev);
533 s = sysbus_from_qdev(dev);
534 /* 8-bit plane */
535 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
536 /* DAC */
537 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
538 /* TEC (dummy) */
539 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
540 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
541 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
542 if (depth == 24) {
543 /* 24-bit plane */
544 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
545 /* Control plane */
546 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
547 } else {
548 /* THC 8 bit (dummy) */
549 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
550 }
551 }
552
553 /* NCR89C100/MACIO Internal ID register */
554 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
555
556 static void idreg_init(target_phys_addr_t addr)
557 {
558 DeviceState *dev;
559 SysBusDevice *s;
560
561 dev = qdev_create(NULL, "macio_idreg");
562 qdev_init(dev);
563 s = sysbus_from_qdev(dev);
564
565 sysbus_mmio_map(s, 0, addr);
566 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
567 }
568
569 static void idreg_init1(SysBusDevice *dev)
570 {
571 ram_addr_t idreg_offset;
572
573 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
574 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
575 }
576
577 static SysBusDeviceInfo idreg_info = {
578 .init = idreg_init1,
579 .qdev.name = "macio_idreg",
580 .qdev.size = sizeof(SysBusDevice),
581 };
582
583 static void idreg_register_devices(void)
584 {
585 sysbus_register_withprop(&idreg_info);
586 }
587
588 device_init(idreg_register_devices);
589
590 /* Boot PROM (OpenBIOS) */
591 static void prom_init(target_phys_addr_t addr, const char *bios_name)
592 {
593 DeviceState *dev;
594 SysBusDevice *s;
595 char *filename;
596 int ret;
597
598 dev = qdev_create(NULL, "openprom");
599 qdev_init(dev);
600 s = sysbus_from_qdev(dev);
601
602 sysbus_mmio_map(s, 0, addr);
603
604 /* load boot prom */
605 if (bios_name == NULL) {
606 bios_name = PROM_FILENAME;
607 }
608 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
609 if (filename) {
610 ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
611 if (ret < 0 || ret > PROM_SIZE_MAX) {
612 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
613 }
614 qemu_free(filename);
615 } else {
616 ret = -1;
617 }
618 if (ret < 0 || ret > PROM_SIZE_MAX) {
619 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
620 exit(1);
621 }
622 }
623
624 static void prom_init1(SysBusDevice *dev)
625 {
626 ram_addr_t prom_offset;
627
628 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
629 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
630 }
631
632 static SysBusDeviceInfo prom_info = {
633 .init = prom_init1,
634 .qdev.name = "openprom",
635 .qdev.size = sizeof(SysBusDevice),
636 .qdev.props = (Property[]) {
637 {/* end of property list */}
638 }
639 };
640
641 static void prom_register_devices(void)
642 {
643 sysbus_register_withprop(&prom_info);
644 }
645
646 device_init(prom_register_devices);
647
648 typedef struct RamDevice
649 {
650 SysBusDevice busdev;
651 uint64_t size;
652 } RamDevice;
653
654 /* System RAM */
655 static void ram_init1(SysBusDevice *dev)
656 {
657 ram_addr_t RAM_size, ram_offset;
658 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
659
660 RAM_size = d->size;
661
662 ram_offset = qemu_ram_alloc(RAM_size);
663 sysbus_init_mmio(dev, RAM_size, ram_offset);
664 }
665
666 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
667 uint64_t max_mem)
668 {
669 DeviceState *dev;
670 SysBusDevice *s;
671 RamDevice *d;
672
673 /* allocate RAM */
674 if ((uint64_t)RAM_size > max_mem) {
675 fprintf(stderr,
676 "qemu: Too much memory for this machine: %d, maximum %d\n",
677 (unsigned int)(RAM_size / (1024 * 1024)),
678 (unsigned int)(max_mem / (1024 * 1024)));
679 exit(1);
680 }
681 dev = qdev_create(NULL, "memory");
682 s = sysbus_from_qdev(dev);
683
684 d = FROM_SYSBUS(RamDevice, s);
685 d->size = RAM_size;
686 qdev_init(dev);
687
688 sysbus_mmio_map(s, 0, addr);
689 }
690
691 static SysBusDeviceInfo ram_info = {
692 .init = ram_init1,
693 .qdev.name = "memory",
694 .qdev.size = sizeof(RamDevice),
695 .qdev.props = (Property[]) {
696 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
697 DEFINE_PROP_END_OF_LIST(),
698 }
699 };
700
701 static void ram_register_devices(void)
702 {
703 sysbus_register_withprop(&ram_info);
704 }
705
706 device_init(ram_register_devices);
707
708 static CPUState *cpu_devinit(const char *cpu_model, unsigned int id,
709 uint64_t prom_addr, qemu_irq **cpu_irqs)
710 {
711 CPUState *env;
712
713 env = cpu_init(cpu_model);
714 if (!env) {
715 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
716 exit(1);
717 }
718
719 cpu_sparc_set_id(env, id);
720 if (id == 0) {
721 qemu_register_reset(main_cpu_reset, env);
722 } else {
723 qemu_register_reset(secondary_cpu_reset, env);
724 env->halted = 1;
725 }
726 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
727 env->prom_addr = prom_addr;
728
729 return env;
730 }
731
732 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
733 const char *boot_device,
734 const char *kernel_filename,
735 const char *kernel_cmdline,
736 const char *initrd_filename, const char *cpu_model)
737 {
738 CPUState *envs[MAX_CPUS];
739 unsigned int i;
740 void *iommu, *espdma, *ledma, *nvram;
741 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
742 espdma_irq, ledma_irq;
743 qemu_irq esp_reset;
744 qemu_irq fdc_tc;
745 qemu_irq *cpu_halt;
746 unsigned long kernel_size;
747 BlockDriverState *fd[MAX_FD];
748 void *fw_cfg;
749 DriveInfo *dinfo;
750
751 /* init CPUs */
752 if (!cpu_model)
753 cpu_model = hwdef->default_cpu_model;
754
755 for(i = 0; i < smp_cpus; i++) {
756 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
757 }
758
759 for (i = smp_cpus; i < MAX_CPUS; i++)
760 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
761
762
763 /* set up devices */
764 ram_init(0, RAM_size, hwdef->max_mem);
765
766 prom_init(hwdef->slavio_base, bios_name);
767
768 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
769 hwdef->intctl_base + 0x10000ULL,
770 cpu_irqs);
771
772 for (i = 0; i < 32; i++) {
773 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
774 }
775 for (i = 0; i < MAX_CPUS; i++) {
776 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
777 }
778
779 if (hwdef->idreg_base) {
780 idreg_init(hwdef->idreg_base);
781 }
782
783 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
784 slavio_irq[30]);
785
786 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
787 iommu, &espdma_irq);
788
789 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
790 slavio_irq[16], iommu, &ledma_irq);
791
792 if (graphic_depth != 8 && graphic_depth != 24) {
793 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
794 exit (1);
795 }
796 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
797 graphic_depth);
798
799 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
800
801 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
802
803 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
804
805 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
806 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
807 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
808 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
809 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
810 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
811
812 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
813 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
814 slavio_irq[30], fdc_tc);
815
816 if (hwdef->apc_base) {
817 apc_init(hwdef->apc_base, cpu_halt[0]);
818 }
819
820 if (hwdef->fd_base) {
821 /* there is zero or one floppy drive */
822 memset(fd, 0, sizeof(fd));
823 dinfo = drive_get(IF_FLOPPY, 0, 0);
824 if (dinfo)
825 fd[0] = dinfo->bdrv;
826
827 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
828 &fdc_tc);
829 }
830
831 if (drive_get_max_bus(IF_SCSI) > 0) {
832 fprintf(stderr, "qemu: too many SCSI bus\n");
833 exit(1);
834 }
835
836 esp_reset = qdev_get_gpio_in(espdma, 0);
837 esp_init(hwdef->esp_base, 2,
838 espdma_memory_read, espdma_memory_write,
839 espdma, espdma_irq, &esp_reset);
840
841
842 if (hwdef->cs_base) {
843 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
844 slavio_irq[5]);
845 }
846
847 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
848 RAM_size);
849
850 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
851 boot_device, RAM_size, kernel_size, graphic_width,
852 graphic_height, graphic_depth, hwdef->nvram_machine_id,
853 "Sun4m");
854
855 if (hwdef->ecc_base)
856 ecc_init(hwdef->ecc_base, slavio_irq[28],
857 hwdef->ecc_version);
858
859 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
860 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
861 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
862 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
863 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
864 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
865 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
866 if (kernel_cmdline) {
867 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
868 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
869 } else {
870 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
871 }
872 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
873 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
874 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
875 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
876 }
877
878 enum {
879 ss2_id = 0,
880 ss5_id = 32,
881 vger_id,
882 lx_id,
883 ss4_id,
884 scls_id,
885 sbook_id,
886 ss10_id = 64,
887 ss20_id,
888 ss600mp_id,
889 ss1000_id = 96,
890 ss2000_id,
891 };
892
893 static const struct sun4m_hwdef sun4m_hwdefs[] = {
894 /* SS-5 */
895 {
896 .iommu_base = 0x10000000,
897 .tcx_base = 0x50000000,
898 .cs_base = 0x6c000000,
899 .slavio_base = 0x70000000,
900 .ms_kb_base = 0x71000000,
901 .serial_base = 0x71100000,
902 .nvram_base = 0x71200000,
903 .fd_base = 0x71400000,
904 .counter_base = 0x71d00000,
905 .intctl_base = 0x71e00000,
906 .idreg_base = 0x78000000,
907 .dma_base = 0x78400000,
908 .esp_base = 0x78800000,
909 .le_base = 0x78c00000,
910 .apc_base = 0x6a000000,
911 .aux1_base = 0x71900000,
912 .aux2_base = 0x71910000,
913 .nvram_machine_id = 0x80,
914 .machine_id = ss5_id,
915 .iommu_version = 0x05000000,
916 .max_mem = 0x10000000,
917 .default_cpu_model = "Fujitsu MB86904",
918 },
919 /* SS-10 */
920 {
921 .iommu_base = 0xfe0000000ULL,
922 .tcx_base = 0xe20000000ULL,
923 .slavio_base = 0xff0000000ULL,
924 .ms_kb_base = 0xff1000000ULL,
925 .serial_base = 0xff1100000ULL,
926 .nvram_base = 0xff1200000ULL,
927 .fd_base = 0xff1700000ULL,
928 .counter_base = 0xff1300000ULL,
929 .intctl_base = 0xff1400000ULL,
930 .idreg_base = 0xef0000000ULL,
931 .dma_base = 0xef0400000ULL,
932 .esp_base = 0xef0800000ULL,
933 .le_base = 0xef0c00000ULL,
934 .apc_base = 0xefa000000ULL, // XXX should not exist
935 .aux1_base = 0xff1800000ULL,
936 .aux2_base = 0xff1a01000ULL,
937 .ecc_base = 0xf00000000ULL,
938 .ecc_version = 0x10000000, // version 0, implementation 1
939 .nvram_machine_id = 0x72,
940 .machine_id = ss10_id,
941 .iommu_version = 0x03000000,
942 .max_mem = 0xf00000000ULL,
943 .default_cpu_model = "TI SuperSparc II",
944 },
945 /* SS-600MP */
946 {
947 .iommu_base = 0xfe0000000ULL,
948 .tcx_base = 0xe20000000ULL,
949 .slavio_base = 0xff0000000ULL,
950 .ms_kb_base = 0xff1000000ULL,
951 .serial_base = 0xff1100000ULL,
952 .nvram_base = 0xff1200000ULL,
953 .counter_base = 0xff1300000ULL,
954 .intctl_base = 0xff1400000ULL,
955 .dma_base = 0xef0081000ULL,
956 .esp_base = 0xef0080000ULL,
957 .le_base = 0xef0060000ULL,
958 .apc_base = 0xefa000000ULL, // XXX should not exist
959 .aux1_base = 0xff1800000ULL,
960 .aux2_base = 0xff1a01000ULL, // XXX should not exist
961 .ecc_base = 0xf00000000ULL,
962 .ecc_version = 0x00000000, // version 0, implementation 0
963 .nvram_machine_id = 0x71,
964 .machine_id = ss600mp_id,
965 .iommu_version = 0x01000000,
966 .max_mem = 0xf00000000ULL,
967 .default_cpu_model = "TI SuperSparc II",
968 },
969 /* SS-20 */
970 {
971 .iommu_base = 0xfe0000000ULL,
972 .tcx_base = 0xe20000000ULL,
973 .slavio_base = 0xff0000000ULL,
974 .ms_kb_base = 0xff1000000ULL,
975 .serial_base = 0xff1100000ULL,
976 .nvram_base = 0xff1200000ULL,
977 .fd_base = 0xff1700000ULL,
978 .counter_base = 0xff1300000ULL,
979 .intctl_base = 0xff1400000ULL,
980 .idreg_base = 0xef0000000ULL,
981 .dma_base = 0xef0400000ULL,
982 .esp_base = 0xef0800000ULL,
983 .le_base = 0xef0c00000ULL,
984 .apc_base = 0xefa000000ULL, // XXX should not exist
985 .aux1_base = 0xff1800000ULL,
986 .aux2_base = 0xff1a01000ULL,
987 .ecc_base = 0xf00000000ULL,
988 .ecc_version = 0x20000000, // version 0, implementation 2
989 .nvram_machine_id = 0x72,
990 .machine_id = ss20_id,
991 .iommu_version = 0x13000000,
992 .max_mem = 0xf00000000ULL,
993 .default_cpu_model = "TI SuperSparc II",
994 },
995 /* Voyager */
996 {
997 .iommu_base = 0x10000000,
998 .tcx_base = 0x50000000,
999 .slavio_base = 0x70000000,
1000 .ms_kb_base = 0x71000000,
1001 .serial_base = 0x71100000,
1002 .nvram_base = 0x71200000,
1003 .fd_base = 0x71400000,
1004 .counter_base = 0x71d00000,
1005 .intctl_base = 0x71e00000,
1006 .idreg_base = 0x78000000,
1007 .dma_base = 0x78400000,
1008 .esp_base = 0x78800000,
1009 .le_base = 0x78c00000,
1010 .apc_base = 0x71300000, // pmc
1011 .aux1_base = 0x71900000,
1012 .aux2_base = 0x71910000,
1013 .nvram_machine_id = 0x80,
1014 .machine_id = vger_id,
1015 .iommu_version = 0x05000000,
1016 .max_mem = 0x10000000,
1017 .default_cpu_model = "Fujitsu MB86904",
1018 },
1019 /* LX */
1020 {
1021 .iommu_base = 0x10000000,
1022 .tcx_base = 0x50000000,
1023 .slavio_base = 0x70000000,
1024 .ms_kb_base = 0x71000000,
1025 .serial_base = 0x71100000,
1026 .nvram_base = 0x71200000,
1027 .fd_base = 0x71400000,
1028 .counter_base = 0x71d00000,
1029 .intctl_base = 0x71e00000,
1030 .idreg_base = 0x78000000,
1031 .dma_base = 0x78400000,
1032 .esp_base = 0x78800000,
1033 .le_base = 0x78c00000,
1034 .aux1_base = 0x71900000,
1035 .aux2_base = 0x71910000,
1036 .nvram_machine_id = 0x80,
1037 .machine_id = lx_id,
1038 .iommu_version = 0x04000000,
1039 .max_mem = 0x10000000,
1040 .default_cpu_model = "TI MicroSparc I",
1041 },
1042 /* SS-4 */
1043 {
1044 .iommu_base = 0x10000000,
1045 .tcx_base = 0x50000000,
1046 .cs_base = 0x6c000000,
1047 .slavio_base = 0x70000000,
1048 .ms_kb_base = 0x71000000,
1049 .serial_base = 0x71100000,
1050 .nvram_base = 0x71200000,
1051 .fd_base = 0x71400000,
1052 .counter_base = 0x71d00000,
1053 .intctl_base = 0x71e00000,
1054 .idreg_base = 0x78000000,
1055 .dma_base = 0x78400000,
1056 .esp_base = 0x78800000,
1057 .le_base = 0x78c00000,
1058 .apc_base = 0x6a000000,
1059 .aux1_base = 0x71900000,
1060 .aux2_base = 0x71910000,
1061 .nvram_machine_id = 0x80,
1062 .machine_id = ss4_id,
1063 .iommu_version = 0x05000000,
1064 .max_mem = 0x10000000,
1065 .default_cpu_model = "Fujitsu MB86904",
1066 },
1067 /* SPARCClassic */
1068 {
1069 .iommu_base = 0x10000000,
1070 .tcx_base = 0x50000000,
1071 .slavio_base = 0x70000000,
1072 .ms_kb_base = 0x71000000,
1073 .serial_base = 0x71100000,
1074 .nvram_base = 0x71200000,
1075 .fd_base = 0x71400000,
1076 .counter_base = 0x71d00000,
1077 .intctl_base = 0x71e00000,
1078 .idreg_base = 0x78000000,
1079 .dma_base = 0x78400000,
1080 .esp_base = 0x78800000,
1081 .le_base = 0x78c00000,
1082 .apc_base = 0x6a000000,
1083 .aux1_base = 0x71900000,
1084 .aux2_base = 0x71910000,
1085 .nvram_machine_id = 0x80,
1086 .machine_id = scls_id,
1087 .iommu_version = 0x05000000,
1088 .max_mem = 0x10000000,
1089 .default_cpu_model = "TI MicroSparc I",
1090 },
1091 /* SPARCbook */
1092 {
1093 .iommu_base = 0x10000000,
1094 .tcx_base = 0x50000000, // XXX
1095 .slavio_base = 0x70000000,
1096 .ms_kb_base = 0x71000000,
1097 .serial_base = 0x71100000,
1098 .nvram_base = 0x71200000,
1099 .fd_base = 0x71400000,
1100 .counter_base = 0x71d00000,
1101 .intctl_base = 0x71e00000,
1102 .idreg_base = 0x78000000,
1103 .dma_base = 0x78400000,
1104 .esp_base = 0x78800000,
1105 .le_base = 0x78c00000,
1106 .apc_base = 0x6a000000,
1107 .aux1_base = 0x71900000,
1108 .aux2_base = 0x71910000,
1109 .nvram_machine_id = 0x80,
1110 .machine_id = sbook_id,
1111 .iommu_version = 0x05000000,
1112 .max_mem = 0x10000000,
1113 .default_cpu_model = "TI MicroSparc I",
1114 },
1115 };
1116
1117 /* SPARCstation 5 hardware initialisation */
1118 static void ss5_init(ram_addr_t RAM_size,
1119 const char *boot_device,
1120 const char *kernel_filename, const char *kernel_cmdline,
1121 const char *initrd_filename, const char *cpu_model)
1122 {
1123 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1124 kernel_cmdline, initrd_filename, cpu_model);
1125 }
1126
1127 /* SPARCstation 10 hardware initialisation */
1128 static void ss10_init(ram_addr_t RAM_size,
1129 const char *boot_device,
1130 const char *kernel_filename, const char *kernel_cmdline,
1131 const char *initrd_filename, const char *cpu_model)
1132 {
1133 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1134 kernel_cmdline, initrd_filename, cpu_model);
1135 }
1136
1137 /* SPARCserver 600MP hardware initialisation */
1138 static void ss600mp_init(ram_addr_t RAM_size,
1139 const char *boot_device,
1140 const char *kernel_filename,
1141 const char *kernel_cmdline,
1142 const char *initrd_filename, const char *cpu_model)
1143 {
1144 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1145 kernel_cmdline, initrd_filename, cpu_model);
1146 }
1147
1148 /* SPARCstation 20 hardware initialisation */
1149 static void ss20_init(ram_addr_t RAM_size,
1150 const char *boot_device,
1151 const char *kernel_filename, const char *kernel_cmdline,
1152 const char *initrd_filename, const char *cpu_model)
1153 {
1154 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1155 kernel_cmdline, initrd_filename, cpu_model);
1156 }
1157
1158 /* SPARCstation Voyager hardware initialisation */
1159 static void vger_init(ram_addr_t RAM_size,
1160 const char *boot_device,
1161 const char *kernel_filename, const char *kernel_cmdline,
1162 const char *initrd_filename, const char *cpu_model)
1163 {
1164 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1165 kernel_cmdline, initrd_filename, cpu_model);
1166 }
1167
1168 /* SPARCstation LX hardware initialisation */
1169 static void ss_lx_init(ram_addr_t RAM_size,
1170 const char *boot_device,
1171 const char *kernel_filename, const char *kernel_cmdline,
1172 const char *initrd_filename, const char *cpu_model)
1173 {
1174 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1175 kernel_cmdline, initrd_filename, cpu_model);
1176 }
1177
1178 /* SPARCstation 4 hardware initialisation */
1179 static void ss4_init(ram_addr_t RAM_size,
1180 const char *boot_device,
1181 const char *kernel_filename, const char *kernel_cmdline,
1182 const char *initrd_filename, const char *cpu_model)
1183 {
1184 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1185 kernel_cmdline, initrd_filename, cpu_model);
1186 }
1187
1188 /* SPARCClassic hardware initialisation */
1189 static void scls_init(ram_addr_t RAM_size,
1190 const char *boot_device,
1191 const char *kernel_filename, const char *kernel_cmdline,
1192 const char *initrd_filename, const char *cpu_model)
1193 {
1194 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1195 kernel_cmdline, initrd_filename, cpu_model);
1196 }
1197
1198 /* SPARCbook hardware initialisation */
1199 static void sbook_init(ram_addr_t RAM_size,
1200 const char *boot_device,
1201 const char *kernel_filename, const char *kernel_cmdline,
1202 const char *initrd_filename, const char *cpu_model)
1203 {
1204 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1205 kernel_cmdline, initrd_filename, cpu_model);
1206 }
1207
1208 static QEMUMachine ss5_machine = {
1209 .name = "SS-5",
1210 .desc = "Sun4m platform, SPARCstation 5",
1211 .init = ss5_init,
1212 .use_scsi = 1,
1213 .is_default = 1,
1214 };
1215
1216 static QEMUMachine ss10_machine = {
1217 .name = "SS-10",
1218 .desc = "Sun4m platform, SPARCstation 10",
1219 .init = ss10_init,
1220 .use_scsi = 1,
1221 .max_cpus = 4,
1222 };
1223
1224 static QEMUMachine ss600mp_machine = {
1225 .name = "SS-600MP",
1226 .desc = "Sun4m platform, SPARCserver 600MP",
1227 .init = ss600mp_init,
1228 .use_scsi = 1,
1229 .max_cpus = 4,
1230 };
1231
1232 static QEMUMachine ss20_machine = {
1233 .name = "SS-20",
1234 .desc = "Sun4m platform, SPARCstation 20",
1235 .init = ss20_init,
1236 .use_scsi = 1,
1237 .max_cpus = 4,
1238 };
1239
1240 static QEMUMachine voyager_machine = {
1241 .name = "Voyager",
1242 .desc = "Sun4m platform, SPARCstation Voyager",
1243 .init = vger_init,
1244 .use_scsi = 1,
1245 };
1246
1247 static QEMUMachine ss_lx_machine = {
1248 .name = "LX",
1249 .desc = "Sun4m platform, SPARCstation LX",
1250 .init = ss_lx_init,
1251 .use_scsi = 1,
1252 };
1253
1254 static QEMUMachine ss4_machine = {
1255 .name = "SS-4",
1256 .desc = "Sun4m platform, SPARCstation 4",
1257 .init = ss4_init,
1258 .use_scsi = 1,
1259 };
1260
1261 static QEMUMachine scls_machine = {
1262 .name = "SPARCClassic",
1263 .desc = "Sun4m platform, SPARCClassic",
1264 .init = scls_init,
1265 .use_scsi = 1,
1266 };
1267
1268 static QEMUMachine sbook_machine = {
1269 .name = "SPARCbook",
1270 .desc = "Sun4m platform, SPARCbook",
1271 .init = sbook_init,
1272 .use_scsi = 1,
1273 };
1274
1275 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1276 /* SS-1000 */
1277 {
1278 .iounit_bases = {
1279 0xfe0200000ULL,
1280 0xfe1200000ULL,
1281 0xfe2200000ULL,
1282 0xfe3200000ULL,
1283 -1,
1284 },
1285 .tcx_base = 0x820000000ULL,
1286 .slavio_base = 0xf00000000ULL,
1287 .ms_kb_base = 0xf00240000ULL,
1288 .serial_base = 0xf00200000ULL,
1289 .nvram_base = 0xf00280000ULL,
1290 .counter_base = 0xf00300000ULL,
1291 .espdma_base = 0x800081000ULL,
1292 .esp_base = 0x800080000ULL,
1293 .ledma_base = 0x800040000ULL,
1294 .le_base = 0x800060000ULL,
1295 .sbi_base = 0xf02800000ULL,
1296 .nvram_machine_id = 0x80,
1297 .machine_id = ss1000_id,
1298 .iounit_version = 0x03000000,
1299 .max_mem = 0xf00000000ULL,
1300 .default_cpu_model = "TI SuperSparc II",
1301 },
1302 /* SS-2000 */
1303 {
1304 .iounit_bases = {
1305 0xfe0200000ULL,
1306 0xfe1200000ULL,
1307 0xfe2200000ULL,
1308 0xfe3200000ULL,
1309 0xfe4200000ULL,
1310 },
1311 .tcx_base = 0x820000000ULL,
1312 .slavio_base = 0xf00000000ULL,
1313 .ms_kb_base = 0xf00240000ULL,
1314 .serial_base = 0xf00200000ULL,
1315 .nvram_base = 0xf00280000ULL,
1316 .counter_base = 0xf00300000ULL,
1317 .espdma_base = 0x800081000ULL,
1318 .esp_base = 0x800080000ULL,
1319 .ledma_base = 0x800040000ULL,
1320 .le_base = 0x800060000ULL,
1321 .sbi_base = 0xf02800000ULL,
1322 .nvram_machine_id = 0x80,
1323 .machine_id = ss2000_id,
1324 .iounit_version = 0x03000000,
1325 .max_mem = 0xf00000000ULL,
1326 .default_cpu_model = "TI SuperSparc II",
1327 },
1328 };
1329
1330 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1331 {
1332 DeviceState *dev;
1333 SysBusDevice *s;
1334 unsigned int i;
1335
1336 dev = qdev_create(NULL, "sbi");
1337 qdev_init(dev);
1338
1339 s = sysbus_from_qdev(dev);
1340
1341 for (i = 0; i < MAX_CPUS; i++) {
1342 sysbus_connect_irq(s, i, *parent_irq[i]);
1343 }
1344
1345 sysbus_mmio_map(s, 0, addr);
1346
1347 return dev;
1348 }
1349
1350 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1351 const char *boot_device,
1352 const char *kernel_filename,
1353 const char *kernel_cmdline,
1354 const char *initrd_filename, const char *cpu_model)
1355 {
1356 CPUState *envs[MAX_CPUS];
1357 unsigned int i;
1358 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1359 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1360 espdma_irq, ledma_irq;
1361 qemu_irq esp_reset;
1362 unsigned long kernel_size;
1363 void *fw_cfg;
1364 DeviceState *dev;
1365
1366 /* init CPUs */
1367 if (!cpu_model)
1368 cpu_model = hwdef->default_cpu_model;
1369
1370 for(i = 0; i < smp_cpus; i++) {
1371 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1372 }
1373
1374 for (i = smp_cpus; i < MAX_CPUS; i++)
1375 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1376
1377 /* set up devices */
1378 ram_init(0, RAM_size, hwdef->max_mem);
1379
1380 prom_init(hwdef->slavio_base, bios_name);
1381
1382 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1383
1384 for (i = 0; i < 32; i++) {
1385 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1386 }
1387 for (i = 0; i < MAX_CPUS; i++) {
1388 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1389 }
1390
1391 for (i = 0; i < MAX_IOUNITS; i++)
1392 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1393 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1394 hwdef->iounit_version,
1395 sbi_irq[0]);
1396
1397 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1398 iounits[0], &espdma_irq);
1399
1400 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1401 iounits[0], &ledma_irq);
1402
1403 if (graphic_depth != 8 && graphic_depth != 24) {
1404 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1405 exit (1);
1406 }
1407 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1408 graphic_depth);
1409
1410 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1411
1412 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1413
1414 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1415
1416 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1417 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1418 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1419 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1420 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1421 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1422
1423 if (drive_get_max_bus(IF_SCSI) > 0) {
1424 fprintf(stderr, "qemu: too many SCSI bus\n");
1425 exit(1);
1426 }
1427
1428 esp_reset = qdev_get_gpio_in(espdma, 0);
1429 esp_init(hwdef->esp_base, 2,
1430 espdma_memory_read, espdma_memory_write,
1431 espdma, espdma_irq, &esp_reset);
1432
1433 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1434 RAM_size);
1435
1436 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1437 boot_device, RAM_size, kernel_size, graphic_width,
1438 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1439 "Sun4d");
1440
1441 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1442 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1443 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1444 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1445 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1446 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1447 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1448 if (kernel_cmdline) {
1449 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1450 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1451 } else {
1452 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1453 }
1454 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1455 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1456 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1457 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1458 }
1459
1460 /* SPARCserver 1000 hardware initialisation */
1461 static void ss1000_init(ram_addr_t RAM_size,
1462 const char *boot_device,
1463 const char *kernel_filename, const char *kernel_cmdline,
1464 const char *initrd_filename, const char *cpu_model)
1465 {
1466 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1467 kernel_cmdline, initrd_filename, cpu_model);
1468 }
1469
1470 /* SPARCcenter 2000 hardware initialisation */
1471 static void ss2000_init(ram_addr_t RAM_size,
1472 const char *boot_device,
1473 const char *kernel_filename, const char *kernel_cmdline,
1474 const char *initrd_filename, const char *cpu_model)
1475 {
1476 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1477 kernel_cmdline, initrd_filename, cpu_model);
1478 }
1479
1480 static QEMUMachine ss1000_machine = {
1481 .name = "SS-1000",
1482 .desc = "Sun4d platform, SPARCserver 1000",
1483 .init = ss1000_init,
1484 .use_scsi = 1,
1485 .max_cpus = 8,
1486 };
1487
1488 static QEMUMachine ss2000_machine = {
1489 .name = "SS-2000",
1490 .desc = "Sun4d platform, SPARCcenter 2000",
1491 .init = ss2000_init,
1492 .use_scsi = 1,
1493 .max_cpus = 20,
1494 };
1495
1496 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1497 /* SS-2 */
1498 {
1499 .iommu_base = 0xf8000000,
1500 .tcx_base = 0xfe000000,
1501 .slavio_base = 0xf6000000,
1502 .intctl_base = 0xf5000000,
1503 .counter_base = 0xf3000000,
1504 .ms_kb_base = 0xf0000000,
1505 .serial_base = 0xf1000000,
1506 .nvram_base = 0xf2000000,
1507 .fd_base = 0xf7200000,
1508 .dma_base = 0xf8400000,
1509 .esp_base = 0xf8800000,
1510 .le_base = 0xf8c00000,
1511 .aux1_base = 0xf7400003,
1512 .nvram_machine_id = 0x55,
1513 .machine_id = ss2_id,
1514 .max_mem = 0x10000000,
1515 .default_cpu_model = "Cypress CY7C601",
1516 },
1517 };
1518
1519 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1520 qemu_irq *parent_irq)
1521 {
1522 DeviceState *dev;
1523 SysBusDevice *s;
1524 unsigned int i;
1525
1526 dev = qdev_create(NULL, "sun4c_intctl");
1527 qdev_init(dev);
1528
1529 s = sysbus_from_qdev(dev);
1530
1531 for (i = 0; i < MAX_PILS; i++) {
1532 sysbus_connect_irq(s, i, parent_irq[i]);
1533 }
1534 sysbus_mmio_map(s, 0, addr);
1535
1536 return dev;
1537 }
1538
1539 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1540 const char *boot_device,
1541 const char *kernel_filename,
1542 const char *kernel_cmdline,
1543 const char *initrd_filename, const char *cpu_model)
1544 {
1545 CPUState *env;
1546 void *iommu, *espdma, *ledma, *nvram;
1547 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1548 qemu_irq esp_reset;
1549 qemu_irq fdc_tc;
1550 unsigned long kernel_size;
1551 BlockDriverState *fd[MAX_FD];
1552 void *fw_cfg;
1553 DeviceState *dev;
1554 unsigned int i;
1555 DriveInfo *dinfo;
1556
1557 /* init CPU */
1558 if (!cpu_model)
1559 cpu_model = hwdef->default_cpu_model;
1560
1561 env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1562
1563 /* set up devices */
1564 ram_init(0, RAM_size, hwdef->max_mem);
1565
1566 prom_init(hwdef->slavio_base, bios_name);
1567
1568 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1569
1570 for (i = 0; i < 8; i++) {
1571 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1572 }
1573
1574 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1575 slavio_irq[1]);
1576
1577 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1578 iommu, &espdma_irq);
1579
1580 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1581 slavio_irq[3], iommu, &ledma_irq);
1582
1583 if (graphic_depth != 8 && graphic_depth != 24) {
1584 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1585 exit (1);
1586 }
1587 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1588 graphic_depth);
1589
1590 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1591
1592 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1593
1594 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1595 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1596 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1597 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1598 escc_init(hwdef->serial_base, slavio_irq[1],
1599 slavio_irq[1], serial_hds[0], serial_hds[1],
1600 ESCC_CLOCK, 1);
1601
1602 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1603
1604 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1605 /* there is zero or one floppy drive */
1606 memset(fd, 0, sizeof(fd));
1607 dinfo = drive_get(IF_FLOPPY, 0, 0);
1608 if (dinfo)
1609 fd[0] = dinfo->bdrv;
1610
1611 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1612 &fdc_tc);
1613 }
1614
1615 if (drive_get_max_bus(IF_SCSI) > 0) {
1616 fprintf(stderr, "qemu: too many SCSI bus\n");
1617 exit(1);
1618 }
1619
1620 esp_reset = qdev_get_gpio_in(espdma, 0);
1621 esp_init(hwdef->esp_base, 2,
1622 espdma_memory_read, espdma_memory_write,
1623 espdma, espdma_irq, &esp_reset);
1624
1625 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1626 RAM_size);
1627
1628 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1629 boot_device, RAM_size, kernel_size, graphic_width,
1630 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1631 "Sun4c");
1632
1633 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1634 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1635 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1636 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1637 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1638 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1639 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1640 if (kernel_cmdline) {
1641 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1642 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1643 } else {
1644 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1645 }
1646 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1647 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1648 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1649 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1650 }
1651
1652 /* SPARCstation 2 hardware initialisation */
1653 static void ss2_init(ram_addr_t RAM_size,
1654 const char *boot_device,
1655 const char *kernel_filename, const char *kernel_cmdline,
1656 const char *initrd_filename, const char *cpu_model)
1657 {
1658 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1659 kernel_cmdline, initrd_filename, cpu_model);
1660 }
1661
1662 static QEMUMachine ss2_machine = {
1663 .name = "SS-2",
1664 .desc = "Sun4c platform, SPARCstation 2",
1665 .init = ss2_init,
1666 .use_scsi = 1,
1667 };
1668
1669 static void ss2_machine_init(void)
1670 {
1671 qemu_register_machine(&ss5_machine);
1672 qemu_register_machine(&ss10_machine);
1673 qemu_register_machine(&ss600mp_machine);
1674 qemu_register_machine(&ss20_machine);
1675 qemu_register_machine(&voyager_machine);
1676 qemu_register_machine(&ss_lx_machine);
1677 qemu_register_machine(&ss4_machine);
1678 qemu_register_machine(&scls_machine);
1679 qemu_register_machine(&sbook_machine);
1680 qemu_register_machine(&ss1000_machine);
1681 qemu_register_machine(&ss2000_machine);
1682 qemu_register_machine(&ss2_machine);
1683 }
1684
1685 machine_init(ss2_machine_init);
CRIS target port of Qemu