4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
30 #define ACPI_DBG_IO_ADDR 0xb044
32 #define GPE_BASE 0xafe0
33 #define PCI_BASE 0xae00
34 #define PCI_EJ_BASE 0xae08
37 uint16_t sts
; /* status */
38 uint16_t en
; /* enabled */
46 typedef struct PIIX4PMState
{
55 int64_t tmr_overflow_time
;
67 struct pci_status pci0_status
;
70 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
);
72 #define ACPI_ENABLE 0xf1
73 #define ACPI_DISABLE 0xf0
75 static uint32_t get_pmtmr(PIIX4PMState
*s
)
78 d
= muldiv64(qemu_get_clock(vm_clock
), PM_TIMER_FREQUENCY
, get_ticks_per_sec());
82 static int get_pmsts(PIIX4PMState
*s
)
86 d
= muldiv64(qemu_get_clock(vm_clock
), PM_TIMER_FREQUENCY
,
88 if (d
>= s
->tmr_overflow_time
)
89 s
->pmsts
|= ACPI_BITMASK_TIMER_STATUS
;
93 static void pm_update_sci(PIIX4PMState
*s
)
99 sci_level
= (((pmsts
& s
->pmen
) &
100 (ACPI_BITMASK_RT_CLOCK_ENABLE
|
101 ACPI_BITMASK_POWER_BUTTON_ENABLE
|
102 ACPI_BITMASK_GLOBAL_LOCK_ENABLE
|
103 ACPI_BITMASK_TIMER_ENABLE
)) != 0);
104 qemu_set_irq(s
->irq
, sci_level
);
105 /* schedule a timer interruption if needed */
106 if ((s
->pmen
& ACPI_BITMASK_TIMER_ENABLE
) &&
107 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
)) {
108 expire_time
= muldiv64(s
->tmr_overflow_time
, get_ticks_per_sec(),
110 qemu_mod_timer(s
->tmr_timer
, expire_time
);
112 qemu_del_timer(s
->tmr_timer
);
116 static void pm_tmr_timer(void *opaque
)
118 PIIX4PMState
*s
= opaque
;
122 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
124 PIIX4PMState
*s
= opaque
;
131 pmsts
= get_pmsts(s
);
132 if (pmsts
& val
& ACPI_BITMASK_TIMER_STATUS
) {
133 /* if TMRSTS is reset, then compute the new overflow time */
134 d
= muldiv64(qemu_get_clock(vm_clock
), PM_TIMER_FREQUENCY
,
135 get_ticks_per_sec());
136 s
->tmr_overflow_time
= (d
+ 0x800000LL
) & ~0x7fffffLL
;
149 s
->pmcntrl
= val
& ~(ACPI_BITMASK_SLEEP_ENABLE
);
150 if (val
& ACPI_BITMASK_SLEEP_ENABLE
) {
151 /* change suspend type */
152 sus_typ
= (val
>> 10) & 7;
154 case 0: /* soft power off */
155 qemu_system_shutdown_request();
158 /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
159 Pretend that resume was caused by power button */
160 s
->pmsts
|= (ACPI_BITMASK_WAKE_STATUS
|
161 ACPI_BITMASK_POWER_BUTTON_STATUS
);
162 qemu_system_reset_request();
164 qemu_irq_raise(s
->cmos_s3
);
176 printf("PM writew port=0x%04x val=0x%04x\n", addr
, val
);
180 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
182 PIIX4PMState
*s
= opaque
;
201 printf("PM readw port=0x%04x val=0x%04x\n", addr
, val
);
206 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
208 // PIIX4PMState *s = opaque;
211 printf("PM writel port=0x%04x val=0x%08x\n", addr
, val
);
215 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
217 PIIX4PMState
*s
= opaque
;
230 printf("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
235 static void apm_ctrl_changed(uint32_t val
, void *arg
)
237 PIIX4PMState
*s
= arg
;
239 /* ACPI specs 3.0, 4.7.2.5 */
240 if (val
== ACPI_ENABLE
) {
241 s
->pmcntrl
|= ACPI_BITMASK_SCI_ENABLE
;
242 } else if (val
== ACPI_DISABLE
) {
243 s
->pmcntrl
&= ~ACPI_BITMASK_SCI_ENABLE
;
246 if (s
->dev
.config
[0x5b] & (1 << 1)) {
248 qemu_irq_raise(s
->smi_irq
);
253 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
256 printf("ACPI: DBG: 0x%08x\n", val
);
260 static void pm_io_space_update(PIIX4PMState
*s
)
264 if (s
->dev
.config
[0x80] & 1) {
265 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
266 pm_io_base
&= 0xffc0;
268 /* XXX: need to improve memory and ioport allocation */
270 printf("PM: mapping to 0x%x\n", pm_io_base
);
272 register_ioport_write(pm_io_base
, 64, 2, pm_ioport_writew
, s
);
273 register_ioport_read(pm_io_base
, 64, 2, pm_ioport_readw
, s
);
274 register_ioport_write(pm_io_base
, 64, 4, pm_ioport_writel
, s
);
275 register_ioport_read(pm_io_base
, 64, 4, pm_ioport_readl
, s
);
279 static void pm_write_config(PCIDevice
*d
,
280 uint32_t address
, uint32_t val
, int len
)
282 pci_default_write_config(d
, address
, val
, len
);
283 if (range_covers_byte(address
, len
, 0x80))
284 pm_io_space_update((PIIX4PMState
*)d
);
287 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
289 PIIX4PMState
*s
= opaque
;
291 pm_io_space_update(s
);
295 static const VMStateDescription vmstate_acpi
= {
298 .minimum_version_id
= 1,
299 .minimum_version_id_old
= 1,
300 .post_load
= vmstate_acpi_post_load
,
301 .fields
= (VMStateField
[]) {
302 VMSTATE_PCI_DEVICE(dev
, PIIX4PMState
),
303 VMSTATE_UINT16(pmsts
, PIIX4PMState
),
304 VMSTATE_UINT16(pmen
, PIIX4PMState
),
305 VMSTATE_UINT16(pmcntrl
, PIIX4PMState
),
306 VMSTATE_STRUCT(apm
, PIIX4PMState
, 0, vmstate_apm
, APMState
),
307 VMSTATE_TIMER(tmr_timer
, PIIX4PMState
),
308 VMSTATE_INT64(tmr_overflow_time
, PIIX4PMState
),
309 VMSTATE_END_OF_LIST()
313 static void piix4_reset(void *opaque
)
315 PIIX4PMState
*s
= opaque
;
316 uint8_t *pci_conf
= s
->dev
.config
;
323 if (s
->kvm_enabled
) {
324 /* Mark SMM as already inited (until KVM supports SMM). */
325 pci_conf
[0x5B] = 0x02;
329 static void piix4_powerdown(void *opaque
, int irq
, int power_failing
)
331 PIIX4PMState
*s
= opaque
;
334 qemu_system_shutdown_request();
335 } else if (s
->pmen
& ACPI_BITMASK_POWER_BUTTON_ENABLE
) {
336 s
->pmsts
|= ACPI_BITMASK_POWER_BUTTON_STATUS
;
341 static int piix4_pm_initfn(PCIDevice
*dev
)
343 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
346 pci_conf
= s
->dev
.config
;
347 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
348 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82371AB_3
);
349 pci_conf
[0x06] = 0x80;
350 pci_conf
[0x07] = 0x02;
351 pci_conf
[0x08] = 0x03; // revision number
352 pci_conf
[0x09] = 0x00;
353 pci_config_set_class(pci_conf
, PCI_CLASS_BRIDGE_OTHER
);
354 pci_conf
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
355 pci_conf
[0x3d] = 0x01; // interrupt pin 1
357 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
360 apm_init(&s
->apm
, apm_ctrl_changed
, s
);
362 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
364 if (s
->kvm_enabled
) {
365 /* Mark SMM as already inited to prevent SMM from running. KVM does not
366 * support SMM mode. */
367 pci_conf
[0x5B] = 0x02;
370 /* XXX: which specification is used ? The i82731AB has different
372 pci_conf
[0x5f] = (parallel_hds
[0] != NULL
? 0x80 : 0) | 0x10;
373 pci_conf
[0x63] = 0x60;
374 pci_conf
[0x67] = (serial_hds
[0] != NULL
? 0x08 : 0) |
375 (serial_hds
[1] != NULL
? 0x90 : 0);
377 pci_conf
[0x90] = s
->smb_io_base
| 1;
378 pci_conf
[0x91] = s
->smb_io_base
>> 8;
379 pci_conf
[0xd2] = 0x09;
380 register_ioport_write(s
->smb_io_base
, 64, 1, smb_ioport_writeb
, &s
->smb
);
381 register_ioport_read(s
->smb_io_base
, 64, 1, smb_ioport_readb
, &s
->smb
);
383 s
->tmr_timer
= qemu_new_timer(vm_clock
, pm_tmr_timer
, s
);
385 qemu_system_powerdown
= *qemu_allocate_irqs(piix4_powerdown
, s
, 1);
387 pm_smbus_init(&s
->dev
.qdev
, &s
->smb
);
388 qemu_register_reset(piix4_reset
, s
);
389 piix4_acpi_system_hot_add_init(dev
->bus
, s
);
394 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
395 qemu_irq sci_irq
, qemu_irq cmos_s3
, qemu_irq smi_irq
,
401 dev
= pci_create(bus
, devfn
, "PIIX4_PM");
402 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
404 s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
406 s
->cmos_s3
= cmos_s3
;
407 s
->smi_irq
= smi_irq
;
408 s
->kvm_enabled
= kvm_enabled
;
410 qdev_init_nofail(&dev
->qdev
);
415 static PCIDeviceInfo piix4_pm_info
= {
416 .qdev
.name
= "PIIX4_PM",
418 .qdev
.size
= sizeof(PIIX4PMState
),
419 .qdev
.vmsd
= &vmstate_acpi
,
420 .init
= piix4_pm_initfn
,
421 .config_write
= pm_write_config
,
422 .qdev
.props
= (Property
[]) {
423 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState
, smb_io_base
, 0),
424 DEFINE_PROP_END_OF_LIST(),
428 static void piix4_pm_register(void)
430 pci_qdev_register(&piix4_pm_info
);
433 device_init(piix4_pm_register
);
435 static uint32_t gpe_read_val(uint16_t val
, uint32_t addr
)
438 return (val
>> 8) & 0xff;
442 static uint32_t gpe_readb(void *opaque
, uint32_t addr
)
445 struct gpe_regs
*g
= opaque
;
449 val
= gpe_read_val(g
->sts
, addr
);
453 val
= gpe_read_val(g
->en
, addr
);
460 printf("gpe read %x == %x\n", addr
, val
);
465 static void gpe_write_val(uint16_t *cur
, int addr
, uint32_t val
)
468 *cur
= (*cur
& 0xff) | (val
<< 8);
470 *cur
= (*cur
& 0xff00) | (val
& 0xff);
473 static void gpe_reset_val(uint16_t *cur
, int addr
, uint32_t val
)
475 uint16_t x1
, x0
= val
& 0xff;
476 int shift
= (addr
& 1) ? 8 : 0;
478 x1
= (*cur
>> shift
) & 0xff;
482 *cur
= (*cur
& (0xff << (8 - shift
))) | (x1
<< shift
);
485 static void gpe_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
487 struct gpe_regs
*g
= opaque
;
491 gpe_reset_val(&g
->sts
, addr
, val
);
495 gpe_write_val(&g
->en
, addr
, val
);
502 printf("gpe write %x <== %d\n", addr
, val
);
506 static uint32_t pcihotplug_read(void *opaque
, uint32_t addr
)
509 struct pci_status
*g
= opaque
;
522 printf("pcihotplug read %x == %x\n", addr
, val
);
527 static void pcihotplug_write(void *opaque
, uint32_t addr
, uint32_t val
)
529 struct pci_status
*g
= opaque
;
540 printf("pcihotplug write %x <== %d\n", addr
, val
);
544 static uint32_t pciej_read(void *opaque
, uint32_t addr
)
547 printf("pciej read %x\n", addr
);
552 static void pciej_write(void *opaque
, uint32_t addr
, uint32_t val
)
554 BusState
*bus
= opaque
;
555 DeviceState
*qdev
, *next
;
557 int slot
= ffs(val
) - 1;
559 QLIST_FOREACH_SAFE(qdev
, &bus
->children
, sibling
, next
) {
560 dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
561 if (PCI_SLOT(dev
->devfn
) == slot
) {
568 printf("pciej write %x <== %d\n", addr
, val
);
572 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
, int state
);
574 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
)
576 struct gpe_regs
*gpe
= &s
->gpe
;
577 struct pci_status
*pci0_status
= &s
->pci0_status
;
579 register_ioport_write(GPE_BASE
, 4, 1, gpe_writeb
, gpe
);
580 register_ioport_read(GPE_BASE
, 4, 1, gpe_readb
, gpe
);
582 register_ioport_write(PCI_BASE
, 8, 4, pcihotplug_write
, pci0_status
);
583 register_ioport_read(PCI_BASE
, 8, 4, pcihotplug_read
, pci0_status
);
585 register_ioport_write(PCI_EJ_BASE
, 4, 4, pciej_write
, bus
);
586 register_ioport_read(PCI_EJ_BASE
, 4, 4, pciej_read
, bus
);
588 pci_bus_hotplug(bus
, piix4_device_hotplug
, &s
->dev
.qdev
);
591 static void enable_device(PIIX4PMState
*s
, int slot
)
594 s
->pci0_status
.up
|= (1 << slot
);
597 static void disable_device(PIIX4PMState
*s
, int slot
)
600 s
->pci0_status
.down
|= (1 << slot
);
603 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
, int state
)
605 int slot
= PCI_SLOT(dev
->devfn
);
606 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
,
607 DO_UPCAST(PCIDevice
, qdev
, qdev
));
609 s
->pci0_status
.up
= 0;
610 s
->pci0_status
.down
= 0;
612 enable_device(s
, slot
);
614 disable_device(s
, slot
);
617 qemu_set_irq(s
->irq
, 1);
618 qemu_set_irq(s
->irq
, 0);