hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/hw.h"
  26 #include "hw/ppc/mac.h"
  27 #include "hw/ppc/mac_dbdma.h"
  28 #include "sysemu/block-backend.h"
  29 #include "sysemu/dma.h"
  30
  31 #include <hw/ide/internal.h>
  32
  33 /* debug MACIO */
  34 // #define DEBUG_MACIO
  35
  36 #ifdef DEBUG_MACIO
  37 static const int debug_macio = 1;
  38 #else
  39 static const int debug_macio = 0;
  40 #endif
  41
  42 #define MACIO_DPRINTF(fmt, ...) do { \
  43         if (debug_macio) { \
  44             printf(fmt , ## __VA_ARGS__); \
  45         } \
  46     } while (0)
  47
  48
  49 /***********************************************************/
  50 /* MacIO based PowerPC IDE */
  51
  52 #define MACIO_PAGE_SIZE 4096
  53
  54 /*
  55  * Unaligned DMA read/write access functions required for OS X/Darwin which
  56  * don't perform DMA transactions on sector boundaries. These functions are
  57  * modelled on bdrv_co_do_preadv()/bdrv_co_do_pwritev() and so should be
  58  * easy to remove if the unaligned block APIs are ever exposed.
  59  */
  60
  61 static void pmac_dma_read(BlockBackend *blk,
  62                           int64_t offset, unsigned int bytes,
  63                           void (*cb)(void *opaque, int ret), void *opaque)
  64 {
  65     DBDMA_io *io = opaque;
  66     MACIOIDEState *m = io->opaque;
  67     IDEState *s = idebus_active_if(&m->bus);
  68     dma_addr_t dma_addr, dma_len;
  69     void *mem;
  70     int64_t sector_num;
  71     int nsector;
  72     uint64_t align = BDRV_SECTOR_SIZE;
  73     size_t head_bytes, tail_bytes;
  74
  75     qemu_iovec_destroy(&io->iov);
  76     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
  77
  78     sector_num = (offset >> 9);
  79     nsector = (io->len >> 9);
  80
  81     MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
  82                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
  83                   sector_num, nsector);
  84
  85     dma_addr = io->addr;
  86     dma_len = io->len;
  87     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
  88                          DMA_DIRECTION_FROM_DEVICE);
  89
  90     if (offset & (align - 1)) {
  91         head_bytes = offset & (align - 1);
  92
  93         MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
  94                       "discarding %zu bytes\n", sector_num, head_bytes);
  95
  96         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
  97
  98         bytes += offset & (align - 1);
  99         offset = offset & ~(align - 1);
 100     }
 101
 102     qemu_iovec_add(&io->iov, mem, io->len);
 103
 104     if ((offset + bytes) & (align - 1)) {
 105         tail_bytes = (offset + bytes) & (align - 1);
 106
 107         MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
 108                       "discarding bytes %zu\n", sector_num, tail_bytes);
 109
 110         qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
 111         bytes = ROUND_UP(bytes, align);
 112     }
 113
 114     s->io_buffer_size -= io->len;
 115     s->io_buffer_index += io->len;
 116
 117     io->len = 0;
 118
 119     MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 "  "
 120                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
 121
 122     m->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov, (bytes >> 9),
 123                              cb, io);
 124 }
 125
 126 static void pmac_dma_write(BlockBackend *blk,
 127                          int64_t offset, int bytes,
 128                          void (*cb)(void *opaque, int ret), void *opaque)
 129 {
 130     DBDMA_io *io = opaque;
 131     MACIOIDEState *m = io->opaque;
 132     IDEState *s = idebus_active_if(&m->bus);
 133     dma_addr_t dma_addr, dma_len;
 134     void *mem;
 135     int64_t sector_num;
 136     int nsector;
 137     uint64_t align = BDRV_SECTOR_SIZE;
 138     size_t head_bytes, tail_bytes;
 139     bool unaligned_head = false, unaligned_tail = false;
 140
 141     qemu_iovec_destroy(&io->iov);
 142     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
 143
 144     sector_num = (offset >> 9);
 145     nsector = (io->len >> 9);
 146
 147     MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
 148                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
 149                   sector_num, nsector);
 150
 151     dma_addr = io->addr;
 152     dma_len = io->len;
 153     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
 154                          DMA_DIRECTION_TO_DEVICE);
 155
 156     if (offset & (align - 1)) {
 157         head_bytes = offset & (align - 1);
 158         sector_num = ((offset & ~(align - 1)) >> 9);
 159
 160         MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
 161                       PRId64 "\n", sector_num);
 162
 163         blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
 164
 165         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
 166         qemu_iovec_add(&io->iov, mem, io->len);
 167
 168         bytes += offset & (align - 1);
 169         offset = offset & ~(align - 1);
 170
 171         unaligned_head = true;
 172     }
 173
 174     if ((offset + bytes) & (align - 1)) {
 175         tail_bytes = (offset + bytes) & (align - 1);
 176         sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
 177
 178         MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
 179                       PRId64 "\n", sector_num);
 180
 181         blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
 182
 183         if (!unaligned_head) {
 184             qemu_iovec_add(&io->iov, mem, io->len);
 185         }
 186
 187         qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
 188                        align - tail_bytes);
 189
 190         bytes = ROUND_UP(bytes, align);
 191
 192         unaligned_tail = true;
 193     }
 194
 195     if (!unaligned_head && !unaligned_tail) {
 196         qemu_iovec_add(&io->iov, mem, io->len);
 197     }
 198
 199     s->io_buffer_size -= io->len;
 200     s->io_buffer_index += io->len;
 201
 202     io->len = 0;
 203
 204     MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 "  "
 205                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
 206
 207     m->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov, (bytes >> 9),
 208                               cb, io);
 209 }
 210
 211 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
 212 {
 213     DBDMA_io *io = opaque;
 214     MACIOIDEState *m = io->opaque;
 215     IDEState *s = idebus_active_if(&m->bus);
 216     int64_t offset;
 217
 218     MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
 219
 220     if (ret < 0) {
 221         MACIO_DPRINTF("DMA error: %d\n", ret);
 222         ide_atapi_io_error(s, ret);
 223         goto done;
 224     }
 225
 226     if (!m->dma_active) {
 227         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 228                       s->nsector, io->len, s->status);
 229         /* data not ready yet, wait for the channel to get restarted */
 230         io->processing = false;
 231         return;
 232     }
 233
 234     if (s->io_buffer_size <= 0) {
 235         MACIO_DPRINTF("End of IDE transfer\n");
 236         ide_atapi_cmd_ok(s);
 237         m->dma_active = false;
 238         goto done;
 239     }
 240
 241     if (io->len == 0) {
 242         MACIO_DPRINTF("End of DMA transfer\n");
 243         goto done;
 244     }
 245
 246     if (s->lba == -1) {
 247         /* Non-block ATAPI transfer - just copy to RAM */
 248         s->io_buffer_size = MIN(s->io_buffer_size, io->len);
 249         cpu_physical_memory_write(io->addr, s->io_buffer, s->io_buffer_size);
 250         ide_atapi_cmd_ok(s);
 251         m->dma_active = false;
 252         goto done;
 253     }
 254
 255     /* Calculate current offset */
 256     offset = (int64_t)(s->lba << 11) + s->io_buffer_index;
 257
 258     pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
 259     return;
 260
 261 done:
 262     block_acct_done(blk_get_stats(s->blk), &s->acct);
 263     io->dma_end(opaque);
 264
 265     return;
 266 }
 267
 268 static void pmac_ide_transfer_cb(void *opaque, int ret)
 269 {
 270     DBDMA_io *io = opaque;
 271     MACIOIDEState *m = io->opaque;
 272     IDEState *s = idebus_active_if(&m->bus);
 273     int64_t offset;
 274
 275     MACIO_DPRINTF("pmac_ide_transfer_cb\n");
 276
 277     if (ret < 0) {
 278         MACIO_DPRINTF("DMA error: %d\n", ret);
 279         m->aiocb = NULL;
 280         ide_dma_error(s);
 281         io->remainder_len = 0;
 282         goto done;
 283     }
 284
 285     if (!m->dma_active) {
 286         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 287                       s->nsector, io->len, s->status);
 288         /* data not ready yet, wait for the channel to get restarted */
 289         io->processing = false;
 290         return;
 291     }
 292
 293     if (s->io_buffer_size <= 0) {
 294         MACIO_DPRINTF("End of IDE transfer\n");
 295         s->status = READY_STAT | SEEK_STAT;
 296         ide_set_irq(s->bus);
 297         m->dma_active = false;
 298         goto done;
 299     }
 300
 301     if (io->len == 0) {
 302         MACIO_DPRINTF("End of DMA transfer\n");
 303         goto done;
 304     }
 305
 306     /* Calculate number of sectors */
 307     offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
 308
 309     switch (s->dma_cmd) {
 310     case IDE_DMA_READ:
 311         pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 312         break;
 313     case IDE_DMA_WRITE:
 314         pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 315         break;
 316     case IDE_DMA_TRIM:
 317         break;
 318     }
 319
 320     return;
 321
 322 done:
 323     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
 324         block_acct_done(blk_get_stats(s->blk), &s->acct);
 325     }
 326     io->dma_end(opaque);
 327 }
 328
 329 static void pmac_ide_transfer(DBDMA_io *io)
 330 {
 331     MACIOIDEState *m = io->opaque;
 332     IDEState *s = idebus_active_if(&m->bus);
 333
 334     MACIO_DPRINTF("\n");
 335
 336     if (s->drive_kind == IDE_CD) {
 337         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 338                          BLOCK_ACCT_READ);
 339
 340         pmac_ide_atapi_transfer_cb(io, 0);
 341         return;
 342     }
 343
 344     switch (s->dma_cmd) {
 345     case IDE_DMA_READ:
 346         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 347                          BLOCK_ACCT_READ);
 348         break;
 349     case IDE_DMA_WRITE:
 350         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 351                          BLOCK_ACCT_WRITE);
 352         break;
 353     default:
 354         break;
 355     }
 356
 357     pmac_ide_transfer_cb(io, 0);
 358 }
 359
 360 static void pmac_ide_flush(DBDMA_io *io)
 361 {
 362     MACIOIDEState *m = io->opaque;
 363
 364     if (m->aiocb) {
 365         blk_drain_all();
 366     }
 367 }
 368
 369 /* PowerMac IDE memory IO */
 370 static void pmac_ide_writeb (void *opaque,
 371                              hwaddr addr, uint32_t val)
 372 {
 373     MACIOIDEState *d = opaque;
 374
 375     addr = (addr & 0xFFF) >> 4;
 376     switch (addr) {
 377     case 1 ... 7:
 378         ide_ioport_write(&d->bus, addr, val);
 379         break;
 380     case 8:
 381     case 22:
 382         ide_cmd_write(&d->bus, 0, val);
 383         break;
 384     default:
 385         break;
 386     }
 387 }
 388
 389 static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
 390 {
 391     uint8_t retval;
 392     MACIOIDEState *d = opaque;
 393
 394     addr = (addr & 0xFFF) >> 4;
 395     switch (addr) {
 396     case 1 ... 7:
 397         retval = ide_ioport_read(&d->bus, addr);
 398         break;
 399     case 8:
 400     case 22:
 401         retval = ide_status_read(&d->bus, 0);
 402         break;
 403     default:
 404         retval = 0xFF;
 405         break;
 406     }
 407     return retval;
 408 }
 409
 410 static void pmac_ide_writew (void *opaque,
 411                              hwaddr addr, uint32_t val)
 412 {
 413     MACIOIDEState *d = opaque;
 414
 415     addr = (addr & 0xFFF) >> 4;
 416     val = bswap16(val);
 417     if (addr == 0) {
 418         ide_data_writew(&d->bus, 0, val);
 419     }
 420 }
 421
 422 static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
 423 {
 424     uint16_t retval;
 425     MACIOIDEState *d = opaque;
 426
 427     addr = (addr & 0xFFF) >> 4;
 428     if (addr == 0) {
 429         retval = ide_data_readw(&d->bus, 0);
 430     } else {
 431         retval = 0xFFFF;
 432     }
 433     retval = bswap16(retval);
 434     return retval;
 435 }
 436
 437 static void pmac_ide_writel (void *opaque,
 438                              hwaddr addr, uint32_t val)
 439 {
 440     MACIOIDEState *d = opaque;
 441
 442     addr = (addr & 0xFFF) >> 4;
 443     val = bswap32(val);
 444     if (addr == 0) {
 445         ide_data_writel(&d->bus, 0, val);
 446     }
 447 }
 448
 449 static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
 450 {
 451     uint32_t retval;
 452     MACIOIDEState *d = opaque;
 453
 454     addr = (addr & 0xFFF) >> 4;
 455     if (addr == 0) {
 456         retval = ide_data_readl(&d->bus, 0);
 457     } else {
 458         retval = 0xFFFFFFFF;
 459     }
 460     retval = bswap32(retval);
 461     return retval;
 462 }
 463
 464 static const MemoryRegionOps pmac_ide_ops = {
 465     .old_mmio = {
 466         .write = {
 467             pmac_ide_writeb,
 468             pmac_ide_writew,
 469             pmac_ide_writel,
 470         },
 471         .read = {
 472             pmac_ide_readb,
 473             pmac_ide_readw,
 474             pmac_ide_readl,
 475         },
 476     },
 477     .endianness = DEVICE_NATIVE_ENDIAN,
 478 };
 479
 480 static const VMStateDescription vmstate_pmac = {
 481     .name = "ide",
 482     .version_id = 3,
 483     .minimum_version_id = 0,
 484     .fields = (VMStateField[]) {
 485         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 486         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 487         VMSTATE_END_OF_LIST()
 488     }
 489 };
 490
 491 static void macio_ide_reset(DeviceState *dev)
 492 {
 493     MACIOIDEState *d = MACIO_IDE(dev);
 494
 495     ide_bus_reset(&d->bus);
 496 }
 497
 498 static int ide_nop_int(IDEDMA *dma, int x)
 499 {
 500     return 0;
 501 }
 502
 503 static int32_t ide_nop_int32(IDEDMA *dma, int x)
 504 {
 505     return 0;
 506 }
 507
 508 static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
 509                             BlockCompletionFunc *cb)
 510 {
 511     MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
 512     DBDMAState *dbdma = m->dbdma;
 513     DBDMA_io *io;
 514     int i;
 515
 516     s->io_buffer_index = 0;
 517     if (s->drive_kind == IDE_CD) {
 518         s->io_buffer_size = s->packet_transfer_size;
 519     } else {
 520         s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
 521     }
 522
 523     MACIO_DPRINTF("\n\n------------ IDE transfer\n");
 524     MACIO_DPRINTF("buffer_size: %x   buffer_index: %x\n",
 525                   s->io_buffer_size, s->io_buffer_index);
 526     MACIO_DPRINTF("lba: %x    size: %x\n", s->lba, s->io_buffer_size);
 527     MACIO_DPRINTF("-------------------------\n");
 528
 529     for (i = 0; i < DBDMA_CHANNELS; i++) {
 530         io = &dbdma->channels[i].io;
 531
 532         if (io->opaque == m) {
 533             io->remainder_len = 0;
 534         }
 535     }
 536
 537     MACIO_DPRINTF("\n");
 538     m->dma_active = true;
 539     DBDMA_kick(m->dbdma);
 540 }
 541
 542 static const IDEDMAOps dbdma_ops = {
 543     .start_dma      = ide_dbdma_start,
 544     .prepare_buf    = ide_nop_int32,
 545     .rw_buf         = ide_nop_int,
 546 };
 547
 548 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
 549 {
 550     MACIOIDEState *s = MACIO_IDE(dev);
 551
 552     ide_init2(&s->bus, s->irq);
 553
 554     /* Register DMA callbacks */
 555     s->dma.ops = &dbdma_ops;
 556     s->bus.dma = &s->dma;
 557 }
 558
 559 static void macio_ide_initfn(Object *obj)
 560 {
 561     SysBusDevice *d = SYS_BUS_DEVICE(obj);
 562     MACIOIDEState *s = MACIO_IDE(obj);
 563
 564     ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
 565     memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
 566     sysbus_init_mmio(d, &s->mem);
 567     sysbus_init_irq(d, &s->irq);
 568     sysbus_init_irq(d, &s->dma_irq);
 569 }
 570
 571 static void macio_ide_class_init(ObjectClass *oc, void *data)
 572 {
 573     DeviceClass *dc = DEVICE_CLASS(oc);
 574
 575     dc->realize = macio_ide_realizefn;
 576     dc->reset = macio_ide_reset;
 577     dc->vmsd = &vmstate_pmac;
 578 }
 579
 580 static const TypeInfo macio_ide_type_info = {
 581     .name = TYPE_MACIO_IDE,
 582     .parent = TYPE_SYS_BUS_DEVICE,
 583     .instance_size = sizeof(MACIOIDEState),
 584     .instance_init = macio_ide_initfn,
 585     .class_init = macio_ide_class_init,
 586 };
 587
 588 static void macio_ide_register_types(void)
 589 {
 590     type_register_static(&macio_ide_type_info);
 591 }
 592
 593 /* hd_table must contain 2 block drivers */
 594 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
 595 {
 596     int i;
 597
 598     for (i = 0; i < 2; i++) {
 599         if (hd_table[i]) {
 600             ide_create_drive(&s->bus, i, hd_table[i]);
 601         }
 602     }
 603 }
 604
 605 void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
 606 {
 607     s->dbdma = dbdma;
 608     DBDMA_register_channel(dbdma, channel, s->dma_irq,
 609                            pmac_ide_transfer, pmac_ide_flush, s);
 610 }
 611
 612 type_init(macio_ide_register_types)