?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
migration: dump vmstate info as a json file for static analysis
[qemu/cris-port.git] / hw / block / fdc.c
blob490d127df55e86b7ecd5aebe2174fc755cc5ded5
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw/hw.h"
31 #include "hw/block/fdc.h"
32 #include "qemu/error-report.h"
33 #include "qemu/timer.h"
34 #include "hw/isa/isa.h"
35 #include "hw/sysbus.h"
36 #include "sysemu/blockdev.h"
37 #include "sysemu/sysemu.h"
38 #include "qemu/log.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 /********************************************************/
52 /* Floppy drive emulation */
53
54 typedef enum FDriveRate {
55 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
56 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
57 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
58 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
59 } FDriveRate;
60
61 typedef struct FDFormat {
62 FDriveType drive;
63 uint8_t last_sect;
64 uint8_t max_track;
65 uint8_t max_head;
66 FDriveRate rate;
67 } FDFormat;
68
69 static const FDFormat fd_formats[] = {
70 /* First entry is default format */
71 /* 1.44 MB 3"1/2 floppy disks */
72 { FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, },
73 { FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, },
74 { FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, },
75 { FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, },
76 { FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, },
77 { FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, },
78 { FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, },
79 { FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, },
80 /* 2.88 MB 3"1/2 floppy disks */
81 { FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, },
82 { FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, },
83 { FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, },
84 { FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, },
85 { FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, },
86 /* 720 kB 3"1/2 floppy disks */
87 { FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, },
88 { FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, },
89 { FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, },
90 { FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, },
91 { FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, },
92 { FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, },
93 /* 1.2 MB 5"1/4 floppy disks */
94 { FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, },
95 { FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, },
96 { FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, },
97 { FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, },
98 { FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, },
99 /* 720 kB 5"1/4 floppy disks */
100 { FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, },
101 { FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, },
102 /* 360 kB 5"1/4 floppy disks */
103 { FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, },
104 { FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, },
105 { FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, },
106 { FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, },
107 /* 320 kB 5"1/4 floppy disks */
108 { FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, },
109 { FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, },
110 /* 360 kB must match 5"1/4 better than 3"1/2... */
111 { FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, },
112 /* end */
113 { FDRIVE_DRV_NONE, -1, -1, 0, 0, },
114 };
115
116 static void pick_geometry(BlockDriverState *bs, int *nb_heads,
117 int *max_track, int *last_sect,
118 FDriveType drive_in, FDriveType *drive,
119 FDriveRate *rate)
120 {
121 const FDFormat *parse;
122 uint64_t nb_sectors, size;
123 int i, first_match, match;
124
125 bdrv_get_geometry(bs, &nb_sectors);
126 match = -1;
127 first_match = -1;
128 for (i = 0; ; i++) {
129 parse = &fd_formats[i];
130 if (parse->drive == FDRIVE_DRV_NONE) {
131 break;
132 }
133 if (drive_in == parse->drive ||
134 drive_in == FDRIVE_DRV_NONE) {
135 size = (parse->max_head + 1) * parse->max_track *
136 parse->last_sect;
137 if (nb_sectors == size) {
138 match = i;
139 break;
140 }
141 if (first_match == -1) {
142 first_match = i;
143 }
144 }
145 }
146 if (match == -1) {
147 if (first_match == -1) {
148 match = 1;
149 } else {
150 match = first_match;
151 }
152 parse = &fd_formats[match];
153 }
154 *nb_heads = parse->max_head + 1;
155 *max_track = parse->max_track;
156 *last_sect = parse->last_sect;
157 *drive = parse->drive;
158 *rate = parse->rate;
159 }
160
161 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
162 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
163
164 /* Will always be a fixed parameter for us */
165 #define FD_SECTOR_LEN 512
166 #define FD_SECTOR_SC 2 /* Sector size code */
167 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
168
169 typedef struct FDCtrl FDCtrl;
170
171 /* Floppy disk drive emulation */
172 typedef enum FDiskFlags {
173 FDISK_DBL_SIDES = 0x01,
174 } FDiskFlags;
175
176 typedef struct FDrive {
177 FDCtrl *fdctrl;
178 BlockDriverState *bs;
179 /* Drive status */
180 FDriveType drive;
181 uint8_t perpendicular; /* 2.88 MB access mode */
182 /* Position */
183 uint8_t head;
184 uint8_t track;
185 uint8_t sect;
186 /* Media */
187 FDiskFlags flags;
188 uint8_t last_sect; /* Nb sector per track */
189 uint8_t max_track; /* Nb of tracks */
190 uint16_t bps; /* Bytes per sector */
191 uint8_t ro; /* Is read-only */
192 uint8_t media_changed; /* Is media changed */
193 uint8_t media_rate; /* Data rate of medium */
194 } FDrive;
195
196 static void fd_init(FDrive *drv)
197 {
198 /* Drive */
199 drv->drive = FDRIVE_DRV_NONE;
200 drv->perpendicular = 0;
201 /* Disk */
202 drv->last_sect = 0;
203 drv->max_track = 0;
204 }
205
206 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
207
208 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
209 uint8_t last_sect, uint8_t num_sides)
210 {
211 return (((track * num_sides) + head) * last_sect) + sect - 1;
212 }
213
214 /* Returns current position, in sectors, for given drive */
215 static int fd_sector(FDrive *drv)
216 {
217 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
218 NUM_SIDES(drv));
219 }
220
221 /* Seek to a new position:
222 * returns 0 if already on right track
223 * returns 1 if track changed
224 * returns 2 if track is invalid
225 * returns 3 if sector is invalid
226 * returns 4 if seek is disabled
227 */
228 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
229 int enable_seek)
230 {
231 uint32_t sector;
232 int ret;
233
234 if (track > drv->max_track ||
235 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
236 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
237 head, track, sect, 1,
238 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
239 drv->max_track, drv->last_sect);
240 return 2;
241 }
242 if (sect > drv->last_sect) {
243 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
244 head, track, sect, 1,
245 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
246 drv->max_track, drv->last_sect);
247 return 3;
248 }
249 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
250 ret = 0;
251 if (sector != fd_sector(drv)) {
252 #if 0
253 if (!enable_seek) {
254 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
255 " (max=%d %02x %02x)\n",
256 head, track, sect, 1, drv->max_track,
257 drv->last_sect);
258 return 4;
259 }
260 #endif
261 drv->head = head;
262 if (drv->track != track) {
263 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
264 drv->media_changed = 0;
265 }
266 ret = 1;
267 }
268 drv->track = track;
269 drv->sect = sect;
270 }
271
272 if (drv->bs == NULL || !bdrv_is_inserted(drv->bs)) {
273 ret = 2;
274 }
275
276 return ret;
277 }
278
279 /* Set drive back to track 0 */
280 static void fd_recalibrate(FDrive *drv)
281 {
282 FLOPPY_DPRINTF("recalibrate\n");
283 fd_seek(drv, 0, 0, 1, 1);
284 }
285
286 /* Revalidate a disk drive after a disk change */
287 static void fd_revalidate(FDrive *drv)
288 {
289 int nb_heads, max_track, last_sect, ro;
290 FDriveType drive;
291 FDriveRate rate;
292
293 FLOPPY_DPRINTF("revalidate\n");
294 if (drv->bs != NULL) {
295 ro = bdrv_is_read_only(drv->bs);
296 pick_geometry(drv->bs, &nb_heads, &max_track,
297 &last_sect, drv->drive, &drive, &rate);
298 if (!bdrv_is_inserted(drv->bs)) {
299 FLOPPY_DPRINTF("No disk in drive\n");
300 } else {
301 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
302 max_track, last_sect, ro ? "ro" : "rw");
303 }
304 if (nb_heads == 1) {
305 drv->flags &= ~FDISK_DBL_SIDES;
306 } else {
307 drv->flags |= FDISK_DBL_SIDES;
308 }
309 drv->max_track = max_track;
310 drv->last_sect = last_sect;
311 drv->ro = ro;
312 drv->drive = drive;
313 drv->media_rate = rate;
314 } else {
315 FLOPPY_DPRINTF("No drive connected\n");
316 drv->last_sect = 0;
317 drv->max_track = 0;
318 drv->flags &= ~FDISK_DBL_SIDES;
319 }
320 }
321
322 /********************************************************/
323 /* Intel 82078 floppy disk controller emulation */
324
325 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
326 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
327 static int fdctrl_transfer_handler (void *opaque, int nchan,
328 int dma_pos, int dma_len);
329 static void fdctrl_raise_irq(FDCtrl *fdctrl);
330 static FDrive *get_cur_drv(FDCtrl *fdctrl);
331
332 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
333 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
334 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
335 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
336 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
337 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
338 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
339 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
340 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
341 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
342 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
343 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
344
345 enum {
346 FD_DIR_WRITE = 0,
347 FD_DIR_READ = 1,
348 FD_DIR_SCANE = 2,
349 FD_DIR_SCANL = 3,
350 FD_DIR_SCANH = 4,
351 FD_DIR_VERIFY = 5,
352 };
353
354 enum {
355 FD_STATE_MULTI = 0x01, /* multi track flag */
356 FD_STATE_FORMAT = 0x02, /* format flag */
357 };
358
359 enum {
360 FD_REG_SRA = 0x00,
361 FD_REG_SRB = 0x01,
362 FD_REG_DOR = 0x02,
363 FD_REG_TDR = 0x03,
364 FD_REG_MSR = 0x04,
365 FD_REG_DSR = 0x04,
366 FD_REG_FIFO = 0x05,
367 FD_REG_DIR = 0x07,
368 FD_REG_CCR = 0x07,
369 };
370
371 enum {
372 FD_CMD_READ_TRACK = 0x02,
373 FD_CMD_SPECIFY = 0x03,
374 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
375 FD_CMD_WRITE = 0x05,
376 FD_CMD_READ = 0x06,
377 FD_CMD_RECALIBRATE = 0x07,
378 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
379 FD_CMD_WRITE_DELETED = 0x09,
380 FD_CMD_READ_ID = 0x0a,
381 FD_CMD_READ_DELETED = 0x0c,
382 FD_CMD_FORMAT_TRACK = 0x0d,
383 FD_CMD_DUMPREG = 0x0e,
384 FD_CMD_SEEK = 0x0f,
385 FD_CMD_VERSION = 0x10,
386 FD_CMD_SCAN_EQUAL = 0x11,
387 FD_CMD_PERPENDICULAR_MODE = 0x12,
388 FD_CMD_CONFIGURE = 0x13,
389 FD_CMD_LOCK = 0x14,
390 FD_CMD_VERIFY = 0x16,
391 FD_CMD_POWERDOWN_MODE = 0x17,
392 FD_CMD_PART_ID = 0x18,
393 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
394 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
395 FD_CMD_SAVE = 0x2e,
396 FD_CMD_OPTION = 0x33,
397 FD_CMD_RESTORE = 0x4e,
398 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
399 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
400 FD_CMD_FORMAT_AND_WRITE = 0xcd,
401 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
402 };
403
404 enum {
405 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
406 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
407 FD_CONFIG_POLL = 0x10, /* Poll enabled */
408 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
409 FD_CONFIG_EIS = 0x40, /* No implied seeks */
410 };
411
412 enum {
413 FD_SR0_DS0 = 0x01,
414 FD_SR0_DS1 = 0x02,
415 FD_SR0_HEAD = 0x04,
416 FD_SR0_EQPMT = 0x10,
417 FD_SR0_SEEK = 0x20,
418 FD_SR0_ABNTERM = 0x40,
419 FD_SR0_INVCMD = 0x80,
420 FD_SR0_RDYCHG = 0xc0,
421 };
422
423 enum {
424 FD_SR1_MA = 0x01, /* Missing address mark */
425 FD_SR1_NW = 0x02, /* Not writable */
426 FD_SR1_EC = 0x80, /* End of cylinder */
427 };
428
429 enum {
430 FD_SR2_SNS = 0x04, /* Scan not satisfied */
431 FD_SR2_SEH = 0x08, /* Scan equal hit */
432 };
433
434 enum {
435 FD_SRA_DIR = 0x01,
436 FD_SRA_nWP = 0x02,
437 FD_SRA_nINDX = 0x04,
438 FD_SRA_HDSEL = 0x08,
439 FD_SRA_nTRK0 = 0x10,
440 FD_SRA_STEP = 0x20,
441 FD_SRA_nDRV2 = 0x40,
442 FD_SRA_INTPEND = 0x80,
443 };
444
445 enum {
446 FD_SRB_MTR0 = 0x01,
447 FD_SRB_MTR1 = 0x02,
448 FD_SRB_WGATE = 0x04,
449 FD_SRB_RDATA = 0x08,
450 FD_SRB_WDATA = 0x10,
451 FD_SRB_DR0 = 0x20,
452 };
453
454 enum {
455 #if MAX_FD == 4
456 FD_DOR_SELMASK = 0x03,
457 #else
458 FD_DOR_SELMASK = 0x01,
459 #endif
460 FD_DOR_nRESET = 0x04,
461 FD_DOR_DMAEN = 0x08,
462 FD_DOR_MOTEN0 = 0x10,
463 FD_DOR_MOTEN1 = 0x20,
464 FD_DOR_MOTEN2 = 0x40,
465 FD_DOR_MOTEN3 = 0x80,
466 };
467
468 enum {
469 #if MAX_FD == 4
470 FD_TDR_BOOTSEL = 0x0c,
471 #else
472 FD_TDR_BOOTSEL = 0x04,
473 #endif
474 };
475
476 enum {
477 FD_DSR_DRATEMASK= 0x03,
478 FD_DSR_PWRDOWN = 0x40,
479 FD_DSR_SWRESET = 0x80,
480 };
481
482 enum {
483 FD_MSR_DRV0BUSY = 0x01,
484 FD_MSR_DRV1BUSY = 0x02,
485 FD_MSR_DRV2BUSY = 0x04,
486 FD_MSR_DRV3BUSY = 0x08,
487 FD_MSR_CMDBUSY = 0x10,
488 FD_MSR_NONDMA = 0x20,
489 FD_MSR_DIO = 0x40,
490 FD_MSR_RQM = 0x80,
491 };
492
493 enum {
494 FD_DIR_DSKCHG = 0x80,
495 };
496
497 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
498 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
499
500 struct FDCtrl {
501 MemoryRegion iomem;
502 qemu_irq irq;
503 /* Controller state */
504 QEMUTimer *result_timer;
505 int dma_chann;
506 /* Controller's identification */
507 uint8_t version;
508 /* HW */
509 uint8_t sra;
510 uint8_t srb;
511 uint8_t dor;
512 uint8_t dor_vmstate; /* only used as temp during vmstate */
513 uint8_t tdr;
514 uint8_t dsr;
515 uint8_t msr;
516 uint8_t cur_drv;
517 uint8_t status0;
518 uint8_t status1;
519 uint8_t status2;
520 /* Command FIFO */
521 uint8_t *fifo;
522 int32_t fifo_size;
523 uint32_t data_pos;
524 uint32_t data_len;
525 uint8_t data_state;
526 uint8_t data_dir;
527 uint8_t eot; /* last wanted sector */
528 /* States kept only to be returned back */
529 /* precompensation */
530 uint8_t precomp_trk;
531 uint8_t config;
532 uint8_t lock;
533 /* Power down config (also with status regB access mode */
534 uint8_t pwrd;
535 /* Floppy drives */
536 uint8_t num_floppies;
537 /* Sun4m quirks? */
538 int sun4m;
539 FDrive drives[MAX_FD];
540 int reset_sensei;
541 uint32_t check_media_rate;
542 /* Timers state */
543 uint8_t timer0;
544 uint8_t timer1;
545 };
546
547 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
548 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
549
550 typedef struct FDCtrlSysBus {
551 /*< private >*/
552 SysBusDevice parent_obj;
553 /*< public >*/
554
555 struct FDCtrl state;
556 } FDCtrlSysBus;
557
558 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
559
560 typedef struct FDCtrlISABus {
561 ISADevice parent_obj;
562
563 uint32_t iobase;
564 uint32_t irq;
565 uint32_t dma;
566 struct FDCtrl state;
567 int32_t bootindexA;
568 int32_t bootindexB;
569 } FDCtrlISABus;
570
571 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
572 {
573 FDCtrl *fdctrl = opaque;
574 uint32_t retval;
575
576 reg &= 7;
577 switch (reg) {
578 case FD_REG_SRA:
579 retval = fdctrl_read_statusA(fdctrl);
580 break;
581 case FD_REG_SRB:
582 retval = fdctrl_read_statusB(fdctrl);
583 break;
584 case FD_REG_DOR:
585 retval = fdctrl_read_dor(fdctrl);
586 break;
587 case FD_REG_TDR:
588 retval = fdctrl_read_tape(fdctrl);
589 break;
590 case FD_REG_MSR:
591 retval = fdctrl_read_main_status(fdctrl);
592 break;
593 case FD_REG_FIFO:
594 retval = fdctrl_read_data(fdctrl);
595 break;
596 case FD_REG_DIR:
597 retval = fdctrl_read_dir(fdctrl);
598 break;
599 default:
600 retval = (uint32_t)(-1);
601 break;
602 }
603 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
604
605 return retval;
606 }
607
608 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
609 {
610 FDCtrl *fdctrl = opaque;
611
612 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
613
614 reg &= 7;
615 switch (reg) {
616 case FD_REG_DOR:
617 fdctrl_write_dor(fdctrl, value);
618 break;
619 case FD_REG_TDR:
620 fdctrl_write_tape(fdctrl, value);
621 break;
622 case FD_REG_DSR:
623 fdctrl_write_rate(fdctrl, value);
624 break;
625 case FD_REG_FIFO:
626 fdctrl_write_data(fdctrl, value);
627 break;
628 case FD_REG_CCR:
629 fdctrl_write_ccr(fdctrl, value);
630 break;
631 default:
632 break;
633 }
634 }
635
636 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
637 unsigned ize)
638 {
639 return fdctrl_read(opaque, (uint32_t)reg);
640 }
641
642 static void fdctrl_write_mem (void *opaque, hwaddr reg,
643 uint64_t value, unsigned size)
644 {
645 fdctrl_write(opaque, (uint32_t)reg, value);
646 }
647
648 static const MemoryRegionOps fdctrl_mem_ops = {
649 .read = fdctrl_read_mem,
650 .write = fdctrl_write_mem,
651 .endianness = DEVICE_NATIVE_ENDIAN,
652 };
653
654 static const MemoryRegionOps fdctrl_mem_strict_ops = {
655 .read = fdctrl_read_mem,
656 .write = fdctrl_write_mem,
657 .endianness = DEVICE_NATIVE_ENDIAN,
658 .valid = {
659 .min_access_size = 1,
660 .max_access_size = 1,
661 },
662 };
663
664 static bool fdrive_media_changed_needed(void *opaque)
665 {
666 FDrive *drive = opaque;
667
668 return (drive->bs != NULL && drive->media_changed != 1);
669 }
670
671 static const VMStateDescription vmstate_fdrive_media_changed = {
672 .name = "fdrive/media_changed",
673 .version_id = 1,
674 .minimum_version_id = 1,
675 .fields = (VMStateField[]) {
676 VMSTATE_UINT8(media_changed, FDrive),
677 VMSTATE_END_OF_LIST()
678 }
679 };
680
681 static bool fdrive_media_rate_needed(void *opaque)
682 {
683 FDrive *drive = opaque;
684
685 return drive->fdctrl->check_media_rate;
686 }
687
688 static const VMStateDescription vmstate_fdrive_media_rate = {
689 .name = "fdrive/media_rate",
690 .version_id = 1,
691 .minimum_version_id = 1,
692 .fields = (VMStateField[]) {
693 VMSTATE_UINT8(media_rate, FDrive),
694 VMSTATE_END_OF_LIST()
695 }
696 };
697
698 static const VMStateDescription vmstate_fdrive = {
699 .name = "fdrive",
700 .version_id = 1,
701 .minimum_version_id = 1,
702 .fields = (VMStateField[]) {
703 VMSTATE_UINT8(head, FDrive),
704 VMSTATE_UINT8(track, FDrive),
705 VMSTATE_UINT8(sect, FDrive),
706 VMSTATE_END_OF_LIST()
707 },
708 .subsections = (VMStateSubsection[]) {
709 {
710 .vmsd = &vmstate_fdrive_media_changed,
711 .needed = &fdrive_media_changed_needed,
712 } , {
713 .vmsd = &vmstate_fdrive_media_rate,
714 .needed = &fdrive_media_rate_needed,
715 } , {
716 /* empty */
717 }
718 }
719 };
720
721 static void fdc_pre_save(void *opaque)
722 {
723 FDCtrl *s = opaque;
724
725 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
726 }
727
728 static int fdc_post_load(void *opaque, int version_id)
729 {
730 FDCtrl *s = opaque;
731
732 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
733 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
734 return 0;
735 }
736
737 static const VMStateDescription vmstate_fdc = {
738 .name = "fdc",
739 .version_id = 2,
740 .minimum_version_id = 2,
741 .pre_save = fdc_pre_save,
742 .post_load = fdc_post_load,
743 .fields = (VMStateField[]) {
744 /* Controller State */
745 VMSTATE_UINT8(sra, FDCtrl),
746 VMSTATE_UINT8(srb, FDCtrl),
747 VMSTATE_UINT8(dor_vmstate, FDCtrl),
748 VMSTATE_UINT8(tdr, FDCtrl),
749 VMSTATE_UINT8(dsr, FDCtrl),
750 VMSTATE_UINT8(msr, FDCtrl),
751 VMSTATE_UINT8(status0, FDCtrl),
752 VMSTATE_UINT8(status1, FDCtrl),
753 VMSTATE_UINT8(status2, FDCtrl),
754 /* Command FIFO */
755 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
756 uint8_t),
757 VMSTATE_UINT32(data_pos, FDCtrl),
758 VMSTATE_UINT32(data_len, FDCtrl),
759 VMSTATE_UINT8(data_state, FDCtrl),
760 VMSTATE_UINT8(data_dir, FDCtrl),
761 VMSTATE_UINT8(eot, FDCtrl),
762 /* States kept only to be returned back */
763 VMSTATE_UINT8(timer0, FDCtrl),
764 VMSTATE_UINT8(timer1, FDCtrl),
765 VMSTATE_UINT8(precomp_trk, FDCtrl),
766 VMSTATE_UINT8(config, FDCtrl),
767 VMSTATE_UINT8(lock, FDCtrl),
768 VMSTATE_UINT8(pwrd, FDCtrl),
769 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
770 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
771 vmstate_fdrive, FDrive),
772 VMSTATE_END_OF_LIST()
773 }
774 };
775
776 static void fdctrl_external_reset_sysbus(DeviceState *d)
777 {
778 FDCtrlSysBus *sys = SYSBUS_FDC(d);
779 FDCtrl *s = &sys->state;
780
781 fdctrl_reset(s, 0);
782 }
783
784 static void fdctrl_external_reset_isa(DeviceState *d)
785 {
786 FDCtrlISABus *isa = ISA_FDC(d);
787 FDCtrl *s = &isa->state;
788
789 fdctrl_reset(s, 0);
790 }
791
792 static void fdctrl_handle_tc(void *opaque, int irq, int level)
793 {
794 //FDCtrl *s = opaque;
795
796 if (level) {
797 // XXX
798 FLOPPY_DPRINTF("TC pulsed\n");
799 }
800 }
801
802 /* Change IRQ state */
803 static void fdctrl_reset_irq(FDCtrl *fdctrl)
804 {
805 fdctrl->status0 = 0;
806 if (!(fdctrl->sra & FD_SRA_INTPEND))
807 return;
808 FLOPPY_DPRINTF("Reset interrupt\n");
809 qemu_set_irq(fdctrl->irq, 0);
810 fdctrl->sra &= ~FD_SRA_INTPEND;
811 }
812
813 static void fdctrl_raise_irq(FDCtrl *fdctrl)
814 {
815 /* Sparc mutation */
816 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
817 /* XXX: not sure */
818 fdctrl->msr &= ~FD_MSR_CMDBUSY;
819 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
820 return;
821 }
822 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
823 qemu_set_irq(fdctrl->irq, 1);
824 fdctrl->sra |= FD_SRA_INTPEND;
825 }
826
827 fdctrl->reset_sensei = 0;
828 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
829 }
830
831 /* Reset controller */
832 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
833 {
834 int i;
835
836 FLOPPY_DPRINTF("reset controller\n");
837 fdctrl_reset_irq(fdctrl);
838 /* Initialise controller */
839 fdctrl->sra = 0;
840 fdctrl->srb = 0xc0;
841 if (!fdctrl->drives[1].bs)
842 fdctrl->sra |= FD_SRA_nDRV2;
843 fdctrl->cur_drv = 0;
844 fdctrl->dor = FD_DOR_nRESET;
845 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
846 fdctrl->msr = FD_MSR_RQM;
847 /* FIFO state */
848 fdctrl->data_pos = 0;
849 fdctrl->data_len = 0;
850 fdctrl->data_state = 0;
851 fdctrl->data_dir = FD_DIR_WRITE;
852 for (i = 0; i < MAX_FD; i++)
853 fd_recalibrate(&fdctrl->drives[i]);
854 fdctrl_reset_fifo(fdctrl);
855 if (do_irq) {
856 fdctrl->status0 |= FD_SR0_RDYCHG;
857 fdctrl_raise_irq(fdctrl);
858 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
859 }
860 }
861
862 static inline FDrive *drv0(FDCtrl *fdctrl)
863 {
864 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
865 }
866
867 static inline FDrive *drv1(FDCtrl *fdctrl)
868 {
869 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
870 return &fdctrl->drives[1];
871 else
872 return &fdctrl->drives[0];
873 }
874
875 #if MAX_FD == 4
876 static inline FDrive *drv2(FDCtrl *fdctrl)
877 {
878 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
879 return &fdctrl->drives[2];
880 else
881 return &fdctrl->drives[1];
882 }
883
884 static inline FDrive *drv3(FDCtrl *fdctrl)
885 {
886 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
887 return &fdctrl->drives[3];
888 else
889 return &fdctrl->drives[2];
890 }
891 #endif
892
893 static FDrive *get_cur_drv(FDCtrl *fdctrl)
894 {
895 switch (fdctrl->cur_drv) {
896 case 0: return drv0(fdctrl);
897 case 1: return drv1(fdctrl);
898 #if MAX_FD == 4
899 case 2: return drv2(fdctrl);
900 case 3: return drv3(fdctrl);
901 #endif
902 default: return NULL;
903 }
904 }
905
906 /* Status A register : 0x00 (read-only) */
907 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
908 {
909 uint32_t retval = fdctrl->sra;
910
911 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
912
913 return retval;
914 }
915
916 /* Status B register : 0x01 (read-only) */
917 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
918 {
919 uint32_t retval = fdctrl->srb;
920
921 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
922
923 return retval;
924 }
925
926 /* Digital output register : 0x02 */
927 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
928 {
929 uint32_t retval = fdctrl->dor;
930
931 /* Selected drive */
932 retval |= fdctrl->cur_drv;
933 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
934
935 return retval;
936 }
937
938 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
939 {
940 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
941
942 /* Motors */
943 if (value & FD_DOR_MOTEN0)
944 fdctrl->srb |= FD_SRB_MTR0;
945 else
946 fdctrl->srb &= ~FD_SRB_MTR0;
947 if (value & FD_DOR_MOTEN1)
948 fdctrl->srb |= FD_SRB_MTR1;
949 else
950 fdctrl->srb &= ~FD_SRB_MTR1;
951
952 /* Drive */
953 if (value & 1)
954 fdctrl->srb |= FD_SRB_DR0;
955 else
956 fdctrl->srb &= ~FD_SRB_DR0;
957
958 /* Reset */
959 if (!(value & FD_DOR_nRESET)) {
960 if (fdctrl->dor & FD_DOR_nRESET) {
961 FLOPPY_DPRINTF("controller enter RESET state\n");
962 }
963 } else {
964 if (!(fdctrl->dor & FD_DOR_nRESET)) {
965 FLOPPY_DPRINTF("controller out of RESET state\n");
966 fdctrl_reset(fdctrl, 1);
967 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
968 }
969 }
970 /* Selected drive */
971 fdctrl->cur_drv = value & FD_DOR_SELMASK;
972
973 fdctrl->dor = value;
974 }
975
976 /* Tape drive register : 0x03 */
977 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
978 {
979 uint32_t retval = fdctrl->tdr;
980
981 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
982
983 return retval;
984 }
985
986 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
987 {
988 /* Reset mode */
989 if (!(fdctrl->dor & FD_DOR_nRESET)) {
990 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
991 return;
992 }
993 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
994 /* Disk boot selection indicator */
995 fdctrl->tdr = value & FD_TDR_BOOTSEL;
996 /* Tape indicators: never allow */
997 }
998
999 /* Main status register : 0x04 (read) */
1000 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1001 {
1002 uint32_t retval = fdctrl->msr;
1003
1004 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1005 fdctrl->dor |= FD_DOR_nRESET;
1006
1007 /* Sparc mutation */
1008 if (fdctrl->sun4m) {
1009 retval |= FD_MSR_DIO;
1010 fdctrl_reset_irq(fdctrl);
1011 };
1012
1013 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1014
1015 return retval;
1016 }
1017
1018 /* Data select rate register : 0x04 (write) */
1019 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1020 {
1021 /* Reset mode */
1022 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1023 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1024 return;
1025 }
1026 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1027 /* Reset: autoclear */
1028 if (value & FD_DSR_SWRESET) {
1029 fdctrl->dor &= ~FD_DOR_nRESET;
1030 fdctrl_reset(fdctrl, 1);
1031 fdctrl->dor |= FD_DOR_nRESET;
1032 }
1033 if (value & FD_DSR_PWRDOWN) {
1034 fdctrl_reset(fdctrl, 1);
1035 }
1036 fdctrl->dsr = value;
1037 }
1038
1039 /* Configuration control register: 0x07 (write) */
1040 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1041 {
1042 /* Reset mode */
1043 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1044 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1045 return;
1046 }
1047 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1048
1049 /* Only the rate selection bits used in AT mode, and we
1050 * store those in the DSR.
1051 */
1052 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1053 (value & FD_DSR_DRATEMASK);
1054 }
1055
1056 static int fdctrl_media_changed(FDrive *drv)
1057 {
1058 return drv->media_changed;
1059 }
1060
1061 /* Digital input register : 0x07 (read-only) */
1062 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1063 {
1064 uint32_t retval = 0;
1065
1066 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1067 retval |= FD_DIR_DSKCHG;
1068 }
1069 if (retval != 0) {
1070 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1071 }
1072
1073 return retval;
1074 }
1075
1076 /* FIFO state control */
1077 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
1078 {
1079 fdctrl->data_dir = FD_DIR_WRITE;
1080 fdctrl->data_pos = 0;
1081 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1082 }
1083
1084 /* Set FIFO status for the host to read */
1085 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len)
1086 {
1087 fdctrl->data_dir = FD_DIR_READ;
1088 fdctrl->data_len = fifo_len;
1089 fdctrl->data_pos = 0;
1090 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1091 }
1092
1093 /* Set an error: unimplemented/unknown command */
1094 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1095 {
1096 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1097 fdctrl->fifo[0]);
1098 fdctrl->fifo[0] = FD_SR0_INVCMD;
1099 fdctrl_set_fifo(fdctrl, 1);
1100 }
1101
1102 /* Seek to next sector
1103 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1104 * otherwise returns 1
1105 */
1106 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1107 {
1108 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1109 cur_drv->head, cur_drv->track, cur_drv->sect,
1110 fd_sector(cur_drv));
1111 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1112 error in fact */
1113 uint8_t new_head = cur_drv->head;
1114 uint8_t new_track = cur_drv->track;
1115 uint8_t new_sect = cur_drv->sect;
1116
1117 int ret = 1;
1118
1119 if (new_sect >= cur_drv->last_sect ||
1120 new_sect == fdctrl->eot) {
1121 new_sect = 1;
1122 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1123 if (new_head == 0 &&
1124 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1125 new_head = 1;
1126 } else {
1127 new_head = 0;
1128 new_track++;
1129 fdctrl->status0 |= FD_SR0_SEEK;
1130 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1131 ret = 0;
1132 }
1133 }
1134 } else {
1135 fdctrl->status0 |= FD_SR0_SEEK;
1136 new_track++;
1137 ret = 0;
1138 }
1139 if (ret == 1) {
1140 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1141 new_head, new_track, new_sect, fd_sector(cur_drv));
1142 }
1143 } else {
1144 new_sect++;
1145 }
1146 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1147 return ret;
1148 }
1149
1150 /* Callback for transfer end (stop or abort) */
1151 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1152 uint8_t status1, uint8_t status2)
1153 {
1154 FDrive *cur_drv;
1155 cur_drv = get_cur_drv(fdctrl);
1156
1157 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1158 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1159 if (cur_drv->head) {
1160 fdctrl->status0 |= FD_SR0_HEAD;
1161 }
1162 fdctrl->status0 |= status0;
1163
1164 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1165 status0, status1, status2, fdctrl->status0);
1166 fdctrl->fifo[0] = fdctrl->status0;
1167 fdctrl->fifo[1] = status1;
1168 fdctrl->fifo[2] = status2;
1169 fdctrl->fifo[3] = cur_drv->track;
1170 fdctrl->fifo[4] = cur_drv->head;
1171 fdctrl->fifo[5] = cur_drv->sect;
1172 fdctrl->fifo[6] = FD_SECTOR_SC;
1173 fdctrl->data_dir = FD_DIR_READ;
1174 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1175 DMA_release_DREQ(fdctrl->dma_chann);
1176 }
1177 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1178 fdctrl->msr &= ~FD_MSR_NONDMA;
1179
1180 fdctrl_set_fifo(fdctrl, 7);
1181 fdctrl_raise_irq(fdctrl);
1182 }
1183
1184 /* Prepare a data transfer (either DMA or FIFO) */
1185 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1186 {
1187 FDrive *cur_drv;
1188 uint8_t kh, kt, ks;
1189
1190 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1191 cur_drv = get_cur_drv(fdctrl);
1192 kt = fdctrl->fifo[2];
1193 kh = fdctrl->fifo[3];
1194 ks = fdctrl->fifo[4];
1195 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1196 GET_CUR_DRV(fdctrl), kh, kt, ks,
1197 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1198 NUM_SIDES(cur_drv)));
1199 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1200 case 2:
1201 /* sect too big */
1202 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1203 fdctrl->fifo[3] = kt;
1204 fdctrl->fifo[4] = kh;
1205 fdctrl->fifo[5] = ks;
1206 return;
1207 case 3:
1208 /* track too big */
1209 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1210 fdctrl->fifo[3] = kt;
1211 fdctrl->fifo[4] = kh;
1212 fdctrl->fifo[5] = ks;
1213 return;
1214 case 4:
1215 /* No seek enabled */
1216 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1217 fdctrl->fifo[3] = kt;
1218 fdctrl->fifo[4] = kh;
1219 fdctrl->fifo[5] = ks;
1220 return;
1221 case 1:
1222 fdctrl->status0 |= FD_SR0_SEEK;
1223 break;
1224 default:
1225 break;
1226 }
1227
1228 /* Check the data rate. If the programmed data rate does not match
1229 * the currently inserted medium, the operation has to fail. */
1230 if (fdctrl->check_media_rate &&
1231 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1232 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1233 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1234 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1235 fdctrl->fifo[3] = kt;
1236 fdctrl->fifo[4] = kh;
1237 fdctrl->fifo[5] = ks;
1238 return;
1239 }
1240
1241 /* Set the FIFO state */
1242 fdctrl->data_dir = direction;
1243 fdctrl->data_pos = 0;
1244 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1245 if (fdctrl->fifo[0] & 0x80)
1246 fdctrl->data_state |= FD_STATE_MULTI;
1247 else
1248 fdctrl->data_state &= ~FD_STATE_MULTI;
1249 if (fdctrl->fifo[5] == 0) {
1250 fdctrl->data_len = fdctrl->fifo[8];
1251 } else {
1252 int tmp;
1253 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1254 tmp = (fdctrl->fifo[6] - ks + 1);
1255 if (fdctrl->fifo[0] & 0x80)
1256 tmp += fdctrl->fifo[6];
1257 fdctrl->data_len *= tmp;
1258 }
1259 fdctrl->eot = fdctrl->fifo[6];
1260 if (fdctrl->dor & FD_DOR_DMAEN) {
1261 int dma_mode;
1262 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1263 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1264 dma_mode = (dma_mode >> 2) & 3;
1265 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1266 dma_mode, direction,
1267 (128 << fdctrl->fifo[5]) *
1268 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1269 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1270 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1271 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1272 (direction == FD_DIR_READ && dma_mode == 1) ||
1273 (direction == FD_DIR_VERIFY)) {
1274 /* No access is allowed until DMA transfer has completed */
1275 fdctrl->msr &= ~FD_MSR_RQM;
1276 if (direction != FD_DIR_VERIFY) {
1277 /* Now, we just have to wait for the DMA controller to
1278 * recall us...
1279 */
1280 DMA_hold_DREQ(fdctrl->dma_chann);
1281 DMA_schedule(fdctrl->dma_chann);
1282 } else {
1283 /* Start transfer */
1284 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1285 fdctrl->data_len);
1286 }
1287 return;
1288 } else {
1289 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1290 direction);
1291 }
1292 }
1293 FLOPPY_DPRINTF("start non-DMA transfer\n");
1294 fdctrl->msr |= FD_MSR_NONDMA;
1295 if (direction != FD_DIR_WRITE)
1296 fdctrl->msr |= FD_MSR_DIO;
1297 /* IO based transfer: calculate len */
1298 fdctrl_raise_irq(fdctrl);
1299 }
1300
1301 /* Prepare a transfer of deleted data */
1302 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1303 {
1304 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1305
1306 /* We don't handle deleted data,
1307 * so we don't return *ANYTHING*
1308 */
1309 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1310 }
1311
1312 /* handlers for DMA transfers */
1313 static int fdctrl_transfer_handler (void *opaque, int nchan,
1314 int dma_pos, int dma_len)
1315 {
1316 FDCtrl *fdctrl;
1317 FDrive *cur_drv;
1318 int len, start_pos, rel_pos;
1319 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1320
1321 fdctrl = opaque;
1322 if (fdctrl->msr & FD_MSR_RQM) {
1323 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1324 return 0;
1325 }
1326 cur_drv = get_cur_drv(fdctrl);
1327 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1328 fdctrl->data_dir == FD_DIR_SCANH)
1329 status2 = FD_SR2_SNS;
1330 if (dma_len > fdctrl->data_len)
1331 dma_len = fdctrl->data_len;
1332 if (cur_drv->bs == NULL) {
1333 if (fdctrl->data_dir == FD_DIR_WRITE)
1334 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1335 else
1336 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1337 len = 0;
1338 goto transfer_error;
1339 }
1340 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1341 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1342 len = dma_len - fdctrl->data_pos;
1343 if (len + rel_pos > FD_SECTOR_LEN)
1344 len = FD_SECTOR_LEN - rel_pos;
1345 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1346 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1347 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1348 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1349 fd_sector(cur_drv) * FD_SECTOR_LEN);
1350 if (fdctrl->data_dir != FD_DIR_WRITE ||
1351 len < FD_SECTOR_LEN || rel_pos != 0) {
1352 /* READ & SCAN commands and realign to a sector for WRITE */
1353 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1354 fdctrl->fifo, 1) < 0) {
1355 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1356 fd_sector(cur_drv));
1357 /* Sure, image size is too small... */
1358 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1359 }
1360 }
1361 switch (fdctrl->data_dir) {
1362 case FD_DIR_READ:
1363 /* READ commands */
1364 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1365 fdctrl->data_pos, len);
1366 break;
1367 case FD_DIR_WRITE:
1368 /* WRITE commands */
1369 if (cur_drv->ro) {
1370 /* Handle readonly medium early, no need to do DMA, touch the
1371 * LED or attempt any writes. A real floppy doesn't attempt
1372 * to write to readonly media either. */
1373 fdctrl_stop_transfer(fdctrl,
1374 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1375 0x00);
1376 goto transfer_error;
1377 }
1378
1379 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1380 fdctrl->data_pos, len);
1381 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1382 fdctrl->fifo, 1) < 0) {
1383 FLOPPY_DPRINTF("error writing sector %d\n",
1384 fd_sector(cur_drv));
1385 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1386 goto transfer_error;
1387 }
1388 break;
1389 case FD_DIR_VERIFY:
1390 /* VERIFY commands */
1391 break;
1392 default:
1393 /* SCAN commands */
1394 {
1395 uint8_t tmpbuf[FD_SECTOR_LEN];
1396 int ret;
1397 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1398 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1399 if (ret == 0) {
1400 status2 = FD_SR2_SEH;
1401 goto end_transfer;
1402 }
1403 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1404 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1405 status2 = 0x00;
1406 goto end_transfer;
1407 }
1408 }
1409 break;
1410 }
1411 fdctrl->data_pos += len;
1412 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1413 if (rel_pos == 0) {
1414 /* Seek to next sector */
1415 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1416 break;
1417 }
1418 }
1419 end_transfer:
1420 len = fdctrl->data_pos - start_pos;
1421 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1422 fdctrl->data_pos, len, fdctrl->data_len);
1423 if (fdctrl->data_dir == FD_DIR_SCANE ||
1424 fdctrl->data_dir == FD_DIR_SCANL ||
1425 fdctrl->data_dir == FD_DIR_SCANH)
1426 status2 = FD_SR2_SEH;
1427 fdctrl->data_len -= len;
1428 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1429 transfer_error:
1430
1431 return len;
1432 }
1433
1434 /* Data register : 0x05 */
1435 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1436 {
1437 FDrive *cur_drv;
1438 uint32_t retval = 0;
1439 int pos;
1440
1441 cur_drv = get_cur_drv(fdctrl);
1442 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1443 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1444 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1445 return 0;
1446 }
1447 pos = fdctrl->data_pos;
1448 if (fdctrl->msr & FD_MSR_NONDMA) {
1449 pos %= FD_SECTOR_LEN;
1450 if (pos == 0) {
1451 if (fdctrl->data_pos != 0)
1452 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1453 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1454 fd_sector(cur_drv));
1455 return 0;
1456 }
1457 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1458 FLOPPY_DPRINTF("error getting sector %d\n",
1459 fd_sector(cur_drv));
1460 /* Sure, image size is too small... */
1461 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1462 }
1463 }
1464 }
1465 retval = fdctrl->fifo[pos];
1466 if (++fdctrl->data_pos == fdctrl->data_len) {
1467 fdctrl->data_pos = 0;
1468 /* Switch from transfer mode to status mode
1469 * then from status mode to command mode
1470 */
1471 if (fdctrl->msr & FD_MSR_NONDMA) {
1472 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1473 } else {
1474 fdctrl_reset_fifo(fdctrl);
1475 fdctrl_reset_irq(fdctrl);
1476 }
1477 }
1478 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1479
1480 return retval;
1481 }
1482
1483 static void fdctrl_format_sector(FDCtrl *fdctrl)
1484 {
1485 FDrive *cur_drv;
1486 uint8_t kh, kt, ks;
1487
1488 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1489 cur_drv = get_cur_drv(fdctrl);
1490 kt = fdctrl->fifo[6];
1491 kh = fdctrl->fifo[7];
1492 ks = fdctrl->fifo[8];
1493 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1494 GET_CUR_DRV(fdctrl), kh, kt, ks,
1495 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1496 NUM_SIDES(cur_drv)));
1497 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1498 case 2:
1499 /* sect too big */
1500 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1501 fdctrl->fifo[3] = kt;
1502 fdctrl->fifo[4] = kh;
1503 fdctrl->fifo[5] = ks;
1504 return;
1505 case 3:
1506 /* track too big */
1507 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1508 fdctrl->fifo[3] = kt;
1509 fdctrl->fifo[4] = kh;
1510 fdctrl->fifo[5] = ks;
1511 return;
1512 case 4:
1513 /* No seek enabled */
1514 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1515 fdctrl->fifo[3] = kt;
1516 fdctrl->fifo[4] = kh;
1517 fdctrl->fifo[5] = ks;
1518 return;
1519 case 1:
1520 fdctrl->status0 |= FD_SR0_SEEK;
1521 break;
1522 default:
1523 break;
1524 }
1525 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1526 if (cur_drv->bs == NULL ||
1527 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1528 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1529 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1530 } else {
1531 if (cur_drv->sect == cur_drv->last_sect) {
1532 fdctrl->data_state &= ~FD_STATE_FORMAT;
1533 /* Last sector done */
1534 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1535 } else {
1536 /* More to do */
1537 fdctrl->data_pos = 0;
1538 fdctrl->data_len = 4;
1539 }
1540 }
1541 }
1542
1543 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1544 {
1545 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1546 fdctrl->fifo[0] = fdctrl->lock << 4;
1547 fdctrl_set_fifo(fdctrl, 1);
1548 }
1549
1550 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1551 {
1552 FDrive *cur_drv = get_cur_drv(fdctrl);
1553
1554 /* Drives position */
1555 fdctrl->fifo[0] = drv0(fdctrl)->track;
1556 fdctrl->fifo[1] = drv1(fdctrl)->track;
1557 #if MAX_FD == 4
1558 fdctrl->fifo[2] = drv2(fdctrl)->track;
1559 fdctrl->fifo[3] = drv3(fdctrl)->track;
1560 #else
1561 fdctrl->fifo[2] = 0;
1562 fdctrl->fifo[3] = 0;
1563 #endif
1564 /* timers */
1565 fdctrl->fifo[4] = fdctrl->timer0;
1566 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1567 fdctrl->fifo[6] = cur_drv->last_sect;
1568 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1569 (cur_drv->perpendicular << 2);
1570 fdctrl->fifo[8] = fdctrl->config;
1571 fdctrl->fifo[9] = fdctrl->precomp_trk;
1572 fdctrl_set_fifo(fdctrl, 10);
1573 }
1574
1575 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1576 {
1577 /* Controller's version */
1578 fdctrl->fifo[0] = fdctrl->version;
1579 fdctrl_set_fifo(fdctrl, 1);
1580 }
1581
1582 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1583 {
1584 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1585 fdctrl_set_fifo(fdctrl, 1);
1586 }
1587
1588 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1589 {
1590 FDrive *cur_drv = get_cur_drv(fdctrl);
1591
1592 /* Drives position */
1593 drv0(fdctrl)->track = fdctrl->fifo[3];
1594 drv1(fdctrl)->track = fdctrl->fifo[4];
1595 #if MAX_FD == 4
1596 drv2(fdctrl)->track = fdctrl->fifo[5];
1597 drv3(fdctrl)->track = fdctrl->fifo[6];
1598 #endif
1599 /* timers */
1600 fdctrl->timer0 = fdctrl->fifo[7];
1601 fdctrl->timer1 = fdctrl->fifo[8];
1602 cur_drv->last_sect = fdctrl->fifo[9];
1603 fdctrl->lock = fdctrl->fifo[10] >> 7;
1604 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1605 fdctrl->config = fdctrl->fifo[11];
1606 fdctrl->precomp_trk = fdctrl->fifo[12];
1607 fdctrl->pwrd = fdctrl->fifo[13];
1608 fdctrl_reset_fifo(fdctrl);
1609 }
1610
1611 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1612 {
1613 FDrive *cur_drv = get_cur_drv(fdctrl);
1614
1615 fdctrl->fifo[0] = 0;
1616 fdctrl->fifo[1] = 0;
1617 /* Drives position */
1618 fdctrl->fifo[2] = drv0(fdctrl)->track;
1619 fdctrl->fifo[3] = drv1(fdctrl)->track;
1620 #if MAX_FD == 4
1621 fdctrl->fifo[4] = drv2(fdctrl)->track;
1622 fdctrl->fifo[5] = drv3(fdctrl)->track;
1623 #else
1624 fdctrl->fifo[4] = 0;
1625 fdctrl->fifo[5] = 0;
1626 #endif
1627 /* timers */
1628 fdctrl->fifo[6] = fdctrl->timer0;
1629 fdctrl->fifo[7] = fdctrl->timer1;
1630 fdctrl->fifo[8] = cur_drv->last_sect;
1631 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1632 (cur_drv->perpendicular << 2);
1633 fdctrl->fifo[10] = fdctrl->config;
1634 fdctrl->fifo[11] = fdctrl->precomp_trk;
1635 fdctrl->fifo[12] = fdctrl->pwrd;
1636 fdctrl->fifo[13] = 0;
1637 fdctrl->fifo[14] = 0;
1638 fdctrl_set_fifo(fdctrl, 15);
1639 }
1640
1641 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1642 {
1643 FDrive *cur_drv = get_cur_drv(fdctrl);
1644
1645 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1646 timer_mod(fdctrl->result_timer,
1647 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50));
1648 }
1649
1650 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1651 {
1652 FDrive *cur_drv;
1653
1654 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1655 cur_drv = get_cur_drv(fdctrl);
1656 fdctrl->data_state |= FD_STATE_FORMAT;
1657 if (fdctrl->fifo[0] & 0x80)
1658 fdctrl->data_state |= FD_STATE_MULTI;
1659 else
1660 fdctrl->data_state &= ~FD_STATE_MULTI;
1661 cur_drv->bps =
1662 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1663 #if 0
1664 cur_drv->last_sect =
1665 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1666 fdctrl->fifo[3] / 2;
1667 #else
1668 cur_drv->last_sect = fdctrl->fifo[3];
1669 #endif
1670 /* TODO: implement format using DMA expected by the Bochs BIOS
1671 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1672 * the sector with the specified fill byte
1673 */
1674 fdctrl->data_state &= ~FD_STATE_FORMAT;
1675 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1676 }
1677
1678 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1679 {
1680 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1681 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1682 if (fdctrl->fifo[2] & 1)
1683 fdctrl->dor &= ~FD_DOR_DMAEN;
1684 else
1685 fdctrl->dor |= FD_DOR_DMAEN;
1686 /* No result back */
1687 fdctrl_reset_fifo(fdctrl);
1688 }
1689
1690 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1691 {
1692 FDrive *cur_drv;
1693
1694 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1695 cur_drv = get_cur_drv(fdctrl);
1696 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1697 /* 1 Byte status back */
1698 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1699 (cur_drv->track == 0 ? 0x10 : 0x00) |
1700 (cur_drv->head << 2) |
1701 GET_CUR_DRV(fdctrl) |
1702 0x28;
1703 fdctrl_set_fifo(fdctrl, 1);
1704 }
1705
1706 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1707 {
1708 FDrive *cur_drv;
1709
1710 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1711 cur_drv = get_cur_drv(fdctrl);
1712 fd_recalibrate(cur_drv);
1713 fdctrl_reset_fifo(fdctrl);
1714 /* Raise Interrupt */
1715 fdctrl->status0 |= FD_SR0_SEEK;
1716 fdctrl_raise_irq(fdctrl);
1717 }
1718
1719 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1720 {
1721 FDrive *cur_drv = get_cur_drv(fdctrl);
1722
1723 if (fdctrl->reset_sensei > 0) {
1724 fdctrl->fifo[0] =
1725 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1726 fdctrl->reset_sensei--;
1727 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1728 fdctrl->fifo[0] = FD_SR0_INVCMD;
1729 fdctrl_set_fifo(fdctrl, 1);
1730 return;
1731 } else {
1732 fdctrl->fifo[0] =
1733 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
1734 | GET_CUR_DRV(fdctrl);
1735 }
1736
1737 fdctrl->fifo[1] = cur_drv->track;
1738 fdctrl_set_fifo(fdctrl, 2);
1739 fdctrl_reset_irq(fdctrl);
1740 fdctrl->status0 = FD_SR0_RDYCHG;
1741 }
1742
1743 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1744 {
1745 FDrive *cur_drv;
1746
1747 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1748 cur_drv = get_cur_drv(fdctrl);
1749 fdctrl_reset_fifo(fdctrl);
1750 /* The seek command just sends step pulses to the drive and doesn't care if
1751 * there is a medium inserted of if it's banging the head against the drive.
1752 */
1753 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1754 /* Raise Interrupt */
1755 fdctrl->status0 |= FD_SR0_SEEK;
1756 fdctrl_raise_irq(fdctrl);
1757 }
1758
1759 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1760 {
1761 FDrive *cur_drv = get_cur_drv(fdctrl);
1762
1763 if (fdctrl->fifo[1] & 0x80)
1764 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1765 /* No result back */
1766 fdctrl_reset_fifo(fdctrl);
1767 }
1768
1769 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1770 {
1771 fdctrl->config = fdctrl->fifo[2];
1772 fdctrl->precomp_trk = fdctrl->fifo[3];
1773 /* No result back */
1774 fdctrl_reset_fifo(fdctrl);
1775 }
1776
1777 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1778 {
1779 fdctrl->pwrd = fdctrl->fifo[1];
1780 fdctrl->fifo[0] = fdctrl->fifo[1];
1781 fdctrl_set_fifo(fdctrl, 1);
1782 }
1783
1784 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1785 {
1786 /* No result back */
1787 fdctrl_reset_fifo(fdctrl);
1788 }
1789
1790 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1791 {
1792 FDrive *cur_drv = get_cur_drv(fdctrl);
1793
1794 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1795 /* Command parameters done */
1796 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1797 fdctrl->fifo[0] = fdctrl->fifo[1];
1798 fdctrl->fifo[2] = 0;
1799 fdctrl->fifo[3] = 0;
1800 fdctrl_set_fifo(fdctrl, 4);
1801 } else {
1802 fdctrl_reset_fifo(fdctrl);
1803 }
1804 } else if (fdctrl->data_len > 7) {
1805 /* ERROR */
1806 fdctrl->fifo[0] = 0x80 |
1807 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1808 fdctrl_set_fifo(fdctrl, 1);
1809 }
1810 }
1811
1812 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1813 {
1814 FDrive *cur_drv;
1815
1816 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1817 cur_drv = get_cur_drv(fdctrl);
1818 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1819 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
1820 cur_drv->sect, 1);
1821 } else {
1822 fd_seek(cur_drv, cur_drv->head,
1823 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
1824 }
1825 fdctrl_reset_fifo(fdctrl);
1826 /* Raise Interrupt */
1827 fdctrl->status0 |= FD_SR0_SEEK;
1828 fdctrl_raise_irq(fdctrl);
1829 }
1830
1831 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1832 {
1833 FDrive *cur_drv;
1834
1835 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1836 cur_drv = get_cur_drv(fdctrl);
1837 if (fdctrl->fifo[2] > cur_drv->track) {
1838 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
1839 } else {
1840 fd_seek(cur_drv, cur_drv->head,
1841 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
1842 }
1843 fdctrl_reset_fifo(fdctrl);
1844 /* Raise Interrupt */
1845 fdctrl->status0 |= FD_SR0_SEEK;
1846 fdctrl_raise_irq(fdctrl);
1847 }
1848
1849 static const struct {
1850 uint8_t value;
1851 uint8_t mask;
1852 const char* name;
1853 int parameters;
1854 void (*handler)(FDCtrl *fdctrl, int direction);
1855 int direction;
1856 } handlers[] = {
1857 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1858 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1859 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1860 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1861 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1862 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1863 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1864 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1865 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1866 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1867 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1868 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
1869 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1870 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1871 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1872 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1873 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1874 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1875 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1876 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1877 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1878 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1879 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1880 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1881 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1882 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1883 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1884 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1885 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1886 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1887 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1888 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1889 };
1890 /* Associate command to an index in the 'handlers' array */
1891 static uint8_t command_to_handler[256];
1892
1893 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1894 {
1895 FDrive *cur_drv;
1896 int pos;
1897
1898 /* Reset mode */
1899 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1900 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1901 return;
1902 }
1903 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1904 FLOPPY_DPRINTF("error: controller not ready for writing\n");
1905 return;
1906 }
1907 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1908 /* Is it write command time ? */
1909 if (fdctrl->msr & FD_MSR_NONDMA) {
1910 /* FIFO data write */
1911 pos = fdctrl->data_pos++;
1912 pos %= FD_SECTOR_LEN;
1913 fdctrl->fifo[pos] = value;
1914 if (pos == FD_SECTOR_LEN - 1 ||
1915 fdctrl->data_pos == fdctrl->data_len) {
1916 cur_drv = get_cur_drv(fdctrl);
1917 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1918 FLOPPY_DPRINTF("error writing sector %d\n",
1919 fd_sector(cur_drv));
1920 return;
1921 }
1922 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1923 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1924 fd_sector(cur_drv));
1925 return;
1926 }
1927 }
1928 /* Switch from transfer mode to status mode
1929 * then from status mode to command mode
1930 */
1931 if (fdctrl->data_pos == fdctrl->data_len)
1932 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1933 return;
1934 }
1935 if (fdctrl->data_pos == 0) {
1936 /* Command */
1937 pos = command_to_handler[value & 0xff];
1938 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1939 fdctrl->data_len = handlers[pos].parameters + 1;
1940 fdctrl->msr |= FD_MSR_CMDBUSY;
1941 }
1942
1943 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1944 fdctrl->fifo[fdctrl->data_pos++] = value;
1945 if (fdctrl->data_pos == fdctrl->data_len) {
1946 /* We now have all parameters
1947 * and will be able to treat the command
1948 */
1949 if (fdctrl->data_state & FD_STATE_FORMAT) {
1950 fdctrl_format_sector(fdctrl);
1951 return;
1952 }
1953
1954 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1955 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1956 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1957 }
1958 }
1959
1960 static void fdctrl_result_timer(void *opaque)
1961 {
1962 FDCtrl *fdctrl = opaque;
1963 FDrive *cur_drv = get_cur_drv(fdctrl);
1964
1965 /* Pretend we are spinning.
1966 * This is needed for Coherent, which uses READ ID to check for
1967 * sector interleaving.
1968 */
1969 if (cur_drv->last_sect != 0) {
1970 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1971 }
1972 /* READ_ID can't automatically succeed! */
1973 if (fdctrl->check_media_rate &&
1974 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1975 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1976 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1977 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1978 } else {
1979 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1980 }
1981 }
1982
1983 static void fdctrl_change_cb(void *opaque, bool load)
1984 {
1985 FDrive *drive = opaque;
1986
1987 drive->media_changed = 1;
1988 fd_revalidate(drive);
1989 }
1990
1991 static const BlockDevOps fdctrl_block_ops = {
1992 .change_media_cb = fdctrl_change_cb,
1993 };
1994
1995 /* Init functions */
1996 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
1997 {
1998 unsigned int i;
1999 FDrive *drive;
2000
2001 for (i = 0; i < MAX_FD; i++) {
2002 drive = &fdctrl->drives[i];
2003 drive->fdctrl = fdctrl;
2004
2005 if (drive->bs) {
2006 if (bdrv_get_on_error(drive->bs, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
2007 error_setg(errp, "fdc doesn't support drive option werror");
2008 return;
2009 }
2010 if (bdrv_get_on_error(drive->bs, 1) != BLOCKDEV_ON_ERROR_REPORT) {
2011 error_setg(errp, "fdc doesn't support drive option rerror");
2012 return;
2013 }
2014 }
2015
2016 fd_init(drive);
2017 fdctrl_change_cb(drive, 0);
2018 if (drive->bs) {
2019 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
2020 }
2021 }
2022 }
2023
2024 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2025 {
2026 DeviceState *dev;
2027 ISADevice *isadev;
2028
2029 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2030 if (!isadev) {
2031 return NULL;
2032 }
2033 dev = DEVICE(isadev);
2034
2035 if (fds[0]) {
2036 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
2037 }
2038 if (fds[1]) {
2039 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
2040 }
2041 qdev_init_nofail(dev);
2042
2043 return isadev;
2044 }
2045
2046 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2047 hwaddr mmio_base, DriveInfo **fds)
2048 {
2049 FDCtrl *fdctrl;
2050 DeviceState *dev;
2051 SysBusDevice *sbd;
2052 FDCtrlSysBus *sys;
2053
2054 dev = qdev_create(NULL, "sysbus-fdc");
2055 sys = SYSBUS_FDC(dev);
2056 fdctrl = &sys->state;
2057 fdctrl->dma_chann = dma_chann; /* FIXME */
2058 if (fds[0]) {
2059 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
2060 }
2061 if (fds[1]) {
2062 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
2063 }
2064 qdev_init_nofail(dev);
2065 sbd = SYS_BUS_DEVICE(dev);
2066 sysbus_connect_irq(sbd, 0, irq);
2067 sysbus_mmio_map(sbd, 0, mmio_base);
2068 }
2069
2070 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2071 DriveInfo **fds, qemu_irq *fdc_tc)
2072 {
2073 DeviceState *dev;
2074 FDCtrlSysBus *sys;
2075
2076 dev = qdev_create(NULL, "SUNW,fdtwo");
2077 if (fds[0]) {
2078 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
2079 }
2080 qdev_init_nofail(dev);
2081 sys = SYSBUS_FDC(dev);
2082 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2083 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2084 *fdc_tc = qdev_get_gpio_in(dev, 0);
2085 }
2086
2087 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
2088 {
2089 int i, j;
2090 static int command_tables_inited = 0;
2091
2092 /* Fill 'command_to_handler' lookup table */
2093 if (!command_tables_inited) {
2094 command_tables_inited = 1;
2095 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2096 for (j = 0; j < sizeof(command_to_handler); j++) {
2097 if ((j & handlers[i].mask) == handlers[i].value) {
2098 command_to_handler[j] = i;
2099 }
2100 }
2101 }
2102 }
2103
2104 FLOPPY_DPRINTF("init controller\n");
2105 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2106 fdctrl->fifo_size = 512;
2107 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2108 fdctrl_result_timer, fdctrl);
2109
2110 fdctrl->version = 0x90; /* Intel 82078 controller */
2111 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2112 fdctrl->num_floppies = MAX_FD;
2113
2114 if (fdctrl->dma_chann != -1) {
2115 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
2116 }
2117 fdctrl_connect_drives(fdctrl, errp);
2118 }
2119
2120 static const MemoryRegionPortio fdc_portio_list[] = {
2121 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2122 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2123 PORTIO_END_OF_LIST(),
2124 };
2125
2126 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2127 {
2128 ISADevice *isadev = ISA_DEVICE(dev);
2129 FDCtrlISABus *isa = ISA_FDC(dev);
2130 FDCtrl *fdctrl = &isa->state;
2131 Error *err = NULL;
2132
2133 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2134 "fdc");
2135
2136 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2137 fdctrl->dma_chann = isa->dma;
2138
2139 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2140 fdctrl_realize_common(fdctrl, &err);
2141 if (err != NULL) {
2142 error_propagate(errp, err);
2143 return;
2144 }
2145
2146 add_boot_device_path(isa->bootindexA, dev, "/floppy@0");
2147 add_boot_device_path(isa->bootindexB, dev, "/floppy@1");
2148 }
2149
2150 static void sysbus_fdc_initfn(Object *obj)
2151 {
2152 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2153 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2154 FDCtrl *fdctrl = &sys->state;
2155
2156 fdctrl->dma_chann = -1;
2157
2158 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2159 "fdc", 0x08);
2160 sysbus_init_mmio(sbd, &fdctrl->iomem);
2161 }
2162
2163 static void sun4m_fdc_initfn(Object *obj)
2164 {
2165 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2166 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2167 FDCtrl *fdctrl = &sys->state;
2168
2169 fdctrl->sun4m = 1;
2170
2171 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2172 fdctrl, "fdctrl", 0x08);
2173 sysbus_init_mmio(sbd, &fdctrl->iomem);
2174 }
2175
2176 static void sysbus_fdc_common_initfn(Object *obj)
2177 {
2178 DeviceState *dev = DEVICE(obj);
2179 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2180 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2181 FDCtrl *fdctrl = &sys->state;
2182
2183 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2184
2185 sysbus_init_irq(sbd, &fdctrl->irq);
2186 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2187 }
2188
2189 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2190 {
2191 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2192 FDCtrl *fdctrl = &sys->state;
2193
2194 fdctrl_realize_common(fdctrl, errp);
2195 }
2196
2197 FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2198 {
2199 FDCtrlISABus *isa = ISA_FDC(fdc);
2200
2201 return isa->state.drives[i].drive;
2202 }
2203
2204 static const VMStateDescription vmstate_isa_fdc ={
2205 .name = "fdc",
2206 .version_id = 2,
2207 .minimum_version_id = 2,
2208 .fields = (VMStateField[]) {
2209 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2210 VMSTATE_END_OF_LIST()
2211 }
2212 };
2213
2214 static Property isa_fdc_properties[] = {
2215 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2216 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2217 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2218 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2219 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2220 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2221 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2222 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2223 0, true),
2224 DEFINE_PROP_END_OF_LIST(),
2225 };
2226
2227 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2228 {
2229 DeviceClass *dc = DEVICE_CLASS(klass);
2230
2231 dc->realize = isabus_fdc_realize;
2232 dc->fw_name = "fdc";
2233 dc->reset = fdctrl_external_reset_isa;
2234 dc->vmsd = &vmstate_isa_fdc;
2235 dc->props = isa_fdc_properties;
2236 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2237 }
2238
2239 static const TypeInfo isa_fdc_info = {
2240 .name = TYPE_ISA_FDC,
2241 .parent = TYPE_ISA_DEVICE,
2242 .instance_size = sizeof(FDCtrlISABus),
2243 .class_init = isabus_fdc_class_init,
2244 };
2245
2246 static const VMStateDescription vmstate_sysbus_fdc ={
2247 .name = "fdc",
2248 .version_id = 2,
2249 .minimum_version_id = 2,
2250 .fields = (VMStateField[]) {
2251 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2252 VMSTATE_END_OF_LIST()
2253 }
2254 };
2255
2256 static Property sysbus_fdc_properties[] = {
2257 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2258 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2259 DEFINE_PROP_END_OF_LIST(),
2260 };
2261
2262 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2263 {
2264 DeviceClass *dc = DEVICE_CLASS(klass);
2265
2266 dc->props = sysbus_fdc_properties;
2267 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2268 }
2269
2270 static const TypeInfo sysbus_fdc_info = {
2271 .name = "sysbus-fdc",
2272 .parent = TYPE_SYSBUS_FDC,
2273 .instance_init = sysbus_fdc_initfn,
2274 .class_init = sysbus_fdc_class_init,
2275 };
2276
2277 static Property sun4m_fdc_properties[] = {
2278 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2279 DEFINE_PROP_END_OF_LIST(),
2280 };
2281
2282 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2283 {
2284 DeviceClass *dc = DEVICE_CLASS(klass);
2285
2286 dc->props = sun4m_fdc_properties;
2287 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2288 }
2289
2290 static const TypeInfo sun4m_fdc_info = {
2291 .name = "SUNW,fdtwo",
2292 .parent = TYPE_SYSBUS_FDC,
2293 .instance_init = sun4m_fdc_initfn,
2294 .class_init = sun4m_fdc_class_init,
2295 };
2296
2297 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2298 {
2299 DeviceClass *dc = DEVICE_CLASS(klass);
2300
2301 dc->realize = sysbus_fdc_common_realize;
2302 dc->reset = fdctrl_external_reset_sysbus;
2303 dc->vmsd = &vmstate_sysbus_fdc;
2304 }
2305
2306 static const TypeInfo sysbus_fdc_type_info = {
2307 .name = TYPE_SYSBUS_FDC,
2308 .parent = TYPE_SYS_BUS_DEVICE,
2309 .instance_size = sizeof(FDCtrlSysBus),
2310 .instance_init = sysbus_fdc_common_initfn,
2311 .abstract = true,
2312 .class_init = sysbus_fdc_common_class_init,
2313 };
2314
2315 static void fdc_register_types(void)
2316 {
2317 type_register_static(&isa_fdc_info);
2318 type_register_static(&sysbus_fdc_type_info);
2319 type_register_static(&sysbus_fdc_info);
2320 type_register_static(&sun4m_fdc_info);
2321 }
2322
2323 type_init(fdc_register_types)
CRIS target port of Qemu