target-arm/psci.c

   1 /*
   2  * Copyright (C) 2014 - Linaro
   3  * Author: Rob Herring <rob.herring@linaro.org>
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation; either version 2 of the License, or
   8  *  (at your option) any later version.
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include "qemu/osdep.h"
  19 #include <cpu.h>
  20 #include <exec/helper-proto.h>
  21 #include <kvm-consts.h>
  22 #include <sysemu/sysemu.h>
  23 #include "internals.h"
  24 #include "arm-powerctl.h"
  25
  26 bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
  27 {
  28     /* Return true if the r0/x0 value indicates a PSCI call and
  29      * the exception type matches the configured PSCI conduit. This is
  30      * called before the SMC/HVC instruction is executed, to decide whether
  31      * we should treat it as a PSCI call or with the architecturally
  32      * defined behaviour for an SMC or HVC (which might be UNDEF or trap
  33      * to EL2 or to EL3).
  34      */
  35     CPUARMState *env = &cpu->env;
  36     uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
  37
  38     switch (excp_type) {
  39     case EXCP_HVC:
  40         if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) {
  41             return false;
  42         }
  43         break;
  44     case EXCP_SMC:
  45         if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
  46             return false;
  47         }
  48         break;
  49     default:
  50         return false;
  51     }
  52
  53     switch (param) {
  54     case QEMU_PSCI_0_2_FN_PSCI_VERSION:
  55     case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
  56     case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
  57     case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
  58     case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
  59     case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
  60     case QEMU_PSCI_0_1_FN_CPU_ON:
  61     case QEMU_PSCI_0_2_FN_CPU_ON:
  62     case QEMU_PSCI_0_2_FN64_CPU_ON:
  63     case QEMU_PSCI_0_1_FN_CPU_OFF:
  64     case QEMU_PSCI_0_2_FN_CPU_OFF:
  65     case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
  66     case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
  67     case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
  68     case QEMU_PSCI_0_1_FN_MIGRATE:
  69     case QEMU_PSCI_0_2_FN_MIGRATE:
  70         return true;
  71     default:
  72         return false;
  73     }
  74 }
  75
  76 void arm_handle_psci_call(ARMCPU *cpu)
  77 {
  78     /*
  79      * This function partially implements the logic for dispatching Power State
  80      * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b),
  81      * to the extent required for bringing up and taking down secondary cores,
  82      * and for handling reset and poweroff requests.
  83      * Additional information about the calling convention used is available in
  84      * the document 'SMC Calling Convention' (ARM DEN 0028)
  85      */
  86     CPUARMState *env = &cpu->env;
  87     uint64_t param[4];
  88     uint64_t context_id, mpidr;
  89     target_ulong entry;
  90     int32_t ret = 0;
  91     int i;
  92
  93     for (i = 0; i < 4; i++) {
  94         /*
  95          * All PSCI functions take explicit 32-bit or native int sized
  96          * arguments so we can simply zero-extend all arguments regardless
  97          * of which exact function we are about to call.
  98          */
  99         param[i] = is_a64(env) ? env->xregs[i] : env->regs[i];
 100     }
 101
 102     if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) {
 103         ret = QEMU_PSCI_RET_INVALID_PARAMS;
 104         goto err;
 105     }
 106
 107     switch (param[0]) {
 108         CPUState *target_cpu_state;
 109         ARMCPU *target_cpu;
 110
 111     case QEMU_PSCI_0_2_FN_PSCI_VERSION:
 112         ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
 113         break;
 114     case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
 115         ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
 116         break;
 117     case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
 118     case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
 119         mpidr = param[1];
 120
 121         switch (param[2]) {
 122         case 0:
 123             target_cpu_state = arm_get_cpu_by_id(mpidr);
 124             if (!target_cpu_state) {
 125                 ret = QEMU_PSCI_RET_INVALID_PARAMS;
 126                 break;
 127             }
 128             target_cpu = ARM_CPU(target_cpu_state);
 129             ret = target_cpu->powered_off ? 1 : 0;
 130             break;
 131         default:
 132             /* Everything above affinity level 0 is always on. */
 133             ret = 0;
 134         }
 135         break;
 136     case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
 137         qemu_system_reset_request();
 138         /* QEMU reset and shutdown are async requests, but PSCI
 139          * mandates that we never return from the reset/shutdown
 140          * call, so power the CPU off now so it doesn't execute
 141          * anything further.
 142          */
 143         goto cpu_off;
 144     case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
 145         qemu_system_shutdown_request();
 146         goto cpu_off;
 147     case QEMU_PSCI_0_1_FN_CPU_ON:
 148     case QEMU_PSCI_0_2_FN_CPU_ON:
 149     case QEMU_PSCI_0_2_FN64_CPU_ON:
 150         mpidr = param[1];
 151         entry = param[2];
 152         context_id = param[3];
 153         /*
 154          * The PSCI spec mandates that newly brought up CPUs enter the
 155          * exception level of the caller in the same execution mode as
 156          * the caller, with context_id in x0/r0, respectively.
 157          */
 158         ret = arm_set_cpu_on(mpidr, entry, context_id, arm_current_el(env),
 159                              is_a64(env));
 160         break;
 161     case QEMU_PSCI_0_1_FN_CPU_OFF:
 162     case QEMU_PSCI_0_2_FN_CPU_OFF:
 163         goto cpu_off;
 164     case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
 165     case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
 166     case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
 167         /* Affinity levels are not supported in QEMU */
 168         if (param[1] & 0xfffe0000) {
 169             ret = QEMU_PSCI_RET_INVALID_PARAMS;
 170             break;
 171         }
 172         /* Powerdown is not supported, we always go into WFI */
 173         if (is_a64(env)) {
 174             env->xregs[0] = 0;
 175         } else {
 176             env->regs[0] = 0;
 177         }
 178         helper_wfi(env);
 179         break;
 180     case QEMU_PSCI_0_1_FN_MIGRATE:
 181     case QEMU_PSCI_0_2_FN_MIGRATE:
 182         ret = QEMU_PSCI_RET_NOT_SUPPORTED;
 183         break;
 184     default:
 185         g_assert_not_reached();
 186     }
 187
 188 err:
 189     if (is_a64(env)) {
 190         env->xregs[0] = ret;
 191     } else {
 192         env->regs[0] = ret;
 193     }
 194     return;
 195
 196 cpu_off:
 197     ret = arm_set_cpu_off(cpu->mp_affinity);
 198     /* notreached */
 199     /* sanity check in case something failed */
 200     assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
 201 }