4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 #ifndef QEMU_PPC_CPU_QOM_H
21 #define QEMU_PPC_CPU_QOM_H
26 #define TYPE_POWERPC_CPU "powerpc64-cpu"
27 #elif defined(TARGET_PPCEMB)
28 #define TYPE_POWERPC_CPU "embedded-powerpc-cpu"
30 #define TYPE_POWERPC_CPU "powerpc-cpu"
33 #define POWERPC_CPU_CLASS(klass) \
34 OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
35 #define POWERPC_CPU(obj) \
36 OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
37 #define POWERPC_CPU_GET_CLASS(obj) \
38 OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
40 typedef struct PowerPCCPU PowerPCCPU
;
41 typedef struct CPUPPCState CPUPPCState
;
42 typedef struct ppc_tb_t ppc_tb_t
;
43 typedef struct ppc_dcr_t ppc_dcr_t
;
45 /*****************************************************************************/
47 typedef enum powerpc_mmu_t powerpc_mmu_t
;
49 POWERPC_MMU_UNKNOWN
= 0x00000000,
50 /* Standard 32 bits PowerPC MMU */
51 POWERPC_MMU_32B
= 0x00000001,
52 /* PowerPC 6xx MMU with software TLB */
53 POWERPC_MMU_SOFT_6xx
= 0x00000002,
54 /* PowerPC 74xx MMU with software TLB */
55 POWERPC_MMU_SOFT_74xx
= 0x00000003,
56 /* PowerPC 4xx MMU with software TLB */
57 POWERPC_MMU_SOFT_4xx
= 0x00000004,
58 /* PowerPC 4xx MMU with software TLB and zones protections */
59 POWERPC_MMU_SOFT_4xx_Z
= 0x00000005,
60 /* PowerPC MMU in real mode only */
61 POWERPC_MMU_REAL
= 0x00000006,
62 /* Freescale MPC8xx MMU model */
63 POWERPC_MMU_MPC8xx
= 0x00000007,
65 POWERPC_MMU_BOOKE
= 0x00000008,
66 /* BookE 2.06 MMU model */
67 POWERPC_MMU_BOOKE206
= 0x00000009,
68 /* PowerPC 601 MMU model (specific BATs format) */
69 POWERPC_MMU_601
= 0x0000000A,
70 #define POWERPC_MMU_64 0x00010000
71 #define POWERPC_MMU_1TSEG 0x00020000
72 #define POWERPC_MMU_AMR 0x00040000
73 /* 64 bits PowerPC MMU */
74 POWERPC_MMU_64B
= POWERPC_MMU_64
| 0x00000001,
75 /* Architecture 2.03 and later (has LPCR) */
76 POWERPC_MMU_2_03
= POWERPC_MMU_64
| 0x00000002,
77 /* Architecture 2.06 variant */
78 POWERPC_MMU_2_06
= POWERPC_MMU_64
| POWERPC_MMU_1TSEG
79 | POWERPC_MMU_AMR
| 0x00000003,
80 /* Architecture 2.06 "degraded" (no 1T segments) */
81 POWERPC_MMU_2_06a
= POWERPC_MMU_64
| POWERPC_MMU_AMR
83 /* Architecture 2.07 variant */
84 POWERPC_MMU_2_07
= POWERPC_MMU_64
| POWERPC_MMU_1TSEG
85 | POWERPC_MMU_AMR
| 0x00000004,
86 /* Architecture 2.07 "degraded" (no 1T segments) */
87 POWERPC_MMU_2_07a
= POWERPC_MMU_64
| POWERPC_MMU_AMR
91 /*****************************************************************************/
93 typedef enum powerpc_excp_t powerpc_excp_t
;
95 POWERPC_EXCP_UNKNOWN
= 0,
96 /* Standard PowerPC exception model */
98 /* PowerPC 40x exception model */
100 /* PowerPC 601 exception model */
102 /* PowerPC 602 exception model */
104 /* PowerPC 603 exception model */
106 /* PowerPC 603e exception model */
108 /* PowerPC G2 exception model */
110 /* PowerPC 604 exception model */
112 /* PowerPC 7x0 exception model */
114 /* PowerPC 7x5 exception model */
116 /* PowerPC 74xx exception model */
118 /* BookE exception model */
120 /* PowerPC 970 exception model */
122 /* POWER7 exception model */
124 /* POWER8 exception model */
128 /*****************************************************************************/
129 /* PM instructions */
137 /*****************************************************************************/
138 /* Input pins model */
139 typedef enum powerpc_input_t powerpc_input_t
;
140 enum powerpc_input_t
{
141 PPC_FLAGS_INPUT_UNKNOWN
= 0,
142 /* PowerPC 6xx bus */
145 PPC_FLAGS_INPUT_BookE
,
146 /* PowerPC 405 bus */
148 /* PowerPC 970 bus */
150 /* PowerPC POWER7 bus */
151 PPC_FLAGS_INPUT_POWER7
,
152 /* PowerPC 401 bus */
154 /* Freescale RCPU bus */
155 PPC_FLAGS_INPUT_RCPU
,
158 struct ppc_segment_page_sizes
;
162 * @parent_realize: The parent class' realize handler.
163 * @parent_reset: The parent class' reset handler.
165 * A PowerPC CPU model.
167 typedef struct PowerPCCPUClass
{
169 CPUClass parent_class
;
172 DeviceRealize parent_realize
;
173 void (*parent_reset
)(CPUState
*cpu
);
176 bool (*pvr_match
)(struct PowerPCCPUClass
*pcc
, uint32_t pvr
);
177 uint64_t pcr_mask
; /* Available bits in PCR register */
178 uint64_t pcr_supported
; /* Bits for supported PowerISA versions */
180 uint64_t insns_flags
;
181 uint64_t insns_flags2
;
183 powerpc_mmu_t mmu_model
;
184 powerpc_excp_t excp_model
;
185 powerpc_input_t bus_model
;
188 uint32_t l1_dcache_size
, l1_icache_size
;
189 const struct ppc_segment_page_sizes
*sps
;
190 void (*init_proc
)(CPUPPCState
*env
);
191 int (*check_pow
)(CPUPPCState
*env
);
192 int (*handle_mmu_fault
)(PowerPCCPU
*cpu
, vaddr eaddr
, int rwx
, int mmu_idx
);
193 bool (*interrupts_big_endian
)(PowerPCCPU
*cpu
);
196 #ifndef CONFIG_USER_ONLY
197 typedef struct PPCTimebase
{
198 uint64_t guest_timebase
;
199 int64_t time_of_the_day_ns
;
202 extern const struct VMStateDescription vmstate_ppc_timebase
;
204 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \
205 .name = (stringify(_field)), \
206 .version_id = (_version), \
207 .size = sizeof(PPCTimebase), \
208 .vmsd = &vmstate_ppc_timebase, \
209 .flags = VMS_STRUCT, \
210 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \