2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "hw/sysbus.h"
12 #include "hw/ssi/ssi.h"
13 #include "hw/arm/arm.h"
14 #include "hw/devices.h"
15 #include "qemu/timer.h"
16 #include "hw/i2c/i2c.h"
18 #include "hw/boards.h"
19 #include "exec/address-spaces.h"
20 #include "sysemu/sysemu.h"
30 #define BP_OLED_I2C 0x01
31 #define BP_OLED_SSI 0x02
32 #define BP_GAMEPAD 0x04
34 #define NUM_IRQ_LINES 64
36 typedef const struct {
46 } stellaris_board_info
;
48 /* General purpose timer module. */
50 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
51 #define STELLARIS_GPTM(obj) \
52 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
54 typedef struct gptm_state
{
55 SysBusDevice parent_obj
;
66 uint32_t match_prescale
[2];
69 struct gptm_state
*opaque
[2];
71 /* The timers have an alternate output used to trigger the ADC. */
76 static void gptm_update_irq(gptm_state
*s
)
79 level
= (s
->state
& s
->mask
) != 0;
80 qemu_set_irq(s
->irq
, level
);
83 static void gptm_stop(gptm_state
*s
, int n
)
85 timer_del(s
->timer
[n
]);
88 static void gptm_reload(gptm_state
*s
, int n
, int reset
)
92 tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
97 /* 32-bit CountDown. */
99 count
= s
->load
[0] | (s
->load
[1] << 16);
100 tick
+= (int64_t)count
* system_clock_scale
;
101 } else if (s
->config
== 1) {
102 /* 32-bit RTC. 1Hz tick. */
103 tick
+= get_ticks_per_sec();
104 } else if (s
->mode
[n
] == 0xa) {
105 /* PWM mode. Not implemented. */
107 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
110 timer_mod(s
->timer
[n
], tick
);
113 static void gptm_tick(void *opaque
)
115 gptm_state
**p
= (gptm_state
**)opaque
;
121 if (s
->config
== 0) {
123 if ((s
->control
& 0x20)) {
124 /* Output trigger. */
125 qemu_irq_pulse(s
->trigger
);
127 if (s
->mode
[0] & 1) {
132 gptm_reload(s
, 0, 0);
134 } else if (s
->config
== 1) {
138 match
= s
->match
[0] | (s
->match
[1] << 16);
144 gptm_reload(s
, 0, 0);
145 } else if (s
->mode
[n
] == 0xa) {
146 /* PWM mode. Not implemented. */
148 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
153 static uint64_t gptm_read(void *opaque
, hwaddr offset
,
156 gptm_state
*s
= (gptm_state
*)opaque
;
161 case 0x04: /* TAMR */
163 case 0x08: /* TBMR */
172 return s
->state
& s
->mask
;
175 case 0x28: /* TAILR */
176 return s
->load
[0] | ((s
->config
< 4) ? (s
->load
[1] << 16) : 0);
177 case 0x2c: /* TBILR */
179 case 0x30: /* TAMARCHR */
180 return s
->match
[0] | ((s
->config
< 4) ? (s
->match
[1] << 16) : 0);
181 case 0x34: /* TBMATCHR */
183 case 0x38: /* TAPR */
184 return s
->prescale
[0];
185 case 0x3c: /* TBPR */
186 return s
->prescale
[1];
187 case 0x40: /* TAPMR */
188 return s
->match_prescale
[0];
189 case 0x44: /* TBPMR */
190 return s
->match_prescale
[1];
192 if (s
->config
== 1) {
195 qemu_log_mask(LOG_UNIMP
,
196 "GPTM: read of TAR but timer read not supported");
199 qemu_log_mask(LOG_UNIMP
,
200 "GPTM: read of TBR but timer read not supported");
203 qemu_log_mask(LOG_GUEST_ERROR
,
204 "GPTM: read at bad offset 0x%x\n", (int)offset
);
209 static void gptm_write(void *opaque
, hwaddr offset
,
210 uint64_t value
, unsigned size
)
212 gptm_state
*s
= (gptm_state
*)opaque
;
215 /* The timers should be disabled before changing the configuration.
216 We take advantage of this and defer everything until the timer
222 case 0x04: /* TAMR */
225 case 0x08: /* TBMR */
231 /* TODO: Implement pause. */
232 if ((oldval
^ value
) & 1) {
234 gptm_reload(s
, 0, 1);
239 if (((oldval
^ value
) & 0x100) && s
->config
>= 4) {
241 gptm_reload(s
, 1, 1);
248 s
->mask
= value
& 0x77;
254 case 0x28: /* TAILR */
255 s
->load
[0] = value
& 0xffff;
257 s
->load
[1] = value
>> 16;
260 case 0x2c: /* TBILR */
261 s
->load
[1] = value
& 0xffff;
263 case 0x30: /* TAMARCHR */
264 s
->match
[0] = value
& 0xffff;
266 s
->match
[1] = value
>> 16;
269 case 0x34: /* TBMATCHR */
270 s
->match
[1] = value
>> 16;
272 case 0x38: /* TAPR */
273 s
->prescale
[0] = value
;
275 case 0x3c: /* TBPR */
276 s
->prescale
[1] = value
;
278 case 0x40: /* TAPMR */
279 s
->match_prescale
[0] = value
;
281 case 0x44: /* TBPMR */
282 s
->match_prescale
[0] = value
;
285 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset
);
290 static const MemoryRegionOps gptm_ops
= {
293 .endianness
= DEVICE_NATIVE_ENDIAN
,
296 static const VMStateDescription vmstate_stellaris_gptm
= {
297 .name
= "stellaris_gptm",
299 .minimum_version_id
= 1,
300 .fields
= (VMStateField
[]) {
301 VMSTATE_UINT32(config
, gptm_state
),
302 VMSTATE_UINT32_ARRAY(mode
, gptm_state
, 2),
303 VMSTATE_UINT32(control
, gptm_state
),
304 VMSTATE_UINT32(state
, gptm_state
),
305 VMSTATE_UINT32(mask
, gptm_state
),
307 VMSTATE_UINT32_ARRAY(load
, gptm_state
, 2),
308 VMSTATE_UINT32_ARRAY(match
, gptm_state
, 2),
309 VMSTATE_UINT32_ARRAY(prescale
, gptm_state
, 2),
310 VMSTATE_UINT32_ARRAY(match_prescale
, gptm_state
, 2),
311 VMSTATE_UINT32(rtc
, gptm_state
),
312 VMSTATE_INT64_ARRAY(tick
, gptm_state
, 2),
313 VMSTATE_TIMER_PTR_ARRAY(timer
, gptm_state
, 2),
314 VMSTATE_END_OF_LIST()
318 static int stellaris_gptm_init(SysBusDevice
*sbd
)
320 DeviceState
*dev
= DEVICE(sbd
);
321 gptm_state
*s
= STELLARIS_GPTM(dev
);
323 sysbus_init_irq(sbd
, &s
->irq
);
324 qdev_init_gpio_out(dev
, &s
->trigger
, 1);
326 memory_region_init_io(&s
->iomem
, OBJECT(s
), &gptm_ops
, s
,
328 sysbus_init_mmio(sbd
, &s
->iomem
);
330 s
->opaque
[0] = s
->opaque
[1] = s
;
331 s
->timer
[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[0]);
332 s
->timer
[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[1]);
333 vmstate_register(dev
, -1, &vmstate_stellaris_gptm
, s
);
338 /* System controller. */
357 stellaris_board_info
*board
;
360 static void ssys_update(ssys_state
*s
)
362 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
365 static uint32_t pllcfg_sandstorm
[16] = {
367 0x1ae0, /* 1.8432 Mhz */
369 0xd573, /* 2.4576 Mhz */
370 0x37a6, /* 3.57954 Mhz */
371 0x1ae2, /* 3.6864 Mhz */
373 0x98bc, /* 4.906 Mhz */
374 0x935b, /* 4.9152 Mhz */
376 0x4dee, /* 5.12 Mhz */
378 0x75db, /* 6.144 Mhz */
379 0x1ae6, /* 7.3728 Mhz */
381 0x585b /* 8.192 Mhz */
384 static uint32_t pllcfg_fury
[16] = {
386 0x1b20, /* 1.8432 Mhz */
388 0xf42b, /* 2.4576 Mhz */
389 0x37e3, /* 3.57954 Mhz */
390 0x1b21, /* 3.6864 Mhz */
392 0x98ee, /* 4.906 Mhz */
393 0xd5b4, /* 4.9152 Mhz */
395 0x4e27, /* 5.12 Mhz */
397 0xec1c, /* 6.144 Mhz */
398 0x1b23, /* 7.3728 Mhz */
400 0xb11c /* 8.192 Mhz */
403 #define DID0_VER_MASK 0x70000000
404 #define DID0_VER_0 0x00000000
405 #define DID0_VER_1 0x10000000
407 #define DID0_CLASS_MASK 0x00FF0000
408 #define DID0_CLASS_SANDSTORM 0x00000000
409 #define DID0_CLASS_FURY 0x00010000
411 static int ssys_board_class(const ssys_state
*s
)
413 uint32_t did0
= s
->board
->did0
;
414 switch (did0
& DID0_VER_MASK
) {
416 return DID0_CLASS_SANDSTORM
;
418 switch (did0
& DID0_CLASS_MASK
) {
419 case DID0_CLASS_SANDSTORM
:
420 case DID0_CLASS_FURY
:
421 return did0
& DID0_CLASS_MASK
;
423 /* for unknown classes, fall through */
425 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0
);
429 static uint64_t ssys_read(void *opaque
, hwaddr offset
,
432 ssys_state
*s
= (ssys_state
*)opaque
;
435 case 0x000: /* DID0 */
436 return s
->board
->did0
;
437 case 0x004: /* DID1 */
438 return s
->board
->did1
;
439 case 0x008: /* DC0 */
440 return s
->board
->dc0
;
441 case 0x010: /* DC1 */
442 return s
->board
->dc1
;
443 case 0x014: /* DC2 */
444 return s
->board
->dc2
;
445 case 0x018: /* DC3 */
446 return s
->board
->dc3
;
447 case 0x01c: /* DC4 */
448 return s
->board
->dc4
;
449 case 0x030: /* PBORCTL */
451 case 0x034: /* LDOPCTL */
453 case 0x040: /* SRCR0 */
455 case 0x044: /* SRCR1 */
457 case 0x048: /* SRCR2 */
459 case 0x050: /* RIS */
460 return s
->int_status
;
461 case 0x054: /* IMC */
463 case 0x058: /* MISC */
464 return s
->int_status
& s
->int_mask
;
465 case 0x05c: /* RESC */
467 case 0x060: /* RCC */
469 case 0x064: /* PLLCFG */
472 xtal
= (s
->rcc
>> 6) & 0xf;
473 switch (ssys_board_class(s
)) {
474 case DID0_CLASS_FURY
:
475 return pllcfg_fury
[xtal
];
476 case DID0_CLASS_SANDSTORM
:
477 return pllcfg_sandstorm
[xtal
];
479 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
483 case 0x070: /* RCC2 */
485 case 0x100: /* RCGC0 */
487 case 0x104: /* RCGC1 */
489 case 0x108: /* RCGC2 */
491 case 0x110: /* SCGC0 */
493 case 0x114: /* SCGC1 */
495 case 0x118: /* SCGC2 */
497 case 0x120: /* DCGC0 */
499 case 0x124: /* DCGC1 */
501 case 0x128: /* DCGC2 */
503 case 0x150: /* CLKVCLR */
505 case 0x160: /* LDOARST */
507 case 0x1e0: /* USER0 */
509 case 0x1e4: /* USER1 */
512 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset
);
517 static bool ssys_use_rcc2(ssys_state
*s
)
519 return (s
->rcc2
>> 31) & 0x1;
523 * Caculate the sys. clock period in ms.
525 static void ssys_calculate_system_clock(ssys_state
*s
)
527 if (ssys_use_rcc2(s
)) {
528 system_clock_scale
= 5 * (((s
->rcc2
>> 23) & 0x3f) + 1);
530 system_clock_scale
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
534 static void ssys_write(void *opaque
, hwaddr offset
,
535 uint64_t value
, unsigned size
)
537 ssys_state
*s
= (ssys_state
*)opaque
;
540 case 0x030: /* PBORCTL */
541 s
->pborctl
= value
& 0xffff;
543 case 0x034: /* LDOPCTL */
544 s
->ldopctl
= value
& 0x1f;
546 case 0x040: /* SRCR0 */
547 case 0x044: /* SRCR1 */
548 case 0x048: /* SRCR2 */
549 fprintf(stderr
, "Peripheral reset not implemented\n");
551 case 0x054: /* IMC */
552 s
->int_mask
= value
& 0x7f;
554 case 0x058: /* MISC */
555 s
->int_status
&= ~value
;
557 case 0x05c: /* RESC */
558 s
->resc
= value
& 0x3f;
560 case 0x060: /* RCC */
561 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
563 s
->int_status
|= (1 << 6);
566 ssys_calculate_system_clock(s
);
568 case 0x070: /* RCC2 */
569 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
573 if ((s
->rcc2
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
575 s
->int_status
|= (1 << 6);
578 ssys_calculate_system_clock(s
);
580 case 0x100: /* RCGC0 */
583 case 0x104: /* RCGC1 */
586 case 0x108: /* RCGC2 */
589 case 0x110: /* SCGC0 */
592 case 0x114: /* SCGC1 */
595 case 0x118: /* SCGC2 */
598 case 0x120: /* DCGC0 */
601 case 0x124: /* DCGC1 */
604 case 0x128: /* DCGC2 */
607 case 0x150: /* CLKVCLR */
610 case 0x160: /* LDOARST */
614 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset
);
619 static const MemoryRegionOps ssys_ops
= {
622 .endianness
= DEVICE_NATIVE_ENDIAN
,
625 static void ssys_reset(void *opaque
)
627 ssys_state
*s
= (ssys_state
*)opaque
;
632 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
635 s
->rcc2
= 0x07802810;
640 ssys_calculate_system_clock(s
);
643 static int stellaris_sys_post_load(void *opaque
, int version_id
)
645 ssys_state
*s
= opaque
;
647 ssys_calculate_system_clock(s
);
652 static const VMStateDescription vmstate_stellaris_sys
= {
653 .name
= "stellaris_sys",
655 .minimum_version_id
= 1,
656 .post_load
= stellaris_sys_post_load
,
657 .fields
= (VMStateField
[]) {
658 VMSTATE_UINT32(pborctl
, ssys_state
),
659 VMSTATE_UINT32(ldopctl
, ssys_state
),
660 VMSTATE_UINT32(int_mask
, ssys_state
),
661 VMSTATE_UINT32(int_status
, ssys_state
),
662 VMSTATE_UINT32(resc
, ssys_state
),
663 VMSTATE_UINT32(rcc
, ssys_state
),
664 VMSTATE_UINT32_V(rcc2
, ssys_state
, 2),
665 VMSTATE_UINT32_ARRAY(rcgc
, ssys_state
, 3),
666 VMSTATE_UINT32_ARRAY(scgc
, ssys_state
, 3),
667 VMSTATE_UINT32_ARRAY(dcgc
, ssys_state
, 3),
668 VMSTATE_UINT32(clkvclr
, ssys_state
),
669 VMSTATE_UINT32(ldoarst
, ssys_state
),
670 VMSTATE_END_OF_LIST()
674 static int stellaris_sys_init(uint32_t base
, qemu_irq irq
,
675 stellaris_board_info
* board
,
680 s
= g_new0(ssys_state
, 1);
683 /* Most devices come preprogrammed with a MAC address in the user data. */
684 s
->user0
= macaddr
[0] | (macaddr
[1] << 8) | (macaddr
[2] << 16);
685 s
->user1
= macaddr
[3] | (macaddr
[4] << 8) | (macaddr
[5] << 16);
687 memory_region_init_io(&s
->iomem
, NULL
, &ssys_ops
, s
, "ssys", 0x00001000);
688 memory_region_add_subregion(get_system_memory(), base
, &s
->iomem
);
690 vmstate_register(NULL
, -1, &vmstate_stellaris_sys
, s
);
695 /* I2C controller. */
697 #define TYPE_STELLARIS_I2C "stellaris-i2c"
698 #define STELLARIS_I2C(obj) \
699 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
702 SysBusDevice parent_obj
;
714 } stellaris_i2c_state
;
716 #define STELLARIS_I2C_MCS_BUSY 0x01
717 #define STELLARIS_I2C_MCS_ERROR 0x02
718 #define STELLARIS_I2C_MCS_ADRACK 0x04
719 #define STELLARIS_I2C_MCS_DATACK 0x08
720 #define STELLARIS_I2C_MCS_ARBLST 0x10
721 #define STELLARIS_I2C_MCS_IDLE 0x20
722 #define STELLARIS_I2C_MCS_BUSBSY 0x40
724 static uint64_t stellaris_i2c_read(void *opaque
, hwaddr offset
,
727 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
733 /* We don't emulate timing, so the controller is never busy. */
734 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
737 case 0x0c: /* MTPR */
739 case 0x10: /* MIMR */
741 case 0x14: /* MRIS */
743 case 0x18: /* MMIS */
744 return s
->mris
& s
->mimr
;
748 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset
);
753 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
757 level
= (s
->mris
& s
->mimr
) != 0;
758 qemu_set_irq(s
->irq
, level
);
761 static void stellaris_i2c_write(void *opaque
, hwaddr offset
,
762 uint64_t value
, unsigned size
)
764 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
768 s
->msa
= value
& 0xff;
771 if ((s
->mcr
& 0x10) == 0) {
772 /* Disabled. Do nothing. */
775 /* Grab the bus if this is starting a transfer. */
776 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
777 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
778 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
780 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
781 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
784 /* If we don't have the bus then indicate an error. */
785 if (!i2c_bus_busy(s
->bus
)
786 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
787 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
790 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
792 /* Transfer a byte. */
793 /* TODO: Handle errors. */
796 s
->mdr
= i2c_recv(s
->bus
) & 0xff;
799 i2c_send(s
->bus
, s
->mdr
);
801 /* Raise an interrupt. */
805 /* Finish transfer. */
806 i2c_end_transfer(s
->bus
);
807 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
811 s
->mdr
= value
& 0xff;
813 case 0x0c: /* MTPR */
814 s
->mtpr
= value
& 0xff;
816 case 0x10: /* MIMR */
819 case 0x1c: /* MICR */
825 "stellaris_i2c_write: Loopback not implemented\n");
828 "stellaris_i2c_write: Slave mode not implemented\n");
829 s
->mcr
= value
& 0x31;
832 hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
835 stellaris_i2c_update(s
);
838 static void stellaris_i2c_reset(stellaris_i2c_state
*s
)
840 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
841 i2c_end_transfer(s
->bus
);
850 stellaris_i2c_update(s
);
853 static const MemoryRegionOps stellaris_i2c_ops
= {
854 .read
= stellaris_i2c_read
,
855 .write
= stellaris_i2c_write
,
856 .endianness
= DEVICE_NATIVE_ENDIAN
,
859 static const VMStateDescription vmstate_stellaris_i2c
= {
860 .name
= "stellaris_i2c",
862 .minimum_version_id
= 1,
863 .fields
= (VMStateField
[]) {
864 VMSTATE_UINT32(msa
, stellaris_i2c_state
),
865 VMSTATE_UINT32(mcs
, stellaris_i2c_state
),
866 VMSTATE_UINT32(mdr
, stellaris_i2c_state
),
867 VMSTATE_UINT32(mtpr
, stellaris_i2c_state
),
868 VMSTATE_UINT32(mimr
, stellaris_i2c_state
),
869 VMSTATE_UINT32(mris
, stellaris_i2c_state
),
870 VMSTATE_UINT32(mcr
, stellaris_i2c_state
),
871 VMSTATE_END_OF_LIST()
875 static int stellaris_i2c_init(SysBusDevice
*sbd
)
877 DeviceState
*dev
= DEVICE(sbd
);
878 stellaris_i2c_state
*s
= STELLARIS_I2C(dev
);
881 sysbus_init_irq(sbd
, &s
->irq
);
882 bus
= i2c_init_bus(dev
, "i2c");
885 memory_region_init_io(&s
->iomem
, OBJECT(s
), &stellaris_i2c_ops
, s
,
887 sysbus_init_mmio(sbd
, &s
->iomem
);
888 /* ??? For now we only implement the master interface. */
889 stellaris_i2c_reset(s
);
890 vmstate_register(dev
, -1, &vmstate_stellaris_i2c
, s
);
894 /* Analogue to Digital Converter. This is only partially implemented,
895 enough for applications that use a combined ADC and timer tick. */
897 #define STELLARIS_ADC_EM_CONTROLLER 0
898 #define STELLARIS_ADC_EM_COMP 1
899 #define STELLARIS_ADC_EM_EXTERNAL 4
900 #define STELLARIS_ADC_EM_TIMER 5
901 #define STELLARIS_ADC_EM_PWM0 6
902 #define STELLARIS_ADC_EM_PWM1 7
903 #define STELLARIS_ADC_EM_PWM2 8
905 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
906 #define STELLARIS_ADC_FIFO_FULL 0x1000
908 #define TYPE_STELLARIS_ADC "stellaris-adc"
909 #define STELLARIS_ADC(obj) \
910 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
912 typedef struct StellarisADCState
{
913 SysBusDevice parent_obj
;
932 } stellaris_adc_state
;
934 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state
*s
, int n
)
938 tail
= s
->fifo
[n
].state
& 0xf;
939 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
942 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
943 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
944 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
945 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
947 return s
->fifo
[n
].data
[tail
];
950 static void stellaris_adc_fifo_write(stellaris_adc_state
*s
, int n
,
955 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
956 FIFO fir each sequencer. */
957 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
958 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
962 s
->fifo
[n
].data
[head
] = value
;
963 head
= (head
+ 1) & 0xf;
964 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
965 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
966 if ((s
->fifo
[n
].state
& 0xf) == head
)
967 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
970 static void stellaris_adc_update(stellaris_adc_state
*s
)
975 for (n
= 0; n
< 4; n
++) {
976 level
= (s
->ris
& s
->im
& (1 << n
)) != 0;
977 qemu_set_irq(s
->irq
[n
], level
);
981 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
983 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
986 for (n
= 0; n
< 4; n
++) {
987 if ((s
->actss
& (1 << n
)) == 0) {
991 if (((s
->emux
>> (n
* 4)) & 0xff) != 5) {
995 /* Some applications use the ADC as a random number source, so introduce
996 some variation into the signal. */
997 s
->noise
= s
->noise
* 314159 + 1;
998 /* ??? actual inputs not implemented. Return an arbitrary value. */
999 stellaris_adc_fifo_write(s
, n
, 0x200 + ((s
->noise
>> 16) & 7));
1001 stellaris_adc_update(s
);
1005 static void stellaris_adc_reset(stellaris_adc_state
*s
)
1009 for (n
= 0; n
< 4; n
++) {
1012 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
1016 static uint64_t stellaris_adc_read(void *opaque
, hwaddr offset
,
1019 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1021 /* TODO: Implement this. */
1022 if (offset
>= 0x40 && offset
< 0xc0) {
1024 n
= (offset
- 0x40) >> 5;
1025 switch (offset
& 0x1f) {
1026 case 0x00: /* SSMUX */
1028 case 0x04: /* SSCTL */
1030 case 0x08: /* SSFIFO */
1031 return stellaris_adc_fifo_read(s
, n
);
1032 case 0x0c: /* SSFSTAT */
1033 return s
->fifo
[n
].state
;
1039 case 0x00: /* ACTSS */
1041 case 0x04: /* RIS */
1045 case 0x0c: /* ISC */
1046 return s
->ris
& s
->im
;
1047 case 0x10: /* OSTAT */
1049 case 0x14: /* EMUX */
1051 case 0x18: /* USTAT */
1053 case 0x20: /* SSPRI */
1055 case 0x30: /* SAC */
1058 hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1064 static void stellaris_adc_write(void *opaque
, hwaddr offset
,
1065 uint64_t value
, unsigned size
)
1067 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1069 /* TODO: Implement this. */
1070 if (offset
>= 0x40 && offset
< 0xc0) {
1072 n
= (offset
- 0x40) >> 5;
1073 switch (offset
& 0x1f) {
1074 case 0x00: /* SSMUX */
1075 s
->ssmux
[n
] = value
& 0x33333333;
1077 case 0x04: /* SSCTL */
1079 hw_error("ADC: Unimplemented sequence %" PRIx64
"\n",
1082 s
->ssctl
[n
] = value
;
1089 case 0x00: /* ACTSS */
1090 s
->actss
= value
& 0xf;
1095 case 0x0c: /* ISC */
1098 case 0x10: /* OSTAT */
1101 case 0x14: /* EMUX */
1104 case 0x18: /* USTAT */
1107 case 0x20: /* SSPRI */
1110 case 0x28: /* PSSI */
1111 hw_error("Not implemented: ADC sample initiate\n");
1113 case 0x30: /* SAC */
1117 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset
);
1119 stellaris_adc_update(s
);
1122 static const MemoryRegionOps stellaris_adc_ops
= {
1123 .read
= stellaris_adc_read
,
1124 .write
= stellaris_adc_write
,
1125 .endianness
= DEVICE_NATIVE_ENDIAN
,
1128 static const VMStateDescription vmstate_stellaris_adc
= {
1129 .name
= "stellaris_adc",
1131 .minimum_version_id
= 1,
1132 .fields
= (VMStateField
[]) {
1133 VMSTATE_UINT32(actss
, stellaris_adc_state
),
1134 VMSTATE_UINT32(ris
, stellaris_adc_state
),
1135 VMSTATE_UINT32(im
, stellaris_adc_state
),
1136 VMSTATE_UINT32(emux
, stellaris_adc_state
),
1137 VMSTATE_UINT32(ostat
, stellaris_adc_state
),
1138 VMSTATE_UINT32(ustat
, stellaris_adc_state
),
1139 VMSTATE_UINT32(sspri
, stellaris_adc_state
),
1140 VMSTATE_UINT32(sac
, stellaris_adc_state
),
1141 VMSTATE_UINT32(fifo
[0].state
, stellaris_adc_state
),
1142 VMSTATE_UINT32_ARRAY(fifo
[0].data
, stellaris_adc_state
, 16),
1143 VMSTATE_UINT32(ssmux
[0], stellaris_adc_state
),
1144 VMSTATE_UINT32(ssctl
[0], stellaris_adc_state
),
1145 VMSTATE_UINT32(fifo
[1].state
, stellaris_adc_state
),
1146 VMSTATE_UINT32_ARRAY(fifo
[1].data
, stellaris_adc_state
, 16),
1147 VMSTATE_UINT32(ssmux
[1], stellaris_adc_state
),
1148 VMSTATE_UINT32(ssctl
[1], stellaris_adc_state
),
1149 VMSTATE_UINT32(fifo
[2].state
, stellaris_adc_state
),
1150 VMSTATE_UINT32_ARRAY(fifo
[2].data
, stellaris_adc_state
, 16),
1151 VMSTATE_UINT32(ssmux
[2], stellaris_adc_state
),
1152 VMSTATE_UINT32(ssctl
[2], stellaris_adc_state
),
1153 VMSTATE_UINT32(fifo
[3].state
, stellaris_adc_state
),
1154 VMSTATE_UINT32_ARRAY(fifo
[3].data
, stellaris_adc_state
, 16),
1155 VMSTATE_UINT32(ssmux
[3], stellaris_adc_state
),
1156 VMSTATE_UINT32(ssctl
[3], stellaris_adc_state
),
1157 VMSTATE_UINT32(noise
, stellaris_adc_state
),
1158 VMSTATE_END_OF_LIST()
1162 static int stellaris_adc_init(SysBusDevice
*sbd
)
1164 DeviceState
*dev
= DEVICE(sbd
);
1165 stellaris_adc_state
*s
= STELLARIS_ADC(dev
);
1168 for (n
= 0; n
< 4; n
++) {
1169 sysbus_init_irq(sbd
, &s
->irq
[n
]);
1172 memory_region_init_io(&s
->iomem
, OBJECT(s
), &stellaris_adc_ops
, s
,
1174 sysbus_init_mmio(sbd
, &s
->iomem
);
1175 stellaris_adc_reset(s
);
1176 qdev_init_gpio_in(dev
, stellaris_adc_trigger
, 1);
1177 vmstate_register(dev
, -1, &vmstate_stellaris_adc
, s
);
1182 void do_sys_reset(void *opaque
, int n
, int level
)
1185 qemu_system_reset_request();
1190 static stellaris_board_info stellaris_boards
[] = {
1194 0x001f001f, /* dc0 */
1204 0x00ff007f, /* dc0 */
1209 BP_OLED_SSI
| BP_GAMEPAD
1213 static void stellaris_init(const char *kernel_filename
, const char *cpu_model
,
1214 stellaris_board_info
*board
)
1216 static const int uart_irq
[] = {5, 6, 33, 34};
1217 static const int timer_irq
[] = {19, 21, 23, 35};
1218 static const uint32_t gpio_addr
[7] =
1219 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1220 0x40024000, 0x40025000, 0x40026000};
1221 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
1223 DeviceState
*gpio_dev
[7], *nvic
;
1224 qemu_irq gpio_in
[7][8];
1225 qemu_irq gpio_out
[7][8];
1234 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1235 MemoryRegion
*flash
= g_new(MemoryRegion
, 1);
1236 MemoryRegion
*system_memory
= get_system_memory();
1238 flash_size
= (((board
->dc0
& 0xffff) + 1) << 1) * 1024;
1239 sram_size
= ((board
->dc0
>> 18) + 1) * 1024;
1241 /* Flash programming is done via the SCU, so pretend it is ROM. */
1242 memory_region_init_ram(flash
, NULL
, "stellaris.flash", flash_size
,
1244 vmstate_register_ram_global(flash
);
1245 memory_region_set_readonly(flash
, true);
1246 memory_region_add_subregion(system_memory
, 0, flash
);
1248 memory_region_init_ram(sram
, NULL
, "stellaris.sram", sram_size
,
1250 vmstate_register_ram_global(sram
);
1251 memory_region_add_subregion(system_memory
, 0x20000000, sram
);
1253 nvic
= armv7m_init(system_memory
, flash_size
, NUM_IRQ_LINES
,
1254 kernel_filename
, cpu_model
);
1256 qdev_connect_gpio_out_named(nvic
, "SYSRESETREQ", 0,
1257 qemu_allocate_irq(&do_sys_reset
, NULL
, 0));
1259 if (board
->dc1
& (1 << 16)) {
1260 dev
= sysbus_create_varargs(TYPE_STELLARIS_ADC
, 0x40038000,
1261 qdev_get_gpio_in(nvic
, 14),
1262 qdev_get_gpio_in(nvic
, 15),
1263 qdev_get_gpio_in(nvic
, 16),
1264 qdev_get_gpio_in(nvic
, 17),
1266 adc
= qdev_get_gpio_in(dev
, 0);
1270 for (i
= 0; i
< 4; i
++) {
1271 if (board
->dc2
& (0x10000 << i
)) {
1272 dev
= sysbus_create_simple(TYPE_STELLARIS_GPTM
,
1273 0x40030000 + i
* 0x1000,
1274 qdev_get_gpio_in(nvic
, timer_irq
[i
]));
1275 /* TODO: This is incorrect, but we get away with it because
1276 the ADC output is only ever pulsed. */
1277 qdev_connect_gpio_out(dev
, 0, adc
);
1281 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic
, 28),
1282 board
, nd_table
[0].macaddr
.a
);
1284 for (i
= 0; i
< 7; i
++) {
1285 if (board
->dc4
& (1 << i
)) {
1286 gpio_dev
[i
] = sysbus_create_simple("pl061_luminary", gpio_addr
[i
],
1287 qdev_get_gpio_in(nvic
,
1289 for (j
= 0; j
< 8; j
++) {
1290 gpio_in
[i
][j
] = qdev_get_gpio_in(gpio_dev
[i
], j
);
1291 gpio_out
[i
][j
] = NULL
;
1296 if (board
->dc2
& (1 << 12)) {
1297 dev
= sysbus_create_simple(TYPE_STELLARIS_I2C
, 0x40020000,
1298 qdev_get_gpio_in(nvic
, 8));
1299 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
1300 if (board
->peripherals
& BP_OLED_I2C
) {
1301 i2c_create_slave(i2c
, "ssd0303", 0x3d);
1305 for (i
= 0; i
< 4; i
++) {
1306 if (board
->dc2
& (1 << i
)) {
1307 sysbus_create_simple("pl011_luminary", 0x4000c000 + i
* 0x1000,
1308 qdev_get_gpio_in(nvic
, uart_irq
[i
]));
1311 if (board
->dc2
& (1 << 4)) {
1312 dev
= sysbus_create_simple("pl022", 0x40008000,
1313 qdev_get_gpio_in(nvic
, 7));
1314 if (board
->peripherals
& BP_OLED_SSI
) {
1317 DeviceState
*ssddev
;
1319 /* Some boards have both an OLED controller and SD card connected to
1320 * the same SSI port, with the SD card chip select connected to a
1321 * GPIO pin. Technically the OLED chip select is connected to the
1322 * SSI Fss pin. We do not bother emulating that as both devices
1323 * should never be selected simultaneously, and our OLED controller
1324 * ignores stray 0xff commands that occur when deselecting the SD
1327 bus
= qdev_get_child_bus(dev
, "ssi");
1329 sddev
= ssi_create_slave(bus
, "ssi-sd");
1330 ssddev
= ssi_create_slave(bus
, "ssd0323");
1331 gpio_out
[GPIO_D
][0] = qemu_irq_split(
1332 qdev_get_gpio_in_named(sddev
, SSI_GPIO_CS
, 0),
1333 qdev_get_gpio_in_named(ssddev
, SSI_GPIO_CS
, 0));
1334 gpio_out
[GPIO_C
][7] = qdev_get_gpio_in(ssddev
, 0);
1336 /* Make sure the select pin is high. */
1337 qemu_irq_raise(gpio_out
[GPIO_D
][0]);
1340 if (board
->dc4
& (1 << 28)) {
1343 qemu_check_nic_model(&nd_table
[0], "stellaris");
1345 enet
= qdev_create(NULL
, "stellaris_enet");
1346 qdev_set_nic_properties(enet
, &nd_table
[0]);
1347 qdev_init_nofail(enet
);
1348 sysbus_mmio_map(SYS_BUS_DEVICE(enet
), 0, 0x40048000);
1349 sysbus_connect_irq(SYS_BUS_DEVICE(enet
), 0, qdev_get_gpio_in(nvic
, 42));
1351 if (board
->peripherals
& BP_GAMEPAD
) {
1352 qemu_irq gpad_irq
[5];
1353 static const int gpad_keycode
[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1355 gpad_irq
[0] = qemu_irq_invert(gpio_in
[GPIO_E
][0]); /* up */
1356 gpad_irq
[1] = qemu_irq_invert(gpio_in
[GPIO_E
][1]); /* down */
1357 gpad_irq
[2] = qemu_irq_invert(gpio_in
[GPIO_E
][2]); /* left */
1358 gpad_irq
[3] = qemu_irq_invert(gpio_in
[GPIO_E
][3]); /* right */
1359 gpad_irq
[4] = qemu_irq_invert(gpio_in
[GPIO_F
][1]); /* select */
1361 stellaris_gamepad_init(5, gpad_irq
, gpad_keycode
);
1363 for (i
= 0; i
< 7; i
++) {
1364 if (board
->dc4
& (1 << i
)) {
1365 for (j
= 0; j
< 8; j
++) {
1366 if (gpio_out
[i
][j
]) {
1367 qdev_connect_gpio_out(gpio_dev
[i
], j
, gpio_out
[i
][j
]);
1374 /* FIXME: Figure out how to generate these from stellaris_boards. */
1375 static void lm3s811evb_init(MachineState
*machine
)
1377 const char *cpu_model
= machine
->cpu_model
;
1378 const char *kernel_filename
= machine
->kernel_filename
;
1379 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[0]);
1382 static void lm3s6965evb_init(MachineState
*machine
)
1384 const char *cpu_model
= machine
->cpu_model
;
1385 const char *kernel_filename
= machine
->kernel_filename
;
1386 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[1]);
1389 static void lm3s811evb_class_init(ObjectClass
*oc
, void *data
)
1391 MachineClass
*mc
= MACHINE_CLASS(oc
);
1393 mc
->desc
= "Stellaris LM3S811EVB";
1394 mc
->init
= lm3s811evb_init
;
1397 static const TypeInfo lm3s811evb_type
= {
1398 .name
= MACHINE_TYPE_NAME("lm3s811evb"),
1399 .parent
= TYPE_MACHINE
,
1400 .class_init
= lm3s811evb_class_init
,
1403 static void lm3s6965evb_class_init(ObjectClass
*oc
, void *data
)
1405 MachineClass
*mc
= MACHINE_CLASS(oc
);
1407 mc
->desc
= "Stellaris LM3S6965EVB";
1408 mc
->init
= lm3s6965evb_init
;
1411 static const TypeInfo lm3s6965evb_type
= {
1412 .name
= MACHINE_TYPE_NAME("lm3s6965evb"),
1413 .parent
= TYPE_MACHINE
,
1414 .class_init
= lm3s6965evb_class_init
,
1417 static void stellaris_machine_init(void)
1419 type_register_static(&lm3s811evb_type
);
1420 type_register_static(&lm3s6965evb_type
);
1423 machine_init(stellaris_machine_init
)
1425 static void stellaris_i2c_class_init(ObjectClass
*klass
, void *data
)
1427 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1429 sdc
->init
= stellaris_i2c_init
;
1432 static const TypeInfo stellaris_i2c_info
= {
1433 .name
= TYPE_STELLARIS_I2C
,
1434 .parent
= TYPE_SYS_BUS_DEVICE
,
1435 .instance_size
= sizeof(stellaris_i2c_state
),
1436 .class_init
= stellaris_i2c_class_init
,
1439 static void stellaris_gptm_class_init(ObjectClass
*klass
, void *data
)
1441 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1443 sdc
->init
= stellaris_gptm_init
;
1446 static const TypeInfo stellaris_gptm_info
= {
1447 .name
= TYPE_STELLARIS_GPTM
,
1448 .parent
= TYPE_SYS_BUS_DEVICE
,
1449 .instance_size
= sizeof(gptm_state
),
1450 .class_init
= stellaris_gptm_class_init
,
1453 static void stellaris_adc_class_init(ObjectClass
*klass
, void *data
)
1455 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1457 sdc
->init
= stellaris_adc_init
;
1460 static const TypeInfo stellaris_adc_info
= {
1461 .name
= TYPE_STELLARIS_ADC
,
1462 .parent
= TYPE_SYS_BUS_DEVICE
,
1463 .instance_size
= sizeof(stellaris_adc_state
),
1464 .class_init
= stellaris_adc_class_init
,
1467 static void stellaris_register_types(void)
1469 type_register_static(&stellaris_i2c_info
);
1470 type_register_static(&stellaris_gptm_info
);
1471 type_register_static(&stellaris_adc_info
);
1474 type_init(stellaris_register_types
)