2 * Marvell MV88W8618 / Freecom MusicPal emulation.
4 * Copyright (c) 2008 Jan Kiszka
6 * This code is licensed under the GNU GPL v2.
8 * Contributions after 2012-01-13 are licensed under the terms of the
9 * GNU GPL, version 2 or (at your option) any later version.
12 #include "qemu/osdep.h"
13 #include "hw/sysbus.h"
14 #include "hw/arm/arm.h"
15 #include "hw/devices.h"
17 #include "sysemu/sysemu.h"
18 #include "hw/boards.h"
19 #include "hw/char/serial.h"
20 #include "qemu/timer.h"
21 #include "hw/ptimer.h"
22 #include "hw/block/flash.h"
23 #include "ui/console.h"
24 #include "hw/i2c/i2c.h"
25 #include "sysemu/block-backend.h"
26 #include "exec/address-spaces.h"
27 #include "ui/pixel_ops.h"
29 #define MP_MISC_BASE 0x80002000
30 #define MP_MISC_SIZE 0x00001000
32 #define MP_ETH_BASE 0x80008000
33 #define MP_ETH_SIZE 0x00001000
35 #define MP_WLAN_BASE 0x8000C000
36 #define MP_WLAN_SIZE 0x00000800
38 #define MP_UART1_BASE 0x8000C840
39 #define MP_UART2_BASE 0x8000C940
41 #define MP_GPIO_BASE 0x8000D000
42 #define MP_GPIO_SIZE 0x00001000
44 #define MP_FLASHCFG_BASE 0x90006000
45 #define MP_FLASHCFG_SIZE 0x00001000
47 #define MP_AUDIO_BASE 0x90007000
49 #define MP_PIC_BASE 0x90008000
50 #define MP_PIC_SIZE 0x00001000
52 #define MP_PIT_BASE 0x90009000
53 #define MP_PIT_SIZE 0x00001000
55 #define MP_LCD_BASE 0x9000c000
56 #define MP_LCD_SIZE 0x00001000
58 #define MP_SRAM_BASE 0xC0000000
59 #define MP_SRAM_SIZE 0x00020000
61 #define MP_RAM_DEFAULT_SIZE 32*1024*1024
62 #define MP_FLASH_SIZE_MAX 32*1024*1024
64 #define MP_TIMER1_IRQ 4
65 #define MP_TIMER2_IRQ 5
66 #define MP_TIMER3_IRQ 6
67 #define MP_TIMER4_IRQ 7
70 #define MP_UART1_IRQ 11
71 #define MP_UART2_IRQ 11
72 #define MP_GPIO_IRQ 12
74 #define MP_AUDIO_IRQ 30
76 /* Wolfson 8750 I2C address */
77 #define MP_WM_ADDR 0x1A
79 /* Ethernet register offsets */
80 #define MP_ETH_SMIR 0x010
81 #define MP_ETH_PCXR 0x408
82 #define MP_ETH_SDCMR 0x448
83 #define MP_ETH_ICR 0x450
84 #define MP_ETH_IMR 0x458
85 #define MP_ETH_FRDP0 0x480
86 #define MP_ETH_FRDP1 0x484
87 #define MP_ETH_FRDP2 0x488
88 #define MP_ETH_FRDP3 0x48C
89 #define MP_ETH_CRDP0 0x4A0
90 #define MP_ETH_CRDP1 0x4A4
91 #define MP_ETH_CRDP2 0x4A8
92 #define MP_ETH_CRDP3 0x4AC
93 #define MP_ETH_CTDP0 0x4E0
94 #define MP_ETH_CTDP1 0x4E4
97 #define MP_ETH_SMIR_DATA 0x0000FFFF
98 #define MP_ETH_SMIR_ADDR 0x03FF0000
99 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
100 #define MP_ETH_SMIR_RDVALID (1 << 27)
103 #define MP_ETH_PHY1_BMSR 0x00210000
104 #define MP_ETH_PHY1_PHYSID1 0x00410000
105 #define MP_ETH_PHY1_PHYSID2 0x00610000
107 #define MP_PHY_BMSR_LINK 0x0004
108 #define MP_PHY_BMSR_AUTONEG 0x0008
110 #define MP_PHY_88E3015 0x01410E20
112 /* TX descriptor status */
113 #define MP_ETH_TX_OWN (1U << 31)
115 /* RX descriptor status */
116 #define MP_ETH_RX_OWN (1U << 31)
118 /* Interrupt cause/mask bits */
119 #define MP_ETH_IRQ_RX_BIT 0
120 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
121 #define MP_ETH_IRQ_TXHI_BIT 2
122 #define MP_ETH_IRQ_TXLO_BIT 3
124 /* Port config bits */
125 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
127 /* SDMA command bits */
128 #define MP_ETH_CMD_TXHI (1 << 23)
129 #define MP_ETH_CMD_TXLO (1 << 22)
131 typedef struct mv88w8618_tx_desc
{
139 typedef struct mv88w8618_rx_desc
{
142 uint16_t buffer_size
;
147 #define TYPE_MV88W8618_ETH "mv88w8618_eth"
148 #define MV88W8618_ETH(obj) \
149 OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH)
151 typedef struct mv88w8618_eth_state
{
153 SysBusDevice parent_obj
;
162 uint32_t vlan_header
;
163 uint32_t tx_queue
[2];
164 uint32_t rx_queue
[4];
165 uint32_t frx_queue
[4];
169 } mv88w8618_eth_state
;
171 static void eth_rx_desc_put(uint32_t addr
, mv88w8618_rx_desc
*desc
)
173 cpu_to_le32s(&desc
->cmdstat
);
174 cpu_to_le16s(&desc
->bytes
);
175 cpu_to_le16s(&desc
->buffer_size
);
176 cpu_to_le32s(&desc
->buffer
);
177 cpu_to_le32s(&desc
->next
);
178 cpu_physical_memory_write(addr
, desc
, sizeof(*desc
));
181 static void eth_rx_desc_get(uint32_t addr
, mv88w8618_rx_desc
*desc
)
183 cpu_physical_memory_read(addr
, desc
, sizeof(*desc
));
184 le32_to_cpus(&desc
->cmdstat
);
185 le16_to_cpus(&desc
->bytes
);
186 le16_to_cpus(&desc
->buffer_size
);
187 le32_to_cpus(&desc
->buffer
);
188 le32_to_cpus(&desc
->next
);
191 static ssize_t
eth_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
193 mv88w8618_eth_state
*s
= qemu_get_nic_opaque(nc
);
195 mv88w8618_rx_desc desc
;
198 for (i
= 0; i
< 4; i
++) {
199 desc_addr
= s
->cur_rx
[i
];
204 eth_rx_desc_get(desc_addr
, &desc
);
205 if ((desc
.cmdstat
& MP_ETH_RX_OWN
) && desc
.buffer_size
>= size
) {
206 cpu_physical_memory_write(desc
.buffer
+ s
->vlan_header
,
208 desc
.bytes
= size
+ s
->vlan_header
;
209 desc
.cmdstat
&= ~MP_ETH_RX_OWN
;
210 s
->cur_rx
[i
] = desc
.next
;
212 s
->icr
|= MP_ETH_IRQ_RX
;
213 if (s
->icr
& s
->imr
) {
214 qemu_irq_raise(s
->irq
);
216 eth_rx_desc_put(desc_addr
, &desc
);
219 desc_addr
= desc
.next
;
220 } while (desc_addr
!= s
->rx_queue
[i
]);
225 static void eth_tx_desc_put(uint32_t addr
, mv88w8618_tx_desc
*desc
)
227 cpu_to_le32s(&desc
->cmdstat
);
228 cpu_to_le16s(&desc
->res
);
229 cpu_to_le16s(&desc
->bytes
);
230 cpu_to_le32s(&desc
->buffer
);
231 cpu_to_le32s(&desc
->next
);
232 cpu_physical_memory_write(addr
, desc
, sizeof(*desc
));
235 static void eth_tx_desc_get(uint32_t addr
, mv88w8618_tx_desc
*desc
)
237 cpu_physical_memory_read(addr
, desc
, sizeof(*desc
));
238 le32_to_cpus(&desc
->cmdstat
);
239 le16_to_cpus(&desc
->res
);
240 le16_to_cpus(&desc
->bytes
);
241 le32_to_cpus(&desc
->buffer
);
242 le32_to_cpus(&desc
->next
);
245 static void eth_send(mv88w8618_eth_state
*s
, int queue_index
)
247 uint32_t desc_addr
= s
->tx_queue
[queue_index
];
248 mv88w8618_tx_desc desc
;
254 eth_tx_desc_get(desc_addr
, &desc
);
255 next_desc
= desc
.next
;
256 if (desc
.cmdstat
& MP_ETH_TX_OWN
) {
259 cpu_physical_memory_read(desc
.buffer
, buf
, len
);
260 qemu_send_packet(qemu_get_queue(s
->nic
), buf
, len
);
262 desc
.cmdstat
&= ~MP_ETH_TX_OWN
;
263 s
->icr
|= 1 << (MP_ETH_IRQ_TXLO_BIT
- queue_index
);
264 eth_tx_desc_put(desc_addr
, &desc
);
266 desc_addr
= next_desc
;
267 } while (desc_addr
!= s
->tx_queue
[queue_index
]);
270 static uint64_t mv88w8618_eth_read(void *opaque
, hwaddr offset
,
273 mv88w8618_eth_state
*s
= opaque
;
277 if (s
->smir
& MP_ETH_SMIR_OPCODE
) {
278 switch (s
->smir
& MP_ETH_SMIR_ADDR
) {
279 case MP_ETH_PHY1_BMSR
:
280 return MP_PHY_BMSR_LINK
| MP_PHY_BMSR_AUTONEG
|
282 case MP_ETH_PHY1_PHYSID1
:
283 return (MP_PHY_88E3015
>> 16) | MP_ETH_SMIR_RDVALID
;
284 case MP_ETH_PHY1_PHYSID2
:
285 return (MP_PHY_88E3015
& 0xFFFF) | MP_ETH_SMIR_RDVALID
;
287 return MP_ETH_SMIR_RDVALID
;
298 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
299 return s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4];
301 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
302 return s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4];
304 case MP_ETH_CTDP0
... MP_ETH_CTDP1
:
305 return s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4];
312 static void mv88w8618_eth_write(void *opaque
, hwaddr offset
,
313 uint64_t value
, unsigned size
)
315 mv88w8618_eth_state
*s
= opaque
;
323 s
->vlan_header
= ((value
>> MP_ETH_PCXR_2BSM_BIT
) & 1) * 2;
327 if (value
& MP_ETH_CMD_TXHI
) {
330 if (value
& MP_ETH_CMD_TXLO
) {
333 if (value
& (MP_ETH_CMD_TXHI
| MP_ETH_CMD_TXLO
) && s
->icr
& s
->imr
) {
334 qemu_irq_raise(s
->irq
);
344 if (s
->icr
& s
->imr
) {
345 qemu_irq_raise(s
->irq
);
349 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
350 s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4] = value
;
353 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
354 s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4] =
355 s
->cur_rx
[(offset
- MP_ETH_CRDP0
)/4] = value
;
358 case MP_ETH_CTDP0
... MP_ETH_CTDP1
:
359 s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4] = value
;
364 static const MemoryRegionOps mv88w8618_eth_ops
= {
365 .read
= mv88w8618_eth_read
,
366 .write
= mv88w8618_eth_write
,
367 .endianness
= DEVICE_NATIVE_ENDIAN
,
370 static void eth_cleanup(NetClientState
*nc
)
372 mv88w8618_eth_state
*s
= qemu_get_nic_opaque(nc
);
377 static NetClientInfo net_mv88w8618_info
= {
378 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
379 .size
= sizeof(NICState
),
380 .receive
= eth_receive
,
381 .cleanup
= eth_cleanup
,
384 static int mv88w8618_eth_init(SysBusDevice
*sbd
)
386 DeviceState
*dev
= DEVICE(sbd
);
387 mv88w8618_eth_state
*s
= MV88W8618_ETH(dev
);
389 sysbus_init_irq(sbd
, &s
->irq
);
390 s
->nic
= qemu_new_nic(&net_mv88w8618_info
, &s
->conf
,
391 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
392 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_eth_ops
, s
,
393 "mv88w8618-eth", MP_ETH_SIZE
);
394 sysbus_init_mmio(sbd
, &s
->iomem
);
398 static const VMStateDescription mv88w8618_eth_vmsd
= {
399 .name
= "mv88w8618_eth",
401 .minimum_version_id
= 1,
402 .fields
= (VMStateField
[]) {
403 VMSTATE_UINT32(smir
, mv88w8618_eth_state
),
404 VMSTATE_UINT32(icr
, mv88w8618_eth_state
),
405 VMSTATE_UINT32(imr
, mv88w8618_eth_state
),
406 VMSTATE_UINT32(vlan_header
, mv88w8618_eth_state
),
407 VMSTATE_UINT32_ARRAY(tx_queue
, mv88w8618_eth_state
, 2),
408 VMSTATE_UINT32_ARRAY(rx_queue
, mv88w8618_eth_state
, 4),
409 VMSTATE_UINT32_ARRAY(frx_queue
, mv88w8618_eth_state
, 4),
410 VMSTATE_UINT32_ARRAY(cur_rx
, mv88w8618_eth_state
, 4),
411 VMSTATE_END_OF_LIST()
415 static Property mv88w8618_eth_properties
[] = {
416 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state
, conf
),
417 DEFINE_PROP_END_OF_LIST(),
420 static void mv88w8618_eth_class_init(ObjectClass
*klass
, void *data
)
422 DeviceClass
*dc
= DEVICE_CLASS(klass
);
423 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
425 k
->init
= mv88w8618_eth_init
;
426 dc
->vmsd
= &mv88w8618_eth_vmsd
;
427 dc
->props
= mv88w8618_eth_properties
;
430 static const TypeInfo mv88w8618_eth_info
= {
431 .name
= TYPE_MV88W8618_ETH
,
432 .parent
= TYPE_SYS_BUS_DEVICE
,
433 .instance_size
= sizeof(mv88w8618_eth_state
),
434 .class_init
= mv88w8618_eth_class_init
,
437 /* LCD register offsets */
438 #define MP_LCD_IRQCTRL 0x180
439 #define MP_LCD_IRQSTAT 0x184
440 #define MP_LCD_SPICTRL 0x1ac
441 #define MP_LCD_INST 0x1bc
442 #define MP_LCD_DATA 0x1c0
445 #define MP_LCD_SPI_DATA 0x00100011
446 #define MP_LCD_SPI_CMD 0x00104011
447 #define MP_LCD_SPI_INVALID 0x00000000
450 #define MP_LCD_INST_SETPAGE0 0xB0
452 #define MP_LCD_INST_SETPAGE7 0xB7
454 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
456 #define TYPE_MUSICPAL_LCD "musicpal_lcd"
457 #define MUSICPAL_LCD(obj) \
458 OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD)
460 typedef struct musicpal_lcd_state
{
462 SysBusDevice parent_obj
;
472 uint8_t video_ram
[128*64/8];
473 } musicpal_lcd_state
;
475 static uint8_t scale_lcd_color(musicpal_lcd_state
*s
, uint8_t col
)
477 switch (s
->brightness
) {
483 return (col
* s
->brightness
) / 7;
487 #define SET_LCD_PIXEL(depth, type) \
488 static inline void glue(set_lcd_pixel, depth) \
489 (musicpal_lcd_state *s, int x, int y, type col) \
492 DisplaySurface *surface = qemu_console_surface(s->con); \
493 type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \
495 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
496 for (dx = 0; dx < 3; dx++, pixel++) \
499 SET_LCD_PIXEL(8, uint8_t)
500 SET_LCD_PIXEL(16, uint16_t)
501 SET_LCD_PIXEL(32, uint32_t)
503 static void lcd_refresh(void *opaque
)
505 musicpal_lcd_state
*s
= opaque
;
506 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
509 switch (surface_bits_per_pixel(surface
)) {
512 #define LCD_REFRESH(depth, func) \
514 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
515 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
516 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
517 for (x = 0; x < 128; x++) { \
518 for (y = 0; y < 64; y++) { \
519 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
520 glue(set_lcd_pixel, depth)(s, x, y, col); \
522 glue(set_lcd_pixel, depth)(s, x, y, 0); \
527 LCD_REFRESH(8, rgb_to_pixel8
)
528 LCD_REFRESH(16, rgb_to_pixel16
)
529 LCD_REFRESH(32, (is_surface_bgr(surface
) ?
530 rgb_to_pixel32bgr
: rgb_to_pixel32
))
532 hw_error("unsupported colour depth %i\n",
533 surface_bits_per_pixel(surface
));
536 dpy_gfx_update(s
->con
, 0, 0, 128*3, 64*3);
539 static void lcd_invalidate(void *opaque
)
543 static void musicpal_lcd_gpio_brightness_in(void *opaque
, int irq
, int level
)
545 musicpal_lcd_state
*s
= opaque
;
546 s
->brightness
&= ~(1 << irq
);
547 s
->brightness
|= level
<< irq
;
550 static uint64_t musicpal_lcd_read(void *opaque
, hwaddr offset
,
553 musicpal_lcd_state
*s
= opaque
;
564 static void musicpal_lcd_write(void *opaque
, hwaddr offset
,
565 uint64_t value
, unsigned size
)
567 musicpal_lcd_state
*s
= opaque
;
575 if (value
== MP_LCD_SPI_DATA
|| value
== MP_LCD_SPI_CMD
) {
578 s
->mode
= MP_LCD_SPI_INVALID
;
583 if (value
>= MP_LCD_INST_SETPAGE0
&& value
<= MP_LCD_INST_SETPAGE7
) {
584 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
590 if (s
->mode
== MP_LCD_SPI_CMD
) {
591 if (value
>= MP_LCD_INST_SETPAGE0
&&
592 value
<= MP_LCD_INST_SETPAGE7
) {
593 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
596 } else if (s
->mode
== MP_LCD_SPI_DATA
) {
597 s
->video_ram
[s
->page
*128 + s
->page_off
] = value
;
598 s
->page_off
= (s
->page_off
+ 1) & 127;
604 static const MemoryRegionOps musicpal_lcd_ops
= {
605 .read
= musicpal_lcd_read
,
606 .write
= musicpal_lcd_write
,
607 .endianness
= DEVICE_NATIVE_ENDIAN
,
610 static const GraphicHwOps musicpal_gfx_ops
= {
611 .invalidate
= lcd_invalidate
,
612 .gfx_update
= lcd_refresh
,
615 static int musicpal_lcd_init(SysBusDevice
*sbd
)
617 DeviceState
*dev
= DEVICE(sbd
);
618 musicpal_lcd_state
*s
= MUSICPAL_LCD(dev
);
622 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_lcd_ops
, s
,
623 "musicpal-lcd", MP_LCD_SIZE
);
624 sysbus_init_mmio(sbd
, &s
->iomem
);
626 s
->con
= graphic_console_init(dev
, 0, &musicpal_gfx_ops
, s
);
627 qemu_console_resize(s
->con
, 128*3, 64*3);
629 qdev_init_gpio_in(dev
, musicpal_lcd_gpio_brightness_in
, 3);
634 static const VMStateDescription musicpal_lcd_vmsd
= {
635 .name
= "musicpal_lcd",
637 .minimum_version_id
= 1,
638 .fields
= (VMStateField
[]) {
639 VMSTATE_UINT32(brightness
, musicpal_lcd_state
),
640 VMSTATE_UINT32(mode
, musicpal_lcd_state
),
641 VMSTATE_UINT32(irqctrl
, musicpal_lcd_state
),
642 VMSTATE_UINT32(page
, musicpal_lcd_state
),
643 VMSTATE_UINT32(page_off
, musicpal_lcd_state
),
644 VMSTATE_BUFFER(video_ram
, musicpal_lcd_state
),
645 VMSTATE_END_OF_LIST()
649 static void musicpal_lcd_class_init(ObjectClass
*klass
, void *data
)
651 DeviceClass
*dc
= DEVICE_CLASS(klass
);
652 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
654 k
->init
= musicpal_lcd_init
;
655 dc
->vmsd
= &musicpal_lcd_vmsd
;
658 static const TypeInfo musicpal_lcd_info
= {
659 .name
= TYPE_MUSICPAL_LCD
,
660 .parent
= TYPE_SYS_BUS_DEVICE
,
661 .instance_size
= sizeof(musicpal_lcd_state
),
662 .class_init
= musicpal_lcd_class_init
,
665 /* PIC register offsets */
666 #define MP_PIC_STATUS 0x00
667 #define MP_PIC_ENABLE_SET 0x08
668 #define MP_PIC_ENABLE_CLR 0x0C
670 #define TYPE_MV88W8618_PIC "mv88w8618_pic"
671 #define MV88W8618_PIC(obj) \
672 OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC)
674 typedef struct mv88w8618_pic_state
{
676 SysBusDevice parent_obj
;
683 } mv88w8618_pic_state
;
685 static void mv88w8618_pic_update(mv88w8618_pic_state
*s
)
687 qemu_set_irq(s
->parent_irq
, (s
->level
& s
->enabled
));
690 static void mv88w8618_pic_set_irq(void *opaque
, int irq
, int level
)
692 mv88w8618_pic_state
*s
= opaque
;
695 s
->level
|= 1 << irq
;
697 s
->level
&= ~(1 << irq
);
699 mv88w8618_pic_update(s
);
702 static uint64_t mv88w8618_pic_read(void *opaque
, hwaddr offset
,
705 mv88w8618_pic_state
*s
= opaque
;
709 return s
->level
& s
->enabled
;
716 static void mv88w8618_pic_write(void *opaque
, hwaddr offset
,
717 uint64_t value
, unsigned size
)
719 mv88w8618_pic_state
*s
= opaque
;
722 case MP_PIC_ENABLE_SET
:
726 case MP_PIC_ENABLE_CLR
:
727 s
->enabled
&= ~value
;
731 mv88w8618_pic_update(s
);
734 static void mv88w8618_pic_reset(DeviceState
*d
)
736 mv88w8618_pic_state
*s
= MV88W8618_PIC(d
);
742 static const MemoryRegionOps mv88w8618_pic_ops
= {
743 .read
= mv88w8618_pic_read
,
744 .write
= mv88w8618_pic_write
,
745 .endianness
= DEVICE_NATIVE_ENDIAN
,
748 static int mv88w8618_pic_init(SysBusDevice
*dev
)
750 mv88w8618_pic_state
*s
= MV88W8618_PIC(dev
);
752 qdev_init_gpio_in(DEVICE(dev
), mv88w8618_pic_set_irq
, 32);
753 sysbus_init_irq(dev
, &s
->parent_irq
);
754 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_pic_ops
, s
,
755 "musicpal-pic", MP_PIC_SIZE
);
756 sysbus_init_mmio(dev
, &s
->iomem
);
760 static const VMStateDescription mv88w8618_pic_vmsd
= {
761 .name
= "mv88w8618_pic",
763 .minimum_version_id
= 1,
764 .fields
= (VMStateField
[]) {
765 VMSTATE_UINT32(level
, mv88w8618_pic_state
),
766 VMSTATE_UINT32(enabled
, mv88w8618_pic_state
),
767 VMSTATE_END_OF_LIST()
771 static void mv88w8618_pic_class_init(ObjectClass
*klass
, void *data
)
773 DeviceClass
*dc
= DEVICE_CLASS(klass
);
774 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
776 k
->init
= mv88w8618_pic_init
;
777 dc
->reset
= mv88w8618_pic_reset
;
778 dc
->vmsd
= &mv88w8618_pic_vmsd
;
781 static const TypeInfo mv88w8618_pic_info
= {
782 .name
= TYPE_MV88W8618_PIC
,
783 .parent
= TYPE_SYS_BUS_DEVICE
,
784 .instance_size
= sizeof(mv88w8618_pic_state
),
785 .class_init
= mv88w8618_pic_class_init
,
788 /* PIT register offsets */
789 #define MP_PIT_TIMER1_LENGTH 0x00
791 #define MP_PIT_TIMER4_LENGTH 0x0C
792 #define MP_PIT_CONTROL 0x10
793 #define MP_PIT_TIMER1_VALUE 0x14
795 #define MP_PIT_TIMER4_VALUE 0x20
796 #define MP_BOARD_RESET 0x34
798 /* Magic board reset value (probably some watchdog behind it) */
799 #define MP_BOARD_RESET_MAGIC 0x10000
801 typedef struct mv88w8618_timer_state
{
802 ptimer_state
*ptimer
;
806 } mv88w8618_timer_state
;
808 #define TYPE_MV88W8618_PIT "mv88w8618_pit"
809 #define MV88W8618_PIT(obj) \
810 OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT)
812 typedef struct mv88w8618_pit_state
{
814 SysBusDevice parent_obj
;
818 mv88w8618_timer_state timer
[4];
819 } mv88w8618_pit_state
;
821 static void mv88w8618_timer_tick(void *opaque
)
823 mv88w8618_timer_state
*s
= opaque
;
825 qemu_irq_raise(s
->irq
);
828 static void mv88w8618_timer_init(SysBusDevice
*dev
, mv88w8618_timer_state
*s
,
833 sysbus_init_irq(dev
, &s
->irq
);
836 bh
= qemu_bh_new(mv88w8618_timer_tick
, s
);
837 s
->ptimer
= ptimer_init(bh
);
840 static uint64_t mv88w8618_pit_read(void *opaque
, hwaddr offset
,
843 mv88w8618_pit_state
*s
= opaque
;
844 mv88w8618_timer_state
*t
;
847 case MP_PIT_TIMER1_VALUE
... MP_PIT_TIMER4_VALUE
:
848 t
= &s
->timer
[(offset
-MP_PIT_TIMER1_VALUE
) >> 2];
849 return ptimer_get_count(t
->ptimer
);
856 static void mv88w8618_pit_write(void *opaque
, hwaddr offset
,
857 uint64_t value
, unsigned size
)
859 mv88w8618_pit_state
*s
= opaque
;
860 mv88w8618_timer_state
*t
;
864 case MP_PIT_TIMER1_LENGTH
... MP_PIT_TIMER4_LENGTH
:
865 t
= &s
->timer
[offset
>> 2];
868 ptimer_set_limit(t
->ptimer
, t
->limit
, 1);
870 ptimer_stop(t
->ptimer
);
875 for (i
= 0; i
< 4; i
++) {
877 if (value
& 0xf && t
->limit
> 0) {
878 ptimer_set_limit(t
->ptimer
, t
->limit
, 0);
879 ptimer_set_freq(t
->ptimer
, t
->freq
);
880 ptimer_run(t
->ptimer
, 0);
882 ptimer_stop(t
->ptimer
);
889 if (value
== MP_BOARD_RESET_MAGIC
) {
890 qemu_system_reset_request();
896 static void mv88w8618_pit_reset(DeviceState
*d
)
898 mv88w8618_pit_state
*s
= MV88W8618_PIT(d
);
901 for (i
= 0; i
< 4; i
++) {
902 ptimer_stop(s
->timer
[i
].ptimer
);
903 s
->timer
[i
].limit
= 0;
907 static const MemoryRegionOps mv88w8618_pit_ops
= {
908 .read
= mv88w8618_pit_read
,
909 .write
= mv88w8618_pit_write
,
910 .endianness
= DEVICE_NATIVE_ENDIAN
,
913 static int mv88w8618_pit_init(SysBusDevice
*dev
)
915 mv88w8618_pit_state
*s
= MV88W8618_PIT(dev
);
918 /* Letting them all run at 1 MHz is likely just a pragmatic
920 for (i
= 0; i
< 4; i
++) {
921 mv88w8618_timer_init(dev
, &s
->timer
[i
], 1000000);
924 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_pit_ops
, s
,
925 "musicpal-pit", MP_PIT_SIZE
);
926 sysbus_init_mmio(dev
, &s
->iomem
);
930 static const VMStateDescription mv88w8618_timer_vmsd
= {
933 .minimum_version_id
= 1,
934 .fields
= (VMStateField
[]) {
935 VMSTATE_PTIMER(ptimer
, mv88w8618_timer_state
),
936 VMSTATE_UINT32(limit
, mv88w8618_timer_state
),
937 VMSTATE_END_OF_LIST()
941 static const VMStateDescription mv88w8618_pit_vmsd
= {
942 .name
= "mv88w8618_pit",
944 .minimum_version_id
= 1,
945 .fields
= (VMStateField
[]) {
946 VMSTATE_STRUCT_ARRAY(timer
, mv88w8618_pit_state
, 4, 1,
947 mv88w8618_timer_vmsd
, mv88w8618_timer_state
),
948 VMSTATE_END_OF_LIST()
952 static void mv88w8618_pit_class_init(ObjectClass
*klass
, void *data
)
954 DeviceClass
*dc
= DEVICE_CLASS(klass
);
955 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
957 k
->init
= mv88w8618_pit_init
;
958 dc
->reset
= mv88w8618_pit_reset
;
959 dc
->vmsd
= &mv88w8618_pit_vmsd
;
962 static const TypeInfo mv88w8618_pit_info
= {
963 .name
= TYPE_MV88W8618_PIT
,
964 .parent
= TYPE_SYS_BUS_DEVICE
,
965 .instance_size
= sizeof(mv88w8618_pit_state
),
966 .class_init
= mv88w8618_pit_class_init
,
969 /* Flash config register offsets */
970 #define MP_FLASHCFG_CFGR0 0x04
972 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg"
973 #define MV88W8618_FLASHCFG(obj) \
974 OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG)
976 typedef struct mv88w8618_flashcfg_state
{
978 SysBusDevice parent_obj
;
983 } mv88w8618_flashcfg_state
;
985 static uint64_t mv88w8618_flashcfg_read(void *opaque
,
989 mv88w8618_flashcfg_state
*s
= opaque
;
992 case MP_FLASHCFG_CFGR0
:
1000 static void mv88w8618_flashcfg_write(void *opaque
, hwaddr offset
,
1001 uint64_t value
, unsigned size
)
1003 mv88w8618_flashcfg_state
*s
= opaque
;
1006 case MP_FLASHCFG_CFGR0
:
1012 static const MemoryRegionOps mv88w8618_flashcfg_ops
= {
1013 .read
= mv88w8618_flashcfg_read
,
1014 .write
= mv88w8618_flashcfg_write
,
1015 .endianness
= DEVICE_NATIVE_ENDIAN
,
1018 static int mv88w8618_flashcfg_init(SysBusDevice
*dev
)
1020 mv88w8618_flashcfg_state
*s
= MV88W8618_FLASHCFG(dev
);
1022 s
->cfgr0
= 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1023 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_flashcfg_ops
, s
,
1024 "musicpal-flashcfg", MP_FLASHCFG_SIZE
);
1025 sysbus_init_mmio(dev
, &s
->iomem
);
1029 static const VMStateDescription mv88w8618_flashcfg_vmsd
= {
1030 .name
= "mv88w8618_flashcfg",
1032 .minimum_version_id
= 1,
1033 .fields
= (VMStateField
[]) {
1034 VMSTATE_UINT32(cfgr0
, mv88w8618_flashcfg_state
),
1035 VMSTATE_END_OF_LIST()
1039 static void mv88w8618_flashcfg_class_init(ObjectClass
*klass
, void *data
)
1041 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1042 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1044 k
->init
= mv88w8618_flashcfg_init
;
1045 dc
->vmsd
= &mv88w8618_flashcfg_vmsd
;
1048 static const TypeInfo mv88w8618_flashcfg_info
= {
1049 .name
= TYPE_MV88W8618_FLASHCFG
,
1050 .parent
= TYPE_SYS_BUS_DEVICE
,
1051 .instance_size
= sizeof(mv88w8618_flashcfg_state
),
1052 .class_init
= mv88w8618_flashcfg_class_init
,
1055 /* Misc register offsets */
1056 #define MP_MISC_BOARD_REVISION 0x18
1058 #define MP_BOARD_REVISION 0x31
1061 SysBusDevice parent_obj
;
1063 } MusicPalMiscState
;
1065 #define TYPE_MUSICPAL_MISC "musicpal-misc"
1066 #define MUSICPAL_MISC(obj) \
1067 OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC)
1069 static uint64_t musicpal_misc_read(void *opaque
, hwaddr offset
,
1073 case MP_MISC_BOARD_REVISION
:
1074 return MP_BOARD_REVISION
;
1081 static void musicpal_misc_write(void *opaque
, hwaddr offset
,
1082 uint64_t value
, unsigned size
)
1086 static const MemoryRegionOps musicpal_misc_ops
= {
1087 .read
= musicpal_misc_read
,
1088 .write
= musicpal_misc_write
,
1089 .endianness
= DEVICE_NATIVE_ENDIAN
,
1092 static void musicpal_misc_init(Object
*obj
)
1094 SysBusDevice
*sd
= SYS_BUS_DEVICE(obj
);
1095 MusicPalMiscState
*s
= MUSICPAL_MISC(obj
);
1097 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_misc_ops
, NULL
,
1098 "musicpal-misc", MP_MISC_SIZE
);
1099 sysbus_init_mmio(sd
, &s
->iomem
);
1102 static const TypeInfo musicpal_misc_info
= {
1103 .name
= TYPE_MUSICPAL_MISC
,
1104 .parent
= TYPE_SYS_BUS_DEVICE
,
1105 .instance_init
= musicpal_misc_init
,
1106 .instance_size
= sizeof(MusicPalMiscState
),
1109 /* WLAN register offsets */
1110 #define MP_WLAN_MAGIC1 0x11c
1111 #define MP_WLAN_MAGIC2 0x124
1113 static uint64_t mv88w8618_wlan_read(void *opaque
, hwaddr offset
,
1117 /* Workaround to allow loading the binary-only wlandrv.ko crap
1118 * from the original Freecom firmware. */
1119 case MP_WLAN_MAGIC1
:
1121 case MP_WLAN_MAGIC2
:
1129 static void mv88w8618_wlan_write(void *opaque
, hwaddr offset
,
1130 uint64_t value
, unsigned size
)
1134 static const MemoryRegionOps mv88w8618_wlan_ops
= {
1135 .read
= mv88w8618_wlan_read
,
1136 .write
=mv88w8618_wlan_write
,
1137 .endianness
= DEVICE_NATIVE_ENDIAN
,
1140 static int mv88w8618_wlan_init(SysBusDevice
*dev
)
1142 MemoryRegion
*iomem
= g_new(MemoryRegion
, 1);
1144 memory_region_init_io(iomem
, OBJECT(dev
), &mv88w8618_wlan_ops
, NULL
,
1145 "musicpal-wlan", MP_WLAN_SIZE
);
1146 sysbus_init_mmio(dev
, iomem
);
1150 /* GPIO register offsets */
1151 #define MP_GPIO_OE_LO 0x008
1152 #define MP_GPIO_OUT_LO 0x00c
1153 #define MP_GPIO_IN_LO 0x010
1154 #define MP_GPIO_IER_LO 0x014
1155 #define MP_GPIO_IMR_LO 0x018
1156 #define MP_GPIO_ISR_LO 0x020
1157 #define MP_GPIO_OE_HI 0x508
1158 #define MP_GPIO_OUT_HI 0x50c
1159 #define MP_GPIO_IN_HI 0x510
1160 #define MP_GPIO_IER_HI 0x514
1161 #define MP_GPIO_IMR_HI 0x518
1162 #define MP_GPIO_ISR_HI 0x520
1164 /* GPIO bits & masks */
1165 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1166 #define MP_GPIO_I2C_DATA_BIT 29
1167 #define MP_GPIO_I2C_CLOCK_BIT 30
1169 /* LCD brightness bits in GPIO_OE_HI */
1170 #define MP_OE_LCD_BRIGHTNESS 0x0007
1172 #define TYPE_MUSICPAL_GPIO "musicpal_gpio"
1173 #define MUSICPAL_GPIO(obj) \
1174 OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO)
1176 typedef struct musicpal_gpio_state
{
1178 SysBusDevice parent_obj
;
1182 uint32_t lcd_brightness
;
1189 qemu_irq out
[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1190 } musicpal_gpio_state
;
1192 static void musicpal_gpio_brightness_update(musicpal_gpio_state
*s
) {
1194 uint32_t brightness
;
1196 /* compute brightness ratio */
1197 switch (s
->lcd_brightness
) {
1231 /* set lcd brightness GPIOs */
1232 for (i
= 0; i
<= 2; i
++) {
1233 qemu_set_irq(s
->out
[i
], (brightness
>> i
) & 1);
1237 static void musicpal_gpio_pin_event(void *opaque
, int pin
, int level
)
1239 musicpal_gpio_state
*s
= opaque
;
1240 uint32_t mask
= 1 << pin
;
1241 uint32_t delta
= level
<< pin
;
1242 uint32_t old
= s
->in_state
& mask
;
1244 s
->in_state
&= ~mask
;
1245 s
->in_state
|= delta
;
1247 if ((old
^ delta
) &&
1248 ((level
&& (s
->imr
& mask
)) || (!level
&& (s
->ier
& mask
)))) {
1250 qemu_irq_raise(s
->irq
);
1254 static uint64_t musicpal_gpio_read(void *opaque
, hwaddr offset
,
1257 musicpal_gpio_state
*s
= opaque
;
1260 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1261 return s
->lcd_brightness
& MP_OE_LCD_BRIGHTNESS
;
1263 case MP_GPIO_OUT_LO
:
1264 return s
->out_state
& 0xFFFF;
1265 case MP_GPIO_OUT_HI
:
1266 return s
->out_state
>> 16;
1269 return s
->in_state
& 0xFFFF;
1271 return s
->in_state
>> 16;
1273 case MP_GPIO_IER_LO
:
1274 return s
->ier
& 0xFFFF;
1275 case MP_GPIO_IER_HI
:
1276 return s
->ier
>> 16;
1278 case MP_GPIO_IMR_LO
:
1279 return s
->imr
& 0xFFFF;
1280 case MP_GPIO_IMR_HI
:
1281 return s
->imr
>> 16;
1283 case MP_GPIO_ISR_LO
:
1284 return s
->isr
& 0xFFFF;
1285 case MP_GPIO_ISR_HI
:
1286 return s
->isr
>> 16;
1293 static void musicpal_gpio_write(void *opaque
, hwaddr offset
,
1294 uint64_t value
, unsigned size
)
1296 musicpal_gpio_state
*s
= opaque
;
1298 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1299 s
->lcd_brightness
= (s
->lcd_brightness
& MP_GPIO_LCD_BRIGHTNESS
) |
1300 (value
& MP_OE_LCD_BRIGHTNESS
);
1301 musicpal_gpio_brightness_update(s
);
1304 case MP_GPIO_OUT_LO
:
1305 s
->out_state
= (s
->out_state
& 0xFFFF0000) | (value
& 0xFFFF);
1307 case MP_GPIO_OUT_HI
:
1308 s
->out_state
= (s
->out_state
& 0xFFFF) | (value
<< 16);
1309 s
->lcd_brightness
= (s
->lcd_brightness
& 0xFFFF) |
1310 (s
->out_state
& MP_GPIO_LCD_BRIGHTNESS
);
1311 musicpal_gpio_brightness_update(s
);
1312 qemu_set_irq(s
->out
[3], (s
->out_state
>> MP_GPIO_I2C_DATA_BIT
) & 1);
1313 qemu_set_irq(s
->out
[4], (s
->out_state
>> MP_GPIO_I2C_CLOCK_BIT
) & 1);
1316 case MP_GPIO_IER_LO
:
1317 s
->ier
= (s
->ier
& 0xFFFF0000) | (value
& 0xFFFF);
1319 case MP_GPIO_IER_HI
:
1320 s
->ier
= (s
->ier
& 0xFFFF) | (value
<< 16);
1323 case MP_GPIO_IMR_LO
:
1324 s
->imr
= (s
->imr
& 0xFFFF0000) | (value
& 0xFFFF);
1326 case MP_GPIO_IMR_HI
:
1327 s
->imr
= (s
->imr
& 0xFFFF) | (value
<< 16);
1332 static const MemoryRegionOps musicpal_gpio_ops
= {
1333 .read
= musicpal_gpio_read
,
1334 .write
= musicpal_gpio_write
,
1335 .endianness
= DEVICE_NATIVE_ENDIAN
,
1338 static void musicpal_gpio_reset(DeviceState
*d
)
1340 musicpal_gpio_state
*s
= MUSICPAL_GPIO(d
);
1342 s
->lcd_brightness
= 0;
1344 s
->in_state
= 0xffffffff;
1350 static int musicpal_gpio_init(SysBusDevice
*sbd
)
1352 DeviceState
*dev
= DEVICE(sbd
);
1353 musicpal_gpio_state
*s
= MUSICPAL_GPIO(dev
);
1355 sysbus_init_irq(sbd
, &s
->irq
);
1357 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_gpio_ops
, s
,
1358 "musicpal-gpio", MP_GPIO_SIZE
);
1359 sysbus_init_mmio(sbd
, &s
->iomem
);
1361 qdev_init_gpio_out(dev
, s
->out
, ARRAY_SIZE(s
->out
));
1363 qdev_init_gpio_in(dev
, musicpal_gpio_pin_event
, 32);
1368 static const VMStateDescription musicpal_gpio_vmsd
= {
1369 .name
= "musicpal_gpio",
1371 .minimum_version_id
= 1,
1372 .fields
= (VMStateField
[]) {
1373 VMSTATE_UINT32(lcd_brightness
, musicpal_gpio_state
),
1374 VMSTATE_UINT32(out_state
, musicpal_gpio_state
),
1375 VMSTATE_UINT32(in_state
, musicpal_gpio_state
),
1376 VMSTATE_UINT32(ier
, musicpal_gpio_state
),
1377 VMSTATE_UINT32(imr
, musicpal_gpio_state
),
1378 VMSTATE_UINT32(isr
, musicpal_gpio_state
),
1379 VMSTATE_END_OF_LIST()
1383 static void musicpal_gpio_class_init(ObjectClass
*klass
, void *data
)
1385 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1386 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1388 k
->init
= musicpal_gpio_init
;
1389 dc
->reset
= musicpal_gpio_reset
;
1390 dc
->vmsd
= &musicpal_gpio_vmsd
;
1393 static const TypeInfo musicpal_gpio_info
= {
1394 .name
= TYPE_MUSICPAL_GPIO
,
1395 .parent
= TYPE_SYS_BUS_DEVICE
,
1396 .instance_size
= sizeof(musicpal_gpio_state
),
1397 .class_init
= musicpal_gpio_class_init
,
1400 /* Keyboard codes & masks */
1401 #define KEY_RELEASED 0x80
1402 #define KEY_CODE 0x7f
1404 #define KEYCODE_TAB 0x0f
1405 #define KEYCODE_ENTER 0x1c
1406 #define KEYCODE_F 0x21
1407 #define KEYCODE_M 0x32
1409 #define KEYCODE_EXTENDED 0xe0
1410 #define KEYCODE_UP 0x48
1411 #define KEYCODE_DOWN 0x50
1412 #define KEYCODE_LEFT 0x4b
1413 #define KEYCODE_RIGHT 0x4d
1415 #define MP_KEY_WHEEL_VOL (1 << 0)
1416 #define MP_KEY_WHEEL_VOL_INV (1 << 1)
1417 #define MP_KEY_WHEEL_NAV (1 << 2)
1418 #define MP_KEY_WHEEL_NAV_INV (1 << 3)
1419 #define MP_KEY_BTN_FAVORITS (1 << 4)
1420 #define MP_KEY_BTN_MENU (1 << 5)
1421 #define MP_KEY_BTN_VOLUME (1 << 6)
1422 #define MP_KEY_BTN_NAVIGATION (1 << 7)
1424 #define TYPE_MUSICPAL_KEY "musicpal_key"
1425 #define MUSICPAL_KEY(obj) \
1426 OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY)
1428 typedef struct musicpal_key_state
{
1430 SysBusDevice parent_obj
;
1434 uint32_t kbd_extended
;
1435 uint32_t pressed_keys
;
1437 } musicpal_key_state
;
1439 static void musicpal_key_event(void *opaque
, int keycode
)
1441 musicpal_key_state
*s
= opaque
;
1445 if (keycode
== KEYCODE_EXTENDED
) {
1446 s
->kbd_extended
= 1;
1450 if (s
->kbd_extended
) {
1451 switch (keycode
& KEY_CODE
) {
1453 event
= MP_KEY_WHEEL_NAV
| MP_KEY_WHEEL_NAV_INV
;
1457 event
= MP_KEY_WHEEL_NAV
;
1461 event
= MP_KEY_WHEEL_VOL
| MP_KEY_WHEEL_VOL_INV
;
1465 event
= MP_KEY_WHEEL_VOL
;
1469 switch (keycode
& KEY_CODE
) {
1471 event
= MP_KEY_BTN_FAVORITS
;
1475 event
= MP_KEY_BTN_VOLUME
;
1479 event
= MP_KEY_BTN_NAVIGATION
;
1483 event
= MP_KEY_BTN_MENU
;
1486 /* Do not repeat already pressed buttons */
1487 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1493 /* Raise GPIO pin first if repeating a key */
1494 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1495 for (i
= 0; i
<= 7; i
++) {
1496 if (event
& (1 << i
)) {
1497 qemu_set_irq(s
->out
[i
], 1);
1501 for (i
= 0; i
<= 7; i
++) {
1502 if (event
& (1 << i
)) {
1503 qemu_set_irq(s
->out
[i
], !!(keycode
& KEY_RELEASED
));
1506 if (keycode
& KEY_RELEASED
) {
1507 s
->pressed_keys
&= ~event
;
1509 s
->pressed_keys
|= event
;
1513 s
->kbd_extended
= 0;
1516 static int musicpal_key_init(SysBusDevice
*sbd
)
1518 DeviceState
*dev
= DEVICE(sbd
);
1519 musicpal_key_state
*s
= MUSICPAL_KEY(dev
);
1521 memory_region_init(&s
->iomem
, OBJECT(s
), "dummy", 0);
1522 sysbus_init_mmio(sbd
, &s
->iomem
);
1524 s
->kbd_extended
= 0;
1525 s
->pressed_keys
= 0;
1527 qdev_init_gpio_out(dev
, s
->out
, ARRAY_SIZE(s
->out
));
1529 qemu_add_kbd_event_handler(musicpal_key_event
, s
);
1534 static const VMStateDescription musicpal_key_vmsd
= {
1535 .name
= "musicpal_key",
1537 .minimum_version_id
= 1,
1538 .fields
= (VMStateField
[]) {
1539 VMSTATE_UINT32(kbd_extended
, musicpal_key_state
),
1540 VMSTATE_UINT32(pressed_keys
, musicpal_key_state
),
1541 VMSTATE_END_OF_LIST()
1545 static void musicpal_key_class_init(ObjectClass
*klass
, void *data
)
1547 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1548 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1550 k
->init
= musicpal_key_init
;
1551 dc
->vmsd
= &musicpal_key_vmsd
;
1554 static const TypeInfo musicpal_key_info
= {
1555 .name
= TYPE_MUSICPAL_KEY
,
1556 .parent
= TYPE_SYS_BUS_DEVICE
,
1557 .instance_size
= sizeof(musicpal_key_state
),
1558 .class_init
= musicpal_key_class_init
,
1561 static struct arm_boot_info musicpal_binfo
= {
1562 .loader_start
= 0x0,
1566 static void musicpal_init(MachineState
*machine
)
1568 const char *cpu_model
= machine
->cpu_model
;
1569 const char *kernel_filename
= machine
->kernel_filename
;
1570 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1571 const char *initrd_filename
= machine
->initrd_filename
;
1575 DeviceState
*i2c_dev
;
1576 DeviceState
*lcd_dev
;
1577 DeviceState
*key_dev
;
1578 DeviceState
*wm8750_dev
;
1582 unsigned long flash_size
;
1584 MemoryRegion
*address_space_mem
= get_system_memory();
1585 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1586 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1589 cpu_model
= "arm926";
1591 cpu
= cpu_arm_init(cpu_model
);
1593 fprintf(stderr
, "Unable to find CPU definition\n");
1597 /* For now we use a fixed - the original - RAM size */
1598 memory_region_allocate_system_memory(ram
, NULL
, "musicpal.ram",
1599 MP_RAM_DEFAULT_SIZE
);
1600 memory_region_add_subregion(address_space_mem
, 0, ram
);
1602 memory_region_init_ram(sram
, NULL
, "musicpal.sram", MP_SRAM_SIZE
,
1604 vmstate_register_ram_global(sram
);
1605 memory_region_add_subregion(address_space_mem
, MP_SRAM_BASE
, sram
);
1607 dev
= sysbus_create_simple(TYPE_MV88W8618_PIC
, MP_PIC_BASE
,
1608 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
));
1609 for (i
= 0; i
< 32; i
++) {
1610 pic
[i
] = qdev_get_gpio_in(dev
, i
);
1612 sysbus_create_varargs(TYPE_MV88W8618_PIT
, MP_PIT_BASE
, pic
[MP_TIMER1_IRQ
],
1613 pic
[MP_TIMER2_IRQ
], pic
[MP_TIMER3_IRQ
],
1614 pic
[MP_TIMER4_IRQ
], NULL
);
1616 if (serial_hds
[0]) {
1617 serial_mm_init(address_space_mem
, MP_UART1_BASE
, 2, pic
[MP_UART1_IRQ
],
1618 1825000, serial_hds
[0], DEVICE_NATIVE_ENDIAN
);
1620 if (serial_hds
[1]) {
1621 serial_mm_init(address_space_mem
, MP_UART2_BASE
, 2, pic
[MP_UART2_IRQ
],
1622 1825000, serial_hds
[1], DEVICE_NATIVE_ENDIAN
);
1625 /* Register flash */
1626 dinfo
= drive_get(IF_PFLASH
, 0, 0);
1628 BlockBackend
*blk
= blk_by_legacy_dinfo(dinfo
);
1630 flash_size
= blk_getlength(blk
);
1631 if (flash_size
!= 8*1024*1024 && flash_size
!= 16*1024*1024 &&
1632 flash_size
!= 32*1024*1024) {
1633 fprintf(stderr
, "Invalid flash image size\n");
1638 * The original U-Boot accesses the flash at 0xFE000000 instead of
1639 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1640 * image is smaller than 32 MB.
1642 #ifdef TARGET_WORDS_BIGENDIAN
1643 pflash_cfi02_register(0x100000000ULL
-MP_FLASH_SIZE_MAX
, NULL
,
1644 "musicpal.flash", flash_size
,
1645 blk
, 0x10000, (flash_size
+ 0xffff) >> 16,
1646 MP_FLASH_SIZE_MAX
/ flash_size
,
1647 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1650 pflash_cfi02_register(0x100000000ULL
-MP_FLASH_SIZE_MAX
, NULL
,
1651 "musicpal.flash", flash_size
,
1652 blk
, 0x10000, (flash_size
+ 0xffff) >> 16,
1653 MP_FLASH_SIZE_MAX
/ flash_size
,
1654 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1659 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG
, MP_FLASHCFG_BASE
, NULL
);
1661 qemu_check_nic_model(&nd_table
[0], "mv88w8618");
1662 dev
= qdev_create(NULL
, TYPE_MV88W8618_ETH
);
1663 qdev_set_nic_properties(dev
, &nd_table
[0]);
1664 qdev_init_nofail(dev
);
1665 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, MP_ETH_BASE
);
1666 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[MP_ETH_IRQ
]);
1668 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE
, NULL
);
1670 sysbus_create_simple(TYPE_MUSICPAL_MISC
, MP_MISC_BASE
, NULL
);
1672 dev
= sysbus_create_simple(TYPE_MUSICPAL_GPIO
, MP_GPIO_BASE
,
1674 i2c_dev
= sysbus_create_simple("gpio_i2c", -1, NULL
);
1675 i2c
= (I2CBus
*)qdev_get_child_bus(i2c_dev
, "i2c");
1677 lcd_dev
= sysbus_create_simple(TYPE_MUSICPAL_LCD
, MP_LCD_BASE
, NULL
);
1678 key_dev
= sysbus_create_simple(TYPE_MUSICPAL_KEY
, -1, NULL
);
1681 qdev_connect_gpio_out(i2c_dev
, 0,
1682 qdev_get_gpio_in(dev
, MP_GPIO_I2C_DATA_BIT
));
1684 qdev_connect_gpio_out(dev
, 3, qdev_get_gpio_in(i2c_dev
, 0));
1686 qdev_connect_gpio_out(dev
, 4, qdev_get_gpio_in(i2c_dev
, 1));
1688 for (i
= 0; i
< 3; i
++) {
1689 qdev_connect_gpio_out(dev
, i
, qdev_get_gpio_in(lcd_dev
, i
));
1691 for (i
= 0; i
< 4; i
++) {
1692 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 8));
1694 for (i
= 4; i
< 8; i
++) {
1695 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 15));
1698 wm8750_dev
= i2c_create_slave(i2c
, "wm8750", MP_WM_ADDR
);
1699 dev
= qdev_create(NULL
, "mv88w8618_audio");
1700 s
= SYS_BUS_DEVICE(dev
);
1701 qdev_prop_set_ptr(dev
, "wm8750", wm8750_dev
);
1702 qdev_init_nofail(dev
);
1703 sysbus_mmio_map(s
, 0, MP_AUDIO_BASE
);
1704 sysbus_connect_irq(s
, 0, pic
[MP_AUDIO_IRQ
]);
1706 musicpal_binfo
.ram_size
= MP_RAM_DEFAULT_SIZE
;
1707 musicpal_binfo
.kernel_filename
= kernel_filename
;
1708 musicpal_binfo
.kernel_cmdline
= kernel_cmdline
;
1709 musicpal_binfo
.initrd_filename
= initrd_filename
;
1710 arm_load_kernel(cpu
, &musicpal_binfo
);
1713 static void musicpal_machine_init(MachineClass
*mc
)
1715 mc
->desc
= "Marvell 88w8618 / MusicPal (ARM926EJ-S)";
1716 mc
->init
= musicpal_init
;
1719 DEFINE_MACHINE("musicpal", musicpal_machine_init
)
1721 static void mv88w8618_wlan_class_init(ObjectClass
*klass
, void *data
)
1723 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1725 sdc
->init
= mv88w8618_wlan_init
;
1728 static const TypeInfo mv88w8618_wlan_info
= {
1729 .name
= "mv88w8618_wlan",
1730 .parent
= TYPE_SYS_BUS_DEVICE
,
1731 .instance_size
= sizeof(SysBusDevice
),
1732 .class_init
= mv88w8618_wlan_class_init
,
1735 static void musicpal_register_types(void)
1737 type_register_static(&mv88w8618_pic_info
);
1738 type_register_static(&mv88w8618_pit_info
);
1739 type_register_static(&mv88w8618_flashcfg_info
);
1740 type_register_static(&mv88w8618_eth_info
);
1741 type_register_static(&mv88w8618_wlan_info
);
1742 type_register_static(&musicpal_lcd_info
);
1743 type_register_static(&musicpal_gpio_info
);
1744 type_register_static(&musicpal_key_info
);
1745 type_register_static(&musicpal_misc_info
);
1748 type_init(musicpal_register_types
)