2 * Calxeda Highbank SoC emulation
4 * Copyright (c) 2010-2012 Calxeda
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "hw/sysbus.h"
22 #include "hw/arm/arm.h"
23 #include "hw/devices.h"
24 #include "hw/loader.h"
26 #include "sysemu/kvm.h"
27 #include "sysemu/sysemu.h"
28 #include "hw/boards.h"
29 #include "sysemu/block-backend.h"
30 #include "exec/address-spaces.h"
31 #include "qemu/error-report.h"
33 #define SMP_BOOT_ADDR 0x100
34 #define SMP_BOOT_REG 0x40
35 #define MPCORE_PERIPHBASE 0xfff10000
37 #define MVBAR_ADDR 0x200
38 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
44 static void hb_write_board_setup(ARMCPU
*cpu
,
45 const struct arm_boot_info
*info
)
47 arm_write_secure_board_setup_dummy_smc(cpu
, info
, MVBAR_ADDR
);
50 static void hb_write_secondary(ARMCPU
*cpu
, const struct arm_boot_info
*info
)
53 uint32_t smpboot
[] = {
54 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
55 0xe210000f, /* ands r0, r0, #0x0f */
56 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
57 0xe0830200, /* add r0, r3, r0, lsl #4 */
58 0xe59f2024, /* ldr r2, privbase */
59 0xe3a01001, /* mov r1, #1 */
60 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
61 0xe3a010ff, /* mov r1, #0xff */
62 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
65 0xe5901000, /* ldr r1, [r0] */
66 0xe1110001, /* tst r1, r1 */
67 0x0afffffb, /* beq <wfi> */
68 0xe12fff11, /* bx r1 */
69 MPCORE_PERIPHBASE
/* privbase: MPCore peripheral base address. */
71 for (n
= 0; n
< ARRAY_SIZE(smpboot
); n
++) {
72 smpboot
[n
] = tswap32(smpboot
[n
]);
74 rom_add_blob_fixed("smpboot", smpboot
, sizeof(smpboot
), SMP_BOOT_ADDR
);
77 static void hb_reset_secondary(ARMCPU
*cpu
, const struct arm_boot_info
*info
)
79 CPUARMState
*env
= &cpu
->env
;
81 switch (info
->nb_cpus
) {
83 address_space_stl_notdirty(&address_space_memory
,
84 SMP_BOOT_REG
+ 0x30, 0,
85 MEMTXATTRS_UNSPECIFIED
, NULL
);
87 address_space_stl_notdirty(&address_space_memory
,
88 SMP_BOOT_REG
+ 0x20, 0,
89 MEMTXATTRS_UNSPECIFIED
, NULL
);
91 address_space_stl_notdirty(&address_space_memory
,
92 SMP_BOOT_REG
+ 0x10, 0,
93 MEMTXATTRS_UNSPECIFIED
, NULL
);
94 env
->regs
[15] = SMP_BOOT_ADDR
;
101 #define NUM_REGS 0x200
102 static void hb_regs_write(void *opaque
, hwaddr offset
,
103 uint64_t value
, unsigned size
)
105 uint32_t *regs
= opaque
;
107 if (offset
== 0xf00) {
108 if (value
== 1 || value
== 2) {
109 qemu_system_reset_request();
110 } else if (value
== 3) {
111 qemu_system_shutdown_request();
115 regs
[offset
/4] = value
;
118 static uint64_t hb_regs_read(void *opaque
, hwaddr offset
,
121 uint32_t *regs
= opaque
;
122 uint32_t value
= regs
[offset
/4];
124 if ((offset
== 0x100) || (offset
== 0x108) || (offset
== 0x10C)) {
131 static const MemoryRegionOps hb_mem_ops
= {
132 .read
= hb_regs_read
,
133 .write
= hb_regs_write
,
134 .endianness
= DEVICE_NATIVE_ENDIAN
,
137 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
138 #define HIGHBANK_REGISTERS(obj) \
139 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
143 SysBusDevice parent_obj
;
147 uint32_t regs
[NUM_REGS
];
150 static VMStateDescription vmstate_highbank_regs
= {
151 .name
= "highbank-regs",
153 .minimum_version_id
= 0,
154 .fields
= (VMStateField
[]) {
155 VMSTATE_UINT32_ARRAY(regs
, HighbankRegsState
, NUM_REGS
),
156 VMSTATE_END_OF_LIST(),
160 static void highbank_regs_reset(DeviceState
*dev
)
162 HighbankRegsState
*s
= HIGHBANK_REGISTERS(dev
);
164 s
->regs
[0x40] = 0x05F20121;
166 s
->regs
[0x42] = 0x05F30121;
167 s
->regs
[0x43] = 0x05F40121;
170 static int highbank_regs_init(SysBusDevice
*dev
)
172 HighbankRegsState
*s
= HIGHBANK_REGISTERS(dev
);
174 memory_region_init_io(&s
->iomem
, OBJECT(s
), &hb_mem_ops
, s
->regs
,
175 "highbank_regs", 0x1000);
176 sysbus_init_mmio(dev
, &s
->iomem
);
181 static void highbank_regs_class_init(ObjectClass
*klass
, void *data
)
183 SysBusDeviceClass
*sbc
= SYS_BUS_DEVICE_CLASS(klass
);
184 DeviceClass
*dc
= DEVICE_CLASS(klass
);
186 sbc
->init
= highbank_regs_init
;
187 dc
->desc
= "Calxeda Highbank registers";
188 dc
->vmsd
= &vmstate_highbank_regs
;
189 dc
->reset
= highbank_regs_reset
;
192 static const TypeInfo highbank_regs_info
= {
193 .name
= TYPE_HIGHBANK_REGISTERS
,
194 .parent
= TYPE_SYS_BUS_DEVICE
,
195 .instance_size
= sizeof(HighbankRegsState
),
196 .class_init
= highbank_regs_class_init
,
199 static void highbank_regs_register_types(void)
201 type_register_static(&highbank_regs_info
);
204 type_init(highbank_regs_register_types
)
206 static struct arm_boot_info highbank_binfo
;
213 /* ram_size must be set to match the upper bound of memory in the
214 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
215 * normally 0xff900000 or -m 4089. When running this board on a
216 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
217 * device tree and pass -m 2047 to QEMU.
219 static void calxeda_init(MachineState
*machine
, enum cxmachines machine_id
)
221 ram_addr_t ram_size
= machine
->ram_size
;
222 const char *cpu_model
= machine
->cpu_model
;
223 const char *kernel_filename
= machine
->kernel_filename
;
224 const char *kernel_cmdline
= machine
->kernel_cmdline
;
225 const char *initrd_filename
= machine
->initrd_filename
;
226 DeviceState
*dev
= NULL
;
227 SysBusDevice
*busdev
;
232 MemoryRegion
*sysram
;
234 MemoryRegion
*sysmem
;
235 char *sysboot_filename
;
237 switch (machine_id
) {
238 case CALXEDA_HIGHBANK
:
239 cpu_model
= "cortex-a9";
242 cpu_model
= "cortex-a15";
246 for (n
= 0; n
< smp_cpus
; n
++) {
247 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpu_model
);
251 cpuobj
= object_new(object_class_get_name(oc
));
252 cpu
= ARM_CPU(cpuobj
);
254 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_SMC
,
255 "psci-conduit", &error_abort
);
258 /* Secondary CPUs start in PSCI powered-down state */
259 object_property_set_bool(cpuobj
, true,
260 "start-powered-off", &error_abort
);
263 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
264 object_property_set_int(cpuobj
, MPCORE_PERIPHBASE
,
265 "reset-cbar", &error_abort
);
267 object_property_set_bool(cpuobj
, true, "realized", &error_fatal
);
268 cpu_irq
[n
] = qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
);
269 cpu_fiq
[n
] = qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_FIQ
);
272 sysmem
= get_system_memory();
273 dram
= g_new(MemoryRegion
, 1);
274 memory_region_allocate_system_memory(dram
, NULL
, "highbank.dram", ram_size
);
275 /* SDRAM at address zero. */
276 memory_region_add_subregion(sysmem
, 0, dram
);
278 sysram
= g_new(MemoryRegion
, 1);
279 memory_region_init_ram(sysram
, NULL
, "highbank.sysram", 0x8000,
281 memory_region_add_subregion(sysmem
, 0xfff88000, sysram
);
282 if (bios_name
!= NULL
) {
283 sysboot_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
284 if (sysboot_filename
!= NULL
) {
285 if (load_image_targphys(sysboot_filename
, 0xfff88000, 0x8000) < 0) {
286 error_report("Unable to load %s", bios_name
);
289 g_free(sysboot_filename
);
291 error_report("Unable to find %s", bios_name
);
296 switch (machine_id
) {
297 case CALXEDA_HIGHBANK
:
298 dev
= qdev_create(NULL
, "l2x0");
299 qdev_init_nofail(dev
);
300 busdev
= SYS_BUS_DEVICE(dev
);
301 sysbus_mmio_map(busdev
, 0, 0xfff12000);
303 dev
= qdev_create(NULL
, "a9mpcore_priv");
306 dev
= qdev_create(NULL
, "a15mpcore_priv");
309 qdev_prop_set_uint32(dev
, "num-cpu", smp_cpus
);
310 qdev_prop_set_uint32(dev
, "num-irq", NIRQ_GIC
);
311 qdev_init_nofail(dev
);
312 busdev
= SYS_BUS_DEVICE(dev
);
313 sysbus_mmio_map(busdev
, 0, MPCORE_PERIPHBASE
);
314 for (n
= 0; n
< smp_cpus
; n
++) {
315 sysbus_connect_irq(busdev
, n
, cpu_irq
[n
]);
316 sysbus_connect_irq(busdev
, n
+ smp_cpus
, cpu_fiq
[n
]);
319 for (n
= 0; n
< 128; n
++) {
320 pic
[n
] = qdev_get_gpio_in(dev
, n
);
323 dev
= qdev_create(NULL
, "sp804");
324 qdev_prop_set_uint32(dev
, "freq0", 150000000);
325 qdev_prop_set_uint32(dev
, "freq1", 150000000);
326 qdev_init_nofail(dev
);
327 busdev
= SYS_BUS_DEVICE(dev
);
328 sysbus_mmio_map(busdev
, 0, 0xfff34000);
329 sysbus_connect_irq(busdev
, 0, pic
[18]);
330 sysbus_create_simple("pl011", 0xfff36000, pic
[20]);
332 dev
= qdev_create(NULL
, "highbank-regs");
333 qdev_init_nofail(dev
);
334 busdev
= SYS_BUS_DEVICE(dev
);
335 sysbus_mmio_map(busdev
, 0, 0xfff3c000);
337 sysbus_create_simple("pl061", 0xfff30000, pic
[14]);
338 sysbus_create_simple("pl061", 0xfff31000, pic
[15]);
339 sysbus_create_simple("pl061", 0xfff32000, pic
[16]);
340 sysbus_create_simple("pl061", 0xfff33000, pic
[17]);
341 sysbus_create_simple("pl031", 0xfff35000, pic
[19]);
342 sysbus_create_simple("pl022", 0xfff39000, pic
[23]);
344 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic
[83]);
346 if (nd_table
[0].used
) {
347 qemu_check_nic_model(&nd_table
[0], "xgmac");
348 dev
= qdev_create(NULL
, "xgmac");
349 qdev_set_nic_properties(dev
, &nd_table
[0]);
350 qdev_init_nofail(dev
);
351 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xfff50000);
352 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[77]);
353 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 1, pic
[78]);
354 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 2, pic
[79]);
356 qemu_check_nic_model(&nd_table
[1], "xgmac");
357 dev
= qdev_create(NULL
, "xgmac");
358 qdev_set_nic_properties(dev
, &nd_table
[1]);
359 qdev_init_nofail(dev
);
360 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xfff51000);
361 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[80]);
362 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 1, pic
[81]);
363 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 2, pic
[82]);
366 highbank_binfo
.ram_size
= ram_size
;
367 highbank_binfo
.kernel_filename
= kernel_filename
;
368 highbank_binfo
.kernel_cmdline
= kernel_cmdline
;
369 highbank_binfo
.initrd_filename
= initrd_filename
;
370 /* highbank requires a dtb in order to boot, and the dtb will override
371 * the board ID. The following value is ignored, so set it to -1 to be
372 * clear that the value is meaningless.
374 highbank_binfo
.board_id
= -1;
375 highbank_binfo
.nb_cpus
= smp_cpus
;
376 highbank_binfo
.loader_start
= 0;
377 highbank_binfo
.write_secondary_boot
= hb_write_secondary
;
378 highbank_binfo
.secondary_cpu_reset_hook
= hb_reset_secondary
;
379 if (!kvm_enabled()) {
380 highbank_binfo
.board_setup_addr
= BOARD_SETUP_ADDR
;
381 highbank_binfo
.write_board_setup
= hb_write_board_setup
;
382 highbank_binfo
.secure_board_setup
= true;
384 error_report("WARNING: cannot load built-in Monitor support "
385 "if KVM is enabled. Some guests (such as Linux) "
389 arm_load_kernel(ARM_CPU(first_cpu
), &highbank_binfo
);
392 static void highbank_init(MachineState
*machine
)
394 calxeda_init(machine
, CALXEDA_HIGHBANK
);
397 static void midway_init(MachineState
*machine
)
399 calxeda_init(machine
, CALXEDA_MIDWAY
);
402 static void highbank_class_init(ObjectClass
*oc
, void *data
)
404 MachineClass
*mc
= MACHINE_CLASS(oc
);
406 mc
->desc
= "Calxeda Highbank (ECX-1000)";
407 mc
->init
= highbank_init
;
408 mc
->block_default_type
= IF_SCSI
;
412 static const TypeInfo highbank_type
= {
413 .name
= MACHINE_TYPE_NAME("highbank"),
414 .parent
= TYPE_MACHINE
,
415 .class_init
= highbank_class_init
,
418 static void midway_class_init(ObjectClass
*oc
, void *data
)
420 MachineClass
*mc
= MACHINE_CLASS(oc
);
422 mc
->desc
= "Calxeda Midway (ECX-2000)";
423 mc
->init
= midway_init
;
424 mc
->block_default_type
= IF_SCSI
;
428 static const TypeInfo midway_type
= {
429 .name
= MACHINE_TYPE_NAME("midway"),
430 .parent
= TYPE_MACHINE
,
431 .class_init
= midway_class_init
,
434 static void calxeda_machines_init(void)
436 type_register_static(&highbank_type
);
437 type_register_static(&midway_type
);
440 machine_init(calxeda_machines_init
)