target-ppc/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "sysemu/kvm.h"
   4 #include "helper_regs.h"
   5
   6 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
   7 {
   8     PowerPCCPU *cpu = opaque;
   9     CPUPPCState *env = &cpu->env;
  10     unsigned int i, j;
  11     target_ulong sdr1;
  12     uint32_t fpscr;
  13     target_ulong xer;
  14
  15     for (i = 0; i < 32; i++)
  16         qemu_get_betls(f, &env->gpr[i]);
  17 #if !defined(TARGET_PPC64)
  18     for (i = 0; i < 32; i++)
  19         qemu_get_betls(f, &env->gprh[i]);
  20 #endif
  21     qemu_get_betls(f, &env->lr);
  22     qemu_get_betls(f, &env->ctr);
  23     for (i = 0; i < 8; i++)
  24         qemu_get_be32s(f, &env->crf[i]);
  25     qemu_get_betls(f, &xer);
  26     cpu_write_xer(env, xer);
  27     qemu_get_betls(f, &env->reserve_addr);
  28     qemu_get_betls(f, &env->msr);
  29     for (i = 0; i < 4; i++)
  30         qemu_get_betls(f, &env->tgpr[i]);
  31     for (i = 0; i < 32; i++) {
  32         union {
  33             float64 d;
  34             uint64_t l;
  35         } u;
  36         u.l = qemu_get_be64(f);
  37         env->fpr[i] = u.d;
  38     }
  39     qemu_get_be32s(f, &fpscr);
  40     env->fpscr = fpscr;
  41     qemu_get_sbe32s(f, &env->access_type);
  42 #if defined(TARGET_PPC64)
  43     qemu_get_betls(f, &env->spr[SPR_ASR]);
  44     qemu_get_sbe32s(f, &env->slb_nr);
  45 #endif
  46     qemu_get_betls(f, &sdr1);
  47     for (i = 0; i < 32; i++)
  48         qemu_get_betls(f, &env->sr[i]);
  49     for (i = 0; i < 2; i++)
  50         for (j = 0; j < 8; j++)
  51             qemu_get_betls(f, &env->DBAT[i][j]);
  52     for (i = 0; i < 2; i++)
  53         for (j = 0; j < 8; j++)
  54             qemu_get_betls(f, &env->IBAT[i][j]);
  55     qemu_get_sbe32s(f, &env->nb_tlb);
  56     qemu_get_sbe32s(f, &env->tlb_per_way);
  57     qemu_get_sbe32s(f, &env->nb_ways);
  58     qemu_get_sbe32s(f, &env->last_way);
  59     qemu_get_sbe32s(f, &env->id_tlbs);
  60     qemu_get_sbe32s(f, &env->nb_pids);
  61     if (env->tlb.tlb6) {
  62         // XXX assumes 6xx
  63         for (i = 0; i < env->nb_tlb; i++) {
  64             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  65             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  66             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  67         }
  68     }
  69     for (i = 0; i < 4; i++)
  70         qemu_get_betls(f, &env->pb[i]);
  71     for (i = 0; i < 1024; i++)
  72         qemu_get_betls(f, &env->spr[i]);
  73     if (!env->external_htab) {
  74         ppc_store_sdr1(env, sdr1);
  75     }
  76     qemu_get_be32s(f, &env->vscr);
  77     qemu_get_be64s(f, &env->spe_acc);
  78     qemu_get_be32s(f, &env->spe_fscr);
  79     qemu_get_betls(f, &env->msr_mask);
  80     qemu_get_be32s(f, &env->flags);
  81     qemu_get_sbe32s(f, &env->error_code);
  82     qemu_get_be32s(f, &env->pending_interrupts);
  83     qemu_get_be32s(f, &env->irq_input_state);
  84     for (i = 0; i < POWERPC_EXCP_NB; i++)
  85         qemu_get_betls(f, &env->excp_vectors[i]);
  86     qemu_get_betls(f, &env->excp_prefix);
  87     qemu_get_betls(f, &env->ivor_mask);
  88     qemu_get_betls(f, &env->ivpr_mask);
  89     qemu_get_betls(f, &env->hreset_vector);
  90     qemu_get_betls(f, &env->nip);
  91     qemu_get_betls(f, &env->hflags);
  92     qemu_get_betls(f, &env->hflags_nmsr);
  93     qemu_get_sbe32s(f, &env->mmu_idx);
  94     qemu_get_sbe32(f); /* Discard unused power_mode */
  95
  96     return 0;
  97 }
  98
  99 static int get_avr(QEMUFile *f, void *pv, size_t size)
 100 {
 101     ppc_avr_t *v = pv;
 102
 103     v->u64[0] = qemu_get_be64(f);
 104     v->u64[1] = qemu_get_be64(f);
 105
 106     return 0;
 107 }
 108
 109 static void put_avr(QEMUFile *f, void *pv, size_t size)
 110 {
 111     ppc_avr_t *v = pv;
 112
 113     qemu_put_be64(f, v->u64[0]);
 114     qemu_put_be64(f, v->u64[1]);
 115 }
 116
 117 static const VMStateInfo vmstate_info_avr = {
 118     .name = "avr",
 119     .get  = get_avr,
 120     .put  = put_avr,
 121 };
 122
 123 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 124     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
 125
 126 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 127     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 128
 129 static void cpu_pre_save(void *opaque)
 130 {
 131     PowerPCCPU *cpu = opaque;
 132     CPUPPCState *env = &cpu->env;
 133     int i;
 134
 135     env->spr[SPR_LR] = env->lr;
 136     env->spr[SPR_CTR] = env->ctr;
 137     env->spr[SPR_XER] = env->xer;
 138 #if defined(TARGET_PPC64)
 139     env->spr[SPR_CFAR] = env->cfar;
 140 #endif
 141     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 142
 143     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 144         env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
 145         env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
 146         env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
 147         env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
 148     }
 149     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 150         env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
 151         env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
 152         env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
 153         env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
 154     }
 155 }
 156
 157 static int cpu_post_load(void *opaque, int version_id)
 158 {
 159     PowerPCCPU *cpu = opaque;
 160     CPUPPCState *env = &cpu->env;
 161     int i;
 162     target_ulong msr;
 163
 164     /*
 165      * We always ignore the source PVR. The user or management
 166      * software has to take care of running QEMU in a compatible mode.
 167      */
 168     env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 169     env->lr = env->spr[SPR_LR];
 170     env->ctr = env->spr[SPR_CTR];
 171     env->xer = env->spr[SPR_XER];
 172 #if defined(TARGET_PPC64)
 173     env->cfar = env->spr[SPR_CFAR];
 174 #endif
 175     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 176
 177     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 178         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
 179         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
 180         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
 181         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
 182     }
 183     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 184         env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
 185         env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
 186         env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
 187         env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
 188     }
 189
 190     if (!env->external_htab) {
 191         /* Restore htab_base and htab_mask variables */
 192         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 193     }
 194
 195     /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
 196     msr = env->msr;
 197     env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
 198     ppc_store_msr(env, msr);
 199
 200     hreg_compute_mem_idx(env);
 201
 202     return 0;
 203 }
 204
 205 static bool fpu_needed(void *opaque)
 206 {
 207     PowerPCCPU *cpu = opaque;
 208
 209     return (cpu->env.insns_flags & PPC_FLOAT);
 210 }
 211
 212 static const VMStateDescription vmstate_fpu = {
 213     .name = "cpu/fpu",
 214     .version_id = 1,
 215     .minimum_version_id = 1,
 216     .fields = (VMStateField[]) {
 217         VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
 218         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 219         VMSTATE_END_OF_LIST()
 220     },
 221 };
 222
 223 static bool altivec_needed(void *opaque)
 224 {
 225     PowerPCCPU *cpu = opaque;
 226
 227     return (cpu->env.insns_flags & PPC_ALTIVEC);
 228 }
 229
 230 static const VMStateDescription vmstate_altivec = {
 231     .name = "cpu/altivec",
 232     .version_id = 1,
 233     .minimum_version_id = 1,
 234     .fields = (VMStateField[]) {
 235         VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
 236         VMSTATE_UINT32(env.vscr, PowerPCCPU),
 237         VMSTATE_END_OF_LIST()
 238     },
 239 };
 240
 241 static bool vsx_needed(void *opaque)
 242 {
 243     PowerPCCPU *cpu = opaque;
 244
 245     return (cpu->env.insns_flags2 & PPC2_VSX);
 246 }
 247
 248 static const VMStateDescription vmstate_vsx = {
 249     .name = "cpu/vsx",
 250     .version_id = 1,
 251     .minimum_version_id = 1,
 252     .fields = (VMStateField[]) {
 253         VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
 254         VMSTATE_END_OF_LIST()
 255     },
 256 };
 257
 258 #ifdef TARGET_PPC64
 259 /* Transactional memory state */
 260 static bool tm_needed(void *opaque)
 261 {
 262     PowerPCCPU *cpu = opaque;
 263     CPUPPCState *env = &cpu->env;
 264     return msr_ts;
 265 }
 266
 267 static const VMStateDescription vmstate_tm = {
 268     .name = "cpu/tm",
 269     .version_id = 1,
 270     .minimum_version_id = 1,
 271     .minimum_version_id_old = 1,
 272     .fields      = (VMStateField []) {
 273         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 274         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 275         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 276         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 277         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 278         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 279         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 280         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 281         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 282         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 283         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 284         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 285         VMSTATE_END_OF_LIST()
 286     },
 287 };
 288 #endif
 289
 290 static bool sr_needed(void *opaque)
 291 {
 292 #ifdef TARGET_PPC64
 293     PowerPCCPU *cpu = opaque;
 294
 295     return !(cpu->env.mmu_model & POWERPC_MMU_64);
 296 #else
 297     return true;
 298 #endif
 299 }
 300
 301 static const VMStateDescription vmstate_sr = {
 302     .name = "cpu/sr",
 303     .version_id = 1,
 304     .minimum_version_id = 1,
 305     .fields = (VMStateField[]) {
 306         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 307         VMSTATE_END_OF_LIST()
 308     },
 309 };
 310
 311 #ifdef TARGET_PPC64
 312 static int get_slbe(QEMUFile *f, void *pv, size_t size)
 313 {
 314     ppc_slb_t *v = pv;
 315
 316     v->esid = qemu_get_be64(f);
 317     v->vsid = qemu_get_be64(f);
 318
 319     return 0;
 320 }
 321
 322 static void put_slbe(QEMUFile *f, void *pv, size_t size)
 323 {
 324     ppc_slb_t *v = pv;
 325
 326     qemu_put_be64(f, v->esid);
 327     qemu_put_be64(f, v->vsid);
 328 }
 329
 330 static const VMStateInfo vmstate_info_slbe = {
 331     .name = "slbe",
 332     .get  = get_slbe,
 333     .put  = put_slbe,
 334 };
 335
 336 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 337     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 338
 339 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 340     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 341
 342 static bool slb_needed(void *opaque)
 343 {
 344     PowerPCCPU *cpu = opaque;
 345
 346     /* We don't support any of the old segment table based 64-bit CPUs */
 347     return (cpu->env.mmu_model & POWERPC_MMU_64);
 348 }
 349
 350 static const VMStateDescription vmstate_slb = {
 351     .name = "cpu/slb",
 352     .version_id = 1,
 353     .minimum_version_id = 1,
 354     .fields = (VMStateField[]) {
 355         VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
 356         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 357         VMSTATE_END_OF_LIST()
 358     }
 359 };
 360 #endif /* TARGET_PPC64 */
 361
 362 static const VMStateDescription vmstate_tlb6xx_entry = {
 363     .name = "cpu/tlb6xx_entry",
 364     .version_id = 1,
 365     .minimum_version_id = 1,
 366     .fields = (VMStateField[]) {
 367         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 368         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 369         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 370         VMSTATE_END_OF_LIST()
 371     },
 372 };
 373
 374 static bool tlb6xx_needed(void *opaque)
 375 {
 376     PowerPCCPU *cpu = opaque;
 377     CPUPPCState *env = &cpu->env;
 378
 379     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 380 }
 381
 382 static const VMStateDescription vmstate_tlb6xx = {
 383     .name = "cpu/tlb6xx",
 384     .version_id = 1,
 385     .minimum_version_id = 1,
 386     .fields = (VMStateField[]) {
 387         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 388         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 389                                             env.nb_tlb,
 390                                             vmstate_tlb6xx_entry,
 391                                             ppc6xx_tlb_t),
 392         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 393         VMSTATE_END_OF_LIST()
 394     }
 395 };
 396
 397 static const VMStateDescription vmstate_tlbemb_entry = {
 398     .name = "cpu/tlbemb_entry",
 399     .version_id = 1,
 400     .minimum_version_id = 1,
 401     .fields = (VMStateField[]) {
 402         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 403         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 404         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 405         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 406         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 407         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 408         VMSTATE_END_OF_LIST()
 409     },
 410 };
 411
 412 static bool tlbemb_needed(void *opaque)
 413 {
 414     PowerPCCPU *cpu = opaque;
 415     CPUPPCState *env = &cpu->env;
 416
 417     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 418 }
 419
 420 static bool pbr403_needed(void *opaque)
 421 {
 422     PowerPCCPU *cpu = opaque;
 423     uint32_t pvr = cpu->env.spr[SPR_PVR];
 424
 425     return (pvr & 0xffff0000) == 0x00200000;
 426 }
 427
 428 static const VMStateDescription vmstate_pbr403 = {
 429     .name = "cpu/pbr403",
 430     .version_id = 1,
 431     .minimum_version_id = 1,
 432     .fields = (VMStateField[]) {
 433         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 434         VMSTATE_END_OF_LIST()
 435     },
 436 };
 437
 438 static const VMStateDescription vmstate_tlbemb = {
 439     .name = "cpu/tlb6xx",
 440     .version_id = 1,
 441     .minimum_version_id = 1,
 442     .fields = (VMStateField[]) {
 443         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 444         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 445                                             env.nb_tlb,
 446                                             vmstate_tlbemb_entry,
 447                                             ppcemb_tlb_t),
 448         /* 403 protection registers */
 449         VMSTATE_END_OF_LIST()
 450     },
 451     .subsections = (VMStateSubsection []) {
 452         {
 453             .vmsd = &vmstate_pbr403,
 454             .needed = pbr403_needed,
 455         } , {
 456             /* empty */
 457         }
 458     }
 459 };
 460
 461 static const VMStateDescription vmstate_tlbmas_entry = {
 462     .name = "cpu/tlbmas_entry",
 463     .version_id = 1,
 464     .minimum_version_id = 1,
 465     .fields = (VMStateField[]) {
 466         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 467         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 468         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 469         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 470         VMSTATE_END_OF_LIST()
 471     },
 472 };
 473
 474 static bool tlbmas_needed(void *opaque)
 475 {
 476     PowerPCCPU *cpu = opaque;
 477     CPUPPCState *env = &cpu->env;
 478
 479     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 480 }
 481
 482 static const VMStateDescription vmstate_tlbmas = {
 483     .name = "cpu/tlbmas",
 484     .version_id = 1,
 485     .minimum_version_id = 1,
 486     .fields = (VMStateField[]) {
 487         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 488         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 489                                             env.nb_tlb,
 490                                             vmstate_tlbmas_entry,
 491                                             ppcmas_tlb_t),
 492         VMSTATE_END_OF_LIST()
 493     }
 494 };
 495
 496 const VMStateDescription vmstate_ppc_cpu = {
 497     .name = "cpu",
 498     .version_id = 5,
 499     .minimum_version_id = 5,
 500     .minimum_version_id_old = 4,
 501     .load_state_old = cpu_load_old,
 502     .pre_save = cpu_pre_save,
 503     .post_load = cpu_post_load,
 504     .fields = (VMStateField[]) {
 505         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 506
 507         /* User mode architected state */
 508         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 509 #if !defined(TARGET_PPC64)
 510         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 511 #endif
 512         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 513         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 514
 515         /* SPRs */
 516         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 517         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 518
 519         /* Reservation */
 520         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 521
 522         /* Supervisor mode architected state */
 523         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 524
 525         /* Internal state */
 526         VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
 527         /* FIXME: access_type? */
 528
 529         /* Sanity checking */
 530         VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
 531         VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
 532         VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
 533         VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
 534         VMSTATE_END_OF_LIST()
 535     },
 536     .subsections = (VMStateSubsection []) {
 537         {
 538             .vmsd = &vmstate_fpu,
 539             .needed = fpu_needed,
 540         } , {
 541             .vmsd = &vmstate_altivec,
 542             .needed = altivec_needed,
 543         } , {
 544             .vmsd = &vmstate_vsx,
 545             .needed = vsx_needed,
 546         } , {
 547             .vmsd = &vmstate_sr,
 548             .needed = sr_needed,
 549         } , {
 550 #ifdef TARGET_PPC64
 551             .vmsd = &vmstate_tm,
 552             .needed = tm_needed,
 553         } , {
 554             .vmsd = &vmstate_slb,
 555             .needed = slb_needed,
 556         } , {
 557 #endif /* TARGET_PPC64 */
 558             .vmsd = &vmstate_tlb6xx,
 559             .needed = tlb6xx_needed,
 560         } , {
 561             .vmsd = &vmstate_tlbemb,
 562             .needed = tlbemb_needed,
 563         } , {
 564             .vmsd = &vmstate_tlbmas,
 565             .needed = tlbmas_needed,
 566         } , {
 567             /* empty */
 568         }
 569     }
 570 };