4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
18 * Contributions after 2012-01-13 are licensed under the terms of the
19 * GNU GPL, version 2 or (at your option) any later version.
31 #include "exec-memory.h"
36 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 # define PIIX4_DPRINTF(format, ...) do { } while (0)
41 #define GPE_BASE 0xafe0
44 #define PCI_HOTPLUG_ADDR 0xae00
45 #define PCI_HOTPLUG_SIZE 0x000f
46 #define PCI_UP_BASE 0xae00
47 #define PCI_DOWN_BASE 0xae04
48 #define PCI_EJ_BASE 0xae08
49 #define PCI_RMV_BASE 0xae0c
51 #define PIIX4_PCI_HOTPLUG_STATUS 2
54 uint32_t up
; /* deprecated, maintained for migration compatibility */
58 typedef struct PIIX4PMState
{
73 Notifier machine_ready
;
74 Notifier powerdown_notifier
;
77 struct pci_status pci0_status
;
78 uint32_t pci0_hotplug_enable
;
79 uint32_t pci0_slot_device_present
;
86 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
);
88 #define ACPI_ENABLE 0xf1
89 #define ACPI_DISABLE 0xf0
91 static void pm_update_sci(PIIX4PMState
*s
)
95 pmsts
= acpi_pm1_evt_get_sts(&s
->ar
);
96 sci_level
= (((pmsts
& s
->ar
.pm1
.evt
.en
) &
97 (ACPI_BITMASK_RT_CLOCK_ENABLE
|
98 ACPI_BITMASK_POWER_BUTTON_ENABLE
|
99 ACPI_BITMASK_GLOBAL_LOCK_ENABLE
|
100 ACPI_BITMASK_TIMER_ENABLE
)) != 0) ||
101 (((s
->ar
.gpe
.sts
[0] & s
->ar
.gpe
.en
[0])
102 & PIIX4_PCI_HOTPLUG_STATUS
) != 0);
104 qemu_set_irq(s
->irq
, sci_level
);
105 /* schedule a timer interruption if needed */
106 acpi_pm_tmr_update(&s
->ar
, (s
->ar
.pm1
.evt
.en
& ACPI_BITMASK_TIMER_ENABLE
) &&
107 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
));
110 static void pm_tmr_timer(ACPIREGS
*ar
)
112 PIIX4PMState
*s
= container_of(ar
, PIIX4PMState
, ar
);
116 static void apm_ctrl_changed(uint32_t val
, void *arg
)
118 PIIX4PMState
*s
= arg
;
120 /* ACPI specs 3.0, 4.7.2.5 */
121 acpi_pm1_cnt_update(&s
->ar
, val
== ACPI_ENABLE
, val
== ACPI_DISABLE
);
123 if (s
->dev
.config
[0x5b] & (1 << 1)) {
125 qemu_irq_raise(s
->smi_irq
);
130 static void pm_io_space_update(PIIX4PMState
*s
)
134 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
135 pm_io_base
&= 0xffc0;
137 memory_region_transaction_begin();
138 memory_region_set_enabled(&s
->io
, s
->dev
.config
[0x80] & 1);
139 memory_region_set_address(&s
->io
, pm_io_base
);
140 memory_region_transaction_commit();
143 static void smbus_io_space_update(PIIX4PMState
*s
)
145 s
->smb_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x90));
146 s
->smb_io_base
&= 0xffc0;
148 memory_region_transaction_begin();
149 memory_region_set_enabled(&s
->smb
.io
, s
->dev
.config
[0xd2] & 1);
150 memory_region_set_address(&s
->smb
.io
, s
->smb_io_base
);
151 memory_region_transaction_commit();
154 static void pm_write_config(PCIDevice
*d
,
155 uint32_t address
, uint32_t val
, int len
)
157 pci_default_write_config(d
, address
, val
, len
);
158 if (range_covers_byte(address
, len
, 0x80) ||
159 ranges_overlap(address
, len
, 0x40, 4)) {
160 pm_io_space_update((PIIX4PMState
*)d
);
162 if (range_covers_byte(address
, len
, 0xd2) ||
163 ranges_overlap(address
, len
, 0x90, 4)) {
164 smbus_io_space_update((PIIX4PMState
*)d
);
168 static void vmstate_pci_status_pre_save(void *opaque
)
170 struct pci_status
*pci0_status
= opaque
;
171 PIIX4PMState
*s
= container_of(pci0_status
, PIIX4PMState
, pci0_status
);
173 /* We no longer track up, so build a safe value for migrating
174 * to a version that still does... of course these might get lost
175 * by an old buggy implementation, but we try. */
176 pci0_status
->up
= s
->pci0_slot_device_present
& s
->pci0_hotplug_enable
;
179 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
181 PIIX4PMState
*s
= opaque
;
183 pm_io_space_update(s
);
187 #define VMSTATE_GPE_ARRAY(_field, _state) \
189 .name = (stringify(_field)), \
191 .info = &vmstate_info_uint16, \
192 .size = sizeof(uint16_t), \
193 .flags = VMS_SINGLE | VMS_POINTER, \
194 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
197 static const VMStateDescription vmstate_gpe
= {
200 .minimum_version_id
= 1,
201 .minimum_version_id_old
= 1,
202 .fields
= (VMStateField
[]) {
203 VMSTATE_GPE_ARRAY(sts
, ACPIGPE
),
204 VMSTATE_GPE_ARRAY(en
, ACPIGPE
),
205 VMSTATE_END_OF_LIST()
209 static const VMStateDescription vmstate_pci_status
= {
210 .name
= "pci_status",
212 .minimum_version_id
= 1,
213 .minimum_version_id_old
= 1,
214 .pre_save
= vmstate_pci_status_pre_save
,
215 .fields
= (VMStateField
[]) {
216 VMSTATE_UINT32(up
, struct pci_status
),
217 VMSTATE_UINT32(down
, struct pci_status
),
218 VMSTATE_END_OF_LIST()
222 static int acpi_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
224 PIIX4PMState
*s
= opaque
;
228 ret
= pci_device_load(&s
->dev
, f
);
232 qemu_get_be16s(f
, &s
->ar
.pm1
.evt
.sts
);
233 qemu_get_be16s(f
, &s
->ar
.pm1
.evt
.en
);
234 qemu_get_be16s(f
, &s
->ar
.pm1
.cnt
.cnt
);
236 ret
= vmstate_load_state(f
, &vmstate_apm
, opaque
, 1);
241 qemu_get_timer(f
, s
->ar
.tmr
.timer
);
242 qemu_get_sbe64s(f
, &s
->ar
.tmr
.overflow_time
);
244 qemu_get_be16s(f
, (uint16_t *)s
->ar
.gpe
.sts
);
245 for (i
= 0; i
< 3; i
++) {
246 qemu_get_be16s(f
, &temp
);
249 qemu_get_be16s(f
, (uint16_t *)s
->ar
.gpe
.en
);
250 for (i
= 0; i
< 3; i
++) {
251 qemu_get_be16s(f
, &temp
);
254 ret
= vmstate_load_state(f
, &vmstate_pci_status
, opaque
, 1);
258 /* qemu-kvm 1.2 uses version 3 but advertised as 2
259 * To support incoming qemu-kvm 1.2 migration, change version_id
260 * and minimum_version_id to 2 below (which breaks migration from
264 static const VMStateDescription vmstate_acpi
= {
267 .minimum_version_id
= 3,
268 .minimum_version_id_old
= 1,
269 .load_state_old
= acpi_load_old
,
270 .post_load
= vmstate_acpi_post_load
,
271 .fields
= (VMStateField
[]) {
272 VMSTATE_PCI_DEVICE(dev
, PIIX4PMState
),
273 VMSTATE_UINT16(ar
.pm1
.evt
.sts
, PIIX4PMState
),
274 VMSTATE_UINT16(ar
.pm1
.evt
.en
, PIIX4PMState
),
275 VMSTATE_UINT16(ar
.pm1
.cnt
.cnt
, PIIX4PMState
),
276 VMSTATE_STRUCT(apm
, PIIX4PMState
, 0, vmstate_apm
, APMState
),
277 VMSTATE_TIMER(ar
.tmr
.timer
, PIIX4PMState
),
278 VMSTATE_INT64(ar
.tmr
.overflow_time
, PIIX4PMState
),
279 VMSTATE_STRUCT(ar
.gpe
, PIIX4PMState
, 2, vmstate_gpe
, ACPIGPE
),
280 VMSTATE_STRUCT(pci0_status
, PIIX4PMState
, 2, vmstate_pci_status
,
282 VMSTATE_END_OF_LIST()
286 static void acpi_piix_eject_slot(PIIX4PMState
*s
, unsigned slots
)
288 BusChild
*kid
, *next
;
289 BusState
*bus
= qdev_get_parent_bus(&s
->dev
.qdev
);
290 int slot
= ffs(slots
) - 1;
291 bool slot_free
= true;
293 /* Mark request as complete */
294 s
->pci0_status
.down
&= ~(1U << slot
);
296 QTAILQ_FOREACH_SAFE(kid
, &bus
->children
, sibling
, next
) {
297 DeviceState
*qdev
= kid
->child
;
298 PCIDevice
*dev
= PCI_DEVICE(qdev
);
299 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
300 if (PCI_SLOT(dev
->devfn
) == slot
) {
301 if (pc
->no_hotplug
) {
309 s
->pci0_slot_device_present
&= ~(1U << slot
);
313 static void piix4_update_hotplug(PIIX4PMState
*s
)
315 PCIDevice
*dev
= &s
->dev
;
316 BusState
*bus
= qdev_get_parent_bus(&dev
->qdev
);
317 BusChild
*kid
, *next
;
319 /* Execute any pending removes during reset */
320 while (s
->pci0_status
.down
) {
321 acpi_piix_eject_slot(s
, s
->pci0_status
.down
);
324 s
->pci0_hotplug_enable
= ~0;
325 s
->pci0_slot_device_present
= 0;
327 QTAILQ_FOREACH_SAFE(kid
, &bus
->children
, sibling
, next
) {
328 DeviceState
*qdev
= kid
->child
;
329 PCIDevice
*pdev
= PCI_DEVICE(qdev
);
330 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pdev
);
331 int slot
= PCI_SLOT(pdev
->devfn
);
333 if (pc
->no_hotplug
) {
334 s
->pci0_hotplug_enable
&= ~(1U << slot
);
337 s
->pci0_slot_device_present
|= (1U << slot
);
341 static void piix4_reset(void *opaque
)
343 PIIX4PMState
*s
= opaque
;
344 uint8_t *pci_conf
= s
->dev
.config
;
351 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
354 if (s
->kvm_enabled
) {
355 /* Mark SMM as already inited (until KVM supports SMM). */
356 pci_conf
[0x5B] = 0x02;
358 piix4_update_hotplug(s
);
361 static void piix4_pm_powerdown_req(Notifier
*n
, void *opaque
)
363 PIIX4PMState
*s
= container_of(n
, PIIX4PMState
, powerdown_notifier
);
366 acpi_pm1_evt_power_down(&s
->ar
);
369 static void piix4_pm_machine_ready(Notifier
*n
, void *opaque
)
371 PIIX4PMState
*s
= container_of(n
, PIIX4PMState
, machine_ready
);
374 pci_conf
= s
->dev
.config
;
375 pci_conf
[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
376 pci_conf
[0x63] = 0x60;
377 pci_conf
[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
378 (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
382 static int piix4_pm_initfn(PCIDevice
*dev
)
384 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
387 pci_conf
= s
->dev
.config
;
388 pci_conf
[0x06] = 0x80;
389 pci_conf
[0x07] = 0x02;
390 pci_conf
[0x09] = 0x00;
391 pci_conf
[0x3d] = 0x01; // interrupt pin 1
394 apm_init(dev
, &s
->apm
, apm_ctrl_changed
, s
);
396 if (s
->kvm_enabled
) {
397 /* Mark SMM as already inited to prevent SMM from running. KVM does not
398 * support SMM mode. */
399 pci_conf
[0x5B] = 0x02;
402 /* XXX: which specification is used ? The i82731AB has different
404 pci_conf
[0x90] = s
->smb_io_base
| 1;
405 pci_conf
[0x91] = s
->smb_io_base
>> 8;
406 pci_conf
[0xd2] = 0x09;
407 pm_smbus_init(&s
->dev
.qdev
, &s
->smb
);
408 memory_region_set_enabled(&s
->smb
.io
, pci_conf
[0xd2] & 1);
409 memory_region_add_subregion(get_system_io(), s
->smb_io_base
, &s
->smb
.io
);
411 memory_region_init(&s
->io
, "piix4-pm", 64);
412 memory_region_set_enabled(&s
->io
, false);
413 memory_region_add_subregion(get_system_io(), 0, &s
->io
);
415 acpi_pm_tmr_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
416 acpi_pm1_evt_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
417 acpi_pm1_cnt_init(&s
->ar
, &s
->io
);
418 acpi_gpe_init(&s
->ar
, GPE_LEN
);
420 s
->powerdown_notifier
.notify
= piix4_pm_powerdown_req
;
421 qemu_register_powerdown_notifier(&s
->powerdown_notifier
);
423 s
->machine_ready
.notify
= piix4_pm_machine_ready
;
424 qemu_add_machine_init_done_notifier(&s
->machine_ready
);
425 qemu_register_reset(piix4_reset
, s
);
426 piix4_acpi_system_hot_add_init(dev
->bus
, s
);
431 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
432 qemu_irq sci_irq
, qemu_irq smi_irq
,
433 int kvm_enabled
, void *fw_cfg
)
438 dev
= pci_create(bus
, devfn
, "PIIX4_PM");
439 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
441 s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
443 s
->smi_irq
= smi_irq
;
444 s
->kvm_enabled
= kvm_enabled
;
446 qdev_init_nofail(&dev
->qdev
);
449 uint8_t suspend
[6] = {128, 0, 0, 129, 128, 128};
450 suspend
[3] = 1 | ((!s
->disable_s3
) << 7);
451 suspend
[4] = s
->s4_val
| ((!s
->disable_s4
) << 7);
453 fw_cfg_add_file(fw_cfg
, "etc/system-states", g_memdup(suspend
, 6), 6);
459 static Property piix4_pm_properties
[] = {
460 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState
, smb_io_base
, 0),
461 DEFINE_PROP_UINT8("disable_s3", PIIX4PMState
, disable_s3
, 0),
462 DEFINE_PROP_UINT8("disable_s4", PIIX4PMState
, disable_s4
, 0),
463 DEFINE_PROP_UINT8("s4_val", PIIX4PMState
, s4_val
, 2),
464 DEFINE_PROP_END_OF_LIST(),
467 static void piix4_pm_class_init(ObjectClass
*klass
, void *data
)
469 DeviceClass
*dc
= DEVICE_CLASS(klass
);
470 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
473 k
->init
= piix4_pm_initfn
;
474 k
->config_write
= pm_write_config
;
475 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
476 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB_3
;
478 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
481 dc
->vmsd
= &vmstate_acpi
;
482 dc
->props
= piix4_pm_properties
;
485 static TypeInfo piix4_pm_info
= {
487 .parent
= TYPE_PCI_DEVICE
,
488 .instance_size
= sizeof(PIIX4PMState
),
489 .class_init
= piix4_pm_class_init
,
492 static void piix4_pm_register_types(void)
494 type_register_static(&piix4_pm_info
);
497 type_init(piix4_pm_register_types
)
499 static uint64_t gpe_readb(void *opaque
, hwaddr addr
, unsigned width
)
501 PIIX4PMState
*s
= opaque
;
502 uint32_t val
= acpi_gpe_ioport_readb(&s
->ar
, addr
);
504 PIIX4_DPRINTF("gpe read %x == %x\n", addr
, val
);
508 static void gpe_writeb(void *opaque
, hwaddr addr
, uint64_t val
,
511 PIIX4PMState
*s
= opaque
;
513 acpi_gpe_ioport_writeb(&s
->ar
, addr
, val
);
516 PIIX4_DPRINTF("gpe write %x <== %d\n", addr
, val
);
519 static const MemoryRegionOps piix4_gpe_ops
= {
522 .valid
.min_access_size
= 1,
523 .valid
.max_access_size
= 4,
524 .impl
.min_access_size
= 1,
525 .impl
.max_access_size
= 1,
526 .endianness
= DEVICE_LITTLE_ENDIAN
,
529 static uint32_t pci_up_read(void *opaque
, uint32_t addr
)
531 PIIX4PMState
*s
= opaque
;
534 /* Manufacture an "up" value to cause a device check on any hotplug
535 * slot with a device. Extra device checks are harmless. */
536 val
= s
->pci0_slot_device_present
& s
->pci0_hotplug_enable
;
538 PIIX4_DPRINTF("pci_up_read %x\n", val
);
542 static uint32_t pci_down_read(void *opaque
, uint32_t addr
)
544 PIIX4PMState
*s
= opaque
;
545 uint32_t val
= s
->pci0_status
.down
;
547 PIIX4_DPRINTF("pci_down_read %x\n", val
);
551 static uint32_t pci_features_read(void *opaque
, uint32_t addr
)
553 /* No feature defined yet */
554 PIIX4_DPRINTF("pci_features_read %x\n", 0);
558 static void pciej_write(void *opaque
, uint32_t addr
, uint32_t val
)
560 acpi_piix_eject_slot(opaque
, val
);
562 PIIX4_DPRINTF("pciej write %x <== %d\n", addr
, val
);
565 static uint32_t pcirmv_read(void *opaque
, uint32_t addr
)
567 PIIX4PMState
*s
= opaque
;
569 return s
->pci0_hotplug_enable
;
572 static const MemoryRegionOps piix4_pci_ops
= {
573 .old_portio
= (MemoryRegionPortio
[]) {
575 .offset
= PCI_UP_BASE
- PCI_HOTPLUG_ADDR
, .len
= 4, .size
= 4,
578 .offset
= PCI_DOWN_BASE
- PCI_HOTPLUG_ADDR
, .len
= 4, .size
= 4,
579 .read
= pci_down_read
,
581 .offset
= PCI_EJ_BASE
- PCI_HOTPLUG_ADDR
, .len
= 4, .size
= 4,
582 .read
= pci_features_read
,
583 .write
= pciej_write
,
585 .offset
= PCI_RMV_BASE
- PCI_HOTPLUG_ADDR
, .len
= 4, .size
= 4,
590 .endianness
= DEVICE_LITTLE_ENDIAN
,
593 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
,
594 PCIHotplugState state
);
596 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
)
598 memory_region_init_io(&s
->io_gpe
, &piix4_gpe_ops
, s
, "apci-gpe0",
600 memory_region_add_subregion(get_system_io(), GPE_BASE
, &s
->io_gpe
);
602 memory_region_init_io(&s
->io_pci
, &piix4_pci_ops
, s
, "apci-pci-hotplug",
604 memory_region_add_subregion(get_system_io(), PCI_HOTPLUG_ADDR
,
606 pci_bus_hotplug(bus
, piix4_device_hotplug
, &s
->dev
.qdev
);
609 static void enable_device(PIIX4PMState
*s
, int slot
)
611 s
->ar
.gpe
.sts
[0] |= PIIX4_PCI_HOTPLUG_STATUS
;
612 s
->pci0_slot_device_present
|= (1U << slot
);
615 static void disable_device(PIIX4PMState
*s
, int slot
)
617 s
->ar
.gpe
.sts
[0] |= PIIX4_PCI_HOTPLUG_STATUS
;
618 s
->pci0_status
.down
|= (1U << slot
);
621 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
,
622 PCIHotplugState state
)
624 int slot
= PCI_SLOT(dev
->devfn
);
625 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
,
628 /* Don't send event when device is enabled during qemu machine creation:
629 * it is present on boot, no hotplug event is necessary. We do send an
630 * event when the device is disabled later. */
631 if (state
== PCI_COLDPLUG_ENABLED
) {
632 s
->pci0_slot_device_present
|= (1U << slot
);
636 if (state
== PCI_HOTPLUG_ENABLED
) {
637 enable_device(s
, slot
);
639 disable_device(s
, slot
);