target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50
  51 #define MMU_USER_IDX 1
  52
  53 #define MAX_EXT_QUEUE 16
  54 #define MAX_IO_QUEUE 16
  55 #define MAX_MCHK_QUEUE 16
  56
  57 #define PSW_MCHK_MASK 0x0004000000000000
  58 #define PSW_IO_MASK 0x0200000000000000
  59
  60 typedef struct PSW {
  61     uint64_t mask;
  62     uint64_t addr;
  63 } PSW;
  64
  65 typedef struct ExtQueue {
  66     uint32_t code;
  67     uint32_t param;
  68     uint32_t param64;
  69 } ExtQueue;
  70
  71 typedef struct IOIntQueue {
  72     uint16_t id;
  73     uint16_t nr;
  74     uint32_t parm;
  75     uint32_t word;
  76 } IOIntQueue;
  77
  78 typedef struct MchkQueue {
  79     uint16_t type;
  80 } MchkQueue;
  81
  82 typedef struct CPUS390XState {
  83     uint64_t regs[16];     /* GP registers */
  84     CPU_DoubleU fregs[16]; /* FP registers */
  85     uint32_t aregs[16];    /* access registers */
  86
  87     uint32_t fpc;          /* floating-point control register */
  88     uint32_t cc_op;
  89
  90     float_status fpu_status; /* passed to softfloat lib */
  91
  92     /* The low part of a 128-bit return, or remainder of a divide.  */
  93     uint64_t retxl;
  94
  95     PSW psw;
  96
  97     uint64_t cc_src;
  98     uint64_t cc_dst;
  99     uint64_t cc_vr;
 100
 101     uint64_t __excp_addr;
 102     uint64_t psa;
 103
 104     uint32_t int_pgm_code;
 105     uint32_t int_pgm_ilen;
 106
 107     uint32_t int_svc_code;
 108     uint32_t int_svc_ilen;
 109
 110     uint64_t cregs[16]; /* control registers */
 111
 112     ExtQueue ext_queue[MAX_EXT_QUEUE];
 113     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 114     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 115
 116     int pending_int;
 117     int ext_index;
 118     int io_index[8];
 119     int mchk_index;
 120
 121     uint64_t ckc;
 122     uint64_t cputm;
 123     uint32_t todpr;
 124
 125     uint64_t pfault_token;
 126     uint64_t pfault_compare;
 127     uint64_t pfault_select;
 128
 129     uint64_t gbea;
 130     uint64_t pp;
 131
 132     CPU_COMMON
 133
 134     /* reset does memset(0) up to here */
 135
 136     int cpu_num;
 137     uint8_t *storage_keys;
 138
 139     uint64_t tod_offset;
 140     uint64_t tod_basetime;
 141     QEMUTimer *tod_timer;
 142
 143     QEMUTimer *cpu_timer;
 144
 145     /*
 146      * The cpu state represents the logical state of a cpu. In contrast to other
 147      * architectures, there is a difference between a halt and a stop on s390.
 148      * If all cpus are either stopped (including check stop) or in the disabled
 149      * wait state, the vm can be shut down.
 150      */
 151 #define CPU_STATE_UNINITIALIZED        0x00
 152 #define CPU_STATE_STOPPED              0x01
 153 #define CPU_STATE_CHECK_STOP           0x02
 154 #define CPU_STATE_OPERATING            0x03
 155 #define CPU_STATE_LOAD                 0x04
 156     uint8_t cpu_state;
 157
 158 } CPUS390XState;
 159
 160 #include "cpu-qom.h"
 161 #include <sysemu/kvm.h>
 162
 163 /* distinguish between 24 bit and 31 bit addressing */
 164 #define HIGH_ORDER_BIT 0x80000000
 165
 166 /* Interrupt Codes */
 167 /* Program Interrupts */
 168 #define PGM_OPERATION                   0x0001
 169 #define PGM_PRIVILEGED                  0x0002
 170 #define PGM_EXECUTE                     0x0003
 171 #define PGM_PROTECTION                  0x0004
 172 #define PGM_ADDRESSING                  0x0005
 173 #define PGM_SPECIFICATION               0x0006
 174 #define PGM_DATA                        0x0007
 175 #define PGM_FIXPT_OVERFLOW              0x0008
 176 #define PGM_FIXPT_DIVIDE                0x0009
 177 #define PGM_DEC_OVERFLOW                0x000a
 178 #define PGM_DEC_DIVIDE                  0x000b
 179 #define PGM_HFP_EXP_OVERFLOW            0x000c
 180 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 181 #define PGM_HFP_SIGNIFICANCE            0x000e
 182 #define PGM_HFP_DIVIDE                  0x000f
 183 #define PGM_SEGMENT_TRANS               0x0010
 184 #define PGM_PAGE_TRANS                  0x0011
 185 #define PGM_TRANS_SPEC                  0x0012
 186 #define PGM_SPECIAL_OP                  0x0013
 187 #define PGM_OPERAND                     0x0015
 188 #define PGM_TRACE_TABLE                 0x0016
 189 #define PGM_SPACE_SWITCH                0x001c
 190 #define PGM_HFP_SQRT                    0x001d
 191 #define PGM_PC_TRANS_SPEC               0x001f
 192 #define PGM_AFX_TRANS                   0x0020
 193 #define PGM_ASX_TRANS                   0x0021
 194 #define PGM_LX_TRANS                    0x0022
 195 #define PGM_EX_TRANS                    0x0023
 196 #define PGM_PRIM_AUTH                   0x0024
 197 #define PGM_SEC_AUTH                    0x0025
 198 #define PGM_ALET_SPEC                   0x0028
 199 #define PGM_ALEN_SPEC                   0x0029
 200 #define PGM_ALE_SEQ                     0x002a
 201 #define PGM_ASTE_VALID                  0x002b
 202 #define PGM_ASTE_SEQ                    0x002c
 203 #define PGM_EXT_AUTH                    0x002d
 204 #define PGM_STACK_FULL                  0x0030
 205 #define PGM_STACK_EMPTY                 0x0031
 206 #define PGM_STACK_SPEC                  0x0032
 207 #define PGM_STACK_TYPE                  0x0033
 208 #define PGM_STACK_OP                    0x0034
 209 #define PGM_ASCE_TYPE                   0x0038
 210 #define PGM_REG_FIRST_TRANS             0x0039
 211 #define PGM_REG_SEC_TRANS               0x003a
 212 #define PGM_REG_THIRD_TRANS             0x003b
 213 #define PGM_MONITOR                     0x0040
 214 #define PGM_PER                         0x0080
 215 #define PGM_CRYPTO                      0x0119
 216
 217 /* External Interrupts */
 218 #define EXT_INTERRUPT_KEY               0x0040
 219 #define EXT_CLOCK_COMP                  0x1004
 220 #define EXT_CPU_TIMER                   0x1005
 221 #define EXT_MALFUNCTION                 0x1200
 222 #define EXT_EMERGENCY                   0x1201
 223 #define EXT_EXTERNAL_CALL               0x1202
 224 #define EXT_ETR                         0x1406
 225 #define EXT_SERVICE                     0x2401
 226 #define EXT_VIRTIO                      0x2603
 227
 228 /* PSW defines */
 229 #undef PSW_MASK_PER
 230 #undef PSW_MASK_DAT
 231 #undef PSW_MASK_IO
 232 #undef PSW_MASK_EXT
 233 #undef PSW_MASK_KEY
 234 #undef PSW_SHIFT_KEY
 235 #undef PSW_MASK_MCHECK
 236 #undef PSW_MASK_WAIT
 237 #undef PSW_MASK_PSTATE
 238 #undef PSW_MASK_ASC
 239 #undef PSW_MASK_CC
 240 #undef PSW_MASK_PM
 241 #undef PSW_MASK_64
 242 #undef PSW_MASK_32
 243 #undef PSW_MASK_ESA_ADDR
 244
 245 #define PSW_MASK_PER            0x4000000000000000ULL
 246 #define PSW_MASK_DAT            0x0400000000000000ULL
 247 #define PSW_MASK_IO             0x0200000000000000ULL
 248 #define PSW_MASK_EXT            0x0100000000000000ULL
 249 #define PSW_MASK_KEY            0x00F0000000000000ULL
 250 #define PSW_SHIFT_KEY           56
 251 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 252 #define PSW_MASK_WAIT           0x0002000000000000ULL
 253 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 254 #define PSW_MASK_ASC            0x0000C00000000000ULL
 255 #define PSW_MASK_CC             0x0000300000000000ULL
 256 #define PSW_MASK_PM             0x00000F0000000000ULL
 257 #define PSW_MASK_64             0x0000000100000000ULL
 258 #define PSW_MASK_32             0x0000000080000000ULL
 259 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 260
 261 #undef PSW_ASC_PRIMARY
 262 #undef PSW_ASC_ACCREG
 263 #undef PSW_ASC_SECONDARY
 264 #undef PSW_ASC_HOME
 265
 266 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 267 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 268 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 269 #define PSW_ASC_HOME            0x0000C00000000000ULL
 270
 271 /* tb flags */
 272
 273 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 274 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 275 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 276 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 277 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 278 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 279 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 280 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 281 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 282 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 283 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 284 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 285 #define FLAG_MASK_32            0x00001000
 286
 287 /* Control register 0 bits */
 288 #define CR0_EDAT                0x0000000000800000ULL
 289
 290 static inline int cpu_mmu_index (CPUS390XState *env)
 291 {
 292     if (env->psw.mask & PSW_MASK_PSTATE) {
 293         return 1;
 294     }
 295
 296     return 0;
 297 }
 298
 299 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 300                                         target_ulong *cs_base, int *flags)
 301 {
 302     *pc = env->psw.addr;
 303     *cs_base = 0;
 304     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 305              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 306 }
 307
 308 /* While the PoO talks about ILC (a number between 1-3) what is actually
 309    stored in LowCore is shifted left one bit (an even between 2-6).  As
 310    this is the actual length of the insn and therefore more useful, that
 311    is what we want to pass around and manipulate.  To make sure that we
 312    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 313 static inline int get_ilen(uint8_t opc)
 314 {
 315     switch (opc >> 6) {
 316     case 0:
 317         return 2;
 318     case 1:
 319     case 2:
 320         return 4;
 321     default:
 322         return 6;
 323     }
 324 }
 325
 326 #ifndef CONFIG_USER_ONLY
 327 /* In several cases of runtime exceptions, we havn't recorded the true
 328    instruction length.  Use these codes when raising exceptions in order
 329    to re-compute the length by examining the insn in memory.  */
 330 #define ILEN_LATER       0x20
 331 #define ILEN_LATER_INC   0x21
 332 #endif
 333
 334 S390CPU *cpu_s390x_init(const char *cpu_model);
 335 void s390x_translate_init(void);
 336 int cpu_s390x_exec(CPUS390XState *s);
 337
 338 /* you can call this signal handler from your SIGBUS and SIGSEGV
 339    signal handlers to inform the virtual CPU of exceptions. non zero
 340    is returned if the signal was handled by the virtual CPU.  */
 341 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 342                            void *puc);
 343 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 344                               int mmu_idx);
 345
 346 #include "ioinst.h"
 347
 348 #ifndef CONFIG_USER_ONLY
 349 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 350                                    int is_write);
 351 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 352                                     int is_write);
 353 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
 354 {
 355     hwaddr addr = 0;
 356     uint8_t reg;
 357
 358     reg = ipb >> 28;
 359     if (reg > 0) {
 360         addr = env->regs[reg];
 361     }
 362     addr += (ipb >> 16) & 0xfff;
 363
 364     return addr;
 365 }
 366
 367 /* Base/displacement are at the same locations. */
 368 #define decode_basedisp_rs decode_basedisp_s
 369
 370 /* helper functions for run_on_cpu() */
 371 static inline void s390_do_cpu_reset(void *arg)
 372 {
 373     CPUState *cs = arg;
 374     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 375
 376     scc->cpu_reset(cs);
 377 }
 378 static inline void s390_do_cpu_full_reset(void *arg)
 379 {
 380     CPUState *cs = arg;
 381
 382     cpu_reset(cs);
 383 }
 384
 385 void s390x_tod_timer(void *opaque);
 386 void s390x_cpu_timer(void *opaque);
 387
 388 int s390_virtio_hypercall(CPUS390XState *env);
 389 void s390_virtio_irq(int config_change, uint64_t token);
 390
 391 #ifdef CONFIG_KVM
 392 void kvm_s390_virtio_irq(int config_change, uint64_t token);
 393 void kvm_s390_service_interrupt(uint32_t parm);
 394 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 395 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 396 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 397 #else
 398 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
 399 {
 400 }
 401 static inline void kvm_s390_service_interrupt(uint32_t parm)
 402 {
 403 }
 404 #endif
 405 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 406 unsigned int s390_cpu_halt(S390CPU *cpu);
 407 void s390_cpu_unhalt(S390CPU *cpu);
 408 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 409
 410 /* service interrupts are floating therefore we must not pass an cpustate */
 411 void s390_sclp_extint(uint32_t parm);
 412
 413 /* from s390-virtio-bus */
 414 extern const hwaddr virtio_size;
 415
 416 #else
 417 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
 418 {
 419     return 0;
 420 }
 421
 422 static inline void s390_cpu_unhalt(S390CPU *cpu)
 423 {
 424 }
 425
 426 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 427 {
 428     return 0;
 429 }
 430 #endif
 431 void cpu_lock(void);
 432 void cpu_unlock(void);
 433
 434 typedef struct SubchDev SubchDev;
 435
 436 #ifndef CONFIG_USER_ONLY
 437 extern void io_subsystem_reset(void);
 438 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 439                          uint16_t schid);
 440 bool css_subch_visible(SubchDev *sch);
 441 void css_conditional_io_interrupt(SubchDev *sch);
 442 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 443 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 444 int css_do_msch(SubchDev *sch, SCHIB *schib);
 445 int css_do_xsch(SubchDev *sch);
 446 int css_do_csch(SubchDev *sch);
 447 int css_do_hsch(SubchDev *sch);
 448 int css_do_ssch(SubchDev *sch, ORB *orb);
 449 int css_do_tsch(SubchDev *sch, IRB *irb);
 450 int css_do_stcrw(CRW *crw);
 451 int css_do_tpi(IOIntCode *int_code, int lowcore);
 452 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 453                          int rfmt, void *buf);
 454 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 455 int css_enable_mcsse(void);
 456 int css_enable_mss(void);
 457 int css_do_rsch(SubchDev *sch);
 458 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 459 bool css_present(uint8_t cssid);
 460 #endif
 461
 462 #define cpu_init(model) (&cpu_s390x_init(model)->env)
 463 #define cpu_exec cpu_s390x_exec
 464 #define cpu_gen_code cpu_s390x_gen_code
 465 #define cpu_signal_handler cpu_s390x_signal_handler
 466
 467 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 468 #define cpu_list s390_cpu_list
 469
 470 #include "exec/exec-all.h"
 471
 472 #define EXCP_EXT 1 /* external interrupt */
 473 #define EXCP_SVC 2 /* supervisor call (syscall) */
 474 #define EXCP_PGM 3 /* program interruption */
 475 #define EXCP_IO  7 /* I/O interrupt */
 476 #define EXCP_MCHK 8 /* machine check */
 477
 478 #define INTERRUPT_EXT        (1 << 0)
 479 #define INTERRUPT_TOD        (1 << 1)
 480 #define INTERRUPT_CPUTIMER   (1 << 2)
 481 #define INTERRUPT_IO         (1 << 3)
 482 #define INTERRUPT_MCHK       (1 << 4)
 483
 484 /* Program Status Word.  */
 485 #define S390_PSWM_REGNUM 0
 486 #define S390_PSWA_REGNUM 1
 487 /* General Purpose Registers.  */
 488 #define S390_R0_REGNUM 2
 489 #define S390_R1_REGNUM 3
 490 #define S390_R2_REGNUM 4
 491 #define S390_R3_REGNUM 5
 492 #define S390_R4_REGNUM 6
 493 #define S390_R5_REGNUM 7
 494 #define S390_R6_REGNUM 8
 495 #define S390_R7_REGNUM 9
 496 #define S390_R8_REGNUM 10
 497 #define S390_R9_REGNUM 11
 498 #define S390_R10_REGNUM 12
 499 #define S390_R11_REGNUM 13
 500 #define S390_R12_REGNUM 14
 501 #define S390_R13_REGNUM 15
 502 #define S390_R14_REGNUM 16
 503 #define S390_R15_REGNUM 17
 504 /* Total Core Registers. */
 505 #define S390_NUM_CORE_REGS 18
 506
 507 /* CC optimization */
 508
 509 enum cc_op {
 510     CC_OP_CONST0 = 0,           /* CC is 0 */
 511     CC_OP_CONST1,               /* CC is 1 */
 512     CC_OP_CONST2,               /* CC is 2 */
 513     CC_OP_CONST3,               /* CC is 3 */
 514
 515     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 516     CC_OP_STATIC,               /* CC value is env->cc_op */
 517
 518     CC_OP_NZ,                   /* env->cc_dst != 0 */
 519     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 520     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 521     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 522     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 523     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 524     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 525
 526     CC_OP_ADD_64,               /* overflow on add (64bit) */
 527     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 528     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 529     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 530     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 531     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 532     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 533     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 534
 535     CC_OP_ADD_32,               /* overflow on add (32bit) */
 536     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 537     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 538     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 539     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 540     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 541     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 542     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 543
 544     CC_OP_COMP_32,              /* complement */
 545     CC_OP_COMP_64,              /* complement */
 546
 547     CC_OP_TM_32,                /* test under mask (32bit) */
 548     CC_OP_TM_64,                /* test under mask (64bit) */
 549
 550     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 551     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 552     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 553
 554     CC_OP_ICM,                  /* insert characters under mask */
 555     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 556     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 557     CC_OP_FLOGR,                /* find leftmost one */
 558     CC_OP_MAX
 559 };
 560
 561 static const char *cc_names[] = {
 562     [CC_OP_CONST0]    = "CC_OP_CONST0",
 563     [CC_OP_CONST1]    = "CC_OP_CONST1",
 564     [CC_OP_CONST2]    = "CC_OP_CONST2",
 565     [CC_OP_CONST3]    = "CC_OP_CONST3",
 566     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 567     [CC_OP_STATIC]    = "CC_OP_STATIC",
 568     [CC_OP_NZ]        = "CC_OP_NZ",
 569     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 570     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 571     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 572     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 573     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 574     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 575     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 576     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 577     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 578     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 579     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 580     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 581     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 582     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 583     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 584     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 585     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 586     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 587     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 588     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 589     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 590     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 591     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 592     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 593     [CC_OP_TM_32]     = "CC_OP_TM_32",
 594     [CC_OP_TM_64]     = "CC_OP_TM_64",
 595     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 596     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 597     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 598     [CC_OP_ICM]       = "CC_OP_ICM",
 599     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 600     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 601     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 602 };
 603
 604 static inline const char *cc_name(int cc_op)
 605 {
 606     return cc_names[cc_op];
 607 }
 608
 609 static inline void setcc(S390CPU *cpu, uint64_t cc)
 610 {
 611     CPUS390XState *env = &cpu->env;
 612
 613     env->psw.mask &= ~(3ull << 44);
 614     env->psw.mask |= (cc & 3) << 44;
 615 }
 616
 617 typedef struct LowCore
 618 {
 619     /* prefix area: defined by architecture */
 620     uint32_t        ccw1[2];                  /* 0x000 */
 621     uint32_t        ccw2[4];                  /* 0x008 */
 622     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 623     uint32_t        ext_params;               /* 0x080 */
 624     uint16_t        cpu_addr;                 /* 0x084 */
 625     uint16_t        ext_int_code;             /* 0x086 */
 626     uint16_t        svc_ilen;                 /* 0x088 */
 627     uint16_t        svc_code;                 /* 0x08a */
 628     uint16_t        pgm_ilen;                 /* 0x08c */
 629     uint16_t        pgm_code;                 /* 0x08e */
 630     uint32_t        data_exc_code;            /* 0x090 */
 631     uint16_t        mon_class_num;            /* 0x094 */
 632     uint16_t        per_perc_atmid;           /* 0x096 */
 633     uint64_t        per_address;              /* 0x098 */
 634     uint8_t         exc_access_id;            /* 0x0a0 */
 635     uint8_t         per_access_id;            /* 0x0a1 */
 636     uint8_t         op_access_id;             /* 0x0a2 */
 637     uint8_t         ar_access_id;             /* 0x0a3 */
 638     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 639     uint64_t        trans_exc_code;           /* 0x0a8 */
 640     uint64_t        monitor_code;             /* 0x0b0 */
 641     uint16_t        subchannel_id;            /* 0x0b8 */
 642     uint16_t        subchannel_nr;            /* 0x0ba */
 643     uint32_t        io_int_parm;              /* 0x0bc */
 644     uint32_t        io_int_word;              /* 0x0c0 */
 645     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 646     uint32_t        stfl_fac_list;            /* 0x0c8 */
 647     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 648     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 649     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 650     uint32_t        external_damage_code;     /* 0x0f4 */
 651     uint64_t        failing_storage_address;  /* 0x0f8 */
 652     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 653     PSW             restart_old_psw;          /* 0x120 */
 654     PSW             external_old_psw;         /* 0x130 */
 655     PSW             svc_old_psw;              /* 0x140 */
 656     PSW             program_old_psw;          /* 0x150 */
 657     PSW             mcck_old_psw;             /* 0x160 */
 658     PSW             io_old_psw;               /* 0x170 */
 659     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 660     PSW             restart_psw;              /* 0x1a0 */
 661     PSW             external_new_psw;         /* 0x1b0 */
 662     PSW             svc_new_psw;              /* 0x1c0 */
 663     PSW             program_new_psw;          /* 0x1d0 */
 664     PSW             mcck_new_psw;             /* 0x1e0 */
 665     PSW             io_new_psw;               /* 0x1f0 */
 666     PSW             return_psw;               /* 0x200 */
 667     uint8_t         irb[64];                  /* 0x210 */
 668     uint64_t        sync_enter_timer;         /* 0x250 */
 669     uint64_t        async_enter_timer;        /* 0x258 */
 670     uint64_t        exit_timer;               /* 0x260 */
 671     uint64_t        last_update_timer;        /* 0x268 */
 672     uint64_t        user_timer;               /* 0x270 */
 673     uint64_t        system_timer;             /* 0x278 */
 674     uint64_t        last_update_clock;        /* 0x280 */
 675     uint64_t        steal_clock;              /* 0x288 */
 676     PSW             return_mcck_psw;          /* 0x290 */
 677     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 678     /* System info area */
 679     uint64_t        save_area[16];            /* 0xc00 */
 680     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 681     uint64_t        kernel_stack;             /* 0xd40 */
 682     uint64_t        thread_info;              /* 0xd48 */
 683     uint64_t        async_stack;              /* 0xd50 */
 684     uint64_t        kernel_asce;              /* 0xd58 */
 685     uint64_t        user_asce;                /* 0xd60 */
 686     uint64_t        panic_stack;              /* 0xd68 */
 687     uint64_t        user_exec_asce;           /* 0xd70 */
 688     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 689
 690     /* SMP info area: defined by DJB */
 691     uint64_t        clock_comparator;         /* 0xdc0 */
 692     uint64_t        ext_call_fast;            /* 0xdc8 */
 693     uint64_t        percpu_offset;            /* 0xdd0 */
 694     uint64_t        current_task;             /* 0xdd8 */
 695     uint32_t        softirq_pending;          /* 0xde0 */
 696     uint32_t        pad_0x0de4;               /* 0xde4 */
 697     uint64_t        int_clock;                /* 0xde8 */
 698     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 699
 700     /* 0xe00 is used as indicator for dump tools */
 701     /* whether the kernel died with panic() or not */
 702     uint32_t        panic_magic;              /* 0xe00 */
 703
 704     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 705
 706     /* 64 bit extparam used for pfault, diag 250 etc  */
 707     uint64_t        ext_params2;               /* 0x11B8 */
 708
 709     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 710
 711     /* System info area */
 712
 713     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 714     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 715     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 716     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 717     uint32_t        prefixreg_save_area;       /* 0x1318 */
 718     uint32_t        fpt_creg_save_area;        /* 0x131c */
 719     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 720     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 721     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 722     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 723     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 724     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 725     uint64_t        cregs_save_area[16];       /* 0x1380 */
 726
 727     /* align to the top of the prefix area */
 728
 729     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 730 } QEMU_PACKED LowCore;
 731
 732 /* STSI */
 733 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 734 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 735 #define STSI_LEVEL_1            0x0000000010000000ULL
 736 #define STSI_LEVEL_2            0x0000000020000000ULL
 737 #define STSI_LEVEL_3            0x0000000030000000ULL
 738 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 739 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 740 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 741 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 742
 743 /* Basic Machine Configuration */
 744 struct sysib_111 {
 745     uint32_t res1[8];
 746     uint8_t  manuf[16];
 747     uint8_t  type[4];
 748     uint8_t  res2[12];
 749     uint8_t  model[16];
 750     uint8_t  sequence[16];
 751     uint8_t  plant[4];
 752     uint8_t  res3[156];
 753 };
 754
 755 /* Basic Machine CPU */
 756 struct sysib_121 {
 757     uint32_t res1[80];
 758     uint8_t  sequence[16];
 759     uint8_t  plant[4];
 760     uint8_t  res2[2];
 761     uint16_t cpu_addr;
 762     uint8_t  res3[152];
 763 };
 764
 765 /* Basic Machine CPUs */
 766 struct sysib_122 {
 767     uint8_t res1[32];
 768     uint32_t capability;
 769     uint16_t total_cpus;
 770     uint16_t active_cpus;
 771     uint16_t standby_cpus;
 772     uint16_t reserved_cpus;
 773     uint16_t adjustments[2026];
 774 };
 775
 776 /* LPAR CPU */
 777 struct sysib_221 {
 778     uint32_t res1[80];
 779     uint8_t  sequence[16];
 780     uint8_t  plant[4];
 781     uint16_t cpu_id;
 782     uint16_t cpu_addr;
 783     uint8_t  res3[152];
 784 };
 785
 786 /* LPAR CPUs */
 787 struct sysib_222 {
 788     uint32_t res1[32];
 789     uint16_t lpar_num;
 790     uint8_t  res2;
 791     uint8_t  lcpuc;
 792     uint16_t total_cpus;
 793     uint16_t conf_cpus;
 794     uint16_t standby_cpus;
 795     uint16_t reserved_cpus;
 796     uint8_t  name[8];
 797     uint32_t caf;
 798     uint8_t  res3[16];
 799     uint16_t dedicated_cpus;
 800     uint16_t shared_cpus;
 801     uint8_t  res4[180];
 802 };
 803
 804 /* VM CPUs */
 805 struct sysib_322 {
 806     uint8_t  res1[31];
 807     uint8_t  count;
 808     struct {
 809         uint8_t  res2[4];
 810         uint16_t total_cpus;
 811         uint16_t conf_cpus;
 812         uint16_t standby_cpus;
 813         uint16_t reserved_cpus;
 814         uint8_t  name[8];
 815         uint32_t caf;
 816         uint8_t  cpi[16];
 817         uint8_t  res3[24];
 818     } vm[8];
 819     uint8_t res4[3552];
 820 };
 821
 822 /* MMU defines */
 823 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 824 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 825 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 826 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 827 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 828 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 829 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 830 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 831 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 832 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 833 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 834 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 835
 836 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 837 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 838 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 839 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 840 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 841 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 842 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 843
 844 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 845 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 846 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 847 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 848
 849 #define _PAGE_RO        0x200            /* HW read-only bit  */
 850 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 851
 852 #define SK_C                    (0x1 << 1)
 853 #define SK_R                    (0x1 << 2)
 854 #define SK_F                    (0x1 << 3)
 855 #define SK_ACC_MASK             (0xf << 4)
 856
 857 #define SIGP_SENSE             0x01
 858 #define SIGP_EXTERNAL_CALL     0x02
 859 #define SIGP_EMERGENCY         0x03
 860 #define SIGP_START             0x04
 861 #define SIGP_STOP              0x05
 862 #define SIGP_RESTART           0x06
 863 #define SIGP_STOP_STORE_STATUS 0x09
 864 #define SIGP_INITIAL_CPU_RESET 0x0b
 865 #define SIGP_CPU_RESET         0x0c
 866 #define SIGP_SET_PREFIX        0x0d
 867 #define SIGP_STORE_STATUS_ADDR 0x0e
 868 #define SIGP_SET_ARCH          0x12
 869
 870 /* cpu status bits */
 871 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 872 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 873 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 874 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 875 #define SIGP_STAT_STOPPED           0x00000040UL
 876 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 877 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 878 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 879 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 880 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 881
 882 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 883 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 884                   target_ulong *raddr, int *flags);
 885 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
 886 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 887                  uint64_t vr);
 888
 889 #define TARGET_HAS_ICE 1
 890
 891 /* The value of the TOD clock for 1.1.1970. */
 892 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 893
 894 /* Converts ns to s390's clock format */
 895 static inline uint64_t time2tod(uint64_t ns) {
 896     return (ns << 9) / 125;
 897 }
 898
 899 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 900                                   uint64_t param64)
 901 {
 902     CPUS390XState *env = &cpu->env;
 903
 904     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 905         /* ugh - can't queue anymore. Let's drop. */
 906         return;
 907     }
 908
 909     env->ext_index++;
 910     assert(env->ext_index < MAX_EXT_QUEUE);
 911
 912     env->ext_queue[env->ext_index].code = code;
 913     env->ext_queue[env->ext_index].param = param;
 914     env->ext_queue[env->ext_index].param64 = param64;
 915
 916     env->pending_int |= INTERRUPT_EXT;
 917     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
 918 }
 919
 920 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
 921                                  uint16_t subchannel_number,
 922                                  uint32_t io_int_parm, uint32_t io_int_word)
 923 {
 924     CPUS390XState *env = &cpu->env;
 925     int isc = IO_INT_WORD_ISC(io_int_word);
 926
 927     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
 928         /* ugh - can't queue anymore. Let's drop. */
 929         return;
 930     }
 931
 932     env->io_index[isc]++;
 933     assert(env->io_index[isc] < MAX_IO_QUEUE);
 934
 935     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
 936     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
 937     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
 938     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
 939
 940     env->pending_int |= INTERRUPT_IO;
 941     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
 942 }
 943
 944 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
 945 {
 946     CPUS390XState *env = &cpu->env;
 947
 948     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
 949         /* ugh - can't queue anymore. Let's drop. */
 950         return;
 951     }
 952
 953     env->mchk_index++;
 954     assert(env->mchk_index < MAX_MCHK_QUEUE);
 955
 956     env->mchk_queue[env->mchk_index].type = 1;
 957
 958     env->pending_int |= INTERRUPT_MCHK;
 959     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
 960 }
 961
 962 /* from s390-virtio-ccw */
 963 #define MEM_SECTION_SIZE             0x10000000UL
 964 #define MAX_AVAIL_SLOTS              32
 965
 966 /* fpu_helper.c */
 967 uint32_t set_cc_nz_f32(float32 v);
 968 uint32_t set_cc_nz_f64(float64 v);
 969 uint32_t set_cc_nz_f128(float128 v);
 970
 971 /* misc_helper.c */
 972 #ifndef CONFIG_USER_ONLY
 973 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
 974 #endif
 975 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
 976 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
 977                                      uintptr_t retaddr);
 978
 979 #ifdef CONFIG_KVM
 980 void kvm_s390_io_interrupt(uint16_t subchannel_id,
 981                            uint16_t subchannel_nr, uint32_t io_int_parm,
 982                            uint32_t io_int_word);
 983 void kvm_s390_crw_mchk(void);
 984 void kvm_s390_enable_css_support(S390CPU *cpu);
 985 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
 986                                     int vq, bool assign);
 987 int kvm_s390_cpu_restart(S390CPU *cpu);
 988 int kvm_s390_get_memslot_count(KVMState *s);
 989 void kvm_s390_clear_cmma_callback(void *opaque);
 990 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
 991 void kvm_s390_reset_vcpu(S390CPU *cpu);
 992 #else
 993 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
 994                                         uint16_t subchannel_nr,
 995                                         uint32_t io_int_parm,
 996                                         uint32_t io_int_word)
 997 {
 998 }
 999 static inline void kvm_s390_crw_mchk(void)
1000 {
1001 }
1002 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1003 {
1004 }
1005 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1006                                                   uint32_t sch, int vq,
1007                                                   bool assign)
1008 {
1009     return -ENOSYS;
1010 }
1011 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1012 {
1013     return -ENOSYS;
1014 }
1015 static inline void kvm_s390_clear_cmma_callback(void *opaque)
1016 {
1017 }
1018 static inline int kvm_s390_get_memslot_count(KVMState *s)
1019 {
1020   return MAX_AVAIL_SLOTS;
1021 }
1022 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1023 {
1024     return -ENOSYS;
1025 }
1026 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1027 {
1028 }
1029 #endif
1030
1031 static inline void cmma_reset(S390CPU *cpu)
1032 {
1033     if (kvm_enabled()) {
1034         CPUState *cs = CPU(cpu);
1035         kvm_s390_clear_cmma_callback(cs->kvm_state);
1036     }
1037 }
1038
1039 static inline int s390_cpu_restart(S390CPU *cpu)
1040 {
1041     if (kvm_enabled()) {
1042         return kvm_s390_cpu_restart(cpu);
1043     }
1044     return -ENOSYS;
1045 }
1046
1047 static inline int s390_get_memslot_count(KVMState *s)
1048 {
1049     if (kvm_enabled()) {
1050         return kvm_s390_get_memslot_count(s);
1051     } else {
1052         return MAX_AVAIL_SLOTS;
1053     }
1054 }
1055
1056 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1057                        uint32_t io_int_parm, uint32_t io_int_word);
1058 void s390_crw_mchk(void);
1059
1060 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1061                                               uint32_t sch_id, int vq,
1062                                               bool assign)
1063 {
1064     if (kvm_enabled()) {
1065         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1066     } else {
1067         return -ENOSYS;
1068     }
1069 }
1070
1071 #endif