4 * Copyright (c) 2008 OKL
5 * Originally Written by Hans Jiang
6 * Copyright (c) 2011 NICTA Pty Ltd.
7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
12 * This is a `bare-bones' implementation of the IMX series serial ports.
14 * -- implement FIFOs. The real hardware has 32 word transmit
15 * and receive FIFOs; we currently use a 1-char buffer
17 * -- implement BAUD-rate and modem lines, for when the backend
18 * is a real serial device.
21 #include "hw/char/imx_serial.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/char.h"
25 #ifndef DEBUG_IMX_UART
26 #define DEBUG_IMX_UART 0
29 #define DPRINTF(fmt, args...) \
31 if (DEBUG_IMX_UART) { \
32 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
37 static const VMStateDescription vmstate_imx_serial
= {
38 .name
= TYPE_IMX_SERIAL
,
40 .minimum_version_id
= 1,
41 .fields
= (VMStateField
[]) {
42 VMSTATE_INT32(readbuff
, IMXSerialState
),
43 VMSTATE_UINT32(usr1
, IMXSerialState
),
44 VMSTATE_UINT32(usr2
, IMXSerialState
),
45 VMSTATE_UINT32(ucr1
, IMXSerialState
),
46 VMSTATE_UINT32(uts1
, IMXSerialState
),
47 VMSTATE_UINT32(onems
, IMXSerialState
),
48 VMSTATE_UINT32(ufcr
, IMXSerialState
),
49 VMSTATE_UINT32(ubmr
, IMXSerialState
),
50 VMSTATE_UINT32(ubrc
, IMXSerialState
),
51 VMSTATE_UINT32(ucr3
, IMXSerialState
),
56 static void imx_update(IMXSerialState
*s
)
60 flags
= (s
->usr1
& s
->ucr1
) & (USR1_TRDY
|USR1_RRDY
);
61 if (s
->ucr1
& UCR1_TXMPTYEN
) {
62 flags
|= (s
->uts1
& UTS1_TXEMPTY
);
67 qemu_set_irq(s
->irq
, !!flags
);
70 static void imx_serial_reset(IMXSerialState
*s
)
73 s
->usr1
= USR1_TRDY
| USR1_RXDS
;
75 * Fake attachment of a terminal: assert RTS.
78 s
->usr2
= USR2_TXFE
| USR2_TXDC
| USR2_DCDIN
;
79 s
->uts1
= UTS1_RXEMPTY
| UTS1_TXEMPTY
;
85 s
->readbuff
= URXD_ERR
;
88 static void imx_serial_reset_at_boot(DeviceState
*dev
)
90 IMXSerialState
*s
= IMX_SERIAL(dev
);
95 * enable the uart on boot, so messages from the linux decompresser
96 * are visible. On real hardware this is done by the boot rom
97 * before anything else is loaded.
99 s
->ucr1
= UCR1_UARTEN
;
104 static uint64_t imx_serial_read(void *opaque
, hwaddr offset
,
107 IMXSerialState
*s
= (IMXSerialState
*)opaque
;
110 DPRINTF("read(offset=0x%" HWADDR_PRIx
")\n", offset
);
112 switch (offset
>> 2) {
115 if (!(s
->uts1
& UTS1_RXEMPTY
)) {
116 /* Character is valid */
118 s
->usr1
&= ~USR1_RRDY
;
119 s
->usr2
&= ~USR2_RDR
;
120 s
->uts1
|= UTS1_RXEMPTY
;
123 qemu_chr_accept_input(s
->chr
);
128 case 0x20: /* UCR1 */
131 case 0x21: /* UCR2 */
134 case 0x25: /* USR1 */
137 case 0x26: /* USR2 */
140 case 0x2A: /* BRM Modulator */
143 case 0x2B: /* Baud Rate Count */
146 case 0x2d: /* Test register */
149 case 0x24: /* UFCR */
155 case 0x22: /* UCR3 */
158 case 0x23: /* UCR4 */
159 case 0x29: /* BRM Incremental */
160 return 0x0; /* TODO */
163 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
164 HWADDR_PRIx
"\n", TYPE_IMX_SERIAL
, __func__
, offset
);
169 static void imx_serial_write(void *opaque
, hwaddr offset
,
170 uint64_t value
, unsigned size
)
172 IMXSerialState
*s
= (IMXSerialState
*)opaque
;
175 DPRINTF("write(offset=0x%" HWADDR_PRIx
", value = 0x%x) to %s\n",
176 offset
, (unsigned int)value
, s
->chr
? s
->chr
->label
: "NODEV");
178 switch (offset
>> 2) {
179 case 0x10: /* UTXD */
181 if (s
->ucr2
& UCR2_TXEN
) {
183 qemu_chr_fe_write(s
->chr
, &ch
, 1);
185 s
->usr1
&= ~USR1_TRDY
;
187 s
->usr1
|= USR1_TRDY
;
192 case 0x20: /* UCR1 */
193 s
->ucr1
= value
& 0xffff;
195 DPRINTF("write(ucr1=%x)\n", (unsigned int)value
);
200 case 0x21: /* UCR2 */
202 * Only a few bits in control register 2 are implemented as yet.
203 * If it's intended to use a real serial device as a back-end, this
204 * register will have to be implemented more fully.
206 if (!(value
& UCR2_SRST
)) {
211 if (value
& UCR2_RXEN
) {
212 if (!(s
->ucr2
& UCR2_RXEN
)) {
214 qemu_chr_accept_input(s
->chr
);
218 s
->ucr2
= value
& 0xffff;
221 case 0x25: /* USR1 */
222 value
&= USR1_AWAKE
| USR1_AIRINT
| USR1_DTRD
| USR1_AGTIM
|
223 USR1_FRAMERR
| USR1_ESCF
| USR1_RTSD
| USR1_PARTYER
;
227 case 0x26: /* USR2 */
229 * Writing 1 to some bits clears them; all other
232 value
&= USR2_ADET
| USR2_DTRF
| USR2_IDLE
| USR2_ACST
|
233 USR2_RIDELT
| USR2_IRINT
| USR2_WAKE
|
234 USR2_DCDDELT
| USR2_RTSF
| USR2_BRCD
| USR2_ORE
;
239 * Linux expects to see what it writes to these registers
240 * We don't currently alter the baud rate
242 case 0x29: /* UBIR */
243 s
->ubrc
= value
& 0xffff;
246 case 0x2a: /* UBMR */
247 s
->ubmr
= value
& 0xffff;
250 case 0x2c: /* One ms reg */
251 s
->onems
= value
& 0xffff;
254 case 0x24: /* FIFO control register */
255 s
->ufcr
= value
& 0xffff;
258 case 0x22: /* UCR3 */
259 s
->ucr3
= value
& 0xffff;
262 case 0x2d: /* UTS1 */
263 case 0x23: /* UCR4 */
264 qemu_log_mask(LOG_UNIMP
, "[%s]%s: Unimplemented reg 0x%"
265 HWADDR_PRIx
"\n", TYPE_IMX_SERIAL
, __func__
, offset
);
270 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
271 HWADDR_PRIx
"\n", TYPE_IMX_SERIAL
, __func__
, offset
);
275 static int imx_can_receive(void *opaque
)
277 IMXSerialState
*s
= (IMXSerialState
*)opaque
;
278 return !(s
->usr1
& USR1_RRDY
);
281 static void imx_put_data(void *opaque
, uint32_t value
)
283 IMXSerialState
*s
= (IMXSerialState
*)opaque
;
285 DPRINTF("received char\n");
287 s
->usr1
|= USR1_RRDY
;
289 s
->uts1
&= ~UTS1_RXEMPTY
;
294 static void imx_receive(void *opaque
, const uint8_t *buf
, int size
)
296 imx_put_data(opaque
, *buf
);
299 static void imx_event(void *opaque
, int event
)
301 if (event
== CHR_EVENT_BREAK
) {
302 imx_put_data(opaque
, URXD_BRK
);
307 static const struct MemoryRegionOps imx_serial_ops
= {
308 .read
= imx_serial_read
,
309 .write
= imx_serial_write
,
310 .endianness
= DEVICE_NATIVE_ENDIAN
,
313 static void imx_serial_realize(DeviceState
*dev
, Error
**errp
)
315 IMXSerialState
*s
= IMX_SERIAL(dev
);
318 qemu_chr_add_handlers(s
->chr
, imx_can_receive
, imx_receive
,
321 DPRINTF("No char dev for uart\n");
325 static void imx_serial_init(Object
*obj
)
327 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
328 IMXSerialState
*s
= IMX_SERIAL(obj
);
330 memory_region_init_io(&s
->iomem
, obj
, &imx_serial_ops
, s
,
331 TYPE_IMX_SERIAL
, 0x1000);
332 sysbus_init_mmio(sbd
, &s
->iomem
);
333 sysbus_init_irq(sbd
, &s
->irq
);
336 static Property imx_serial_properties
[] = {
337 DEFINE_PROP_CHR("chardev", IMXSerialState
, chr
),
338 DEFINE_PROP_END_OF_LIST(),
341 static void imx_serial_class_init(ObjectClass
*klass
, void *data
)
343 DeviceClass
*dc
= DEVICE_CLASS(klass
);
345 dc
->realize
= imx_serial_realize
;
346 dc
->vmsd
= &vmstate_imx_serial
;
347 dc
->reset
= imx_serial_reset_at_boot
;
348 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
349 dc
->desc
= "i.MX series UART";
350 dc
->props
= imx_serial_properties
;
353 static const TypeInfo imx_serial_info
= {
354 .name
= TYPE_IMX_SERIAL
,
355 .parent
= TYPE_SYS_BUS_DEVICE
,
356 .instance_size
= sizeof(IMXSerialState
),
357 .instance_init
= imx_serial_init
,
358 .class_init
= imx_serial_class_init
,
361 static void imx_serial_register_types(void)
363 type_register_static(&imx_serial_info
);
366 type_init(imx_serial_register_types
)