target-tilegx/cpu.h

   1 /*
   2  *  TILE-Gx virtual CPU header
   3  *
   4  *  Copyright (c) 2015 Chen Gang
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef TILEGX_CPU_H
  21 #define TILEGX_CPU_H
  22
  23 #include "qemu-common.h"
  24
  25 #define TARGET_LONG_BITS 64
  26
  27 #define CPUArchState struct CPUTLGState
  28
  29 #include "exec/cpu-defs.h"
  30
  31
  32 /* TILE-Gx common register alias */
  33 #define TILEGX_R_RE    0   /*  0 register, for function/syscall return value */
  34 #define TILEGX_R_ERR   1   /*  1 register, for syscall errno flag */
  35 #define TILEGX_R_NR    10  /* 10 register, for syscall number */
  36 #define TILEGX_R_BP    52  /* 52 register, optional frame pointer */
  37 #define TILEGX_R_TP    53  /* TP register, thread local storage data */
  38 #define TILEGX_R_SP    54  /* SP register, stack pointer */
  39 #define TILEGX_R_LR    55  /* LR register, may save pc, but it is not pc */
  40 #define TILEGX_R_COUNT 56  /* Only 56 registers are really useful */
  41 #define TILEGX_R_SN    56  /* SN register, obsoleted, it likes zero register */
  42 #define TILEGX_R_IDN0  57  /* IDN0 register, cause IDN_ACCESS exception */
  43 #define TILEGX_R_IDN1  58  /* IDN1 register, cause IDN_ACCESS exception */
  44 #define TILEGX_R_UDN0  59  /* UDN0 register, cause UDN_ACCESS exception */
  45 #define TILEGX_R_UDN1  60  /* UDN1 register, cause UDN_ACCESS exception */
  46 #define TILEGX_R_UDN2  61  /* UDN2 register, cause UDN_ACCESS exception */
  47 #define TILEGX_R_UDN3  62  /* UDN3 register, cause UDN_ACCESS exception */
  48 #define TILEGX_R_ZERO  63  /* Zero register, always zero */
  49 #define TILEGX_R_NOREG 255 /* Invalid register value */
  50
  51 /* TILE-Gx special registers used by outside */
  52 enum {
  53     TILEGX_SPR_CMPEXCH = 0,
  54     TILEGX_SPR_CRITICAL_SEC = 1,
  55     TILEGX_SPR_SIM_CONTROL = 2,
  56     TILEGX_SPR_EX_CONTEXT_0_0 = 3,
  57     TILEGX_SPR_EX_CONTEXT_0_1 = 4,
  58     TILEGX_SPR_COUNT
  59 };
  60
  61 /* Exception numbers */
  62 typedef enum {
  63     TILEGX_EXCP_NONE = 0,
  64     TILEGX_EXCP_SYSCALL = 1,
  65     TILEGX_EXCP_SIGNAL = 2,
  66     TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
  67     TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
  68     TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
  69     TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
  70     TILEGX_EXCP_OPCODE_EXCH = 0x105,
  71     TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
  72     TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
  73     TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
  74     TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
  75     TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
  76     TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
  77     TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
  78     TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
  79     TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
  80     TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
  81     TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
  82     TILEGX_EXCP_UNALIGNMENT = 0x201,
  83     TILEGX_EXCP_DBUG_BREAK = 0x301
  84 } TileExcp;
  85
  86 typedef struct CPUTLGState {
  87     uint64_t regs[TILEGX_R_COUNT];     /* Common used registers by outside */
  88     uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
  89     uint64_t pc;                       /* Current pc */
  90
  91 #if defined(CONFIG_USER_ONLY)
  92     uint64_t excaddr;                  /* exception address */
  93     uint64_t atomic_srca;              /* Arguments to atomic "exceptions" */
  94     uint64_t atomic_srcb;
  95     uint32_t atomic_dstr;
  96     uint32_t signo;                    /* Signal number */
  97     uint32_t sigcode;                  /* Signal code */
  98 #endif
  99
 100     CPU_COMMON
 101 } CPUTLGState;
 102
 103 #include "qom/cpu.h"
 104
 105 #define TYPE_TILEGX_CPU "tilegx-cpu"
 106
 107 #define TILEGX_CPU_CLASS(klass) \
 108     OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
 109 #define TILEGX_CPU(obj) \
 110     OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
 111 #define TILEGX_CPU_GET_CLASS(obj) \
 112     OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
 113
 114 /**
 115  * TileGXCPUClass:
 116  * @parent_realize: The parent class' realize handler.
 117  * @parent_reset: The parent class' reset handler.
 118  *
 119  * A Tile-Gx CPU model.
 120  */
 121 typedef struct TileGXCPUClass {
 122     /*< private >*/
 123     CPUClass parent_class;
 124     /*< public >*/
 125
 126     DeviceRealize parent_realize;
 127     void (*parent_reset)(CPUState *cpu);
 128 } TileGXCPUClass;
 129
 130 /**
 131  * TileGXCPU:
 132  * @env: #CPUTLGState
 133  *
 134  * A Tile-GX CPU.
 135  */
 136 typedef struct TileGXCPU {
 137     /*< private >*/
 138     CPUState parent_obj;
 139     /*< public >*/
 140
 141     CPUTLGState env;
 142 } TileGXCPU;
 143
 144 static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
 145 {
 146     return container_of(env, TileGXCPU, env);
 147 }
 148
 149 #define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e))
 150
 151 #define ENV_OFFSET offsetof(TileGXCPU, env)
 152
 153 /* TILE-Gx memory attributes */
 154 #define TARGET_PAGE_BITS 16  /* TILE-Gx uses 64KB page size */
 155 #define TARGET_PHYS_ADDR_SPACE_BITS 42
 156 #define TARGET_VIRT_ADDR_SPACE_BITS 64
 157 #define MMU_USER_IDX    0  /* Current memory operation is in user mode */
 158
 159 #include "exec/cpu-all.h"
 160
 161 void tilegx_tcg_init(void);
 162 int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
 163
 164 TileGXCPU *cpu_tilegx_init(const char *cpu_model);
 165
 166 #define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
 167
 168 #define cpu_signal_handler cpu_tilegx_signal_handler
 169
 170 static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
 171                                         target_ulong *cs_base, uint32_t *flags)
 172 {
 173     *pc = env->pc;
 174     *cs_base = 0;
 175     *flags = 0;
 176 }
 177
 178 #endif