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acpi unit-test: compare DSDT and SSDT tables against expected values
[qemu/cris-port.git] / target-i386 / kvm.c
blob0a21c3085d108423f4d62db2ca5fc9393038ed1d
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "exec/ioport.h"
34 #include <asm/hyperv.h>
35 #include "hw/pci/pci.h"
36
37 //#define DEBUG_KVM
38
39 #ifdef DEBUG_KVM
40 #define DPRINTF(fmt, ...) \
41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42 #else
43 #define DPRINTF(fmt, ...) \
44 do { } while (0)
45 #endif
46
47 #define MSR_KVM_WALL_CLOCK 0x11
48 #define MSR_KVM_SYSTEM_TIME 0x12
49
50 #ifndef BUS_MCEERR_AR
51 #define BUS_MCEERR_AR 4
52 #endif
53 #ifndef BUS_MCEERR_AO
54 #define BUS_MCEERR_AO 5
55 #endif
56
57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
58 KVM_CAP_INFO(SET_TSS_ADDR),
59 KVM_CAP_INFO(EXT_CPUID),
60 KVM_CAP_INFO(MP_STATE),
61 KVM_CAP_LAST_INFO
62 };
63
64 static bool has_msr_star;
65 static bool has_msr_hsave_pa;
66 static bool has_msr_tsc_adjust;
67 static bool has_msr_tsc_deadline;
68 static bool has_msr_feature_control;
69 static bool has_msr_async_pf_en;
70 static bool has_msr_pv_eoi_en;
71 static bool has_msr_misc_enable;
72 static bool has_msr_bndcfgs;
73 static bool has_msr_kvm_steal_time;
74 static int lm_capable_kernel;
75
76 static bool has_msr_architectural_pmu;
77 static uint32_t num_architectural_pmu_counters;
78
79 bool kvm_allows_irq0_override(void)
80 {
81 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
82 }
83
84 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
85 {
86 struct kvm_cpuid2 *cpuid;
87 int r, size;
88
89 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
90 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
91 cpuid->nent = max;
92 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
93 if (r == 0 && cpuid->nent >= max) {
94 r = -E2BIG;
95 }
96 if (r < 0) {
97 if (r == -E2BIG) {
98 g_free(cpuid);
99 return NULL;
100 } else {
101 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
102 strerror(-r));
103 exit(1);
104 }
105 }
106 return cpuid;
107 }
108
109 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
110 * for all entries.
111 */
112 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
113 {
114 struct kvm_cpuid2 *cpuid;
115 int max = 1;
116 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
117 max *= 2;
118 }
119 return cpuid;
120 }
121
122 struct kvm_para_features {
123 int cap;
124 int feature;
125 } para_features[] = {
126 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
127 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
128 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
129 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
130 { -1, -1 }
131 };
132
133 static int get_para_features(KVMState *s)
134 {
135 int i, features = 0;
136
137 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
138 if (kvm_check_extension(s, para_features[i].cap)) {
139 features |= (1 << para_features[i].feature);
140 }
141 }
142
143 return features;
144 }
145
146
147 /* Returns the value for a specific register on the cpuid entry
148 */
149 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
150 {
151 uint32_t ret = 0;
152 switch (reg) {
153 case R_EAX:
154 ret = entry->eax;
155 break;
156 case R_EBX:
157 ret = entry->ebx;
158 break;
159 case R_ECX:
160 ret = entry->ecx;
161 break;
162 case R_EDX:
163 ret = entry->edx;
164 break;
165 }
166 return ret;
167 }
168
169 /* Find matching entry for function/index on kvm_cpuid2 struct
170 */
171 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
172 uint32_t function,
173 uint32_t index)
174 {
175 int i;
176 for (i = 0; i < cpuid->nent; ++i) {
177 if (cpuid->entries[i].function == function &&
178 cpuid->entries[i].index == index) {
179 return &cpuid->entries[i];
180 }
181 }
182 /* not found: */
183 return NULL;
184 }
185
186 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
187 uint32_t index, int reg)
188 {
189 struct kvm_cpuid2 *cpuid;
190 uint32_t ret = 0;
191 uint32_t cpuid_1_edx;
192 bool found = false;
193
194 cpuid = get_supported_cpuid(s);
195
196 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
197 if (entry) {
198 found = true;
199 ret = cpuid_entry_get_reg(entry, reg);
200 }
201
202 /* Fixups for the data returned by KVM, below */
203
204 if (function == 1 && reg == R_EDX) {
205 /* KVM before 2.6.30 misreports the following features */
206 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
207 } else if (function == 1 && reg == R_ECX) {
208 /* We can set the hypervisor flag, even if KVM does not return it on
209 * GET_SUPPORTED_CPUID
210 */
211 ret |= CPUID_EXT_HYPERVISOR;
212 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
213 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
214 * and the irqchip is in the kernel.
215 */
216 if (kvm_irqchip_in_kernel() &&
217 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
218 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
219 }
220
221 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
222 * without the in-kernel irqchip
223 */
224 if (!kvm_irqchip_in_kernel()) {
225 ret &= ~CPUID_EXT_X2APIC;
226 }
227 } else if (function == 0x80000001 && reg == R_EDX) {
228 /* On Intel, kvm returns cpuid according to the Intel spec,
229 * so add missing bits according to the AMD spec:
230 */
231 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
232 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
233 }
234
235 g_free(cpuid);
236
237 /* fallback for older kernels */
238 if ((function == KVM_CPUID_FEATURES) && !found) {
239 ret = get_para_features(s);
240 }
241
242 return ret;
243 }
244
245 typedef struct HWPoisonPage {
246 ram_addr_t ram_addr;
247 QLIST_ENTRY(HWPoisonPage) list;
248 } HWPoisonPage;
249
250 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
251 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
252
253 static void kvm_unpoison_all(void *param)
254 {
255 HWPoisonPage *page, *next_page;
256
257 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
258 QLIST_REMOVE(page, list);
259 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
260 g_free(page);
261 }
262 }
263
264 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
265 {
266 HWPoisonPage *page;
267
268 QLIST_FOREACH(page, &hwpoison_page_list, list) {
269 if (page->ram_addr == ram_addr) {
270 return;
271 }
272 }
273 page = g_malloc(sizeof(HWPoisonPage));
274 page->ram_addr = ram_addr;
275 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
276 }
277
278 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
279 int *max_banks)
280 {
281 int r;
282
283 r = kvm_check_extension(s, KVM_CAP_MCE);
284 if (r > 0) {
285 *max_banks = r;
286 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
287 }
288 return -ENOSYS;
289 }
290
291 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
292 {
293 CPUX86State *env = &cpu->env;
294 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
295 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
296 uint64_t mcg_status = MCG_STATUS_MCIP;
297
298 if (code == BUS_MCEERR_AR) {
299 status |= MCI_STATUS_AR | 0x134;
300 mcg_status |= MCG_STATUS_EIPV;
301 } else {
302 status |= 0xc0;
303 mcg_status |= MCG_STATUS_RIPV;
304 }
305 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
306 (MCM_ADDR_PHYS << 6) | 0xc,
307 cpu_x86_support_mca_broadcast(env) ?
308 MCE_INJECT_BROADCAST : 0);
309 }
310
311 static void hardware_memory_error(void)
312 {
313 fprintf(stderr, "Hardware memory error!\n");
314 exit(1);
315 }
316
317 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
318 {
319 X86CPU *cpu = X86_CPU(c);
320 CPUX86State *env = &cpu->env;
321 ram_addr_t ram_addr;
322 hwaddr paddr;
323
324 if ((env->mcg_cap & MCG_SER_P) && addr
325 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
326 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
327 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
328 fprintf(stderr, "Hardware memory error for memory used by "
329 "QEMU itself instead of guest system!\n");
330 /* Hope we are lucky for AO MCE */
331 if (code == BUS_MCEERR_AO) {
332 return 0;
333 } else {
334 hardware_memory_error();
335 }
336 }
337 kvm_hwpoison_page_add(ram_addr);
338 kvm_mce_inject(cpu, paddr, code);
339 } else {
340 if (code == BUS_MCEERR_AO) {
341 return 0;
342 } else if (code == BUS_MCEERR_AR) {
343 hardware_memory_error();
344 } else {
345 return 1;
346 }
347 }
348 return 0;
349 }
350
351 int kvm_arch_on_sigbus(int code, void *addr)
352 {
353 X86CPU *cpu = X86_CPU(first_cpu);
354
355 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
356 ram_addr_t ram_addr;
357 hwaddr paddr;
358
359 /* Hope we are lucky for AO MCE */
360 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
361 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
362 addr, &paddr)) {
363 fprintf(stderr, "Hardware memory error for memory used by "
364 "QEMU itself instead of guest system!: %p\n", addr);
365 return 0;
366 }
367 kvm_hwpoison_page_add(ram_addr);
368 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
369 } else {
370 if (code == BUS_MCEERR_AO) {
371 return 0;
372 } else if (code == BUS_MCEERR_AR) {
373 hardware_memory_error();
374 } else {
375 return 1;
376 }
377 }
378 return 0;
379 }
380
381 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
382 {
383 CPUX86State *env = &cpu->env;
384
385 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
386 unsigned int bank, bank_num = env->mcg_cap & 0xff;
387 struct kvm_x86_mce mce;
388
389 env->exception_injected = -1;
390
391 /*
392 * There must be at least one bank in use if an MCE is pending.
393 * Find it and use its values for the event injection.
394 */
395 for (bank = 0; bank < bank_num; bank++) {
396 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
397 break;
398 }
399 }
400 assert(bank < bank_num);
401
402 mce.bank = bank;
403 mce.status = env->mce_banks[bank * 4 + 1];
404 mce.mcg_status = env->mcg_status;
405 mce.addr = env->mce_banks[bank * 4 + 2];
406 mce.misc = env->mce_banks[bank * 4 + 3];
407
408 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
409 }
410 return 0;
411 }
412
413 static void cpu_update_state(void *opaque, int running, RunState state)
414 {
415 CPUX86State *env = opaque;
416
417 if (running) {
418 env->tsc_valid = false;
419 }
420 }
421
422 unsigned long kvm_arch_vcpu_id(CPUState *cs)
423 {
424 X86CPU *cpu = X86_CPU(cs);
425 return cpu->env.cpuid_apic_id;
426 }
427
428 #ifndef KVM_CPUID_SIGNATURE_NEXT
429 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
430 #endif
431
432 static bool hyperv_hypercall_available(X86CPU *cpu)
433 {
434 return cpu->hyperv_vapic ||
435 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
436 }
437
438 static bool hyperv_enabled(X86CPU *cpu)
439 {
440 return hyperv_hypercall_available(cpu) ||
441 cpu->hyperv_relaxed_timing;
442 }
443
444 #define KVM_MAX_CPUID_ENTRIES 100
445
446 int kvm_arch_init_vcpu(CPUState *cs)
447 {
448 struct {
449 struct kvm_cpuid2 cpuid;
450 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
451 } QEMU_PACKED cpuid_data;
452 X86CPU *cpu = X86_CPU(cs);
453 CPUX86State *env = &cpu->env;
454 uint32_t limit, i, j, cpuid_i;
455 uint32_t unused;
456 struct kvm_cpuid_entry2 *c;
457 uint32_t signature[3];
458 int r;
459
460 memset(&cpuid_data, 0, sizeof(cpuid_data));
461
462 cpuid_i = 0;
463
464 /* Paravirtualization CPUIDs */
465 c = &cpuid_data.entries[cpuid_i++];
466 c->function = KVM_CPUID_SIGNATURE;
467 if (!hyperv_enabled(cpu)) {
468 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
469 c->eax = 0;
470 } else {
471 memcpy(signature, "Microsoft Hv", 12);
472 c->eax = HYPERV_CPUID_MIN;
473 }
474 c->ebx = signature[0];
475 c->ecx = signature[1];
476 c->edx = signature[2];
477
478 c = &cpuid_data.entries[cpuid_i++];
479 c->function = KVM_CPUID_FEATURES;
480 c->eax = env->features[FEAT_KVM];
481
482 if (hyperv_enabled(cpu)) {
483 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
484 c->eax = signature[0];
485
486 c = &cpuid_data.entries[cpuid_i++];
487 c->function = HYPERV_CPUID_VERSION;
488 c->eax = 0x00001bbc;
489 c->ebx = 0x00060001;
490
491 c = &cpuid_data.entries[cpuid_i++];
492 c->function = HYPERV_CPUID_FEATURES;
493 if (cpu->hyperv_relaxed_timing) {
494 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
495 }
496 if (cpu->hyperv_vapic) {
497 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
498 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
499 }
500
501 c = &cpuid_data.entries[cpuid_i++];
502 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
503 if (cpu->hyperv_relaxed_timing) {
504 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
505 }
506 if (cpu->hyperv_vapic) {
507 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
508 }
509 c->ebx = cpu->hyperv_spinlock_attempts;
510
511 c = &cpuid_data.entries[cpuid_i++];
512 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
513 c->eax = 0x40;
514 c->ebx = 0x40;
515
516 c = &cpuid_data.entries[cpuid_i++];
517 c->function = KVM_CPUID_SIGNATURE_NEXT;
518 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
519 c->eax = 0;
520 c->ebx = signature[0];
521 c->ecx = signature[1];
522 c->edx = signature[2];
523 }
524
525 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
526
527 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
528
529 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
530
531 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
532
533 for (i = 0; i <= limit; i++) {
534 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
535 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
536 abort();
537 }
538 c = &cpuid_data.entries[cpuid_i++];
539
540 switch (i) {
541 case 2: {
542 /* Keep reading function 2 till all the input is received */
543 int times;
544
545 c->function = i;
546 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
547 KVM_CPUID_FLAG_STATE_READ_NEXT;
548 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
549 times = c->eax & 0xff;
550
551 for (j = 1; j < times; ++j) {
552 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
553 fprintf(stderr, "cpuid_data is full, no space for "
554 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
555 abort();
556 }
557 c = &cpuid_data.entries[cpuid_i++];
558 c->function = i;
559 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
560 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
561 }
562 break;
563 }
564 case 4:
565 case 0xb:
566 case 0xd:
567 for (j = 0; ; j++) {
568 if (i == 0xd && j == 64) {
569 break;
570 }
571 c->function = i;
572 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
573 c->index = j;
574 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
575
576 if (i == 4 && c->eax == 0) {
577 break;
578 }
579 if (i == 0xb && !(c->ecx & 0xff00)) {
580 break;
581 }
582 if (i == 0xd && c->eax == 0) {
583 continue;
584 }
585 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
586 fprintf(stderr, "cpuid_data is full, no space for "
587 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
588 abort();
589 }
590 c = &cpuid_data.entries[cpuid_i++];
591 }
592 break;
593 default:
594 c->function = i;
595 c->flags = 0;
596 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
597 break;
598 }
599 }
600
601 if (limit >= 0x0a) {
602 uint32_t ver;
603
604 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
605 if ((ver & 0xff) > 0) {
606 has_msr_architectural_pmu = true;
607 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
608
609 /* Shouldn't be more than 32, since that's the number of bits
610 * available in EBX to tell us _which_ counters are available.
611 * Play it safe.
612 */
613 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
614 num_architectural_pmu_counters = MAX_GP_COUNTERS;
615 }
616 }
617 }
618
619 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
620
621 for (i = 0x80000000; i <= limit; i++) {
622 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
623 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
624 abort();
625 }
626 c = &cpuid_data.entries[cpuid_i++];
627
628 c->function = i;
629 c->flags = 0;
630 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
631 }
632
633 /* Call Centaur's CPUID instructions they are supported. */
634 if (env->cpuid_xlevel2 > 0) {
635 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
636
637 for (i = 0xC0000000; i <= limit; i++) {
638 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
639 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
640 abort();
641 }
642 c = &cpuid_data.entries[cpuid_i++];
643
644 c->function = i;
645 c->flags = 0;
646 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
647 }
648 }
649
650 cpuid_data.cpuid.nent = cpuid_i;
651
652 if (((env->cpuid_version >> 8)&0xF) >= 6
653 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
654 (CPUID_MCE | CPUID_MCA)
655 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
656 uint64_t mcg_cap;
657 int banks;
658 int ret;
659
660 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
661 if (ret < 0) {
662 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
663 return ret;
664 }
665
666 if (banks > MCE_BANKS_DEF) {
667 banks = MCE_BANKS_DEF;
668 }
669 mcg_cap &= MCE_CAP_DEF;
670 mcg_cap |= banks;
671 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
672 if (ret < 0) {
673 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
674 return ret;
675 }
676
677 env->mcg_cap = mcg_cap;
678 }
679
680 qemu_add_vm_change_state_handler(cpu_update_state, env);
681
682 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
683 if (c) {
684 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
685 !!(c->ecx & CPUID_EXT_SMX);
686 }
687
688 cpuid_data.cpuid.padding = 0;
689 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
690 if (r) {
691 return r;
692 }
693
694 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
695 if (r && env->tsc_khz) {
696 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
697 if (r < 0) {
698 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
699 return r;
700 }
701 }
702
703 if (kvm_has_xsave()) {
704 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
705 }
706
707 return 0;
708 }
709
710 void kvm_arch_reset_vcpu(CPUState *cs)
711 {
712 X86CPU *cpu = X86_CPU(cs);
713 CPUX86State *env = &cpu->env;
714
715 env->exception_injected = -1;
716 env->interrupt_injected = -1;
717 env->xcr0 = 1;
718 if (kvm_irqchip_in_kernel()) {
719 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
720 KVM_MP_STATE_UNINITIALIZED;
721 } else {
722 env->mp_state = KVM_MP_STATE_RUNNABLE;
723 }
724 }
725
726 static int kvm_get_supported_msrs(KVMState *s)
727 {
728 static int kvm_supported_msrs;
729 int ret = 0;
730
731 /* first time */
732 if (kvm_supported_msrs == 0) {
733 struct kvm_msr_list msr_list, *kvm_msr_list;
734
735 kvm_supported_msrs = -1;
736
737 /* Obtain MSR list from KVM. These are the MSRs that we must
738 * save/restore */
739 msr_list.nmsrs = 0;
740 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
741 if (ret < 0 && ret != -E2BIG) {
742 return ret;
743 }
744 /* Old kernel modules had a bug and could write beyond the provided
745 memory. Allocate at least a safe amount of 1K. */
746 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
747 msr_list.nmsrs *
748 sizeof(msr_list.indices[0])));
749
750 kvm_msr_list->nmsrs = msr_list.nmsrs;
751 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
752 if (ret >= 0) {
753 int i;
754
755 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
756 if (kvm_msr_list->indices[i] == MSR_STAR) {
757 has_msr_star = true;
758 continue;
759 }
760 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
761 has_msr_hsave_pa = true;
762 continue;
763 }
764 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
765 has_msr_tsc_adjust = true;
766 continue;
767 }
768 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
769 has_msr_tsc_deadline = true;
770 continue;
771 }
772 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
773 has_msr_misc_enable = true;
774 continue;
775 }
776 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
777 has_msr_bndcfgs = true;
778 continue;
779 }
780 }
781 }
782
783 g_free(kvm_msr_list);
784 }
785
786 return ret;
787 }
788
789 int kvm_arch_init(KVMState *s)
790 {
791 uint64_t identity_base = 0xfffbc000;
792 uint64_t shadow_mem;
793 int ret;
794 struct utsname utsname;
795
796 ret = kvm_get_supported_msrs(s);
797 if (ret < 0) {
798 return ret;
799 }
800
801 uname(&utsname);
802 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
803
804 /*
805 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
806 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
807 * Since these must be part of guest physical memory, we need to allocate
808 * them, both by setting their start addresses in the kernel and by
809 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
810 *
811 * Older KVM versions may not support setting the identity map base. In
812 * that case we need to stick with the default, i.e. a 256K maximum BIOS
813 * size.
814 */
815 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
816 /* Allows up to 16M BIOSes. */
817 identity_base = 0xfeffc000;
818
819 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
820 if (ret < 0) {
821 return ret;
822 }
823 }
824
825 /* Set TSS base one page after EPT identity map. */
826 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
827 if (ret < 0) {
828 return ret;
829 }
830
831 /* Tell fw_cfg to notify the BIOS to reserve the range. */
832 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
833 if (ret < 0) {
834 fprintf(stderr, "e820_add_entry() table is full\n");
835 return ret;
836 }
837 qemu_register_reset(kvm_unpoison_all, NULL);
838
839 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
840 "kvm_shadow_mem", -1);
841 if (shadow_mem != -1) {
842 shadow_mem /= 4096;
843 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
844 if (ret < 0) {
845 return ret;
846 }
847 }
848 return 0;
849 }
850
851 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
852 {
853 lhs->selector = rhs->selector;
854 lhs->base = rhs->base;
855 lhs->limit = rhs->limit;
856 lhs->type = 3;
857 lhs->present = 1;
858 lhs->dpl = 3;
859 lhs->db = 0;
860 lhs->s = 1;
861 lhs->l = 0;
862 lhs->g = 0;
863 lhs->avl = 0;
864 lhs->unusable = 0;
865 }
866
867 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
868 {
869 unsigned flags = rhs->flags;
870 lhs->selector = rhs->selector;
871 lhs->base = rhs->base;
872 lhs->limit = rhs->limit;
873 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
874 lhs->present = (flags & DESC_P_MASK) != 0;
875 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
876 lhs->db = (flags >> DESC_B_SHIFT) & 1;
877 lhs->s = (flags & DESC_S_MASK) != 0;
878 lhs->l = (flags >> DESC_L_SHIFT) & 1;
879 lhs->g = (flags & DESC_G_MASK) != 0;
880 lhs->avl = (flags & DESC_AVL_MASK) != 0;
881 lhs->unusable = 0;
882 lhs->padding = 0;
883 }
884
885 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
886 {
887 lhs->selector = rhs->selector;
888 lhs->base = rhs->base;
889 lhs->limit = rhs->limit;
890 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
891 (rhs->present * DESC_P_MASK) |
892 (rhs->dpl << DESC_DPL_SHIFT) |
893 (rhs->db << DESC_B_SHIFT) |
894 (rhs->s * DESC_S_MASK) |
895 (rhs->l << DESC_L_SHIFT) |
896 (rhs->g * DESC_G_MASK) |
897 (rhs->avl * DESC_AVL_MASK);
898 }
899
900 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
901 {
902 if (set) {
903 *kvm_reg = *qemu_reg;
904 } else {
905 *qemu_reg = *kvm_reg;
906 }
907 }
908
909 static int kvm_getput_regs(X86CPU *cpu, int set)
910 {
911 CPUX86State *env = &cpu->env;
912 struct kvm_regs regs;
913 int ret = 0;
914
915 if (!set) {
916 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
917 if (ret < 0) {
918 return ret;
919 }
920 }
921
922 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
923 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
924 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
925 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
926 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
927 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
928 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
929 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
930 #ifdef TARGET_X86_64
931 kvm_getput_reg(&regs.r8, &env->regs[8], set);
932 kvm_getput_reg(&regs.r9, &env->regs[9], set);
933 kvm_getput_reg(&regs.r10, &env->regs[10], set);
934 kvm_getput_reg(&regs.r11, &env->regs[11], set);
935 kvm_getput_reg(&regs.r12, &env->regs[12], set);
936 kvm_getput_reg(&regs.r13, &env->regs[13], set);
937 kvm_getput_reg(&regs.r14, &env->regs[14], set);
938 kvm_getput_reg(&regs.r15, &env->regs[15], set);
939 #endif
940
941 kvm_getput_reg(&regs.rflags, &env->eflags, set);
942 kvm_getput_reg(&regs.rip, &env->eip, set);
943
944 if (set) {
945 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
946 }
947
948 return ret;
949 }
950
951 static int kvm_put_fpu(X86CPU *cpu)
952 {
953 CPUX86State *env = &cpu->env;
954 struct kvm_fpu fpu;
955 int i;
956
957 memset(&fpu, 0, sizeof fpu);
958 fpu.fsw = env->fpus & ~(7 << 11);
959 fpu.fsw |= (env->fpstt & 7) << 11;
960 fpu.fcw = env->fpuc;
961 fpu.last_opcode = env->fpop;
962 fpu.last_ip = env->fpip;
963 fpu.last_dp = env->fpdp;
964 for (i = 0; i < 8; ++i) {
965 fpu.ftwx |= (!env->fptags[i]) << i;
966 }
967 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
968 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
969 fpu.mxcsr = env->mxcsr;
970
971 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
972 }
973
974 #define XSAVE_FCW_FSW 0
975 #define XSAVE_FTW_FOP 1
976 #define XSAVE_CWD_RIP 2
977 #define XSAVE_CWD_RDP 4
978 #define XSAVE_MXCSR 6
979 #define XSAVE_ST_SPACE 8
980 #define XSAVE_XMM_SPACE 40
981 #define XSAVE_XSTATE_BV 128
982 #define XSAVE_YMMH_SPACE 144
983 #define XSAVE_BNDREGS 240
984 #define XSAVE_BNDCSR 256
985
986 static int kvm_put_xsave(X86CPU *cpu)
987 {
988 CPUX86State *env = &cpu->env;
989 struct kvm_xsave* xsave = env->kvm_xsave_buf;
990 uint16_t cwd, swd, twd;
991 int i, r;
992
993 if (!kvm_has_xsave()) {
994 return kvm_put_fpu(cpu);
995 }
996
997 memset(xsave, 0, sizeof(struct kvm_xsave));
998 twd = 0;
999 swd = env->fpus & ~(7 << 11);
1000 swd |= (env->fpstt & 7) << 11;
1001 cwd = env->fpuc;
1002 for (i = 0; i < 8; ++i) {
1003 twd |= (!env->fptags[i]) << i;
1004 }
1005 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1006 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1007 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1008 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1009 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1010 sizeof env->fpregs);
1011 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
1012 sizeof env->xmm_regs);
1013 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1014 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1015 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
1016 sizeof env->ymmh_regs);
1017 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1018 sizeof env->bnd_regs);
1019 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1020 sizeof(env->bndcs_regs));
1021 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1022 return r;
1023 }
1024
1025 static int kvm_put_xcrs(X86CPU *cpu)
1026 {
1027 CPUX86State *env = &cpu->env;
1028 struct kvm_xcrs xcrs;
1029
1030 if (!kvm_has_xcrs()) {
1031 return 0;
1032 }
1033
1034 xcrs.nr_xcrs = 1;
1035 xcrs.flags = 0;
1036 xcrs.xcrs[0].xcr = 0;
1037 xcrs.xcrs[0].value = env->xcr0;
1038 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1039 }
1040
1041 static int kvm_put_sregs(X86CPU *cpu)
1042 {
1043 CPUX86State *env = &cpu->env;
1044 struct kvm_sregs sregs;
1045
1046 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1047 if (env->interrupt_injected >= 0) {
1048 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1049 (uint64_t)1 << (env->interrupt_injected % 64);
1050 }
1051
1052 if ((env->eflags & VM_MASK)) {
1053 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1054 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1055 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1056 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1057 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1058 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1059 } else {
1060 set_seg(&sregs.cs, &env->segs[R_CS]);
1061 set_seg(&sregs.ds, &env->segs[R_DS]);
1062 set_seg(&sregs.es, &env->segs[R_ES]);
1063 set_seg(&sregs.fs, &env->segs[R_FS]);
1064 set_seg(&sregs.gs, &env->segs[R_GS]);
1065 set_seg(&sregs.ss, &env->segs[R_SS]);
1066 }
1067
1068 set_seg(&sregs.tr, &env->tr);
1069 set_seg(&sregs.ldt, &env->ldt);
1070
1071 sregs.idt.limit = env->idt.limit;
1072 sregs.idt.base = env->idt.base;
1073 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1074 sregs.gdt.limit = env->gdt.limit;
1075 sregs.gdt.base = env->gdt.base;
1076 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1077
1078 sregs.cr0 = env->cr[0];
1079 sregs.cr2 = env->cr[2];
1080 sregs.cr3 = env->cr[3];
1081 sregs.cr4 = env->cr[4];
1082
1083 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1084 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1085
1086 sregs.efer = env->efer;
1087
1088 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1089 }
1090
1091 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1092 uint32_t index, uint64_t value)
1093 {
1094 entry->index = index;
1095 entry->data = value;
1096 }
1097
1098 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1099 {
1100 CPUX86State *env = &cpu->env;
1101 struct {
1102 struct kvm_msrs info;
1103 struct kvm_msr_entry entries[1];
1104 } msr_data;
1105 struct kvm_msr_entry *msrs = msr_data.entries;
1106
1107 if (!has_msr_tsc_deadline) {
1108 return 0;
1109 }
1110
1111 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1112
1113 msr_data.info.nmsrs = 1;
1114
1115 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1116 }
1117
1118 /*
1119 * Provide a separate write service for the feature control MSR in order to
1120 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1121 * before writing any other state because forcibly leaving nested mode
1122 * invalidates the VCPU state.
1123 */
1124 static int kvm_put_msr_feature_control(X86CPU *cpu)
1125 {
1126 struct {
1127 struct kvm_msrs info;
1128 struct kvm_msr_entry entry;
1129 } msr_data;
1130
1131 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1132 cpu->env.msr_ia32_feature_control);
1133 msr_data.info.nmsrs = 1;
1134 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1135 }
1136
1137 static int kvm_put_msrs(X86CPU *cpu, int level)
1138 {
1139 CPUX86State *env = &cpu->env;
1140 struct {
1141 struct kvm_msrs info;
1142 struct kvm_msr_entry entries[100];
1143 } msr_data;
1144 struct kvm_msr_entry *msrs = msr_data.entries;
1145 int n = 0, i;
1146
1147 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1148 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1149 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1150 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1151 if (has_msr_star) {
1152 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1153 }
1154 if (has_msr_hsave_pa) {
1155 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1156 }
1157 if (has_msr_tsc_adjust) {
1158 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1159 }
1160 if (has_msr_misc_enable) {
1161 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1162 env->msr_ia32_misc_enable);
1163 }
1164 if (has_msr_bndcfgs) {
1165 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1166 }
1167 #ifdef TARGET_X86_64
1168 if (lm_capable_kernel) {
1169 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1170 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1171 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1172 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1173 }
1174 #endif
1175 /*
1176 * The following MSRs have side effects on the guest or are too heavy
1177 * for normal writeback. Limit them to reset or full state updates.
1178 */
1179 if (level >= KVM_PUT_RESET_STATE) {
1180 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1181 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1182 env->system_time_msr);
1183 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1184 if (has_msr_async_pf_en) {
1185 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1186 env->async_pf_en_msr);
1187 }
1188 if (has_msr_pv_eoi_en) {
1189 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1190 env->pv_eoi_en_msr);
1191 }
1192 if (has_msr_kvm_steal_time) {
1193 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1194 env->steal_time_msr);
1195 }
1196 if (has_msr_architectural_pmu) {
1197 /* Stop the counter. */
1198 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1199 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1200
1201 /* Set the counter values. */
1202 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1203 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1204 env->msr_fixed_counters[i]);
1205 }
1206 for (i = 0; i < num_architectural_pmu_counters; i++) {
1207 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1208 env->msr_gp_counters[i]);
1209 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1210 env->msr_gp_evtsel[i]);
1211 }
1212 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1213 env->msr_global_status);
1214 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1215 env->msr_global_ovf_ctrl);
1216
1217 /* Now start the PMU. */
1218 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1219 env->msr_fixed_ctr_ctrl);
1220 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1221 env->msr_global_ctrl);
1222 }
1223 if (hyperv_hypercall_available(cpu)) {
1224 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1225 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1226 }
1227 if (cpu->hyperv_vapic) {
1228 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1229 }
1230
1231 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1232 * kvm_put_msr_feature_control. */
1233 }
1234 if (env->mcg_cap) {
1235 int i;
1236
1237 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1238 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1239 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1240 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1241 }
1242 }
1243
1244 msr_data.info.nmsrs = n;
1245
1246 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1247
1248 }
1249
1250
1251 static int kvm_get_fpu(X86CPU *cpu)
1252 {
1253 CPUX86State *env = &cpu->env;
1254 struct kvm_fpu fpu;
1255 int i, ret;
1256
1257 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1258 if (ret < 0) {
1259 return ret;
1260 }
1261
1262 env->fpstt = (fpu.fsw >> 11) & 7;
1263 env->fpus = fpu.fsw;
1264 env->fpuc = fpu.fcw;
1265 env->fpop = fpu.last_opcode;
1266 env->fpip = fpu.last_ip;
1267 env->fpdp = fpu.last_dp;
1268 for (i = 0; i < 8; ++i) {
1269 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1270 }
1271 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1272 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1273 env->mxcsr = fpu.mxcsr;
1274
1275 return 0;
1276 }
1277
1278 static int kvm_get_xsave(X86CPU *cpu)
1279 {
1280 CPUX86State *env = &cpu->env;
1281 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1282 int ret, i;
1283 uint16_t cwd, swd, twd;
1284
1285 if (!kvm_has_xsave()) {
1286 return kvm_get_fpu(cpu);
1287 }
1288
1289 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1290 if (ret < 0) {
1291 return ret;
1292 }
1293
1294 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1295 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1296 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1297 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1298 env->fpstt = (swd >> 11) & 7;
1299 env->fpus = swd;
1300 env->fpuc = cwd;
1301 for (i = 0; i < 8; ++i) {
1302 env->fptags[i] = !((twd >> i) & 1);
1303 }
1304 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1305 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1306 env->mxcsr = xsave->region[XSAVE_MXCSR];
1307 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1308 sizeof env->fpregs);
1309 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1310 sizeof env->xmm_regs);
1311 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1312 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1313 sizeof env->ymmh_regs);
1314 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1315 sizeof env->bnd_regs);
1316 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1317 sizeof(env->bndcs_regs));
1318 return 0;
1319 }
1320
1321 static int kvm_get_xcrs(X86CPU *cpu)
1322 {
1323 CPUX86State *env = &cpu->env;
1324 int i, ret;
1325 struct kvm_xcrs xcrs;
1326
1327 if (!kvm_has_xcrs()) {
1328 return 0;
1329 }
1330
1331 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1332 if (ret < 0) {
1333 return ret;
1334 }
1335
1336 for (i = 0; i < xcrs.nr_xcrs; i++) {
1337 /* Only support xcr0 now */
1338 if (xcrs.xcrs[i].xcr == 0) {
1339 env->xcr0 = xcrs.xcrs[i].value;
1340 break;
1341 }
1342 }
1343 return 0;
1344 }
1345
1346 static int kvm_get_sregs(X86CPU *cpu)
1347 {
1348 CPUX86State *env = &cpu->env;
1349 struct kvm_sregs sregs;
1350 uint32_t hflags;
1351 int bit, i, ret;
1352
1353 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1354 if (ret < 0) {
1355 return ret;
1356 }
1357
1358 /* There can only be one pending IRQ set in the bitmap at a time, so try
1359 to find it and save its number instead (-1 for none). */
1360 env->interrupt_injected = -1;
1361 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1362 if (sregs.interrupt_bitmap[i]) {
1363 bit = ctz64(sregs.interrupt_bitmap[i]);
1364 env->interrupt_injected = i * 64 + bit;
1365 break;
1366 }
1367 }
1368
1369 get_seg(&env->segs[R_CS], &sregs.cs);
1370 get_seg(&env->segs[R_DS], &sregs.ds);
1371 get_seg(&env->segs[R_ES], &sregs.es);
1372 get_seg(&env->segs[R_FS], &sregs.fs);
1373 get_seg(&env->segs[R_GS], &sregs.gs);
1374 get_seg(&env->segs[R_SS], &sregs.ss);
1375
1376 get_seg(&env->tr, &sregs.tr);
1377 get_seg(&env->ldt, &sregs.ldt);
1378
1379 env->idt.limit = sregs.idt.limit;
1380 env->idt.base = sregs.idt.base;
1381 env->gdt.limit = sregs.gdt.limit;
1382 env->gdt.base = sregs.gdt.base;
1383
1384 env->cr[0] = sregs.cr0;
1385 env->cr[2] = sregs.cr2;
1386 env->cr[3] = sregs.cr3;
1387 env->cr[4] = sregs.cr4;
1388
1389 env->efer = sregs.efer;
1390
1391 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1392
1393 #define HFLAG_COPY_MASK \
1394 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1395 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1396 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1397 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1398
1399 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1400 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1401 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1402 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1403 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1404 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1405 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1406
1407 if (env->efer & MSR_EFER_LMA) {
1408 hflags |= HF_LMA_MASK;
1409 }
1410
1411 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1412 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1413 } else {
1414 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1415 (DESC_B_SHIFT - HF_CS32_SHIFT);
1416 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1417 (DESC_B_SHIFT - HF_SS32_SHIFT);
1418 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1419 !(hflags & HF_CS32_MASK)) {
1420 hflags |= HF_ADDSEG_MASK;
1421 } else {
1422 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1423 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1424 }
1425 }
1426 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1427
1428 return 0;
1429 }
1430
1431 static int kvm_get_msrs(X86CPU *cpu)
1432 {
1433 CPUX86State *env = &cpu->env;
1434 struct {
1435 struct kvm_msrs info;
1436 struct kvm_msr_entry entries[100];
1437 } msr_data;
1438 struct kvm_msr_entry *msrs = msr_data.entries;
1439 int ret, i, n;
1440
1441 n = 0;
1442 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1443 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1444 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1445 msrs[n++].index = MSR_PAT;
1446 if (has_msr_star) {
1447 msrs[n++].index = MSR_STAR;
1448 }
1449 if (has_msr_hsave_pa) {
1450 msrs[n++].index = MSR_VM_HSAVE_PA;
1451 }
1452 if (has_msr_tsc_adjust) {
1453 msrs[n++].index = MSR_TSC_ADJUST;
1454 }
1455 if (has_msr_tsc_deadline) {
1456 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1457 }
1458 if (has_msr_misc_enable) {
1459 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1460 }
1461 if (has_msr_feature_control) {
1462 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1463 }
1464 if (has_msr_bndcfgs) {
1465 msrs[n++].index = MSR_IA32_BNDCFGS;
1466 }
1467
1468 if (!env->tsc_valid) {
1469 msrs[n++].index = MSR_IA32_TSC;
1470 env->tsc_valid = !runstate_is_running();
1471 }
1472
1473 #ifdef TARGET_X86_64
1474 if (lm_capable_kernel) {
1475 msrs[n++].index = MSR_CSTAR;
1476 msrs[n++].index = MSR_KERNELGSBASE;
1477 msrs[n++].index = MSR_FMASK;
1478 msrs[n++].index = MSR_LSTAR;
1479 }
1480 #endif
1481 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1482 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1483 if (has_msr_async_pf_en) {
1484 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1485 }
1486 if (has_msr_pv_eoi_en) {
1487 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1488 }
1489 if (has_msr_kvm_steal_time) {
1490 msrs[n++].index = MSR_KVM_STEAL_TIME;
1491 }
1492 if (has_msr_architectural_pmu) {
1493 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1494 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1495 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1496 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1497 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1498 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1499 }
1500 for (i = 0; i < num_architectural_pmu_counters; i++) {
1501 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1502 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1503 }
1504 }
1505
1506 if (env->mcg_cap) {
1507 msrs[n++].index = MSR_MCG_STATUS;
1508 msrs[n++].index = MSR_MCG_CTL;
1509 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1510 msrs[n++].index = MSR_MC0_CTL + i;
1511 }
1512 }
1513
1514 msr_data.info.nmsrs = n;
1515 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1516 if (ret < 0) {
1517 return ret;
1518 }
1519
1520 for (i = 0; i < ret; i++) {
1521 uint32_t index = msrs[i].index;
1522 switch (index) {
1523 case MSR_IA32_SYSENTER_CS:
1524 env->sysenter_cs = msrs[i].data;
1525 break;
1526 case MSR_IA32_SYSENTER_ESP:
1527 env->sysenter_esp = msrs[i].data;
1528 break;
1529 case MSR_IA32_SYSENTER_EIP:
1530 env->sysenter_eip = msrs[i].data;
1531 break;
1532 case MSR_PAT:
1533 env->pat = msrs[i].data;
1534 break;
1535 case MSR_STAR:
1536 env->star = msrs[i].data;
1537 break;
1538 #ifdef TARGET_X86_64
1539 case MSR_CSTAR:
1540 env->cstar = msrs[i].data;
1541 break;
1542 case MSR_KERNELGSBASE:
1543 env->kernelgsbase = msrs[i].data;
1544 break;
1545 case MSR_FMASK:
1546 env->fmask = msrs[i].data;
1547 break;
1548 case MSR_LSTAR:
1549 env->lstar = msrs[i].data;
1550 break;
1551 #endif
1552 case MSR_IA32_TSC:
1553 env->tsc = msrs[i].data;
1554 break;
1555 case MSR_TSC_ADJUST:
1556 env->tsc_adjust = msrs[i].data;
1557 break;
1558 case MSR_IA32_TSCDEADLINE:
1559 env->tsc_deadline = msrs[i].data;
1560 break;
1561 case MSR_VM_HSAVE_PA:
1562 env->vm_hsave = msrs[i].data;
1563 break;
1564 case MSR_KVM_SYSTEM_TIME:
1565 env->system_time_msr = msrs[i].data;
1566 break;
1567 case MSR_KVM_WALL_CLOCK:
1568 env->wall_clock_msr = msrs[i].data;
1569 break;
1570 case MSR_MCG_STATUS:
1571 env->mcg_status = msrs[i].data;
1572 break;
1573 case MSR_MCG_CTL:
1574 env->mcg_ctl = msrs[i].data;
1575 break;
1576 case MSR_IA32_MISC_ENABLE:
1577 env->msr_ia32_misc_enable = msrs[i].data;
1578 break;
1579 case MSR_IA32_FEATURE_CONTROL:
1580 env->msr_ia32_feature_control = msrs[i].data;
1581 break;
1582 case MSR_IA32_BNDCFGS:
1583 env->msr_bndcfgs = msrs[i].data;
1584 break;
1585 default:
1586 if (msrs[i].index >= MSR_MC0_CTL &&
1587 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1588 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1589 }
1590 break;
1591 case MSR_KVM_ASYNC_PF_EN:
1592 env->async_pf_en_msr = msrs[i].data;
1593 break;
1594 case MSR_KVM_PV_EOI_EN:
1595 env->pv_eoi_en_msr = msrs[i].data;
1596 break;
1597 case MSR_KVM_STEAL_TIME:
1598 env->steal_time_msr = msrs[i].data;
1599 break;
1600 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1601 env->msr_fixed_ctr_ctrl = msrs[i].data;
1602 break;
1603 case MSR_CORE_PERF_GLOBAL_CTRL:
1604 env->msr_global_ctrl = msrs[i].data;
1605 break;
1606 case MSR_CORE_PERF_GLOBAL_STATUS:
1607 env->msr_global_status = msrs[i].data;
1608 break;
1609 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1610 env->msr_global_ovf_ctrl = msrs[i].data;
1611 break;
1612 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1613 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1614 break;
1615 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1616 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1617 break;
1618 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1619 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1620 break;
1621 }
1622 }
1623
1624 return 0;
1625 }
1626
1627 static int kvm_put_mp_state(X86CPU *cpu)
1628 {
1629 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1630
1631 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1632 }
1633
1634 static int kvm_get_mp_state(X86CPU *cpu)
1635 {
1636 CPUState *cs = CPU(cpu);
1637 CPUX86State *env = &cpu->env;
1638 struct kvm_mp_state mp_state;
1639 int ret;
1640
1641 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1642 if (ret < 0) {
1643 return ret;
1644 }
1645 env->mp_state = mp_state.mp_state;
1646 if (kvm_irqchip_in_kernel()) {
1647 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1648 }
1649 return 0;
1650 }
1651
1652 static int kvm_get_apic(X86CPU *cpu)
1653 {
1654 DeviceState *apic = cpu->apic_state;
1655 struct kvm_lapic_state kapic;
1656 int ret;
1657
1658 if (apic && kvm_irqchip_in_kernel()) {
1659 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1660 if (ret < 0) {
1661 return ret;
1662 }
1663
1664 kvm_get_apic_state(apic, &kapic);
1665 }
1666 return 0;
1667 }
1668
1669 static int kvm_put_apic(X86CPU *cpu)
1670 {
1671 DeviceState *apic = cpu->apic_state;
1672 struct kvm_lapic_state kapic;
1673
1674 if (apic && kvm_irqchip_in_kernel()) {
1675 kvm_put_apic_state(apic, &kapic);
1676
1677 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1678 }
1679 return 0;
1680 }
1681
1682 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1683 {
1684 CPUX86State *env = &cpu->env;
1685 struct kvm_vcpu_events events;
1686
1687 if (!kvm_has_vcpu_events()) {
1688 return 0;
1689 }
1690
1691 events.exception.injected = (env->exception_injected >= 0);
1692 events.exception.nr = env->exception_injected;
1693 events.exception.has_error_code = env->has_error_code;
1694 events.exception.error_code = env->error_code;
1695 events.exception.pad = 0;
1696
1697 events.interrupt.injected = (env->interrupt_injected >= 0);
1698 events.interrupt.nr = env->interrupt_injected;
1699 events.interrupt.soft = env->soft_interrupt;
1700
1701 events.nmi.injected = env->nmi_injected;
1702 events.nmi.pending = env->nmi_pending;
1703 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1704 events.nmi.pad = 0;
1705
1706 events.sipi_vector = env->sipi_vector;
1707
1708 events.flags = 0;
1709 if (level >= KVM_PUT_RESET_STATE) {
1710 events.flags |=
1711 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1712 }
1713
1714 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1715 }
1716
1717 static int kvm_get_vcpu_events(X86CPU *cpu)
1718 {
1719 CPUX86State *env = &cpu->env;
1720 struct kvm_vcpu_events events;
1721 int ret;
1722
1723 if (!kvm_has_vcpu_events()) {
1724 return 0;
1725 }
1726
1727 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1728 if (ret < 0) {
1729 return ret;
1730 }
1731 env->exception_injected =
1732 events.exception.injected ? events.exception.nr : -1;
1733 env->has_error_code = events.exception.has_error_code;
1734 env->error_code = events.exception.error_code;
1735
1736 env->interrupt_injected =
1737 events.interrupt.injected ? events.interrupt.nr : -1;
1738 env->soft_interrupt = events.interrupt.soft;
1739
1740 env->nmi_injected = events.nmi.injected;
1741 env->nmi_pending = events.nmi.pending;
1742 if (events.nmi.masked) {
1743 env->hflags2 |= HF2_NMI_MASK;
1744 } else {
1745 env->hflags2 &= ~HF2_NMI_MASK;
1746 }
1747
1748 env->sipi_vector = events.sipi_vector;
1749
1750 return 0;
1751 }
1752
1753 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1754 {
1755 CPUState *cs = CPU(cpu);
1756 CPUX86State *env = &cpu->env;
1757 int ret = 0;
1758 unsigned long reinject_trap = 0;
1759
1760 if (!kvm_has_vcpu_events()) {
1761 if (env->exception_injected == 1) {
1762 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1763 } else if (env->exception_injected == 3) {
1764 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1765 }
1766 env->exception_injected = -1;
1767 }
1768
1769 /*
1770 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1771 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1772 * by updating the debug state once again if single-stepping is on.
1773 * Another reason to call kvm_update_guest_debug here is a pending debug
1774 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1775 * reinject them via SET_GUEST_DEBUG.
1776 */
1777 if (reinject_trap ||
1778 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1779 ret = kvm_update_guest_debug(cs, reinject_trap);
1780 }
1781 return ret;
1782 }
1783
1784 static int kvm_put_debugregs(X86CPU *cpu)
1785 {
1786 CPUX86State *env = &cpu->env;
1787 struct kvm_debugregs dbgregs;
1788 int i;
1789
1790 if (!kvm_has_debugregs()) {
1791 return 0;
1792 }
1793
1794 for (i = 0; i < 4; i++) {
1795 dbgregs.db[i] = env->dr[i];
1796 }
1797 dbgregs.dr6 = env->dr[6];
1798 dbgregs.dr7 = env->dr[7];
1799 dbgregs.flags = 0;
1800
1801 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1802 }
1803
1804 static int kvm_get_debugregs(X86CPU *cpu)
1805 {
1806 CPUX86State *env = &cpu->env;
1807 struct kvm_debugregs dbgregs;
1808 int i, ret;
1809
1810 if (!kvm_has_debugregs()) {
1811 return 0;
1812 }
1813
1814 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1815 if (ret < 0) {
1816 return ret;
1817 }
1818 for (i = 0; i < 4; i++) {
1819 env->dr[i] = dbgregs.db[i];
1820 }
1821 env->dr[4] = env->dr[6] = dbgregs.dr6;
1822 env->dr[5] = env->dr[7] = dbgregs.dr7;
1823
1824 return 0;
1825 }
1826
1827 int kvm_arch_put_registers(CPUState *cpu, int level)
1828 {
1829 X86CPU *x86_cpu = X86_CPU(cpu);
1830 int ret;
1831
1832 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1833
1834 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
1835 ret = kvm_put_msr_feature_control(x86_cpu);
1836 if (ret < 0) {
1837 return ret;
1838 }
1839 }
1840
1841 ret = kvm_getput_regs(x86_cpu, 1);
1842 if (ret < 0) {
1843 return ret;
1844 }
1845 ret = kvm_put_xsave(x86_cpu);
1846 if (ret < 0) {
1847 return ret;
1848 }
1849 ret = kvm_put_xcrs(x86_cpu);
1850 if (ret < 0) {
1851 return ret;
1852 }
1853 ret = kvm_put_sregs(x86_cpu);
1854 if (ret < 0) {
1855 return ret;
1856 }
1857 /* must be before kvm_put_msrs */
1858 ret = kvm_inject_mce_oldstyle(x86_cpu);
1859 if (ret < 0) {
1860 return ret;
1861 }
1862 ret = kvm_put_msrs(x86_cpu, level);
1863 if (ret < 0) {
1864 return ret;
1865 }
1866 if (level >= KVM_PUT_RESET_STATE) {
1867 ret = kvm_put_mp_state(x86_cpu);
1868 if (ret < 0) {
1869 return ret;
1870 }
1871 ret = kvm_put_apic(x86_cpu);
1872 if (ret < 0) {
1873 return ret;
1874 }
1875 }
1876
1877 ret = kvm_put_tscdeadline_msr(x86_cpu);
1878 if (ret < 0) {
1879 return ret;
1880 }
1881
1882 ret = kvm_put_vcpu_events(x86_cpu, level);
1883 if (ret < 0) {
1884 return ret;
1885 }
1886 ret = kvm_put_debugregs(x86_cpu);
1887 if (ret < 0) {
1888 return ret;
1889 }
1890 /* must be last */
1891 ret = kvm_guest_debug_workarounds(x86_cpu);
1892 if (ret < 0) {
1893 return ret;
1894 }
1895 return 0;
1896 }
1897
1898 int kvm_arch_get_registers(CPUState *cs)
1899 {
1900 X86CPU *cpu = X86_CPU(cs);
1901 int ret;
1902
1903 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1904
1905 ret = kvm_getput_regs(cpu, 0);
1906 if (ret < 0) {
1907 return ret;
1908 }
1909 ret = kvm_get_xsave(cpu);
1910 if (ret < 0) {
1911 return ret;
1912 }
1913 ret = kvm_get_xcrs(cpu);
1914 if (ret < 0) {
1915 return ret;
1916 }
1917 ret = kvm_get_sregs(cpu);
1918 if (ret < 0) {
1919 return ret;
1920 }
1921 ret = kvm_get_msrs(cpu);
1922 if (ret < 0) {
1923 return ret;
1924 }
1925 ret = kvm_get_mp_state(cpu);
1926 if (ret < 0) {
1927 return ret;
1928 }
1929 ret = kvm_get_apic(cpu);
1930 if (ret < 0) {
1931 return ret;
1932 }
1933 ret = kvm_get_vcpu_events(cpu);
1934 if (ret < 0) {
1935 return ret;
1936 }
1937 ret = kvm_get_debugregs(cpu);
1938 if (ret < 0) {
1939 return ret;
1940 }
1941 return 0;
1942 }
1943
1944 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1945 {
1946 X86CPU *x86_cpu = X86_CPU(cpu);
1947 CPUX86State *env = &x86_cpu->env;
1948 int ret;
1949
1950 /* Inject NMI */
1951 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
1952 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
1953 DPRINTF("injected NMI\n");
1954 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
1955 if (ret < 0) {
1956 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1957 strerror(-ret));
1958 }
1959 }
1960
1961 if (!kvm_irqchip_in_kernel()) {
1962 /* Force the VCPU out of its inner loop to process any INIT requests
1963 * or pending TPR access reports. */
1964 if (cpu->interrupt_request &
1965 (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1966 cpu->exit_request = 1;
1967 }
1968
1969 /* Try to inject an interrupt if the guest can accept it */
1970 if (run->ready_for_interrupt_injection &&
1971 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
1972 (env->eflags & IF_MASK)) {
1973 int irq;
1974
1975 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
1976 irq = cpu_get_pic_interrupt(env);
1977 if (irq >= 0) {
1978 struct kvm_interrupt intr;
1979
1980 intr.irq = irq;
1981 DPRINTF("injected interrupt %d\n", irq);
1982 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
1983 if (ret < 0) {
1984 fprintf(stderr,
1985 "KVM: injection failed, interrupt lost (%s)\n",
1986 strerror(-ret));
1987 }
1988 }
1989 }
1990
1991 /* If we have an interrupt but the guest is not ready to receive an
1992 * interrupt, request an interrupt window exit. This will
1993 * cause a return to userspace as soon as the guest is ready to
1994 * receive interrupts. */
1995 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
1996 run->request_interrupt_window = 1;
1997 } else {
1998 run->request_interrupt_window = 0;
1999 }
2000
2001 DPRINTF("setting tpr\n");
2002 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2003 }
2004 }
2005
2006 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2007 {
2008 X86CPU *x86_cpu = X86_CPU(cpu);
2009 CPUX86State *env = &x86_cpu->env;
2010
2011 if (run->if_flag) {
2012 env->eflags |= IF_MASK;
2013 } else {
2014 env->eflags &= ~IF_MASK;
2015 }
2016 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2017 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2018 }
2019
2020 int kvm_arch_process_async_events(CPUState *cs)
2021 {
2022 X86CPU *cpu = X86_CPU(cs);
2023 CPUX86State *env = &cpu->env;
2024
2025 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2026 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2027 assert(env->mcg_cap);
2028
2029 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2030
2031 kvm_cpu_synchronize_state(cs);
2032
2033 if (env->exception_injected == EXCP08_DBLE) {
2034 /* this means triple fault */
2035 qemu_system_reset_request();
2036 cs->exit_request = 1;
2037 return 0;
2038 }
2039 env->exception_injected = EXCP12_MCHK;
2040 env->has_error_code = 0;
2041
2042 cs->halted = 0;
2043 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2044 env->mp_state = KVM_MP_STATE_RUNNABLE;
2045 }
2046 }
2047
2048 if (kvm_irqchip_in_kernel()) {
2049 return 0;
2050 }
2051
2052 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2053 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2054 apic_poll_irq(cpu->apic_state);
2055 }
2056 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2057 (env->eflags & IF_MASK)) ||
2058 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2059 cs->halted = 0;
2060 }
2061 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2062 kvm_cpu_synchronize_state(cs);
2063 do_cpu_init(cpu);
2064 }
2065 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2066 kvm_cpu_synchronize_state(cs);
2067 do_cpu_sipi(cpu);
2068 }
2069 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2070 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2071 kvm_cpu_synchronize_state(cs);
2072 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2073 env->tpr_access_type);
2074 }
2075
2076 return cs->halted;
2077 }
2078
2079 static int kvm_handle_halt(X86CPU *cpu)
2080 {
2081 CPUState *cs = CPU(cpu);
2082 CPUX86State *env = &cpu->env;
2083
2084 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2085 (env->eflags & IF_MASK)) &&
2086 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2087 cs->halted = 1;
2088 return EXCP_HLT;
2089 }
2090
2091 return 0;
2092 }
2093
2094 static int kvm_handle_tpr_access(X86CPU *cpu)
2095 {
2096 CPUState *cs = CPU(cpu);
2097 struct kvm_run *run = cs->kvm_run;
2098
2099 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2100 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2101 : TPR_ACCESS_READ);
2102 return 1;
2103 }
2104
2105 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2106 {
2107 static const uint8_t int3 = 0xcc;
2108
2109 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2110 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2111 return -EINVAL;
2112 }
2113 return 0;
2114 }
2115
2116 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2117 {
2118 uint8_t int3;
2119
2120 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2121 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2122 return -EINVAL;
2123 }
2124 return 0;
2125 }
2126
2127 static struct {
2128 target_ulong addr;
2129 int len;
2130 int type;
2131 } hw_breakpoint[4];
2132
2133 static int nb_hw_breakpoint;
2134
2135 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2136 {
2137 int n;
2138
2139 for (n = 0; n < nb_hw_breakpoint; n++) {
2140 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2141 (hw_breakpoint[n].len == len || len == -1)) {
2142 return n;
2143 }
2144 }
2145 return -1;
2146 }
2147
2148 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2149 target_ulong len, int type)
2150 {
2151 switch (type) {
2152 case GDB_BREAKPOINT_HW:
2153 len = 1;
2154 break;
2155 case GDB_WATCHPOINT_WRITE:
2156 case GDB_WATCHPOINT_ACCESS:
2157 switch (len) {
2158 case 1:
2159 break;
2160 case 2:
2161 case 4:
2162 case 8:
2163 if (addr & (len - 1)) {
2164 return -EINVAL;
2165 }
2166 break;
2167 default:
2168 return -EINVAL;
2169 }
2170 break;
2171 default:
2172 return -ENOSYS;
2173 }
2174
2175 if (nb_hw_breakpoint == 4) {
2176 return -ENOBUFS;
2177 }
2178 if (find_hw_breakpoint(addr, len, type) >= 0) {
2179 return -EEXIST;
2180 }
2181 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2182 hw_breakpoint[nb_hw_breakpoint].len = len;
2183 hw_breakpoint[nb_hw_breakpoint].type = type;
2184 nb_hw_breakpoint++;
2185
2186 return 0;
2187 }
2188
2189 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2190 target_ulong len, int type)
2191 {
2192 int n;
2193
2194 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2195 if (n < 0) {
2196 return -ENOENT;
2197 }
2198 nb_hw_breakpoint--;
2199 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2200
2201 return 0;
2202 }
2203
2204 void kvm_arch_remove_all_hw_breakpoints(void)
2205 {
2206 nb_hw_breakpoint = 0;
2207 }
2208
2209 static CPUWatchpoint hw_watchpoint;
2210
2211 static int kvm_handle_debug(X86CPU *cpu,
2212 struct kvm_debug_exit_arch *arch_info)
2213 {
2214 CPUState *cs = CPU(cpu);
2215 CPUX86State *env = &cpu->env;
2216 int ret = 0;
2217 int n;
2218
2219 if (arch_info->exception == 1) {
2220 if (arch_info->dr6 & (1 << 14)) {
2221 if (cs->singlestep_enabled) {
2222 ret = EXCP_DEBUG;
2223 }
2224 } else {
2225 for (n = 0; n < 4; n++) {
2226 if (arch_info->dr6 & (1 << n)) {
2227 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2228 case 0x0:
2229 ret = EXCP_DEBUG;
2230 break;
2231 case 0x1:
2232 ret = EXCP_DEBUG;
2233 env->watchpoint_hit = &hw_watchpoint;
2234 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2235 hw_watchpoint.flags = BP_MEM_WRITE;
2236 break;
2237 case 0x3:
2238 ret = EXCP_DEBUG;
2239 env->watchpoint_hit = &hw_watchpoint;
2240 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2241 hw_watchpoint.flags = BP_MEM_ACCESS;
2242 break;
2243 }
2244 }
2245 }
2246 }
2247 } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
2248 ret = EXCP_DEBUG;
2249 }
2250 if (ret == 0) {
2251 cpu_synchronize_state(CPU(cpu));
2252 assert(env->exception_injected == -1);
2253
2254 /* pass to guest */
2255 env->exception_injected = arch_info->exception;
2256 env->has_error_code = 0;
2257 }
2258
2259 return ret;
2260 }
2261
2262 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2263 {
2264 const uint8_t type_code[] = {
2265 [GDB_BREAKPOINT_HW] = 0x0,
2266 [GDB_WATCHPOINT_WRITE] = 0x1,
2267 [GDB_WATCHPOINT_ACCESS] = 0x3
2268 };
2269 const uint8_t len_code[] = {
2270 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2271 };
2272 int n;
2273
2274 if (kvm_sw_breakpoints_active(cpu)) {
2275 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2276 }
2277 if (nb_hw_breakpoint > 0) {
2278 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2279 dbg->arch.debugreg[7] = 0x0600;
2280 for (n = 0; n < nb_hw_breakpoint; n++) {
2281 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2282 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2283 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2284 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2285 }
2286 }
2287 }
2288
2289 static bool host_supports_vmx(void)
2290 {
2291 uint32_t ecx, unused;
2292
2293 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2294 return ecx & CPUID_EXT_VMX;
2295 }
2296
2297 #define VMX_INVALID_GUEST_STATE 0x80000021
2298
2299 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2300 {
2301 X86CPU *cpu = X86_CPU(cs);
2302 uint64_t code;
2303 int ret;
2304
2305 switch (run->exit_reason) {
2306 case KVM_EXIT_HLT:
2307 DPRINTF("handle_hlt\n");
2308 ret = kvm_handle_halt(cpu);
2309 break;
2310 case KVM_EXIT_SET_TPR:
2311 ret = 0;
2312 break;
2313 case KVM_EXIT_TPR_ACCESS:
2314 ret = kvm_handle_tpr_access(cpu);
2315 break;
2316 case KVM_EXIT_FAIL_ENTRY:
2317 code = run->fail_entry.hardware_entry_failure_reason;
2318 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2319 code);
2320 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2321 fprintf(stderr,
2322 "\nIf you're running a guest on an Intel machine without "
2323 "unrestricted mode\n"
2324 "support, the failure can be most likely due to the guest "
2325 "entering an invalid\n"
2326 "state for Intel VT. For example, the guest maybe running "
2327 "in big real mode\n"
2328 "which is not supported on less recent Intel processors."
2329 "\n\n");
2330 }
2331 ret = -1;
2332 break;
2333 case KVM_EXIT_EXCEPTION:
2334 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2335 run->ex.exception, run->ex.error_code);
2336 ret = -1;
2337 break;
2338 case KVM_EXIT_DEBUG:
2339 DPRINTF("kvm_exit_debug\n");
2340 ret = kvm_handle_debug(cpu, &run->debug.arch);
2341 break;
2342 default:
2343 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2344 ret = -1;
2345 break;
2346 }
2347
2348 return ret;
2349 }
2350
2351 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2352 {
2353 X86CPU *cpu = X86_CPU(cs);
2354 CPUX86State *env = &cpu->env;
2355
2356 kvm_cpu_synchronize_state(cs);
2357 return !(env->cr[0] & CR0_PE_MASK) ||
2358 ((env->segs[R_CS].selector & 3) != 3);
2359 }
2360
2361 void kvm_arch_init_irq_routing(KVMState *s)
2362 {
2363 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2364 /* If kernel can't do irq routing, interrupt source
2365 * override 0->2 cannot be set up as required by HPET.
2366 * So we have to disable it.
2367 */
2368 no_hpet = 1;
2369 }
2370 /* We know at this point that we're using the in-kernel
2371 * irqchip, so we can use irqfds, and on x86 we know
2372 * we can use msi via irqfd and GSI routing.
2373 */
2374 kvm_irqfds_allowed = true;
2375 kvm_msi_via_irqfd_allowed = true;
2376 kvm_gsi_routing_allowed = true;
2377 }
2378
2379 /* Classic KVM device assignment interface. Will remain x86 only. */
2380 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2381 uint32_t flags, uint32_t *dev_id)
2382 {
2383 struct kvm_assigned_pci_dev dev_data = {
2384 .segnr = dev_addr->domain,
2385 .busnr = dev_addr->bus,
2386 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2387 .flags = flags,
2388 };
2389 int ret;
2390
2391 dev_data.assigned_dev_id =
2392 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2393
2394 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2395 if (ret < 0) {
2396 return ret;
2397 }
2398
2399 *dev_id = dev_data.assigned_dev_id;
2400
2401 return 0;
2402 }
2403
2404 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2405 {
2406 struct kvm_assigned_pci_dev dev_data = {
2407 .assigned_dev_id = dev_id,
2408 };
2409
2410 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2411 }
2412
2413 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2414 uint32_t irq_type, uint32_t guest_irq)
2415 {
2416 struct kvm_assigned_irq assigned_irq = {
2417 .assigned_dev_id = dev_id,
2418 .guest_irq = guest_irq,
2419 .flags = irq_type,
2420 };
2421
2422 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2423 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2424 } else {
2425 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2426 }
2427 }
2428
2429 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2430 uint32_t guest_irq)
2431 {
2432 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2433 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2434
2435 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2436 }
2437
2438 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2439 {
2440 struct kvm_assigned_pci_dev dev_data = {
2441 .assigned_dev_id = dev_id,
2442 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2443 };
2444
2445 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2446 }
2447
2448 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2449 uint32_t type)
2450 {
2451 struct kvm_assigned_irq assigned_irq = {
2452 .assigned_dev_id = dev_id,
2453 .flags = type,
2454 };
2455
2456 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2457 }
2458
2459 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2460 {
2461 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2462 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2463 }
2464
2465 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2466 {
2467 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2468 KVM_DEV_IRQ_GUEST_MSI, virq);
2469 }
2470
2471 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2472 {
2473 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2474 KVM_DEV_IRQ_HOST_MSI);
2475 }
2476
2477 bool kvm_device_msix_supported(KVMState *s)
2478 {
2479 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2480 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2481 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2482 }
2483
2484 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2485 uint32_t nr_vectors)
2486 {
2487 struct kvm_assigned_msix_nr msix_nr = {
2488 .assigned_dev_id = dev_id,
2489 .entry_nr = nr_vectors,
2490 };
2491
2492 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2493 }
2494
2495 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2496 int virq)
2497 {
2498 struct kvm_assigned_msix_entry msix_entry = {
2499 .assigned_dev_id = dev_id,
2500 .gsi = virq,
2501 .entry = vector,
2502 };
2503
2504 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2505 }
2506
2507 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2508 {
2509 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2510 KVM_DEV_IRQ_GUEST_MSIX, 0);
2511 }
2512
2513 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2514 {
2515 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2516 KVM_DEV_IRQ_HOST_MSIX);
2517 }
CRIS target port of Qemu