target-microblaze/cpu-qom.h

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20 #ifndef QEMU_MICROBLAZE_CPU_QOM_H
  21 #define QEMU_MICROBLAZE_CPU_QOM_H
  22
  23 #include "qom/cpu.h"
  24
  25 #define TYPE_MICROBLAZE_CPU "microblaze-cpu"
  26
  27 #define MICROBLAZE_CPU_CLASS(klass) \
  28     OBJECT_CLASS_CHECK(MicroBlazeCPUClass, (klass), TYPE_MICROBLAZE_CPU)
  29 #define MICROBLAZE_CPU(obj) \
  30     OBJECT_CHECK(MicroBlazeCPU, (obj), TYPE_MICROBLAZE_CPU)
  31 #define MICROBLAZE_CPU_GET_CLASS(obj) \
  32     OBJECT_GET_CLASS(MicroBlazeCPUClass, (obj), TYPE_MICROBLAZE_CPU)
  33
  34 /**
  35  * MicroBlazeCPUClass:
  36  * @parent_realize: The parent class' realize handler.
  37  * @parent_reset: The parent class' reset handler.
  38  *
  39  * A MicroBlaze CPU model.
  40  */
  41 typedef struct MicroBlazeCPUClass {
  42     /*< private >*/
  43     CPUClass parent_class;
  44     /*< public >*/
  45
  46     DeviceRealize parent_realize;
  47     void (*parent_reset)(CPUState *cpu);
  48 } MicroBlazeCPUClass;
  49
  50 /**
  51  * MicroBlazeCPU:
  52  * @env: #CPUMBState
  53  *
  54  * A MicroBlaze CPU.
  55  */
  56 typedef struct MicroBlazeCPU {
  57     /*< private >*/
  58     CPUState parent_obj;
  59     uint32_t base_vectors;
  60     /*< public >*/
  61
  62     CPUMBState env;
  63 } MicroBlazeCPU;
  64
  65 static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
  66 {
  67     return container_of(env, MicroBlazeCPU, env);
  68 }
  69
  70 #define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
  71
  72 #define ENV_OFFSET offsetof(MicroBlazeCPU, env)
  73
  74 void mb_cpu_do_interrupt(CPUState *cs);
  75 bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
  76 void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
  77                        int flags);
  78 hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  79 int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
  80 int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  81
  82 #endif