2 * Microblaze helper routines.
4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "host-utils.h"
27 #if !defined(CONFIG_USER_ONLY)
28 #define MMUSUFFIX _mmu
30 #include "softmmu_template.h"
32 #include "softmmu_template.h"
34 #include "softmmu_template.h"
36 #include "softmmu_template.h"
38 /* Try to fill the TLB and return an exception if error. If retaddr is
39 NULL, it means that the function was called in C code (i.e. not
40 from generated code or from helper.c) */
41 /* XXX: fix it to restore all registers */
42 void tlb_fill (target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
49 /* XXX: hack to restore env in all cases, even if not called from
54 ret
= cpu_mb_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
57 /* now we have a real cpu fault */
58 pc
= (unsigned long)retaddr
;
61 /* the PC is inside the translated code. It means that we have
62 a virtual CPU fault */
63 cpu_restore_state(tb
, env
, pc
, NULL
);
72 void helper_raise_exception(uint32_t index
)
74 env
->exception_index
= index
;
78 void helper_debug(void)
82 qemu_log("PC=%8.8x\n", env
->sregs
[SR_PC
]);
83 qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
84 env
->sregs
[SR_MSR
], env
->sregs
[SR_ESR
], env
->sregs
[SR_EAR
],
85 env
->debug
, env
->imm
, env
->iflags
);
86 qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
87 env
->btaken
, env
->btarget
,
88 (env
->sregs
[SR_MSR
] & MSR_UM
) ? "user" : "kernel",
89 (env
->sregs
[SR_MSR
] & MSR_UMS
) ? "user" : "kernel",
90 (env
->sregs
[SR_MSR
] & MSR_EIP
),
91 (env
->sregs
[SR_MSR
] & MSR_IE
));
92 for (i
= 0; i
< 32; i
++) {
93 qemu_log("r%2.2d=%8.8x ", i
, env
->regs
[i
]);
100 static inline uint32_t compute_carry(uint32_t a
, uint32_t b
, uint32_t cin
)
104 if ((b
== ~0) && cin
)
106 else if ((~0 - a
) < (b
+ cin
))
111 uint32_t helper_cmp(uint32_t a
, uint32_t b
)
116 if ((b
& 0x80000000) ^ (a
& 0x80000000))
117 t
= (t
& 0x7fffffff) | (b
& 0x80000000);
121 uint32_t helper_cmpu(uint32_t a
, uint32_t b
)
126 if ((b
& 0x80000000) ^ (a
& 0x80000000))
127 t
= (t
& 0x7fffffff) | (a
& 0x80000000);
131 uint32_t helper_addkc(uint32_t a
, uint32_t b
, uint32_t k
, uint32_t c
)
133 uint32_t d
, cf
= 0, ncf
;
136 cf
= env
->sregs
[SR_MSR
] >> 31;
137 assert(cf
== 0 || cf
== 1);
141 ncf
= compute_carry(a
, b
, cf
);
142 assert(ncf
== 0 || ncf
== 1);
144 env
->sregs
[SR_MSR
] |= MSR_C
| MSR_CC
;
146 env
->sregs
[SR_MSR
] &= ~(MSR_C
| MSR_CC
);
148 D(qemu_log("%x = %x + %x cf=%d ncf=%d k=%d c=%d\n",
149 d
, a
, b
, cf
, ncf
, k
, c
));
153 uint32_t helper_subkc(uint32_t a
, uint32_t b
, uint32_t k
, uint32_t c
)
155 uint32_t d
, cf
= 1, ncf
;
158 cf
= env
->sregs
[SR_MSR
] >> 31;
159 assert(cf
== 0 || cf
== 1);
163 ncf
= compute_carry(b
, ~a
, cf
);
164 assert(ncf
== 0 || ncf
== 1);
166 env
->sregs
[SR_MSR
] |= MSR_C
| MSR_CC
;
168 env
->sregs
[SR_MSR
] &= ~(MSR_C
| MSR_CC
);
170 D(qemu_log("%x = %x + %x cf=%d ncf=%d k=%d c=%d\n",
171 d
, a
, b
, cf
, ncf
, k
, c
));
175 static inline int div_prepare(uint32_t a
, uint32_t b
)
178 env
->sregs
[SR_MSR
] |= MSR_DZ
;
180 if ((env
->sregs
[SR_MSR
] & MSR_EE
)
181 && !(env
->pvr
.regs
[2] & PVR2_DIV_ZERO_EXC_MASK
)) {
182 env
->sregs
[SR_ESR
] = ESR_EC_DIVZERO
;
183 helper_raise_exception(EXCP_HW_EXCP
);
187 env
->sregs
[SR_MSR
] &= ~MSR_DZ
;
191 uint32_t helper_divs(uint32_t a
, uint32_t b
)
193 if (!div_prepare(a
, b
))
195 return (int32_t)a
/ (int32_t)b
;
198 uint32_t helper_divu(uint32_t a
, uint32_t b
)
200 if (!div_prepare(a
, b
))
205 /* raise FPU exception. */
206 static void raise_fpu_exception(void)
208 env
->sregs
[SR_ESR
] = ESR_EC_FPU
;
209 helper_raise_exception(EXCP_HW_EXCP
);
212 static void update_fpu_flags(int flags
)
216 if (flags
& float_flag_invalid
) {
217 env
->sregs
[SR_FSR
] |= FSR_IO
;
220 if (flags
& float_flag_divbyzero
) {
221 env
->sregs
[SR_FSR
] |= FSR_DZ
;
224 if (flags
& float_flag_overflow
) {
225 env
->sregs
[SR_FSR
] |= FSR_OF
;
228 if (flags
& float_flag_underflow
) {
229 env
->sregs
[SR_FSR
] |= FSR_UF
;
233 && (env
->pvr
.regs
[2] & PVR2_FPU_EXC_MASK
)
234 && (env
->sregs
[SR_MSR
] & MSR_EE
)) {
235 raise_fpu_exception();
239 uint32_t helper_fadd(uint32_t a
, uint32_t b
)
241 CPU_FloatU fd
, fa
, fb
;
244 set_float_exception_flags(0, &env
->fp_status
);
247 fd
.f
= float32_add(fa
.f
, fb
.f
, &env
->fp_status
);
249 flags
= get_float_exception_flags(&env
->fp_status
);
250 update_fpu_flags(flags
);
254 uint32_t helper_frsub(uint32_t a
, uint32_t b
)
256 CPU_FloatU fd
, fa
, fb
;
259 set_float_exception_flags(0, &env
->fp_status
);
262 fd
.f
= float32_sub(fb
.f
, fa
.f
, &env
->fp_status
);
263 flags
= get_float_exception_flags(&env
->fp_status
);
264 update_fpu_flags(flags
);
268 uint32_t helper_fmul(uint32_t a
, uint32_t b
)
270 CPU_FloatU fd
, fa
, fb
;
273 set_float_exception_flags(0, &env
->fp_status
);
276 fd
.f
= float32_mul(fa
.f
, fb
.f
, &env
->fp_status
);
277 flags
= get_float_exception_flags(&env
->fp_status
);
278 update_fpu_flags(flags
);
283 uint32_t helper_fdiv(uint32_t a
, uint32_t b
)
285 CPU_FloatU fd
, fa
, fb
;
288 set_float_exception_flags(0, &env
->fp_status
);
291 fd
.f
= float32_div(fb
.f
, fa
.f
, &env
->fp_status
);
292 flags
= get_float_exception_flags(&env
->fp_status
);
293 update_fpu_flags(flags
);
298 uint32_t helper_fcmp_un(uint32_t a
, uint32_t b
)
300 cpu_abort(env
, "Unsupported fcmp.un\n");
304 uint32_t helper_fcmp_lt(uint32_t a
, uint32_t b
)
310 set_float_exception_flags(0, &env
->fp_status
);
313 r
= float32_lt(fb
.f
, fa
.f
, &env
->fp_status
);
314 flags
= get_float_exception_flags(&env
->fp_status
);
315 update_fpu_flags(flags
& float_flag_invalid
);
320 uint32_t helper_fcmp_eq(uint32_t a
, uint32_t b
)
326 set_float_exception_flags(0, &env
->fp_status
);
329 r
= float32_eq(fa
.f
, fb
.f
, &env
->fp_status
);
330 flags
= get_float_exception_flags(&env
->fp_status
);
331 update_fpu_flags(flags
& float_flag_invalid
);
336 uint32_t helper_fcmp_le(uint32_t a
, uint32_t b
)
344 set_float_exception_flags(0, &env
->fp_status
);
345 r
= float32_le(fa
.f
, fb
.f
, &env
->fp_status
);
346 flags
= get_float_exception_flags(&env
->fp_status
);
347 update_fpu_flags(flags
& float_flag_invalid
);
353 uint32_t helper_fcmp_gt(uint32_t a
, uint32_t b
)
360 set_float_exception_flags(0, &env
->fp_status
);
361 r
= float32_lt(fa
.f
, fb
.f
, &env
->fp_status
);
362 flags
= get_float_exception_flags(&env
->fp_status
);
363 update_fpu_flags(flags
& float_flag_invalid
);
367 uint32_t helper_fcmp_ne(uint32_t a
, uint32_t b
)
374 set_float_exception_flags(0, &env
->fp_status
);
375 r
= !float32_eq(fa
.f
, fb
.f
, &env
->fp_status
);
376 flags
= get_float_exception_flags(&env
->fp_status
);
377 update_fpu_flags(flags
& float_flag_invalid
);
382 uint32_t helper_fcmp_ge(uint32_t a
, uint32_t b
)
389 set_float_exception_flags(0, &env
->fp_status
);
390 r
= !float32_lt(fa
.f
, fb
.f
, &env
->fp_status
);
391 flags
= get_float_exception_flags(&env
->fp_status
);
392 update_fpu_flags(flags
& float_flag_invalid
);
397 uint32_t helper_flt(uint32_t a
)
402 fd
.f
= int32_to_float32(fa
.l
, &env
->fp_status
);
406 uint32_t helper_fint(uint32_t a
)
412 set_float_exception_flags(0, &env
->fp_status
);
414 r
= float32_to_int32(fa
.f
, &env
->fp_status
);
415 flags
= get_float_exception_flags(&env
->fp_status
);
416 update_fpu_flags(flags
);
421 uint32_t helper_fsqrt(uint32_t a
)
426 set_float_exception_flags(0, &env
->fp_status
);
428 fd
.l
= float32_sqrt(fa
.f
, &env
->fp_status
);
429 flags
= get_float_exception_flags(&env
->fp_status
);
430 update_fpu_flags(flags
);
435 uint32_t helper_pcmpbf(uint32_t a
, uint32_t b
)
438 uint32_t mask
= 0xff000000;
440 for (i
= 0; i
< 4; i
++) {
441 if ((a
& mask
) == (b
& mask
))
448 void helper_memalign(uint32_t addr
, uint32_t dr
, uint32_t wr
, uint32_t mask
)
451 qemu_log_mask(CPU_LOG_INT
,
452 "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
454 env
->sregs
[SR_EAR
] = addr
;
455 env
->sregs
[SR_ESR
] = ESR_EC_UNALIGNED_DATA
| (wr
<< 10) \
458 env
->sregs
[SR_ESR
] |= 1 << 11;
460 if (!(env
->sregs
[SR_MSR
] & MSR_EE
)) {
463 helper_raise_exception(EXCP_HW_EXCP
);
467 #if !defined(CONFIG_USER_ONLY)
468 /* Writes/reads to the MMU's special regs end up here. */
469 uint32_t helper_mmu_read(uint32_t rn
)
471 return mmu_read(env
, rn
);
474 void helper_mmu_write(uint32_t rn
, uint32_t v
)
476 mmu_write(env
, rn
, v
);
479 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
480 int is_asi
, int size
)
484 if (!cpu_single_env
) {
489 /* XXX: hack to restore env in all cases, even if not called from
492 env
= cpu_single_env
;
493 qemu_log_mask(CPU_LOG_INT
, "Unassigned " TARGET_FMT_plx
" wr=%d exe=%d\n",
494 addr
, is_write
, is_exec
);
495 if (!(env
->sregs
[SR_MSR
] & MSR_EE
)) {
500 env
->sregs
[SR_EAR
] = addr
;
502 if ((env
->pvr
.regs
[2] & PVR2_IOPB_BUS_EXC_MASK
)) {
503 env
->sregs
[SR_ESR
] = ESR_EC_INSN_BUS
;
504 helper_raise_exception(EXCP_HW_EXCP
);
507 if ((env
->pvr
.regs
[2] & PVR2_DOPB_BUS_EXC_MASK
)) {
508 env
->sregs
[SR_ESR
] = ESR_EC_DATA_BUS
;
509 helper_raise_exception(EXCP_HW_EXCP
);