2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GPL.
10 #include "hw/sysbus.h"
11 #include "hw/arm/pxa.h"
12 #include "sysemu/sysemu.h"
13 #include "hw/char/serial.h"
14 #include "hw/i2c/i2c.h"
16 #include "sysemu/char.h"
17 #include "sysemu/blockdev.h"
23 { 0x40100000, PXA2XX_PIC_FFUART
},
24 { 0x40200000, PXA2XX_PIC_BTUART
},
25 { 0x40700000, PXA2XX_PIC_STUART
},
26 { 0x41600000, PXA25X_PIC_HWUART
},
28 }, pxa270_serial
[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART
},
30 { 0x40200000, PXA2XX_PIC_BTUART
},
31 { 0x40700000, PXA2XX_PIC_STUART
},
35 typedef struct PXASSPDef
{
41 static PXASSPDef pxa250_ssp
[] = {
42 { 0x41000000, PXA2XX_PIC_SSP
},
47 static PXASSPDef pxa255_ssp
[] = {
48 { 0x41000000, PXA2XX_PIC_SSP
},
49 { 0x41400000, PXA25X_PIC_NSSP
},
54 static PXASSPDef pxa26x_ssp
[] = {
55 { 0x41000000, PXA2XX_PIC_SSP
},
56 { 0x41400000, PXA25X_PIC_NSSP
},
57 { 0x41500000, PXA26X_PIC_ASSP
},
62 static PXASSPDef pxa27x_ssp
[] = {
63 { 0x41000000, PXA2XX_PIC_SSP
},
64 { 0x41700000, PXA27X_PIC_SSP2
},
65 { 0x41900000, PXA2XX_PIC_SSP3
},
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
91 static uint64_t pxa2xx_pm_read(void *opaque
, hwaddr addr
,
94 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
101 return s
->pm_regs
[addr
>> 2];
104 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
110 static void pxa2xx_pm_write(void *opaque
, hwaddr addr
,
111 uint64_t value
, unsigned size
)
113 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
117 /* Clear the write-one-to-clear bits... */
118 s
->pm_regs
[addr
>> 2] &= ~(value
& 0x2a);
119 /* ...and set the plain r/w bits */
120 s
->pm_regs
[addr
>> 2] &= ~0x15;
121 s
->pm_regs
[addr
>> 2] |= value
& 0x15;
124 case PSSR
: /* Read-clean registers */
127 s
->pm_regs
[addr
>> 2] &= ~value
;
130 default: /* Read-write registers */
132 s
->pm_regs
[addr
>> 2] = value
;
136 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
141 static const MemoryRegionOps pxa2xx_pm_ops
= {
142 .read
= pxa2xx_pm_read
,
143 .write
= pxa2xx_pm_write
,
144 .endianness
= DEVICE_NATIVE_ENDIAN
,
147 static const VMStateDescription vmstate_pxa2xx_pm
= {
150 .minimum_version_id
= 0,
151 .minimum_version_id_old
= 0,
152 .fields
= (VMStateField
[]) {
153 VMSTATE_UINT32_ARRAY(pm_regs
, PXA2xxState
, 0x40),
154 VMSTATE_END_OF_LIST()
158 #define CCCR 0x00 /* Core Clock Configuration register */
159 #define CKEN 0x04 /* Clock Enable register */
160 #define OSCC 0x08 /* Oscillator Configuration register */
161 #define CCSR 0x0c /* Core Clock Status register */
163 static uint64_t pxa2xx_cm_read(void *opaque
, hwaddr addr
,
166 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
172 return s
->cm_regs
[addr
>> 2];
175 return s
->cm_regs
[CCCR
>> 2] | (3 << 28);
178 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
184 static void pxa2xx_cm_write(void *opaque
, hwaddr addr
,
185 uint64_t value
, unsigned size
)
187 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
192 s
->cm_regs
[addr
>> 2] = value
;
196 s
->cm_regs
[addr
>> 2] &= ~0x6c;
197 s
->cm_regs
[addr
>> 2] |= value
& 0x6e;
198 if ((value
>> 1) & 1) /* OON */
199 s
->cm_regs
[addr
>> 2] |= 1 << 0; /* Oscillator is now stable */
203 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
208 static const MemoryRegionOps pxa2xx_cm_ops
= {
209 .read
= pxa2xx_cm_read
,
210 .write
= pxa2xx_cm_write
,
211 .endianness
= DEVICE_NATIVE_ENDIAN
,
214 static const VMStateDescription vmstate_pxa2xx_cm
= {
217 .minimum_version_id
= 0,
218 .minimum_version_id_old
= 0,
219 .fields
= (VMStateField
[]) {
220 VMSTATE_UINT32_ARRAY(cm_regs
, PXA2xxState
, 4),
221 VMSTATE_UINT32(clkcfg
, PXA2xxState
),
222 VMSTATE_UINT32(pmnc
, PXA2xxState
),
223 VMSTATE_END_OF_LIST()
227 static int pxa2xx_clkcfg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
230 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
235 static int pxa2xx_clkcfg_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
238 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
239 s
->clkcfg
= value
& 0xf;
241 printf("%s: CPU frequency change attempt\n", __func__
);
246 static int pxa2xx_pwrmode_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
249 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
250 static const char *pwrmode
[8] = {
251 "Normal", "Idle", "Deep-idle", "Standby",
252 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
256 printf("%s: CPU voltage change attempt\n", __func__
);
265 if (!(s
->cm_regs
[CCCR
>> 2] & (1 << 31))) { /* CPDIS */
266 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HALT
);
273 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HALT
);
274 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
278 s
->cpu
->env
.uncached_cpsr
=
279 ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
280 s
->cpu
->env
.cp15
.c1_sys
= 0;
281 s
->cpu
->env
.cp15
.c1_coproc
= 0;
282 s
->cpu
->env
.cp15
.c2_base0
= 0;
283 s
->cpu
->env
.cp15
.c3
= 0;
284 s
->pm_regs
[PSSR
>> 2] |= 0x8; /* Set STS */
285 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
288 * The scratch-pad register is almost universally used
289 * for storing the return address on suspend. For the
290 * lack of a resuming bootloader, perform a jump
291 * directly to that address.
293 memset(s
->cpu
->env
.regs
, 0, 4 * 15);
294 s
->cpu
->env
.regs
[15] = s
->pm_regs
[PSPR
>> 2];
297 buffer
= 0xe59ff000; /* ldr pc, [pc, #0] */
298 cpu_physical_memory_write(0, &buffer
, 4);
299 buffer
= s
->pm_regs
[PSPR
>> 2];
300 cpu_physical_memory_write(8, &buffer
, 4);
304 cpu_interrupt(current_cpu
, CPU_INTERRUPT_HALT
);
310 printf("%s: machine entered %s mode\n", __func__
,
317 static int pxa2xx_cppmnc_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
320 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
325 static int pxa2xx_cppmnc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
328 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
333 static int pxa2xx_cpccnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
336 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
338 *value
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
345 static const ARMCPRegInfo pxa_cp_reginfo
[] = {
346 /* cp14 crm==1: perf registers */
347 { .name
= "CPPMNC", .cp
= 14, .crn
= 0, .crm
= 1, .opc1
= 0, .opc2
= 0,
349 .readfn
= pxa2xx_cppmnc_read
, .writefn
= pxa2xx_cppmnc_write
},
350 { .name
= "CPCCNT", .cp
= 14, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
352 .readfn
= pxa2xx_cpccnt_read
, .writefn
= arm_cp_write_ignore
},
353 { .name
= "CPINTEN", .cp
= 14, .crn
= 4, .crm
= 1, .opc1
= 0, .opc2
= 0,
354 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
355 { .name
= "CPFLAG", .cp
= 14, .crn
= 5, .crm
= 1, .opc1
= 0, .opc2
= 0,
356 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
357 { .name
= "CPEVTSEL", .cp
= 14, .crn
= 8, .crm
= 1, .opc1
= 0, .opc2
= 0,
358 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
359 /* cp14 crm==2: performance count registers */
360 { .name
= "CPPMN0", .cp
= 14, .crn
= 0, .crm
= 2, .opc1
= 0, .opc2
= 0,
361 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
362 { .name
= "CPPMN1", .cp
= 14, .crn
= 1, .crm
= 2, .opc1
= 0, .opc2
= 0,
363 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
364 { .name
= "CPPMN2", .cp
= 14, .crn
= 2, .crm
= 2, .opc1
= 0, .opc2
= 0,
365 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
366 { .name
= "CPPMN3", .cp
= 14, .crn
= 2, .crm
= 3, .opc1
= 0, .opc2
= 0,
367 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
368 /* cp14 crn==6: CLKCFG */
369 { .name
= "CLKCFG", .cp
= 14, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
371 .readfn
= pxa2xx_clkcfg_read
, .writefn
= pxa2xx_clkcfg_write
},
372 /* cp14 crn==7: PWRMODE */
373 { .name
= "PWRMODE", .cp
= 14, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 0,
375 .readfn
= arm_cp_read_zero
, .writefn
= pxa2xx_pwrmode_write
},
379 static void pxa2xx_setup_cp14(PXA2xxState
*s
)
381 define_arm_cp_regs_with_opaque(s
->cpu
, pxa_cp_reginfo
, s
);
384 #define MDCNFG 0x00 /* SDRAM Configuration register */
385 #define MDREFR 0x04 /* SDRAM Refresh Control register */
386 #define MSC0 0x08 /* Static Memory Control register 0 */
387 #define MSC1 0x0c /* Static Memory Control register 1 */
388 #define MSC2 0x10 /* Static Memory Control register 2 */
389 #define MECR 0x14 /* Expansion Memory Bus Config register */
390 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
391 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
392 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
393 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
394 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
395 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
396 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
397 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
398 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
399 #define ARB_CNTL 0x48 /* Arbiter Control register */
400 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
401 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
402 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
403 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
404 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
405 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
406 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
408 static uint64_t pxa2xx_mm_read(void *opaque
, hwaddr addr
,
411 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
414 case MDCNFG
... SA1110
:
416 return s
->mm_regs
[addr
>> 2];
419 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
425 static void pxa2xx_mm_write(void *opaque
, hwaddr addr
,
426 uint64_t value
, unsigned size
)
428 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
431 case MDCNFG
... SA1110
:
432 if ((addr
& 3) == 0) {
433 s
->mm_regs
[addr
>> 2] = value
;
438 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
443 static const MemoryRegionOps pxa2xx_mm_ops
= {
444 .read
= pxa2xx_mm_read
,
445 .write
= pxa2xx_mm_write
,
446 .endianness
= DEVICE_NATIVE_ENDIAN
,
449 static const VMStateDescription vmstate_pxa2xx_mm
= {
452 .minimum_version_id
= 0,
453 .minimum_version_id_old
= 0,
454 .fields
= (VMStateField
[]) {
455 VMSTATE_UINT32_ARRAY(mm_regs
, PXA2xxState
, 0x1a),
456 VMSTATE_END_OF_LIST()
460 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
461 #define PXA2XX_SSP(obj) \
462 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
464 /* Synchronous Serial Ports */
467 SysBusDevice parent_obj
;
484 uint32_t rx_fifo
[16];
489 #define SSCR0 0x00 /* SSP Control register 0 */
490 #define SSCR1 0x04 /* SSP Control register 1 */
491 #define SSSR 0x08 /* SSP Status register */
492 #define SSITR 0x0c /* SSP Interrupt Test register */
493 #define SSDR 0x10 /* SSP Data register */
494 #define SSTO 0x28 /* SSP Time-Out register */
495 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
496 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
497 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
498 #define SSTSS 0x38 /* SSP Time Slot Status register */
499 #define SSACD 0x3c /* SSP Audio Clock Divider register */
501 /* Bitfields for above registers */
502 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
503 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
504 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
505 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
506 #define SSCR0_SSE (1 << 7)
507 #define SSCR0_RIM (1 << 22)
508 #define SSCR0_TIM (1 << 23)
509 #define SSCR0_MOD (1 << 31)
510 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
511 #define SSCR1_RIE (1 << 0)
512 #define SSCR1_TIE (1 << 1)
513 #define SSCR1_LBM (1 << 2)
514 #define SSCR1_MWDS (1 << 5)
515 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
516 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
517 #define SSCR1_EFWR (1 << 14)
518 #define SSCR1_PINTE (1 << 18)
519 #define SSCR1_TINTE (1 << 19)
520 #define SSCR1_RSRE (1 << 20)
521 #define SSCR1_TSRE (1 << 21)
522 #define SSCR1_EBCEI (1 << 29)
523 #define SSITR_INT (7 << 5)
524 #define SSSR_TNF (1 << 2)
525 #define SSSR_RNE (1 << 3)
526 #define SSSR_TFS (1 << 5)
527 #define SSSR_RFS (1 << 6)
528 #define SSSR_ROR (1 << 7)
529 #define SSSR_PINT (1 << 18)
530 #define SSSR_TINT (1 << 19)
531 #define SSSR_EOC (1 << 20)
532 #define SSSR_TUR (1 << 21)
533 #define SSSR_BCE (1 << 23)
534 #define SSSR_RW 0x00bc0080
536 static void pxa2xx_ssp_int_update(PXA2xxSSPState
*s
)
540 level
|= s
->ssitr
& SSITR_INT
;
541 level
|= (s
->sssr
& SSSR_BCE
) && (s
->sscr
[1] & SSCR1_EBCEI
);
542 level
|= (s
->sssr
& SSSR_TUR
) && !(s
->sscr
[0] & SSCR0_TIM
);
543 level
|= (s
->sssr
& SSSR_EOC
) && (s
->sssr
& (SSSR_TINT
| SSSR_PINT
));
544 level
|= (s
->sssr
& SSSR_TINT
) && (s
->sscr
[1] & SSCR1_TINTE
);
545 level
|= (s
->sssr
& SSSR_PINT
) && (s
->sscr
[1] & SSCR1_PINTE
);
546 level
|= (s
->sssr
& SSSR_ROR
) && !(s
->sscr
[0] & SSCR0_RIM
);
547 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
548 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
549 qemu_set_irq(s
->irq
, !!level
);
552 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState
*s
)
554 s
->sssr
&= ~(0xf << 12); /* Clear RFL */
555 s
->sssr
&= ~(0xf << 8); /* Clear TFL */
556 s
->sssr
&= ~SSSR_TFS
;
557 s
->sssr
&= ~SSSR_TNF
;
559 s
->sssr
|= ((s
->rx_level
- 1) & 0xf) << 12;
560 if (s
->rx_level
>= SSCR1_RFT(s
->sscr
[1]))
563 s
->sssr
&= ~SSSR_RFS
;
567 s
->sssr
&= ~SSSR_RNE
;
568 /* TX FIFO is never filled, so it is always in underrun
569 condition if SSP is enabled */
574 pxa2xx_ssp_int_update(s
);
577 static uint64_t pxa2xx_ssp_read(void *opaque
, hwaddr addr
,
580 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
595 return s
->sssr
| s
->ssitr
;
599 if (s
->rx_level
< 1) {
600 printf("%s: SSP Rx Underrun\n", __FUNCTION__
);
604 retval
= s
->rx_fifo
[s
->rx_start
++];
606 pxa2xx_ssp_fifo_update(s
);
617 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
623 static void pxa2xx_ssp_write(void *opaque
, hwaddr addr
,
624 uint64_t value64
, unsigned size
)
626 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
627 uint32_t value
= value64
;
631 s
->sscr
[0] = value
& 0xc7ffffff;
632 s
->enable
= value
& SSCR0_SSE
;
633 if (value
& SSCR0_MOD
)
634 printf("%s: Attempt to use network mode\n", __FUNCTION__
);
635 if (s
->enable
&& SSCR0_DSS(value
) < 4)
636 printf("%s: Wrong data size: %i bits\n", __FUNCTION__
,
638 if (!(value
& SSCR0_SSE
)) {
643 pxa2xx_ssp_fifo_update(s
);
648 if (value
& (SSCR1_LBM
| SSCR1_EFWR
))
649 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__
);
650 pxa2xx_ssp_fifo_update(s
);
662 s
->ssitr
= value
& SSITR_INT
;
663 pxa2xx_ssp_int_update(s
);
667 s
->sssr
&= ~(value
& SSSR_RW
);
668 pxa2xx_ssp_int_update(s
);
672 if (SSCR0_UWIRE(s
->sscr
[0])) {
673 if (s
->sscr
[1] & SSCR1_MWDS
)
678 /* Note how 32bits overflow does no harm here */
679 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
681 /* Data goes from here to the Tx FIFO and is shifted out from
682 * there directly to the slave, no need to buffer it.
686 readval
= ssi_transfer(s
->bus
, value
);
687 if (s
->rx_level
< 0x10) {
688 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] = readval
;
693 pxa2xx_ssp_fifo_update(s
);
709 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
714 static const MemoryRegionOps pxa2xx_ssp_ops
= {
715 .read
= pxa2xx_ssp_read
,
716 .write
= pxa2xx_ssp_write
,
717 .endianness
= DEVICE_NATIVE_ENDIAN
,
720 static void pxa2xx_ssp_save(QEMUFile
*f
, void *opaque
)
722 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
725 qemu_put_be32(f
, s
->enable
);
727 qemu_put_be32s(f
, &s
->sscr
[0]);
728 qemu_put_be32s(f
, &s
->sscr
[1]);
729 qemu_put_be32s(f
, &s
->sspsp
);
730 qemu_put_be32s(f
, &s
->ssto
);
731 qemu_put_be32s(f
, &s
->ssitr
);
732 qemu_put_be32s(f
, &s
->sssr
);
733 qemu_put_8s(f
, &s
->sstsa
);
734 qemu_put_8s(f
, &s
->ssrsa
);
735 qemu_put_8s(f
, &s
->ssacd
);
737 qemu_put_byte(f
, s
->rx_level
);
738 for (i
= 0; i
< s
->rx_level
; i
++)
739 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 0xf]);
742 static int pxa2xx_ssp_load(QEMUFile
*f
, void *opaque
, int version_id
)
744 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
747 s
->enable
= qemu_get_be32(f
);
749 qemu_get_be32s(f
, &s
->sscr
[0]);
750 qemu_get_be32s(f
, &s
->sscr
[1]);
751 qemu_get_be32s(f
, &s
->sspsp
);
752 qemu_get_be32s(f
, &s
->ssto
);
753 qemu_get_be32s(f
, &s
->ssitr
);
754 qemu_get_be32s(f
, &s
->sssr
);
755 qemu_get_8s(f
, &s
->sstsa
);
756 qemu_get_8s(f
, &s
->ssrsa
);
757 qemu_get_8s(f
, &s
->ssacd
);
759 s
->rx_level
= qemu_get_byte(f
);
761 for (i
= 0; i
< s
->rx_level
; i
++)
762 s
->rx_fifo
[i
] = qemu_get_byte(f
);
767 static int pxa2xx_ssp_init(SysBusDevice
*sbd
)
769 DeviceState
*dev
= DEVICE(sbd
);
770 PXA2xxSSPState
*s
= PXA2XX_SSP(dev
);
772 sysbus_init_irq(sbd
, &s
->irq
);
774 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pxa2xx_ssp_ops
, s
,
775 "pxa2xx-ssp", 0x1000);
776 sysbus_init_mmio(sbd
, &s
->iomem
);
777 register_savevm(dev
, "pxa2xx_ssp", -1, 0,
778 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
780 s
->bus
= ssi_create_bus(dev
, "ssi");
784 /* Real-Time Clock */
785 #define RCNR 0x00 /* RTC Counter register */
786 #define RTAR 0x04 /* RTC Alarm register */
787 #define RTSR 0x08 /* RTC Status register */
788 #define RTTR 0x0c /* RTC Timer Trim register */
789 #define RDCR 0x10 /* RTC Day Counter register */
790 #define RYCR 0x14 /* RTC Year Counter register */
791 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
792 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
793 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
794 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
795 #define SWCR 0x28 /* RTC Stopwatch Counter register */
796 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
797 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
798 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
799 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
801 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
802 #define PXA2XX_RTC(obj) \
803 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
807 SysBusDevice parent_obj
;
825 uint32_t last_rtcpicr
;
830 QEMUTimer
*rtc_rdal1
;
831 QEMUTimer
*rtc_rdal2
;
832 QEMUTimer
*rtc_swal1
;
833 QEMUTimer
*rtc_swal2
;
838 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState
*s
)
840 qemu_set_irq(s
->rtc_irq
, !!(s
->rtsr
& 0x2553));
843 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState
*s
)
845 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
846 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
847 (1000 * ((s
->rttr
& 0xffff) + 1));
848 s
->last_rdcr
+= ((rt
- s
->last_hz
) << 15) /
849 (1000 * ((s
->rttr
& 0xffff) + 1));
853 static void pxa2xx_rtc_swupdate(PXA2xxRTCState
*s
)
855 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
856 if (s
->rtsr
& (1 << 12))
857 s
->last_swcr
+= (rt
- s
->last_sw
) / 10;
861 static void pxa2xx_rtc_piupdate(PXA2xxRTCState
*s
)
863 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
864 if (s
->rtsr
& (1 << 15))
865 s
->last_swcr
+= rt
- s
->last_pi
;
869 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState
*s
,
872 if ((rtsr
& (1 << 2)) && !(rtsr
& (1 << 0)))
873 timer_mod(s
->rtc_hz
, s
->last_hz
+
874 (((s
->rtar
- s
->last_rcnr
) * 1000 *
875 ((s
->rttr
& 0xffff) + 1)) >> 15));
877 timer_del(s
->rtc_hz
);
879 if ((rtsr
& (1 << 5)) && !(rtsr
& (1 << 4)))
880 timer_mod(s
->rtc_rdal1
, s
->last_hz
+
881 (((s
->rdar1
- s
->last_rdcr
) * 1000 *
882 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
884 timer_del(s
->rtc_rdal1
);
886 if ((rtsr
& (1 << 7)) && !(rtsr
& (1 << 6)))
887 timer_mod(s
->rtc_rdal2
, s
->last_hz
+
888 (((s
->rdar2
- s
->last_rdcr
) * 1000 *
889 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
891 timer_del(s
->rtc_rdal2
);
893 if ((rtsr
& 0x1200) == 0x1200 && !(rtsr
& (1 << 8)))
894 timer_mod(s
->rtc_swal1
, s
->last_sw
+
895 (s
->swar1
- s
->last_swcr
) * 10); /* TODO: fixup */
897 timer_del(s
->rtc_swal1
);
899 if ((rtsr
& 0x1800) == 0x1800 && !(rtsr
& (1 << 10)))
900 timer_mod(s
->rtc_swal2
, s
->last_sw
+
901 (s
->swar2
- s
->last_swcr
) * 10); /* TODO: fixup */
903 timer_del(s
->rtc_swal2
);
905 if ((rtsr
& 0xc000) == 0xc000 && !(rtsr
& (1 << 13)))
906 timer_mod(s
->rtc_pi
, s
->last_pi
+
907 (s
->piar
& 0xffff) - s
->last_rtcpicr
);
909 timer_del(s
->rtc_pi
);
912 static inline void pxa2xx_rtc_hz_tick(void *opaque
)
914 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
916 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
917 pxa2xx_rtc_int_update(s
);
920 static inline void pxa2xx_rtc_rdal1_tick(void *opaque
)
922 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
924 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
925 pxa2xx_rtc_int_update(s
);
928 static inline void pxa2xx_rtc_rdal2_tick(void *opaque
)
930 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
932 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
933 pxa2xx_rtc_int_update(s
);
936 static inline void pxa2xx_rtc_swal1_tick(void *opaque
)
938 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
940 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
941 pxa2xx_rtc_int_update(s
);
944 static inline void pxa2xx_rtc_swal2_tick(void *opaque
)
946 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
947 s
->rtsr
|= (1 << 10);
948 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
949 pxa2xx_rtc_int_update(s
);
952 static inline void pxa2xx_rtc_pi_tick(void *opaque
)
954 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
955 s
->rtsr
|= (1 << 13);
956 pxa2xx_rtc_piupdate(s
);
958 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
959 pxa2xx_rtc_int_update(s
);
962 static uint64_t pxa2xx_rtc_read(void *opaque
, hwaddr addr
,
965 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
989 return s
->last_rcnr
+
990 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
991 (1000 * ((s
->rttr
& 0xffff) + 1));
993 return s
->last_rdcr
+
994 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
995 (1000 * ((s
->rttr
& 0xffff) + 1));
999 if (s
->rtsr
& (1 << 12))
1000 return s
->last_swcr
+
1001 (qemu_clock_get_ms(rtc_clock
) - s
->last_sw
) / 10;
1003 return s
->last_swcr
;
1005 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1011 static void pxa2xx_rtc_write(void *opaque
, hwaddr addr
,
1012 uint64_t value64
, unsigned size
)
1014 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1015 uint32_t value
= value64
;
1019 if (!(s
->rttr
& (1 << 31))) {
1020 pxa2xx_rtc_hzupdate(s
);
1022 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1027 if ((s
->rtsr
^ value
) & (1 << 15))
1028 pxa2xx_rtc_piupdate(s
);
1030 if ((s
->rtsr
^ value
) & (1 << 12))
1031 pxa2xx_rtc_swupdate(s
);
1033 if (((s
->rtsr
^ value
) & 0x4aac) | (value
& ~0xdaac))
1034 pxa2xx_rtc_alarm_update(s
, value
);
1036 s
->rtsr
= (value
& 0xdaac) | (s
->rtsr
& ~(value
& ~0xdaac));
1037 pxa2xx_rtc_int_update(s
);
1042 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1047 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1052 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1057 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1062 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1066 pxa2xx_rtc_swupdate(s
);
1069 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1074 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1079 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1083 pxa2xx_rtc_hzupdate(s
);
1084 s
->last_rcnr
= value
;
1085 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1089 pxa2xx_rtc_hzupdate(s
);
1090 s
->last_rdcr
= value
;
1091 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1095 s
->last_rycr
= value
;
1099 pxa2xx_rtc_swupdate(s
);
1100 s
->last_swcr
= value
;
1101 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1105 pxa2xx_rtc_piupdate(s
);
1106 s
->last_rtcpicr
= value
& 0xffff;
1107 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1111 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1115 static const MemoryRegionOps pxa2xx_rtc_ops
= {
1116 .read
= pxa2xx_rtc_read
,
1117 .write
= pxa2xx_rtc_write
,
1118 .endianness
= DEVICE_NATIVE_ENDIAN
,
1121 static int pxa2xx_rtc_init(SysBusDevice
*dev
)
1123 PXA2xxRTCState
*s
= PXA2XX_RTC(dev
);
1130 qemu_get_timedate(&tm
, 0);
1131 wom
= ((tm
.tm_mday
- 1) / 7) + 1;
1133 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
1134 s
->last_rdcr
= (wom
<< 20) | ((tm
.tm_wday
+ 1) << 17) |
1135 (tm
.tm_hour
<< 12) | (tm
.tm_min
<< 6) | tm
.tm_sec
;
1136 s
->last_rycr
= ((tm
.tm_year
+ 1900) << 9) |
1137 ((tm
.tm_mon
+ 1) << 5) | tm
.tm_mday
;
1138 s
->last_swcr
= (tm
.tm_hour
<< 19) |
1139 (tm
.tm_min
<< 13) | (tm
.tm_sec
<< 7);
1140 s
->last_rtcpicr
= 0;
1141 s
->last_hz
= s
->last_sw
= s
->last_pi
= qemu_clock_get_ms(rtc_clock
);
1143 s
->rtc_hz
= timer_new_ms(rtc_clock
, pxa2xx_rtc_hz_tick
, s
);
1144 s
->rtc_rdal1
= timer_new_ms(rtc_clock
, pxa2xx_rtc_rdal1_tick
, s
);
1145 s
->rtc_rdal2
= timer_new_ms(rtc_clock
, pxa2xx_rtc_rdal2_tick
, s
);
1146 s
->rtc_swal1
= timer_new_ms(rtc_clock
, pxa2xx_rtc_swal1_tick
, s
);
1147 s
->rtc_swal2
= timer_new_ms(rtc_clock
, pxa2xx_rtc_swal2_tick
, s
);
1148 s
->rtc_pi
= timer_new_ms(rtc_clock
, pxa2xx_rtc_pi_tick
, s
);
1150 sysbus_init_irq(dev
, &s
->rtc_irq
);
1152 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pxa2xx_rtc_ops
, s
,
1153 "pxa2xx-rtc", 0x10000);
1154 sysbus_init_mmio(dev
, &s
->iomem
);
1159 static void pxa2xx_rtc_pre_save(void *opaque
)
1161 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1163 pxa2xx_rtc_hzupdate(s
);
1164 pxa2xx_rtc_piupdate(s
);
1165 pxa2xx_rtc_swupdate(s
);
1168 static int pxa2xx_rtc_post_load(void *opaque
, int version_id
)
1170 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1172 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1177 static const VMStateDescription vmstate_pxa2xx_rtc_regs
= {
1178 .name
= "pxa2xx_rtc",
1180 .minimum_version_id
= 0,
1181 .minimum_version_id_old
= 0,
1182 .pre_save
= pxa2xx_rtc_pre_save
,
1183 .post_load
= pxa2xx_rtc_post_load
,
1184 .fields
= (VMStateField
[]) {
1185 VMSTATE_UINT32(rttr
, PXA2xxRTCState
),
1186 VMSTATE_UINT32(rtsr
, PXA2xxRTCState
),
1187 VMSTATE_UINT32(rtar
, PXA2xxRTCState
),
1188 VMSTATE_UINT32(rdar1
, PXA2xxRTCState
),
1189 VMSTATE_UINT32(rdar2
, PXA2xxRTCState
),
1190 VMSTATE_UINT32(ryar1
, PXA2xxRTCState
),
1191 VMSTATE_UINT32(ryar2
, PXA2xxRTCState
),
1192 VMSTATE_UINT32(swar1
, PXA2xxRTCState
),
1193 VMSTATE_UINT32(swar2
, PXA2xxRTCState
),
1194 VMSTATE_UINT32(piar
, PXA2xxRTCState
),
1195 VMSTATE_UINT32(last_rcnr
, PXA2xxRTCState
),
1196 VMSTATE_UINT32(last_rdcr
, PXA2xxRTCState
),
1197 VMSTATE_UINT32(last_rycr
, PXA2xxRTCState
),
1198 VMSTATE_UINT32(last_swcr
, PXA2xxRTCState
),
1199 VMSTATE_UINT32(last_rtcpicr
, PXA2xxRTCState
),
1200 VMSTATE_INT64(last_hz
, PXA2xxRTCState
),
1201 VMSTATE_INT64(last_sw
, PXA2xxRTCState
),
1202 VMSTATE_INT64(last_pi
, PXA2xxRTCState
),
1203 VMSTATE_END_OF_LIST(),
1207 static void pxa2xx_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
1209 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1210 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1212 k
->init
= pxa2xx_rtc_init
;
1213 dc
->desc
= "PXA2xx RTC Controller";
1214 dc
->vmsd
= &vmstate_pxa2xx_rtc_regs
;
1217 static const TypeInfo pxa2xx_rtc_sysbus_info
= {
1218 .name
= TYPE_PXA2XX_RTC
,
1219 .parent
= TYPE_SYS_BUS_DEVICE
,
1220 .instance_size
= sizeof(PXA2xxRTCState
),
1221 .class_init
= pxa2xx_rtc_sysbus_class_init
,
1226 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1227 #define PXA2XX_I2C_SLAVE(obj) \
1228 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1230 typedef struct PXA2xxI2CSlaveState
{
1231 I2CSlave parent_obj
;
1233 PXA2xxI2CState
*host
;
1234 } PXA2xxI2CSlaveState
;
1236 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1237 #define PXA2XX_I2C(obj) \
1238 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1240 struct PXA2xxI2CState
{
1242 SysBusDevice parent_obj
;
1246 PXA2xxI2CSlaveState
*slave
;
1250 uint32_t region_size
;
1258 #define IBMR 0x80 /* I2C Bus Monitor register */
1259 #define IDBR 0x88 /* I2C Data Buffer register */
1260 #define ICR 0x90 /* I2C Control register */
1261 #define ISR 0x98 /* I2C Status register */
1262 #define ISAR 0xa0 /* I2C Slave Address register */
1264 static void pxa2xx_i2c_update(PXA2xxI2CState
*s
)
1267 level
|= s
->status
& s
->control
& (1 << 10); /* BED */
1268 level
|= (s
->status
& (1 << 7)) && (s
->control
& (1 << 9)); /* IRF */
1269 level
|= (s
->status
& (1 << 6)) && (s
->control
& (1 << 8)); /* ITE */
1270 level
|= s
->status
& (1 << 9); /* SAD */
1271 qemu_set_irq(s
->irq
, !!level
);
1274 /* These are only stubs now. */
1275 static void pxa2xx_i2c_event(I2CSlave
*i2c
, enum i2c_event event
)
1277 PXA2xxI2CSlaveState
*slave
= PXA2XX_I2C_SLAVE(i2c
);
1278 PXA2xxI2CState
*s
= slave
->host
;
1281 case I2C_START_SEND
:
1282 s
->status
|= (1 << 9); /* set SAD */
1283 s
->status
&= ~(1 << 0); /* clear RWM */
1285 case I2C_START_RECV
:
1286 s
->status
|= (1 << 9); /* set SAD */
1287 s
->status
|= 1 << 0; /* set RWM */
1290 s
->status
|= (1 << 4); /* set SSD */
1293 s
->status
|= 1 << 1; /* set ACKNAK */
1296 pxa2xx_i2c_update(s
);
1299 static int pxa2xx_i2c_rx(I2CSlave
*i2c
)
1301 PXA2xxI2CSlaveState
*slave
= PXA2XX_I2C_SLAVE(i2c
);
1302 PXA2xxI2CState
*s
= slave
->host
;
1304 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6))) {
1308 if (s
->status
& (1 << 0)) { /* RWM */
1309 s
->status
|= 1 << 6; /* set ITE */
1311 pxa2xx_i2c_update(s
);
1316 static int pxa2xx_i2c_tx(I2CSlave
*i2c
, uint8_t data
)
1318 PXA2xxI2CSlaveState
*slave
= PXA2XX_I2C_SLAVE(i2c
);
1319 PXA2xxI2CState
*s
= slave
->host
;
1321 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6))) {
1325 if (!(s
->status
& (1 << 0))) { /* RWM */
1326 s
->status
|= 1 << 7; /* set IRF */
1329 pxa2xx_i2c_update(s
);
1334 static uint64_t pxa2xx_i2c_read(void *opaque
, hwaddr addr
,
1337 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1345 return s
->status
| (i2c_bus_busy(s
->bus
) << 2);
1347 slave
= I2C_SLAVE(s
->slave
);
1348 return slave
->address
;
1352 if (s
->status
& (1 << 2))
1353 s
->ibmr
^= 3; /* Fake SCL and SDA pin changes */
1358 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1364 static void pxa2xx_i2c_write(void *opaque
, hwaddr addr
,
1365 uint64_t value64
, unsigned size
)
1367 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1368 uint32_t value
= value64
;
1374 s
->control
= value
& 0xfff7;
1375 if ((value
& (1 << 3)) && (value
& (1 << 6))) { /* TB and IUE */
1376 /* TODO: slave mode */
1377 if (value
& (1 << 0)) { /* START condition */
1379 s
->status
|= 1 << 0; /* set RWM */
1381 s
->status
&= ~(1 << 0); /* clear RWM */
1382 ack
= !i2c_start_transfer(s
->bus
, s
->data
>> 1, s
->data
& 1);
1384 if (s
->status
& (1 << 0)) { /* RWM */
1385 s
->data
= i2c_recv(s
->bus
);
1386 if (value
& (1 << 2)) /* ACKNAK */
1390 ack
= !i2c_send(s
->bus
, s
->data
);
1393 if (value
& (1 << 1)) /* STOP condition */
1394 i2c_end_transfer(s
->bus
);
1397 if (value
& (1 << 0)) /* START condition */
1398 s
->status
|= 1 << 6; /* set ITE */
1400 if (s
->status
& (1 << 0)) /* RWM */
1401 s
->status
|= 1 << 7; /* set IRF */
1403 s
->status
|= 1 << 6; /* set ITE */
1404 s
->status
&= ~(1 << 1); /* clear ACKNAK */
1406 s
->status
|= 1 << 6; /* set ITE */
1407 s
->status
|= 1 << 10; /* set BED */
1408 s
->status
|= 1 << 1; /* set ACKNAK */
1411 if (!(value
& (1 << 3)) && (value
& (1 << 6))) /* !TB and IUE */
1412 if (value
& (1 << 4)) /* MA */
1413 i2c_end_transfer(s
->bus
);
1414 pxa2xx_i2c_update(s
);
1418 s
->status
&= ~(value
& 0x07f0);
1419 pxa2xx_i2c_update(s
);
1423 i2c_set_slave_address(I2C_SLAVE(s
->slave
), value
& 0x7f);
1427 s
->data
= value
& 0xff;
1431 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1435 static const MemoryRegionOps pxa2xx_i2c_ops
= {
1436 .read
= pxa2xx_i2c_read
,
1437 .write
= pxa2xx_i2c_write
,
1438 .endianness
= DEVICE_NATIVE_ENDIAN
,
1441 static const VMStateDescription vmstate_pxa2xx_i2c_slave
= {
1442 .name
= "pxa2xx_i2c_slave",
1444 .minimum_version_id
= 1,
1445 .minimum_version_id_old
= 1,
1446 .fields
= (VMStateField
[]) {
1447 VMSTATE_I2C_SLAVE(parent_obj
, PXA2xxI2CSlaveState
),
1448 VMSTATE_END_OF_LIST()
1452 static const VMStateDescription vmstate_pxa2xx_i2c
= {
1453 .name
= "pxa2xx_i2c",
1455 .minimum_version_id
= 1,
1456 .minimum_version_id_old
= 1,
1457 .fields
= (VMStateField
[]) {
1458 VMSTATE_UINT16(control
, PXA2xxI2CState
),
1459 VMSTATE_UINT16(status
, PXA2xxI2CState
),
1460 VMSTATE_UINT8(ibmr
, PXA2xxI2CState
),
1461 VMSTATE_UINT8(data
, PXA2xxI2CState
),
1462 VMSTATE_STRUCT_POINTER(slave
, PXA2xxI2CState
,
1463 vmstate_pxa2xx_i2c_slave
, PXA2xxI2CSlaveState
),
1464 VMSTATE_END_OF_LIST()
1468 static int pxa2xx_i2c_slave_init(I2CSlave
*i2c
)
1470 /* Nothing to do. */
1474 static void pxa2xx_i2c_slave_class_init(ObjectClass
*klass
, void *data
)
1476 I2CSlaveClass
*k
= I2C_SLAVE_CLASS(klass
);
1478 k
->init
= pxa2xx_i2c_slave_init
;
1479 k
->event
= pxa2xx_i2c_event
;
1480 k
->recv
= pxa2xx_i2c_rx
;
1481 k
->send
= pxa2xx_i2c_tx
;
1484 static const TypeInfo pxa2xx_i2c_slave_info
= {
1485 .name
= TYPE_PXA2XX_I2C_SLAVE
,
1486 .parent
= TYPE_I2C_SLAVE
,
1487 .instance_size
= sizeof(PXA2xxI2CSlaveState
),
1488 .class_init
= pxa2xx_i2c_slave_class_init
,
1491 PXA2xxI2CState
*pxa2xx_i2c_init(hwaddr base
,
1492 qemu_irq irq
, uint32_t region_size
)
1495 SysBusDevice
*i2c_dev
;
1499 dev
= qdev_create(NULL
, TYPE_PXA2XX_I2C
);
1500 qdev_prop_set_uint32(dev
, "size", region_size
+ 1);
1501 qdev_prop_set_uint32(dev
, "offset", base
& region_size
);
1502 qdev_init_nofail(dev
);
1504 i2c_dev
= SYS_BUS_DEVICE(dev
);
1505 sysbus_mmio_map(i2c_dev
, 0, base
& ~region_size
);
1506 sysbus_connect_irq(i2c_dev
, 0, irq
);
1508 s
= PXA2XX_I2C(i2c_dev
);
1509 /* FIXME: Should the slave device really be on a separate bus? */
1510 i2cbus
= i2c_init_bus(dev
, "dummy");
1511 dev
= i2c_create_slave(i2cbus
, TYPE_PXA2XX_I2C_SLAVE
, 0);
1512 s
->slave
= PXA2XX_I2C_SLAVE(dev
);
1518 static int pxa2xx_i2c_initfn(SysBusDevice
*sbd
)
1520 DeviceState
*dev
= DEVICE(sbd
);
1521 PXA2xxI2CState
*s
= PXA2XX_I2C(dev
);
1523 s
->bus
= i2c_init_bus(dev
, "i2c");
1525 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pxa2xx_i2c_ops
, s
,
1526 "pxa2xx-i2c", s
->region_size
);
1527 sysbus_init_mmio(sbd
, &s
->iomem
);
1528 sysbus_init_irq(sbd
, &s
->irq
);
1533 I2CBus
*pxa2xx_i2c_bus(PXA2xxI2CState
*s
)
1538 static Property pxa2xx_i2c_properties
[] = {
1539 DEFINE_PROP_UINT32("size", PXA2xxI2CState
, region_size
, 0x10000),
1540 DEFINE_PROP_UINT32("offset", PXA2xxI2CState
, offset
, 0),
1541 DEFINE_PROP_END_OF_LIST(),
1544 static void pxa2xx_i2c_class_init(ObjectClass
*klass
, void *data
)
1546 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1547 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1549 k
->init
= pxa2xx_i2c_initfn
;
1550 dc
->desc
= "PXA2xx I2C Bus Controller";
1551 dc
->vmsd
= &vmstate_pxa2xx_i2c
;
1552 dc
->props
= pxa2xx_i2c_properties
;
1555 static const TypeInfo pxa2xx_i2c_info
= {
1556 .name
= TYPE_PXA2XX_I2C
,
1557 .parent
= TYPE_SYS_BUS_DEVICE
,
1558 .instance_size
= sizeof(PXA2xxI2CState
),
1559 .class_init
= pxa2xx_i2c_class_init
,
1562 /* PXA Inter-IC Sound Controller */
1563 static void pxa2xx_i2s_reset(PXA2xxI2SState
*i2s
)
1569 i2s
->control
[0] = 0x00;
1570 i2s
->control
[1] = 0x00;
1575 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1576 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1577 #define SACR_DREC(val) (val & (1 << 3))
1578 #define SACR_DPRL(val) (val & (1 << 4))
1580 static inline void pxa2xx_i2s_update(PXA2xxI2SState
*i2s
)
1583 rfs
= SACR_RFTH(i2s
->control
[0]) < i2s
->rx_len
&&
1584 !SACR_DREC(i2s
->control
[1]);
1585 tfs
= (i2s
->tx_len
|| i2s
->fifo_len
< SACR_TFTH(i2s
->control
[0])) &&
1586 i2s
->enable
&& !SACR_DPRL(i2s
->control
[1]);
1588 qemu_set_irq(i2s
->rx_dma
, rfs
);
1589 qemu_set_irq(i2s
->tx_dma
, tfs
);
1591 i2s
->status
&= 0xe0;
1592 if (i2s
->fifo_len
< 16 || !i2s
->enable
)
1593 i2s
->status
|= 1 << 0; /* TNF */
1595 i2s
->status
|= 1 << 1; /* RNE */
1597 i2s
->status
|= 1 << 2; /* BSY */
1599 i2s
->status
|= 1 << 3; /* TFS */
1601 i2s
->status
|= 1 << 4; /* RFS */
1602 if (!(i2s
->tx_len
&& i2s
->enable
))
1603 i2s
->status
|= i2s
->fifo_len
<< 8; /* TFL */
1604 i2s
->status
|= MAX(i2s
->rx_len
, 0xf) << 12; /* RFL */
1606 qemu_set_irq(i2s
->irq
, i2s
->status
& i2s
->mask
);
1609 #define SACR0 0x00 /* Serial Audio Global Control register */
1610 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1611 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1612 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1613 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1614 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1615 #define SADR 0x80 /* Serial Audio Data register */
1617 static uint64_t pxa2xx_i2s_read(void *opaque
, hwaddr addr
,
1620 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1624 return s
->control
[0];
1626 return s
->control
[1];
1636 if (s
->rx_len
> 0) {
1638 pxa2xx_i2s_update(s
);
1639 return s
->codec_in(s
->opaque
);
1643 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1649 static void pxa2xx_i2s_write(void *opaque
, hwaddr addr
,
1650 uint64_t value
, unsigned size
)
1652 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1657 if (value
& (1 << 3)) /* RST */
1658 pxa2xx_i2s_reset(s
);
1659 s
->control
[0] = value
& 0xff3d;
1660 if (!s
->enable
&& (value
& 1) && s
->tx_len
) { /* ENB */
1661 for (sample
= s
->fifo
; s
->fifo_len
> 0; s
->fifo_len
--, sample
++)
1662 s
->codec_out(s
->opaque
, *sample
);
1663 s
->status
&= ~(1 << 7); /* I2SOFF */
1665 if (value
& (1 << 4)) /* EFWR */
1666 printf("%s: Attempt to use special function\n", __FUNCTION__
);
1667 s
->enable
= (value
& 9) == 1; /* ENB && !RST*/
1668 pxa2xx_i2s_update(s
);
1671 s
->control
[1] = value
& 0x0039;
1672 if (value
& (1 << 5)) /* ENLBF */
1673 printf("%s: Attempt to use loopback function\n", __FUNCTION__
);
1674 if (value
& (1 << 4)) /* DPRL */
1676 pxa2xx_i2s_update(s
);
1679 s
->mask
= value
& 0x0078;
1680 pxa2xx_i2s_update(s
);
1683 s
->status
&= ~(value
& (3 << 5));
1684 pxa2xx_i2s_update(s
);
1687 s
->clk
= value
& 0x007f;
1690 if (s
->tx_len
&& s
->enable
) {
1692 pxa2xx_i2s_update(s
);
1693 s
->codec_out(s
->opaque
, value
);
1694 } else if (s
->fifo_len
< 16) {
1695 s
->fifo
[s
->fifo_len
++] = value
;
1696 pxa2xx_i2s_update(s
);
1700 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1704 static const MemoryRegionOps pxa2xx_i2s_ops
= {
1705 .read
= pxa2xx_i2s_read
,
1706 .write
= pxa2xx_i2s_write
,
1707 .endianness
= DEVICE_NATIVE_ENDIAN
,
1710 static const VMStateDescription vmstate_pxa2xx_i2s
= {
1711 .name
= "pxa2xx_i2s",
1713 .minimum_version_id
= 0,
1714 .minimum_version_id_old
= 0,
1715 .fields
= (VMStateField
[]) {
1716 VMSTATE_UINT32_ARRAY(control
, PXA2xxI2SState
, 2),
1717 VMSTATE_UINT32(status
, PXA2xxI2SState
),
1718 VMSTATE_UINT32(mask
, PXA2xxI2SState
),
1719 VMSTATE_UINT32(clk
, PXA2xxI2SState
),
1720 VMSTATE_INT32(enable
, PXA2xxI2SState
),
1721 VMSTATE_INT32(rx_len
, PXA2xxI2SState
),
1722 VMSTATE_INT32(tx_len
, PXA2xxI2SState
),
1723 VMSTATE_INT32(fifo_len
, PXA2xxI2SState
),
1724 VMSTATE_END_OF_LIST()
1728 static void pxa2xx_i2s_data_req(void *opaque
, int tx
, int rx
)
1730 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1733 /* Signal FIFO errors */
1734 if (s
->enable
&& s
->tx_len
)
1735 s
->status
|= 1 << 5; /* TUR */
1736 if (s
->enable
&& s
->rx_len
)
1737 s
->status
|= 1 << 6; /* ROR */
1739 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1740 * handle the cases where it makes a difference. */
1741 s
->tx_len
= tx
- s
->fifo_len
;
1743 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1745 for (sample
= s
->fifo
; s
->fifo_len
; s
->fifo_len
--, sample
++)
1746 s
->codec_out(s
->opaque
, *sample
);
1747 pxa2xx_i2s_update(s
);
1750 static PXA2xxI2SState
*pxa2xx_i2s_init(MemoryRegion
*sysmem
,
1752 qemu_irq irq
, qemu_irq rx_dma
, qemu_irq tx_dma
)
1754 PXA2xxI2SState
*s
= (PXA2xxI2SState
*)
1755 g_malloc0(sizeof(PXA2xxI2SState
));
1760 s
->data_req
= pxa2xx_i2s_data_req
;
1762 pxa2xx_i2s_reset(s
);
1764 memory_region_init_io(&s
->iomem
, NULL
, &pxa2xx_i2s_ops
, s
,
1765 "pxa2xx-i2s", 0x100000);
1766 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);
1768 vmstate_register(NULL
, base
, &vmstate_pxa2xx_i2s
, s
);
1773 /* PXA Fast Infra-red Communications Port */
1774 struct PXA2xxFIrState
{
1780 CharDriverState
*chr
;
1787 uint8_t rx_fifo
[64];
1790 static void pxa2xx_fir_reset(PXA2xxFIrState
*s
)
1792 s
->control
[0] = 0x00;
1793 s
->control
[1] = 0x00;
1794 s
->control
[2] = 0x00;
1795 s
->status
[0] = 0x00;
1796 s
->status
[1] = 0x00;
1800 static inline void pxa2xx_fir_update(PXA2xxFIrState
*s
)
1802 static const int tresh
[4] = { 8, 16, 32, 0 };
1804 if ((s
->control
[0] & (1 << 4)) && /* RXE */
1805 s
->rx_len
>= tresh
[s
->control
[2] & 3]) /* TRIG */
1806 s
->status
[0] |= 1 << 4; /* RFS */
1808 s
->status
[0] &= ~(1 << 4); /* RFS */
1809 if (s
->control
[0] & (1 << 3)) /* TXE */
1810 s
->status
[0] |= 1 << 3; /* TFS */
1812 s
->status
[0] &= ~(1 << 3); /* TFS */
1814 s
->status
[1] |= 1 << 2; /* RNE */
1816 s
->status
[1] &= ~(1 << 2); /* RNE */
1817 if (s
->control
[0] & (1 << 4)) /* RXE */
1818 s
->status
[1] |= 1 << 0; /* RSY */
1820 s
->status
[1] &= ~(1 << 0); /* RSY */
1822 intr
|= (s
->control
[0] & (1 << 5)) && /* RIE */
1823 (s
->status
[0] & (1 << 4)); /* RFS */
1824 intr
|= (s
->control
[0] & (1 << 6)) && /* TIE */
1825 (s
->status
[0] & (1 << 3)); /* TFS */
1826 intr
|= (s
->control
[2] & (1 << 4)) && /* TRAIL */
1827 (s
->status
[0] & (1 << 6)); /* EOC */
1828 intr
|= (s
->control
[0] & (1 << 2)) && /* TUS */
1829 (s
->status
[0] & (1 << 1)); /* TUR */
1830 intr
|= s
->status
[0] & 0x25; /* FRE, RAB, EIF */
1832 qemu_set_irq(s
->rx_dma
, (s
->status
[0] >> 4) & 1);
1833 qemu_set_irq(s
->tx_dma
, (s
->status
[0] >> 3) & 1);
1835 qemu_set_irq(s
->irq
, intr
&& s
->enable
);
1838 #define ICCR0 0x00 /* FICP Control register 0 */
1839 #define ICCR1 0x04 /* FICP Control register 1 */
1840 #define ICCR2 0x08 /* FICP Control register 2 */
1841 #define ICDR 0x0c /* FICP Data register */
1842 #define ICSR0 0x14 /* FICP Status register 0 */
1843 #define ICSR1 0x18 /* FICP Status register 1 */
1844 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1846 static uint64_t pxa2xx_fir_read(void *opaque
, hwaddr addr
,
1849 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1854 return s
->control
[0];
1856 return s
->control
[1];
1858 return s
->control
[2];
1860 s
->status
[0] &= ~0x01;
1861 s
->status
[1] &= ~0x72;
1864 ret
= s
->rx_fifo
[s
->rx_start
++];
1866 pxa2xx_fir_update(s
);
1869 printf("%s: Rx FIFO underrun.\n", __FUNCTION__
);
1872 return s
->status
[0];
1874 return s
->status
[1] | (1 << 3); /* TNF */
1878 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1884 static void pxa2xx_fir_write(void *opaque
, hwaddr addr
,
1885 uint64_t value64
, unsigned size
)
1887 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1888 uint32_t value
= value64
;
1893 s
->control
[0] = value
;
1894 if (!(value
& (1 << 4))) /* RXE */
1895 s
->rx_len
= s
->rx_start
= 0;
1896 if (!(value
& (1 << 3))) { /* TXE */
1899 s
->enable
= value
& 1; /* ITR */
1902 pxa2xx_fir_update(s
);
1905 s
->control
[1] = value
;
1908 s
->control
[2] = value
& 0x3f;
1909 pxa2xx_fir_update(s
);
1912 if (s
->control
[2] & (1 << 2)) /* TXP */
1916 if (s
->chr
&& s
->enable
&& (s
->control
[0] & (1 << 3))) /* TXE */
1917 qemu_chr_fe_write(s
->chr
, &ch
, 1);
1920 s
->status
[0] &= ~(value
& 0x66);
1921 pxa2xx_fir_update(s
);
1926 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1930 static const MemoryRegionOps pxa2xx_fir_ops
= {
1931 .read
= pxa2xx_fir_read
,
1932 .write
= pxa2xx_fir_write
,
1933 .endianness
= DEVICE_NATIVE_ENDIAN
,
1936 static int pxa2xx_fir_is_empty(void *opaque
)
1938 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1939 return (s
->rx_len
< 64);
1942 static void pxa2xx_fir_rx(void *opaque
, const uint8_t *buf
, int size
)
1944 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1945 if (!(s
->control
[0] & (1 << 4))) /* RXE */
1949 s
->status
[1] |= 1 << 4; /* EOF */
1950 if (s
->rx_len
>= 64) {
1951 s
->status
[1] |= 1 << 6; /* ROR */
1955 if (s
->control
[2] & (1 << 3)) /* RXP */
1956 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = *(buf
++);
1958 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = ~*(buf
++);
1961 pxa2xx_fir_update(s
);
1964 static void pxa2xx_fir_event(void *opaque
, int event
)
1968 static void pxa2xx_fir_save(QEMUFile
*f
, void *opaque
)
1970 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1973 qemu_put_be32(f
, s
->enable
);
1975 qemu_put_8s(f
, &s
->control
[0]);
1976 qemu_put_8s(f
, &s
->control
[1]);
1977 qemu_put_8s(f
, &s
->control
[2]);
1978 qemu_put_8s(f
, &s
->status
[0]);
1979 qemu_put_8s(f
, &s
->status
[1]);
1981 qemu_put_byte(f
, s
->rx_len
);
1982 for (i
= 0; i
< s
->rx_len
; i
++)
1983 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 63]);
1986 static int pxa2xx_fir_load(QEMUFile
*f
, void *opaque
, int version_id
)
1988 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1991 s
->enable
= qemu_get_be32(f
);
1993 qemu_get_8s(f
, &s
->control
[0]);
1994 qemu_get_8s(f
, &s
->control
[1]);
1995 qemu_get_8s(f
, &s
->control
[2]);
1996 qemu_get_8s(f
, &s
->status
[0]);
1997 qemu_get_8s(f
, &s
->status
[1]);
1999 s
->rx_len
= qemu_get_byte(f
);
2001 for (i
= 0; i
< s
->rx_len
; i
++)
2002 s
->rx_fifo
[i
] = qemu_get_byte(f
);
2007 static PXA2xxFIrState
*pxa2xx_fir_init(MemoryRegion
*sysmem
,
2009 qemu_irq irq
, qemu_irq rx_dma
, qemu_irq tx_dma
,
2010 CharDriverState
*chr
)
2012 PXA2xxFIrState
*s
= (PXA2xxFIrState
*)
2013 g_malloc0(sizeof(PXA2xxFIrState
));
2020 pxa2xx_fir_reset(s
);
2022 memory_region_init_io(&s
->iomem
, NULL
, &pxa2xx_fir_ops
, s
, "pxa2xx-fir", 0x1000);
2023 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);
2026 qemu_chr_fe_claim_no_fail(chr
);
2027 qemu_chr_add_handlers(chr
, pxa2xx_fir_is_empty
,
2028 pxa2xx_fir_rx
, pxa2xx_fir_event
, s
);
2031 register_savevm(NULL
, "pxa2xx_fir", 0, 0, pxa2xx_fir_save
,
2032 pxa2xx_fir_load
, s
);
2037 static void pxa2xx_reset(void *opaque
, int line
, int level
)
2039 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
2041 if (level
&& (s
->pm_regs
[PCFR
>> 2] & 0x10)) { /* GPR_EN */
2042 cpu_reset(CPU(s
->cpu
));
2043 /* TODO: reset peripherals */
2047 /* Initialise a PXA270 integrated chip (ARM based core). */
2048 PXA2xxState
*pxa270_init(MemoryRegion
*address_space
,
2049 unsigned int sdram_size
, const char *revision
)
2054 s
= (PXA2xxState
*) g_malloc0(sizeof(PXA2xxState
));
2056 if (revision
&& strncmp(revision
, "pxa27", 5)) {
2057 fprintf(stderr
, "Machine requires a PXA27x processor.\n");
2061 revision
= "pxa270";
2063 s
->cpu
= cpu_arm_init(revision
);
2064 if (s
->cpu
== NULL
) {
2065 fprintf(stderr
, "Unable to find CPU definition\n");
2068 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2070 /* SDRAM & Internal Memory Storage */
2071 memory_region_init_ram(&s
->sdram
, NULL
, "pxa270.sdram", sdram_size
);
2072 vmstate_register_ram_global(&s
->sdram
);
2073 memory_region_add_subregion(address_space
, PXA2XX_SDRAM_BASE
, &s
->sdram
);
2074 memory_region_init_ram(&s
->internal
, NULL
, "pxa270.internal", 0x40000);
2075 vmstate_register_ram_global(&s
->internal
);
2076 memory_region_add_subregion(address_space
, PXA2XX_INTERNAL_BASE
,
2079 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->cpu
);
2081 s
->dma
= pxa27x_dma_init(0x40000000,
2082 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_DMA
));
2084 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2085 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 0),
2086 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 1),
2087 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 2),
2088 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 3),
2089 qdev_get_gpio_in(s
->pic
, PXA27X_PIC_OST_4_11
),
2092 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->cpu
, s
->pic
, 121);
2094 dinfo
= drive_get(IF_SD
, 0, 0);
2096 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2099 s
->mmc
= pxa2xx_mmci_init(address_space
, 0x41100000, dinfo
->bdrv
,
2100 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_MMC
),
2101 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_MMCI
),
2102 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_MMCI
));
2104 for (i
= 0; pxa270_serial
[i
].io_base
; i
++) {
2105 if (serial_hds
[i
]) {
2106 serial_mm_init(address_space
, pxa270_serial
[i
].io_base
, 2,
2107 qdev_get_gpio_in(s
->pic
, pxa270_serial
[i
].irqn
),
2108 14857000 / 16, serial_hds
[i
],
2109 DEVICE_NATIVE_ENDIAN
);
2115 s
->fir
= pxa2xx_fir_init(address_space
, 0x40800000,
2116 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_ICP
),
2117 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_ICP
),
2118 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_ICP
),
2121 s
->lcd
= pxa2xx_lcdc_init(address_space
, 0x44000000,
2122 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_LCD
));
2124 s
->cm_base
= 0x41300000;
2125 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2126 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2127 memory_region_init_io(&s
->cm_iomem
, NULL
, &pxa2xx_cm_ops
, s
, "pxa2xx-cm", 0x1000);
2128 memory_region_add_subregion(address_space
, s
->cm_base
, &s
->cm_iomem
);
2129 vmstate_register(NULL
, 0, &vmstate_pxa2xx_cm
, s
);
2131 pxa2xx_setup_cp14(s
);
2133 s
->mm_base
= 0x48000000;
2134 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2135 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2136 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2137 memory_region_init_io(&s
->mm_iomem
, NULL
, &pxa2xx_mm_ops
, s
, "pxa2xx-mm", 0x1000);
2138 memory_region_add_subregion(address_space
, s
->mm_base
, &s
->mm_iomem
);
2139 vmstate_register(NULL
, 0, &vmstate_pxa2xx_mm
, s
);
2141 s
->pm_base
= 0x40f00000;
2142 memory_region_init_io(&s
->pm_iomem
, NULL
, &pxa2xx_pm_ops
, s
, "pxa2xx-pm", 0x100);
2143 memory_region_add_subregion(address_space
, s
->pm_base
, &s
->pm_iomem
);
2144 vmstate_register(NULL
, 0, &vmstate_pxa2xx_pm
, s
);
2146 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++);
2147 s
->ssp
= (SSIBus
**)g_malloc0(sizeof(SSIBus
*) * i
);
2148 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++) {
2150 dev
= sysbus_create_simple(TYPE_PXA2XX_SSP
, pxa27x_ssp
[i
].io_base
,
2151 qdev_get_gpio_in(s
->pic
, pxa27x_ssp
[i
].irqn
));
2152 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2155 if (usb_enabled(false)) {
2156 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2157 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_USBH1
));
2160 s
->pcmcia
[0] = pxa2xx_pcmcia_init(address_space
, 0x20000000);
2161 s
->pcmcia
[1] = pxa2xx_pcmcia_init(address_space
, 0x30000000);
2163 sysbus_create_simple(TYPE_PXA2XX_RTC
, 0x40900000,
2164 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_RTCALARM
));
2166 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600,
2167 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2C
), 0xffff);
2168 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100,
2169 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_PWRI2C
), 0xff);
2171 s
->i2s
= pxa2xx_i2s_init(address_space
, 0x40400000,
2172 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2S
),
2173 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_I2S
),
2174 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_I2S
));
2176 s
->kp
= pxa27x_keypad_init(address_space
, 0x41500000,
2177 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_KEYPAD
));
2179 /* GPIO1 resets the processor */
2180 /* The handler can be overridden by board-specific code */
2181 qdev_connect_gpio_out(s
->gpio
, 1, s
->reset
);
2185 /* Initialise a PXA255 integrated chip (ARM based core). */
2186 PXA2xxState
*pxa255_init(MemoryRegion
*address_space
, unsigned int sdram_size
)
2192 s
= (PXA2xxState
*) g_malloc0(sizeof(PXA2xxState
));
2194 s
->cpu
= cpu_arm_init("pxa255");
2195 if (s
->cpu
== NULL
) {
2196 fprintf(stderr
, "Unable to find CPU definition\n");
2199 s
->reset
= qemu_allocate_irqs(pxa2xx_reset
, s
, 1)[0];
2201 /* SDRAM & Internal Memory Storage */
2202 memory_region_init_ram(&s
->sdram
, NULL
, "pxa255.sdram", sdram_size
);
2203 vmstate_register_ram_global(&s
->sdram
);
2204 memory_region_add_subregion(address_space
, PXA2XX_SDRAM_BASE
, &s
->sdram
);
2205 memory_region_init_ram(&s
->internal
, NULL
, "pxa255.internal",
2206 PXA2XX_INTERNAL_SIZE
);
2207 vmstate_register_ram_global(&s
->internal
);
2208 memory_region_add_subregion(address_space
, PXA2XX_INTERNAL_BASE
,
2211 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->cpu
);
2213 s
->dma
= pxa255_dma_init(0x40000000,
2214 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_DMA
));
2216 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2217 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 0),
2218 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 1),
2219 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 2),
2220 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 3),
2223 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->cpu
, s
->pic
, 85);
2225 dinfo
= drive_get(IF_SD
, 0, 0);
2227 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2230 s
->mmc
= pxa2xx_mmci_init(address_space
, 0x41100000, dinfo
->bdrv
,
2231 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_MMC
),
2232 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_MMCI
),
2233 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_MMCI
));
2235 for (i
= 0; pxa255_serial
[i
].io_base
; i
++) {
2236 if (serial_hds
[i
]) {
2237 serial_mm_init(address_space
, pxa255_serial
[i
].io_base
, 2,
2238 qdev_get_gpio_in(s
->pic
, pxa255_serial
[i
].irqn
),
2239 14745600 / 16, serial_hds
[i
],
2240 DEVICE_NATIVE_ENDIAN
);
2246 s
->fir
= pxa2xx_fir_init(address_space
, 0x40800000,
2247 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_ICP
),
2248 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_ICP
),
2249 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_ICP
),
2252 s
->lcd
= pxa2xx_lcdc_init(address_space
, 0x44000000,
2253 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_LCD
));
2255 s
->cm_base
= 0x41300000;
2256 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2257 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2258 memory_region_init_io(&s
->cm_iomem
, NULL
, &pxa2xx_cm_ops
, s
, "pxa2xx-cm", 0x1000);
2259 memory_region_add_subregion(address_space
, s
->cm_base
, &s
->cm_iomem
);
2260 vmstate_register(NULL
, 0, &vmstate_pxa2xx_cm
, s
);
2262 pxa2xx_setup_cp14(s
);
2264 s
->mm_base
= 0x48000000;
2265 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2266 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2267 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2268 memory_region_init_io(&s
->mm_iomem
, NULL
, &pxa2xx_mm_ops
, s
, "pxa2xx-mm", 0x1000);
2269 memory_region_add_subregion(address_space
, s
->mm_base
, &s
->mm_iomem
);
2270 vmstate_register(NULL
, 0, &vmstate_pxa2xx_mm
, s
);
2272 s
->pm_base
= 0x40f00000;
2273 memory_region_init_io(&s
->pm_iomem
, NULL
, &pxa2xx_pm_ops
, s
, "pxa2xx-pm", 0x100);
2274 memory_region_add_subregion(address_space
, s
->pm_base
, &s
->pm_iomem
);
2275 vmstate_register(NULL
, 0, &vmstate_pxa2xx_pm
, s
);
2277 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++);
2278 s
->ssp
= (SSIBus
**)g_malloc0(sizeof(SSIBus
*) * i
);
2279 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++) {
2281 dev
= sysbus_create_simple(TYPE_PXA2XX_SSP
, pxa255_ssp
[i
].io_base
,
2282 qdev_get_gpio_in(s
->pic
, pxa255_ssp
[i
].irqn
));
2283 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2286 if (usb_enabled(false)) {
2287 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2288 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_USBH1
));
2291 s
->pcmcia
[0] = pxa2xx_pcmcia_init(address_space
, 0x20000000);
2292 s
->pcmcia
[1] = pxa2xx_pcmcia_init(address_space
, 0x30000000);
2294 sysbus_create_simple(TYPE_PXA2XX_RTC
, 0x40900000,
2295 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_RTCALARM
));
2297 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600,
2298 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2C
), 0xffff);
2299 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100,
2300 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_PWRI2C
), 0xff);
2302 s
->i2s
= pxa2xx_i2s_init(address_space
, 0x40400000,
2303 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2S
),
2304 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_I2S
),
2305 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_I2S
));
2307 /* GPIO1 resets the processor */
2308 /* The handler can be overridden by board-specific code */
2309 qdev_connect_gpio_out(s
->gpio
, 1, s
->reset
);
2313 static void pxa2xx_ssp_class_init(ObjectClass
*klass
, void *data
)
2315 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
2317 sdc
->init
= pxa2xx_ssp_init
;
2320 static const TypeInfo pxa2xx_ssp_info
= {
2321 .name
= TYPE_PXA2XX_SSP
,
2322 .parent
= TYPE_SYS_BUS_DEVICE
,
2323 .instance_size
= sizeof(PXA2xxSSPState
),
2324 .class_init
= pxa2xx_ssp_class_init
,
2327 static void pxa2xx_register_types(void)
2329 type_register_static(&pxa2xx_i2c_slave_info
);
2330 type_register_static(&pxa2xx_ssp_info
);
2331 type_register_static(&pxa2xx_i2c_info
);
2332 type_register_static(&pxa2xx_rtc_sysbus_info
);
2335 type_init(pxa2xx_register_types
)